ADL5320-EVALZ中文资料

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AD5320中文资料

元器件交易网
a
+2.7 V to +5.5 V, 140 ␮A, Rail-to-Rail Output 12-Bit DAC in a SOT-23 AD5320*
FUNCTIONAL BLOCK DIAGRAM
VDD GND POWER-ON RESET
FEATURES Single 12-Bit DAC 6-Lead SOT-23 and 8-Lead ␮SOIC Packages Micropower Operation: 140 ␮A @ 5 V Power-Down to 200 nA @ 5 V, 50 nA @ 3 V +2.7 V to +5.5 V Power Supply Guaranteed Monotonic by Design Reference Derived from Power Supply Power-On-Reset to Zero Volts Three Power-Down Functions Low Power Serial Interface with Schmitt-Triggered Inputs On-Chip Output Buffer Amplifier, Rail-to-Rail Operation SYNC Interrupt Facility APPLICATIONS Portable Battery Powered Instruments Digital Gain and Offset Adjustment Programmable Voltage and Current Sources Programmable Attenuators
VDD 10
1/4 Scale to 3/4 Scale Change (400 Hex to C00 Hex). RL = 2 kΩ; 0 pF < CL < 200 pF. See Figure 16. RL = 2 kΩ; CL = 500 pF RL = ∞ RL = 2 k Ω 1 LSB Change Around Major Carry. See Figure 19.

FLUKE 5320A-LOAD 电气安全校准器说明书

PN 3039085 February 2008 (Simplified Chinese) ©2008 Fluke Corporation. All rights reserved. Printed in USA.Specifications subject to change without notice.15320A-LOADHigh Voltage Load Adapter说明书简介5320A-LOAD High Voltage LoadAdapter （以下简称 Load ）设设用于在使用 5320A电气安全测测校准器（以下简称“校准器”）校准高压测测压压压高压测测压压行加载以产生泄漏电流。

如图 1 所示，Load由一套八个额定功率电阻器组成，其配置可提供从 10 k Ω 至 5 M Ω的八种电阻抽头。

视所选电阻器而定，Load在设设上能够承受 1.2 kV 至 5.5 kV 的最大电压。

ehq059图 1. 负载示意图XW 警告为了避免可能发生的电电或人身伤害，只能按照本说明书或《5320A校准器用户手册》的规定使用本 Load 。

操作准备工作Load随机附带一个电源线适配器（用于驱驱冷却风扇）、一条接地电电和本说明书。

电源线适配器附带五个不同的电源插头适配器，以便与不同的电源插头配置相兼容。

使用之前，选选与本地电源插座匹配的适当插头适配器。

连接插头与电源线适配器之后，即可使用 Load 。

将 Load 置于校准器之上，在 Load后面板接地端子与校准器后面板接地端子之间连接接地电电。

XW 警告为了避免高压电能产生电电，确保将Load后部的接地端子接至校准器后部的接地 (GND)端子。

严禁在外壳未接地的情况下使用 Load 。

W 小心为了防止 Load 损坏，请确保 Load 底部的通风孔和风扇排气孔不被阻塞以保证冷却效果。

将电源线适配器的一端接至 Load后面板上配套的电源输入连接器插座，另一端接至电源插座。

ADL5542 RF IF增益模块说明书

ADI 中文版数据手册是英文版数据手册的译文，敬请谅解翻译中可能存在的语言组织或翻译错误，ADI 不对翻译中存在的差异或由此产生的错误负责。

如需确认任何词语的准确性，请参考ADI 提供的最新英文版数据手册。

50 MHz 至6 GHz RF/IF 增益模块ADL5542Rev. BDocument Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Speci cations subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2007–2013 Analog Devices, Inc. All rights reserved. Technical Support 功能框图2GND 7GND1RFIN 8RFOUT3GND 6GND4CB 5VPOSINPUT MATCHOUTPUT MATCHBIAS CONTROL ADL554206879-001图1.产品特性固定增益：20 dB 工作频率高达6 GHz 输入/输出内部匹配50 Ω集成偏置控制电路输出IP3 46 dBm (500 MHz)40 dBm (900 MHz)1 dB 输出压缩：20.6 dB (900 MHz)噪声系数：3 dB (900 MHz)5 V 单电源供电小尺寸8引脚LFCSP 封装与15 dB 增益的ADL5541引脚兼容1 kV ESD(1C 类)概述ADL5542是一款宽带20 dB 线性放大器，工作频率高达6 GHz ，可用于各种有线电视、蜂窝和仪器仪表设备。

手机模块SIM5320应用经验

手机模块SIM5320应用经验
我是把手机模块SIM5320用来做GPRS数据传输的，这个模块同时支持移动和联通，还带有GPS定位功能，功能强大、外围电路少等优点，我第一次使用这个模块出现好几个问题，如：波特率、接收天线接口等。

下面我把我遇到的问题详细讲解：
1．模块SIM5320模块供电采用4.1V，如果单片机采用5V供电可以稳压4.8V用二极管1N4007降压
0.7V（4.8－0.7＝4.1V），如果单片机采用3.3V供
电可以稳压4.0V用二极管1N4007降压0.7V（4.0
－0.7＝3.3V）。

2．通讯可以直接使用RXD和TXD就可以了，但模块默认波特率是115200，如果需要更改波特率可以
发送更改波特率命令，但下次重启模块后又要重
新设置波特率。

模块的RXD和TXD接口电压是1.8V，
要做好接口电平转换问题。

3．接收天线接口：天线接口要求比较苛刻，处理不好直接影响模块工作，具体要求如下：
注：模块信号不好时会出现发指令不回复，或暂
时死机现象，等一阵子可能恢复正常。

4．模块控制采用AT+指令方式，详细可以参照SIM5320资料，这里就不详细讲解了。

5．工作原理图：。

ADL9005-EVALZ Evaluation Board User Guide

ADL9005-EVALZ Evaluation Board User GuideUG-1859One Technology Way • P .O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • Evaluating the ADL9005 Wideband, Low Noise Amplifier, Single Positive Supply,0.01 GHz to 26.5 GHzPLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS.Rev. 0 | Page 1 of 6FEATURES2-layer Rogers 4350B evaluation board with heat spreader End launch, 2.9 mm RF connectorsThrough calibration path (depopulated)EVALUATION KIT CONTENTSADL9005-EVALZ evaluation boardEQUIPMENT NEEDEDRF signal generator RF spectrum analyzer RF network analyzer5 V, 200 mA power supply External dc blockWideband, bias tee (Marki Microwave BT2-0040)GENERAL DESCRIPTIONThe ADL9005-EV AL Z consists of a 2-layer printed circuit board (PCB) fabricated from 10 mil thick, Rogers 4350B, copper clad, mounted to an aluminum heat spreader. The heat spreader assists in providing thermal relief to the device as well as mechanical support to the PCB. Mounting holes on the heat spreader allow attachment to larger heat s ink s for improved thermal management.The RFIN and RFOUT ports on the ADL9005-EV ALZ are populated with 2.9 mm, female coaxial connectors, and the respective RF traces have a 50 Ω characteristic impedance. The ADL9005-EV ALZ is populated with components suitable for use over the entire −40°C to +85°C operating temperature range of the ADL9005.To calibrate out board trace losses, a through calibration path, THRU CAL, is provided between the RFINTHRU and THRUCAL connectors. RFINTHRU and THRUCAL must be populated with RF connectors to use the through calibration path. The power voltages and ground path are accessed through surface-mounted technology (SMT) test points.An external wideband bias tee must be connected to RFOUT to provide bias current and ac coupling on RFOUT. The BT2-0040 from Marki Microwave is recommended.Alternatively, dc bias can be provided by connecting the dc supply voltage to the VDDOPT SMT test point.EVALUATION BOARD PHOTOGRAPHS24818-001Figure 1. ADL9005-EVALZ Top Side24818-002Figure 2. ADL9005-EVALZ Bottom SideThe RF traces are 50 Ω, grounded, coplanar waveguide. The package ground leads and the exposed pad directly connect to the ground plane. Multiple vias are used to connect the top and bottom ground planes with particular focus on the area directly beneath the ground pad to provide adequate electrical conduction and thermal conduction to the heat spreader.For full details on the ADL9005, see the ADL9005 data sheet, which must be consulted in conjunction with this user guide when using the ADL9005-EV ALZ.UG-1859ADL9005-EVALZ Evaluation Board User GuideRev. 0 | Page 2 of 6TABLE OF CONTENTSFeatures .............................................................................................. 1 Evaluation Kit Contents ................................................................... 1 Equipment Needed ........................................................................... 1 General Description ......................................................................... 1 Evaluation Board Photographs ....................................................... 1 Revision History ............................................................................... 2 Evaluation Board Hardware ............................................................ 3 Providing DC Bias Through a Connectorized Bias Tee ..............3 Providing DC Bias Through the ACG4/V DD2 Pin .........................3 Through Calibration Path ............................................................4 Evaluation Board Schematic and Artwork .....................................5 Ordering Information .......................................................................6 Bill of Materials (6)REVISION HISTORY2/2021—Revision 0: Initial VersionADL9005-EVALZ Evaluation Board User GuideUG-1859Rev. 0 | Page 3 of 6EVALUATION BOARD HARDWAREPROVIDING DC BIAS THROUGH A CONNECTORIZED BIAS TEEA 5 V , 200 mA supply is required to provide the bias to the ADL9005 when using the ADL9005-EV ALZ. Connect the 5 V supply through an external bias tee, such as the Marki Microwave BT2-0040, to the RFOUT port (see Figure 3). Connect the same 5 V supply to the VBIAS SMT test point. A connectorized dc blocking capacitor must be connected to the RFIN port because there is not an ac coupling capacitor on the RF input trace on the ADL9005-EV ALZ. The R1 value (default value is 300 Ω) sets the total current (I DQ ) to 80 mA.DC BLOCK24818-003Figure 3. ADL9005-EVALZ Operation Using a Connectorized Bias TeeRecommended Bias SequencingTo avoid damaging the device, careful attention must be paid to the sequencing of the RF input, the bias voltage, and the drain bias voltage. The following power-up sequencing is recommended: 1. Connect GND.2. Increase the voltage on the VBIAS SMT test point and theexternal bias tee to 5 V . 3. Apply the RF signal.The following power-down sequencing is recommended: 1. Turn off the RF signal.2. Reduce the voltage on the VBIAS SMT test point andthe external bias tee to 0 V .PROVIDING DC BIAS THROUGH THE ACG4/V DD2 PINAn alternative way to bias the ADL9005 when using the ADL9005-EV ALZ is by applying 8.5 V to the ACG4/V DD2 pin through the VDDOPT SMT test point and by applying 5 V to the R BIAS pin through the VBIAS SMT test point.The VDDOPT SMT test point connects directly to the ACG4/ V DD2 pin on the ADL9005. The higher 8.5 V supply is required to make up for the voltage drop across an internal resistor so that the internal drain bias voltage is still equal to 5 V . Applying this 8.5 V supply voltage to the VDDOPT SMT test point removes the need for an external bias tee, which must be replaced with a connectorized dc block on the RFOUT port (see Figure 4).With 5 V applied to the VBIAS SMT test point and the default value of R1 at 300 Ω, the resulting I DQ is 80 mA. The VBIAS SMT test point can also be connected directly to the 8.5 V supply. However, to do this, the R1 value must be increased to 850 Ω to maintain an I DQ of 80 mA.DC BLOCKDCBLOCK24818-004Figure 4. ADL9005-EVALZ Operation with V DD Applied Through theVDDOPT SMT Test PointRecommended Bias Sequencing when Providing Bias Through the VDDOPT SMT Test PointThe following sequencing is recommended for power-up when providing bias through the VDDOPT SMT test point: 1. Connect GND.2. Increase the voltage on the VDDOPT SMT test point to 8.5 V .3. Increase the voltage on the VBIAS SMT test point to 5 V .4.Apply the RF signal.The following sequencing is recommended for power-down when providing bias through the VDDOPT SMT test point: 1. Remove the RF signal.2. Decrease the voltage on the VBIAS SMT test point to 0 V .3. Decrease the voltage on the VDDOPT SMT test point to 0 V .UG-1859ADL9005-EVALZ Evaluation Board User GuideRev. 0 | Page 4 of 6THROUGH CALIBRATION PATHThe ADL9005-EV ALZ includes a calibration path (see the evaluation board schematic in Figure 6). RFINTHRU and THRUCAL must be populated with RF connectors to use the through calibration path. Figure 5 shows the insertion loss, input return loss and output return loss of the through calibration path.Table 1 lists the insertion loss of the through calibration path.FREQUENCY (GHz)246810121416182022242628–40–36–32–28–24–20–16–12–8–40I N S E R T I O N L O S S A N D R E T U R N L O S S (d B )24818-005Figure 5. Insertion Loss and Return Loss (Input and Output) of theThrough Calibration PathTable 1. Insertion Loss of the Through Calibration PathFrequency (GHz) Insertion Loss (dB) 0.01 +0.04 0.25 −0.013 0.5 −0.02 0.75 −0.023 1 −0.04 3 −0.1 5 −0.1 7 −0.2 9 −0.2 11 −0.3 13 −0.3 15 −0.5 17 −0.6 19 −0.5 21 −0.6 23 −0.7 25 −0.8 27−1.1ADL9005-EVALZ Evaluation Board User GuideUG-1859Rev. 0 | Page 5 of 624818-006Figure 6. ADL9005-EVALZ Schematic24818-007Figure 7. ADL9005-EVALZ Assembly Drawing (RFINTHRU and THRUCAL Not Installed)UG-1859ADL9005-EVALZ Evaluation Board User GuideRev. 0 | Page 6 of 6ORDERING INFORMATIONBILL OF MATERIALSTable 2.Reference Designator Description Manufacturer Manufacturer Number C1, C12 4.7 μF capacitors, tantalum, do not install (DNI) AVX TAJA475K020RNJ C2, C8 0.01 μF capacitors, ceramic, 0402, DNI KEMET C0402C103J3RACTU C4, C10 100 pF capacitors, ceramic, 0402 Samsung CL05C101JB5NNNC C5 100 pF capacitors, ceramic, 0402, DNI Samsung CL05C101JB5NNNC C6, C7 4.7 μF capacitors, tantalum AVX TAJA475K020RNJ C9, C11 0.01 μF capacitors, ceramic, 0402 KEMETC0402C103J3RACTU R1 300 Ω resistor, surface-mounted device (SMD), 0402 MULTICOMP (SPC) 0402WGF3000TCE R2, R3 0 Ω resistors, SMD, 0402, DNI PanasonicERJ-2GE0R00X RFINTHRU, THRUCAL Connectors, K jack edge, DNI SRI Connector Gage Co. 25-146-1000-92 VBIAS, VDDOPT, AGND Connectors, SMT test points Keystone Electronics 5016RFIN, RFOUT Connectors, K jack edge SRI Connector Gage Co. 25-146-1000-92 VGG2 Connectors, SMT test points, DNIKeystone Electronics 5016 U1Wideband, low noise amplifier, single positive supply, 0.01 GHz to 26.5 GHzAnalog Devices, Inc.ADL9005ESD CautionESD (electrostatic discharge) sensitive device . Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.Legal Terms and ConditionsBy using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc. (“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal, temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY . Customer understands and agrees that the Evaluation Board is provided for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional limitations: Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third Party to access the Evaluation Board. As used herein, the term “Third Party” includes any entity other than ADI, Customer, their employees, affiliates and in-house consultants. The Evaluation Board is NOT sold to Customer; all rights not expressly granted herein, including ownership of the Evaluation Board, are reserved by ADI. CONFIDENTIALITY . This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI. Customer may not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of use of the Evaluation Board or termination of this Agreement, Customer agrees to promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board, including but not limited to soldering or any other activity that affects the material content of the Evaluation Board. Modifications to the Evaluation Board must comply with applicable law, including but not limited to the RoHS Directive. TERMINATION. ADI may terminate this Agreement at any time upon giving written notice to Customer. Customer agrees to return to ADI the Evaluation Board at that time. L IMITATION OF L IABIL ITY . THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED “AS IS” AND ADI MAKES NO WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT. ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS, ENDORSEMENTS, GUARANTEES, OR WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THE EVALUATION BOARD INCLUDING, BUT NOT LIMITED TO, THE IMPL IED WARRANTY OF MERCHANTABILITY , TITL E, FITNESS FOR A PARTICUL AR PURPOSE OR NONINFRINGEMENT OF INTEL LECTUAL PROPERTY RIGHTS. IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER’S POSSESSION OR USE OF THE EVALUATION BOARD, INCLUDING BUT NOT LIMITED TO LOST PROFITS, DELAY COSTS, LABOR COSTS OR LOSS OF GOODWILL. ADI’S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE AMOUNT OF ONE HUNDRED US DOLLARS ($100.00). EXPORT. Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will comply with all applicable United States federal laws and regulations relating to exports. GOVERNING LAW. This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of Massachusetts (excluding conflict of law rules). Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and Customer hereby submits to the personal jurisdiction and venue of such courts. The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed. ©2021 Ana log Devices, Inc. All rights reserved. Tra dema rks a nd registered tra dema rks a re the property of their respective owners. UG24818-2/21(0)。

Circuits from the Lab

ADI 中文版数据手册是英文版数据手册的译文，敬请谅解翻译中可能存在的语言组织或翻译错误，ADI 不对翻译中存在的差异或由此产生的错误负责。

如需确认任何词语的准确性，请参考ADI 提供的最新英文版数据手册。

Circuits from the Lab™ reference circuits are engineered and tested for quick and easy system integration to help solve today’s analog, mixed-signal, and RF design challenges. For more information and/or support, visit /CN0248.ADRF6510 30 MHz 双通道可编程滤波器和可变增益放大器ADL5387 50 MHz 至2 GHz 正交解调器ADL5336集成48 dB 增益控制范围和可编程RMS 检波器的LF 至1 GHz VGA基于IQ 解调器，具有中频和基带可变增益以及可编程基带滤波功能的中频至基带接收机Rev. 0Circuits from the Lab™ circuits from Analog Devices have been designed and built by Analog Devices engineers. Standard engineering practices have been employed in the design and construction of each circuit, and their function and performance have been tested and veri ed in a lab environment at room temperature. However , you are solely responsible for testing the circuit and determining its suitability and applicability for your use and application. Accordingly , in no event shall Analog Devices be liable for direct, indirect, special, incidental, consequential or punitive damages due to any cause whatsoever connected to the use of any Circuits from the Lab circuits. (Continued on last page)One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ©2012 Analog Devices, Inc. All rights reserved.ADRF6510IQRFDIV BY 2ADL53872xLO0°90°ADF4350ADL5336AD9248BITSBITS10285-001VCO CORE图1. 直接变频接收机原理示意图(所有连接和去耦均未显示)CN-0248电路笔记连接/参考器件评估和设计支持电路评估板ADRF6510评估板(ADRF6510-EVALZ)ADL5387评估板(ADL5387-EVALZ) ADL5336评估板(ADL5336-EVALZ) AD8130评估板(AD8130-EBZ)，需要两个设计和集成文件原理图、布局文件、物料清单电路功能与优势该电路是灵活的频率捷变中频至基带接收机。

adl5315用法

adl5315用法ADL5315是一款电压模拟多功能数字电流表芯片，由美国Analog Devices（ADI）公司生产。

它主要用于电源管理、电源检测和电流测量等领域。

ADL5315拥有很多功能和优势，下面将详细介绍其使用方法。

1.ADL5315基本参数：-供电范围：2.7V至5.25V-电流测量范围：±200mA-分辨率：0.1mA-数字接口：I²C-工作温度范围：-40℃至+85℃2.ADL5315使用方法：ADL5315主要通过I²C接口与微处理器或其他数字电路进行通信。

以下是使用ADL5315的基本步骤：-步骤1：将ADL5315与待测试电路连接，确保电源和地线正确连接。

-步骤2：将ADL5315的SDA引脚连接至I²C总线的数据线上，将SCL引脚连接至I²C总线的时钟线上。

-步骤3：根据连接的电源电压范围选择合适的电源电压输出，接通电源。

-步骤4：使用相应的控制代码，通过I²C总线与ADL5315进行通信。

-步骤5：根据需要，读取和处理ADL5315返回的数据，如电流测量值、过温报警等。

3.ADL5315功能特点：ADL5315具有许多强大的功能和特点，以下是一些主要特点的介绍：-电压负载编程：可以根据需要设置电压负载，从而测试电路在不同负载下的电流表现。

-多通道输出：可同时测量多个电流值，并通过I²C接口输出给主控芯片，提高测试效率。

-精确度高：具备0.1mA的测量精度，可满足大部分电流测量需求。

-过温报警：当芯片温度超过预设阈值时，ADL5315会产生过温报警信号，以保护芯片免受过热损害。

-低功耗：在待机模式下，其功耗可以降低到无损耗水平，有助于延长电池寿命。

4.ADL5315应用领域：ADL5315广泛应用于各种电源管理、电源检测和电流测量的场合，特别适用于以下领域：-便携式设备：如智能手机、平板电脑、手持游戏机等，可用于电池管理和充电控制。

Analog Devices电路笔记 CN-0369参考设计说明书

Rev. 0Circuits from the Lab® reference designs from Analog Devices have been designed and built by Analog Devices engineers. Standard engineering practices have been employed in the design and construction of each circuit, and their function and performance have been tested and verified in a lab environment at room temperature. However, you are solely responsible for testing the circuit anddetermining its suitability and applicability for your use and application. Accordingly, in no event shall Analog Devices be liable for direct, indirect, special, incidental, consequential or punitive damages due to any cause whatsoever One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: /cn电路笔记CN-0369Circuits from the Lab®参考设计是经过测试的参考设计，有助于加速设计，同时简化系统集成，帮助并解决当今模拟、混合信号和RF设计挑战。

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CS5320资料

Preliminary Product InformationThis document contains information for a new product.Cirrus Logic reserves the right to modify this product without notice.Copyright © Cirrus Logic, Inc. 1999CS5320/21/2224-Bit Variable Bandwidth A/D Converter ChipsetFeaturesl CMOS A/D Converter Chipset l Dynamic Range-130 dB @ 25 Hz Bandwidth -121 dB @ 411 Hz Bandwidthl Delta-Sigma Architecture-Fourth-Order Modulator-Variable Oversampling: 64X to 4096X -Internal Track-and-Hold Amplifierl CS5321 Signal-to-Distortion: 115 dB l Clock Jitter Tolerant Architecture l Input Voltage Range: +4.5 V l Flexible Filter Chip-Hardware or Software Selectable Options -Seven Selectable Filter Corners (-3 dB)Frequencies: 25, 51, 102, 205, 411, 824 and 1650 Hzl Low Power Dissipation: <100 mWDescriptionThe CK5320 and CK5321 Chipsets function as a unique A/D converter intended for very high resolution measure-ment of signals below 1500 Hz. The CK5320 Chipset is a cost effective commercial grade solution for applica-tions which require a high dynamic range A/D converter.The chipsets perform sampling, A/D conversion, and anti-alias filtering.The CS5320 and CS5321 use Delta-Sigma modulation to produce highly accurate conversions. The ∆Σ modula-tor oversamples, virtually eliminating the need for external analog anti-alias filters. The CS5322 linear-phase FIR digital filter decimates the output to any one of seven selectable update periods: 16, 8, 4, 2, 1, 0.5and 0.25 milliseconds. Data is output from the digital fil-ter in a 24-bit serial format.ORDERING INFORMATION** Refer to Table 5Chip SetsKitsCS5320-KL & CS5322-KL CK5320-KL1CS5321-BL & CS5322-KL CK5321-KL1CS5321-BL & CS5322-BL CK5321-BL1RSEL V dd1AINR AIN+AIN-V ss1AGNDAnalog ModulatorMDATAMCLK MFLG RESETR/WH/SSCLK SID SOD ERROR DRDY ORCAL DECA DECB DECCCS CLKINSYNCVD+TDATAPWDNUSEORDGNDVD+DGND CSELDigital FilterCS5320/21CS5322V ss2DGNDV dd2LPWR OFSTMDATAHBRMSYNCVREF+VREF-OCT ‘99TABLE OF CONTENTS1. CHARACTERISTICS AND SPECIFICATIONS (4)CS5320 AND CS5321 ANALOG CHARACTERISTICS (4)CS5320 AND CS5321 SWITCHING CHARACTERISTICS (6)CS5320 AND CS5321 DIGITAL CHARACTERISTICS (7)CS5320 AND CS5321 RECOMMENDED OPERATION CONDITIONS (7)CS5320 AND CS5321 ABSOLUTE MAXIMUM RATINGS (7)CS5322 FILTER CHARACTERISTICS (8)CS5322 POWER SUPPLY (10)CS5322 SWITCHING CHARACTERISTICS (10)CS5322 DIGITAL CHARACTERISTICS (15)CS5322 RECOMMENDED OPERATION CONDITIONS (15)CS5322 ABSOLUTE MAXIMUM RATINGS (15)2. GENERAL DESCRIPTION (16)2.1. Analog Input (18)2.2. The OFST Pin (18)2.3. Input Range and Overrange Conditions (19)2.4. Voltage Reference (20)2.5. Clock Source (20)2.6. Low Power Mode (21)2.7. Digital Interface and Data Format (21)2.8. Performance (22)2.9. Power Supply Considerations (23)2.10. Power Supply Rejection Ratio (23)2.11. RESET Operation (23)2.12. Power-down Operation (23)2.13. SYNC Operation (24)2.14. Serial Read Operation (24)2.15. Serial Write Operation (25)2.16. Offset Calibration Operation (25)2.17. Status Bits (26)2.18. Board Layout Considerations (28)3. CS5320/21 PIN DESCRIPTIONS (29)Power Supplies (29)Analog Inputs (29)Digital Inputs (30)Digital Outputs (30)Contacting Cirrus Logic SupportFor a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: /corporate/contacts/Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor-mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provid ed “AS IS” without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Furthermore, no part of this publication ma y be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade-marks and service marks can be found at .4. CS5322 PIN DESCRIPTIONS (31)Power Supplies (31)Digital Outputs (31)Digital Inputs (32)5. ORDERING INFORMATION (34)6. PARAMETER DEFINITIONS (35)7. PACKAGE DIMENSIONS (36)LIST OF FIGURESFigure 1. Rise and Fall Times (6)Figure 2. CS5320 and CS5321 Interface Timing, HBR=1 (6)Figure 3. CS5322 Filter Response (8)Figure 4. CS5322 Digital Filter Passband Ripple f0 = 62.5 Hz (8)Figure 5. CS5322 Digital Filter Passband Ripple f0 = 125 Hz (8)Figure 6. CS5322 Digital Filter Passband Ripple f0 = 250 Hz (8)Figure 7. CS5322 Digital Filter Passband Ripple f0 = 500 Hz (9)Figure 8. CS5322 Digital Filter Passband Ripple f0 = 1000 Hz (9)Figure 9. CS5322 Digital Filter Passband Ripple f0 = 2000 Hz (9)Figure 10. CS5322 Digital Filter Passband Ripple f0 = 4000 Hz (9)Figure 11. CS5322 Impulse Response f0 = 62.5 Hz (9)Figure 12. CS5322 Impulse Response f0 = 1000 Hz (9)Figure 13. CS5322 Serial Port Timing (11)Figure 14. TDATA Setup/Hold Timing (12)Figure 15. DRDY Timing (13)Figure 16. RESET Timing (13)Figure 17. CS5320/21/CS5322 Interface Timing (14)Figure 18. CS5320/21 Block Diagram (16)Figure 19. CS5322 Block Diagram (17)Figure 20. System Connection Diagram (19)Figure 21. 4.5 Voltage Reference with two filter options (20)Figure 22. 1024 Point FFT Plot with -20 dB Input, 100 Hz Input, ten averages (22)Figure 23. 1024 Point FFT Plot with Full Scale Input, 100 Hz Input, ten averages ..22Figure 24. 1024 Point FFT Plot with Full Scale Input, 100 Hz Input, ten averages ..22 LIST OF TABLESTable 1.Output Coding for the CS5320/21 and CS5322 Combination (21)Table 2.Configuration Data Bits (24)Table 3.Status Data (from the SOD Pin) (26)Table 4.Bandwidth Selection: Truth Table (27)Table 5.Detailed Ordering Information (34)1. CHARACTERISTICS AND SPECIFICATIONSCS5320 AND CS5321 ANALOG CHARACTERISTICS (T A = (See Note 1); V ss1, V ss2 = -5V;V dd1, V dd2 = +5V; VD+ = 5V; AGND = DGND = 0V; HBR = V dd LPWR = 0, MCLK = 1.024MHz; Device connected as shown in Figure 20, CS5322 used for filtering; Logic 1 = VD+, Logic 0 = 0V; unless otherwise specified.)Notes: 1.CS5320-KL and CS5322-KL are guaranteed from 0o to 70o C. CS5322-BL is guaranteed from -40o to+85o C. CS5321-BL is guaranteed from -55o to +85o C.2.f O = CS5322 output word rate. Refer to “CS5322 FILTER CHARACTERISTICS” on page 8 for detailson the FIR Filter.3.Characterized with full scale input signal of 50Hz; fo = 500Hz.4.Characterized with input signals of 30 Hz and 50 Hz, each 6 dB down from full scale with fo = 1000 Hz.5.Specification is for the parameter over the specified temperature range and is for the CS5320/21 deviceonly (VREF = +4.5 V). It does not include the effects of external components; OFST = 0.6.Drift specifications are guaranteed by design and/or characterization.7.The offset after calibration specification applies to the effective offset voltage for a ±4.5 volt input to theCS5320/21 modulator, but is relative to the output digital codes from the CS5322 after ORCAL and USEOR have been made active.8.The CS5322 offset calibration is performed digitally and includes ± full scale (±4.5 volts intoCS5320/21). Calibration of offsets greater than ±5% of full scale will begin to subtract from the dynamic range.Parameter*CS5320CS5321Symbol MinTyp MaxMinTyp MaxUnitDynamic Performance Dynamic Range (Note 2)HBR = 1f O = 4000Hz OFST = 1f O = 2000Hz f O = 1000Hz f O = 500Hz f O = 250Hz f O = 125Hz f O = 62.5Hz HBR = 0f O = 4000Hz OFST = 1f O = 2000Hz f O = 1000Hz f O = 500Hz f O = 250Hz f O = 125Hz f O = 62.5HzDR--113-----------10311812112412712913099115118121124126127----------------116-----------10311812112412712913099115118121124126127--------------dB dB dB dB dB dB dB dB dB dB dB dB dB dBSignal-to-Distortion(Note 3)HBR = 1HBR = 0SDR100-110120--100110115120--dB dB Intermodulation Distortion (Note 4)IMD -105--110-dB dc Accuracy Full Scale Error (Note 5)FSE -1--1-%Full Scale Drift (Note 5,6)TC FS -5--5-ppm/°COffset(Note 5)V ZSE-10--10-mV Offset after Calibration (Note 7)-±100--±100-µV Offset Calibration Range (Note 8)-100--100-%F.S.Offset Drift(Note 5,6)TC ZSE-60--60-µV/°CCS5320 AND CS5321 ANALOG CHARACTERISTICS (Continued)Notes:9.The upper bandwidth limit is determined by the CS5322 digital filter.10.This input voltage range is for the configuration shown in Figure 20, the System Connection Diagram,and applies to signal from dc to f3 Hz. Refer to CS5322 Filter Characteristics for the values of f3.11.All outputs unloaded. All logic inputs forced to V dd or GND respectively.12.LPWR = 0.13.The CS5321 power dissipation can be reduced under the following conditions:a) LPWR=1; MCLK=512kHz, HBR=1 b) LWPR=1; MCLK=1.024MHz, HBR=014.Characterized with a 100 mVp-p sine wave applied separately to each supply.* Refer to Parameter Definitions (immediately following pin descriptions at the end of this data sheet).Specifications are subject to change without notice.Parameter*CS5320/21SymbolMin Typ Max Unit Input Characteristics Input Signal Frequencies (Note 9)BW dc -1500Hz Input Voltage Range (Note 10)V IN -4.5-+4.5V Input Overrange Voltage (Note 10)I OVR--5%F.S.Power SuppliesDC Power Supply Currents(Note 11)LPWR = 0 Positive SuppliesNegative SuppliesLPWR = 1 Positive SuppliesNegative Supplies--5.55.53.03.07.57.54.54.5mA mA mA mA Power Consumption(Note 11)Normal Operating Mode (Note12)Lower Power Mode (Note 13)P DN P DL --55307545mW mW Power DownP D-2-mW Power Supply Rejection(dc to 128 kHz) (Note 14)PSR -60-dBCS5320 AND CS5321 SWITCHING CHARACTERISTICS (T A = (See Note 1); V dd1, V dd2 =5V ± 5%; V ss1, V ss2 = -5V ± 5%; Inputs: Logic 0 = 0V Logic 1 = V+; C L = 50 pF (Note 15))Notes:15.Guaranteed by design, characterization, or test.16.If MCLK is removed, the modulator will enter the power down mode.17.Excludes MCLK input. MCLK should be driven with a signal having rise and fall times of 25 ns or faster.ParameterSymbol Min Typ Max Units MCLK Frequency (Note 16)f c0.250 1.024 1.2MHz MCLK Duty Cycle 40-60%MCLK Jitter (In-band)--300ps Rise Times:Any Digital Input (Note 17)Any Digital Output t risein t riseout ---50100200ns ns Fall Times:Any Digital Input (Note 17)Any Digital Outputt fallin t fallout ---50100200ns ns MSYNC Setup Time to MCLK rising t mss 20--ns MSYNC Hold Time after MCLK rising t msh 20--ns MCLK rising to Valid MFLG t mfh -140255ns MCLK rising to Valid MDATAt mdv-170300nsFigure 1. Rise and Fall TimesFigure 2. CS5320 and CS5321 Interface Timing, HBR=1CS5320 AND CS5321 DIGITAL CHARACTERISTICS (T A = (See Note 1); V dd1 = V dd2 =5.0V ± 5%; GND = 0V; measurements performed under static conditions)Notes:18.Device is intended to be driven with CMOS logic levels.19.Device is intended to be interfaced to CMOS logic. Resistive loads are not recommended on these pins.CS5320 AND CS5321 RECOMMENDED OPERATION CONDITIONS (Voltages withrespect to GND = 0V, See Note 20)Notes:20.The maximum voltage differential between the Positive Supply of the CS5320/21 and the PositiveDigital Supply of the CS5322 must be less than 0.25V.CS5320 AND CS5321 ABSOLUTE MAXIMUM RATINGS * (Voltages with respect toGND = 0V)Notes:21.Transient currents of up to 100 mA will not cause SCR latch up.*WARNING: Operation beyond these limits may result in permanent damage to the device. Normal operation isnot guaranteed at these extremes.ParameterSymbol Min Typ Max Units High-Level Input Drive Voltage (Note 18)V IH (V dd )-0.6--V Low-Level Input Drive Voltage(Note 18)V IL -- 1.0V High-Level Output Voltage IOUT = -40 µA (Note 19)V OH (V dd )-0.3--V Low-Level Output Voltage IOUT = +40 µA (Note 19)V OL --0.3V Input Leakage Current I LKG --±10µA Digital Input Capacitance C IN -9-pF Digital Output CapacitanceC OUT-9-pFParameterSymbolMin Typ Max Units DC Supply:Positive Negative V dd1,V dd2V ss1,V ss24.75-4.755.0-5.0 5.25-5.25V V Ambient Operating Temperature-KL -BLT A T A0-55--+70+85°C °CParameterSymbol Min Max Units DC Supply:Positive Negative V dd1,V dd2V ss1,V ss2-0.3+0.3 6.0-6.0V V Input Current, Any Pin Except Supplies (Note 21)I in -±10mA Output CurrentI out -25mA Total Power (all supplies and outputs)P t -1W Digital Input Voltage V IND -0.3(V dd )+0.3V Storage TemperatureT stg-65150°CCS5322 FILTER CHARACTERISTICS (T A = (See Note 1); VD+ = 5.0V; GND = 0V;CLKIN = 1.024 MHz; transfer function shown in Figure 3; unless otherwise specified.)Notes:22.G SB = -130 dB for all Output Word Rates.Output Word Ratef 0 (Hz)Passband f1(Hz)Passband Flatness R PB (dB)-3dB Freq. f2 (Hz)Stopband f3 (Hz)(Note 22)Group Delay(ms)40002000100050025012562.51500750375187.593.846.923.40.20.040.080.10.10.10.11652.5824.3411.9205.9102.951.525.72000100050025012562.531.257.2514.52958116232464Figure 4. CS5322 Digital Filter Passband Ripplef 0= 62.5 HzFigure 5. CS5322 Digital Filter Passband Ripplef 0 = 125 Hz Figure 6. CS5322 Digital Filter Passband Ripplef 0 = 250 HzFigure 7. CS5322 Digital Filter Passband Ripplef0 = 500 Hz Figure 8. CS5322 Digital Filter Passband Ripplef0= 1000 HzFigure 9. CS5322 Digital Filter Passband Ripplef0 = 2000 Hz Figure 10. CS5322 Digital Filter Passband Ripplef0 = 4000 HzFigure 11. CS5322 Impulse Response,f0 = 62.5 Hz Figure 12. CS5322 Impulse Response,f0 = 1000 HzCS5322 POWER SUPPLY (T A = (See Note 1); VD+ = 5V; CLKIN = 1.024 MHz)CS5322 SWITCHING CHARACTERISTICS (T A = (See Note 1); VD+ = 5V ± 5%; DGND = 0V;Inputs: Logic 0 = 0V Logic 1 = VD+; C L = 50 pF (Note 23)23.Guaranteed by design, characterization and/or test.ParameterCS5322-KCS5322-B Min Typ Max Min Typ Max Unit Power Supply Current:ID+(Note 11)- 2.24- 2.24mA Power Dissipation:(Note 11)PWDN Low PWDN High--110.6202.5--110.6202.5mW mWParameterSymbol Min Typ Max Units CLKIN Frequency f c0.512 1.024 1.2MHz CLKIN Duty Cycle 40-60%Rise Times:Any Digital Input Any Digital Output t rise ---50100100ns ns Fall Times:Any Digital Input Any Digital Outputt fall ---50100100ns ns Serial Port Read TimingDRDY to Data Validt ddv --25ns RSEL Setup Time before Data Valid t rss 50--ns Read Setup before CS Active t rsc 20--ns Read Active to Data Valid t rdv --50ns SCLK rising to New SOD bit t rdd --50ns SCLK Pulse Width High t rph 30--ns SCLK Pulse Width Low t rpl 30--ns SCLK Periodt rsp 100--ns SCLK falling to DRDY falling t rst --50ns CS High to Output Hi-Zt rch --20ns Read Hold Time after CS Inactive t rhc 20--ns Read Select Setup to SCLK fallingt rds 20--ns Serial Port Write TimingWrite Setup Before CS Active t wsc 20--ns SCLK Pulse Width Low t wpl 30--ns SCLK Pulse Width High t wph 30--ns SCLK Periodt wsp 100--ns Write Setup Time to First SCLK falling t wws 20--ns Data Setup Time to First SCLK falling t wds 20--ns Write Select Hold Time after SCLK falling t wwh 20--ns Write Hold Time after CS Inactive t whc 20--ns Data Hold Time after SCLK fallingt wdh20--nsSerial Port Read Timing(R/W = 1, CS = 0, RSEL = 1 DRDY Does not toggle if reading status, RSEL = 0)Figure 13. CS5322 Serial Port TimingCS5322 SWITCHING CHARACTERISTICS (continued)ParameterSymbol Min Typ Max Units Test Data (TDATA) TimingSYNC Setup Time to CLKIN rising t ss 20--ns SYNC Hold Time after CLKIN risingt sh 20--ns TDATA Setup Time to CLKIN rising after SYNC t tds -20-ns TDATA Hold Time after CLKIN rising t tdh -150-ns ORCAL Setup Time to CLKIN rising t os 20--ns ORCAL Hold Time after CLKIN rising t oh 20--ns DRDY TimingCLKIN rising to DRDY falling t df -140-ns CLKIN falling to DRDY rising t dr -150-ns CLKIN rising to ERROR change t ec -140-ns RESET TimingRESET Setup Time to CLKIN rising t rs 20--ns RESET Hold Time after CLKIN rising t rh 20--ns SYNC Setup Time to CLKIN rising tss 20--ns SYNC Hold Time after CLKIN risingt sh20--nsFigure 14. TDATA Setup/Hold TimingFigure 15. DRDY TimingFigure 16. RESET TimingCS5322 SWITCHING CHARACTERISTICS (continued)Notes:24.If MCLK is removed, the modulator will enter the power down mode.25.Excludes MCLK input. MCLK should be driven with a signal having rise and fall times of 25 ns or faster.26.Only the rising edge of MSYNC relative to MCLK is used to synchronize the device. MSYNC can returnlow at any time as long as it remains high for at least one MCLK cycle.ParameterSymbol Min Typ Max Units MCLK Frequency (Note 24)f c0.512 1.024 1.1MHz MCLK Duty Cycle 40-60%Rise Times:Any Digital Input (Note 25)Any Digital Output t rise ---50100200ns ns Fall Times:Any Digital Input (Note 25)Any Digital Outputt fall ---50100200ns ns SYNC Setup Time to CLKIN rising t ss 20--ns SYNC Hold Time after CLKIN rising t sh 20--ns CLKIN edge to MCLK edge t mss -30-ns MCLK rising to Valid MDATA t msh-50-ns MSYNC Delay from MCLK rising(Note 26)t msd-90-nsFigure 17. CS5320/21/CS5322 Interface TimingCS5322 DIGITAL CHARACTERISTICS (T A = (See Note 1); VD+ = 5.0V ± 5%; GND = 0V;measurements performed under static conditions)Notes:27.Device is intended to be driven with CMOS logic levels.28.Device is intended to be interfaced to CMOS logic. Resistive loads are not recommended on these pins.CS5322 RECOMMENDED OPERATION CONDITIONS (Voltages with respect to GND = 0V)Notes:29.The maximum voltage differential between the Positive Supply of the CS5320/21 and the PositiveDigital Supply of the CS5322 must be less than 0.25V.CS5322 ABSOLUTE MAXIMUM RATINGS * (Voltages with respect to GND = 0V)Notes:30.Transient currents of up to 100 mA will not cause SCR latch up.*WARNING: Operation beyond these limits may result in permanent damage to the device. Normal operation isnot guaranteed at these extremes.ParameterSymbol Min Typ Max Units High-Level Input Drive Voltage V IH (VD+)-0.3--V Low-Level Input Drive Voltage V IL--0.3V High-Level Input Threshold (Note 27)(VD+)-1.0--V Low-Level Input Threshold(Note 27)-- 1.0V High-Level Output Voltage IOUT = -40µA (Note 28)V OH (VD+)-0.6--V Low-Level Output Voltage IOUT = +1.6 mA (Note 28)V OL --0.4V Input Leakage Current All pins except MFLG, SODI LKG --±10µA Three-State Leakage CurrentI OZ --±10µA Digital Input Capacitance C IN -9-pF Digital Output Capacitance C OUT -9-pFParameterSymbolMinTypMaxUnitsDC Supply:(Note 29)Positive NegativeVD+VD- 4.75-4.75 5.0-5.0 5.25-5.25V V Ambient Operating Temperature-KL -BL T A T A0-40--+70+85°C °CParameterSymbolMinTypMaxUnitsDC Supply:(Note 29)Positive NegativeVD+VD--0.30.3--(VD+)+0.3-6.0V V Input Current, Any Pin Except Supplies (Note 30)I in --±10mA Digital Input Voltage VIND -0.3-(VD+)+0.3V Storage TemperatureT stg-65-150°C2. GENERAL DESCRIPTIONThe CS5320 and CS5321 are fourth-order CMOS monolithic analog modulators designed specifical-ly for very high resolution measurement of signals between dc and 1500 Hz. Configuring the CS5320or CS5321 with the CS5322 FIR filter results in a high resolution A/D converter system that performs sampling and A/D conversion with dynamic range exceeding 120 dB .The CS5320 and CS5321 use a fourth-order over-sampling architecture to achieve high resolution A/D conversion. The modulator consists of a 1-bit A/D converter embedded in a negative feedback loop. The modulator provides an oversampled seri-al bit stream at 256 kbits per second (HBR=1) and 128 kbits per second (HBR=0) operating with a clock rate of 1.024 MHz. Figure 18 illustrates the CS5320/CS5321 Block Diagram.The CS5322 is a monolithic digital Finite Impulse Response (FIR) filter with programmable decima-tion. The CS5322 and CS5320/CS5321 are intend-ed to be used together to form a unique high dynamic range ADC chipset. The CS5322 provides the digital anti-alias filter for the CS5320/CS5321modulator output. The CS5322 consists of: a multi-stage FIR filter, four registers (status, data, offset,and configuration), a flexible serial input and out-put port, and a 2-channel input data multiplexer that selects data from the CS5320/CS5321 (MDA-TA) or user test data (TDATA). The CS5322 deci-mates (64x to 4096x) the output to any of seven selectable up-date periods: 16, 8, 4, 2, 1, 0.5 and 0.25 milliseconds. Data is output from the digital filter in a 24-bit serial format. Figure 19 illustrates the CS5322 Block Diagram.Figure 18. CS5320/21 Block DiagramAINR V dd1ΣOsc.DetectAIN+AIN-VREF+VREF-D/AA/DDigitalControlMDATAMDATAClockGenerationMSYNC MCLK HBR MFLGOFST LPWR V ss1AGNDV dd2V ss2DGNDFigure 19. CS5322 Block Diagram2.1 Analog InputThe CS5320 and CS5321 modulators use a switched capacitor architecture for its signal and voltage reference inputs. The signal input uses three pins; AINR, AIN+, and AIN-. The AIN- pin acts as the return pin for the AINR and AIN+ pins. The AINR pin is a switched capacitor "rough charge" in-put for the AIN+ pin. The input impedance for the rough charge pin (AINR) is 1/fC where f is two times the modulator sampling clock rate and C is the internal sampling capacitor (about 40 pF). Us-ing a 1.024 MHz master clock (HBR = 1) yields an input impedance of about 1/(512 kHz)X(40 pF) or about 50 kΩ. Internal to the chip the rough charge input pre-charges the sampling capacitor used on the AIN+ input, therefore the effective input imped-ance on the AIN+ pin is orders of magnitude above the impedance seen on the AINR pin.The analog input structure inside the VREF+ pin is very similar to the AINR pin but includes addition-al circuitry whose operating current can change over temperature and from device to device. There-fore, if gain accuracy is important, the VREF+ pin should be driven from a low source impedance. The current demand of the VREF+ pin will produce a voltage drop of approximately 45 mV across the 200 Ω source resistor of Figure 20 and Figure 21 Option A with MCLK = 1.024 MHz, HBR = 1, and temperature = 25°C.When the CS5320/21 modulator is operated with a 4.5 V reference it will accept a 9 V p-p input signal, but modulator loop stability can be adversely af-fected by high frequency out-of-band signals. Therefore, input signals must be band-limited by an input filter. The -3 dB corner of the input filter must be equal to the modulator sampling clock divided by 64. The modulator sampling clock is MCLK/4 when HBR = 1 or MCLK/8 when HBR = 0. With MCLK = 1.024 MHz, HBR = 1, the modulator sampling clock is 256 kHz which requires an input filter with a -3 dB corner of 4 kHz. The bandlimit-ing may be accomplished in an amplifier stage ahead of the CS5320/21 modulator or with the RC input filter at the AIN+ and AINR input pins. The RC filter at the AIN+ and AINR pins is recom-mended to reduce the "charge kick" that the driving amplifier sees as the switched capacitor sampling is performed.Figure 20 illustrates the CS5320/21 and CS5322 system connections. The input components on AINR and AIN+ should be identical values for op-timum performance. In choosing the components the capacitor should be a minimum of 0.1 µF (C0G dielectric ceramic preferred). For minimum board space, the RC components on the AINR input can be removed, but this will force the driving amplifi-er to source the full dynamic charging current of the AINR input. This can increase distortion in the driving amplifier and reduce system performance. In choosing the RC filter components, increasing C and minimizing R is preferred. Increasing C reduc-es the instantaneous voltage change on the pin, but may require paralleling capacitors to maintain smaller size (the recommended 0.1 µF C0G ceram-ic capacitor is larger than other similar-valued ca-pacitors with different dielectrics). Larger resistor values will increase the voltage drop across the re-sistor as the recharging current charges the switched capacitor input.2.2 The OFST PinThe CS5320/21 modulator can produce "idle tones" which occur in the passband when the input signal is steady state dc signal within about±50 mV of bipolar zero. In the CS5320/21 these tones are about 135 dB down from full scale. The user can force these idle tones "out-of-band" by adding 100 mV of dc offset to the signal at the AIN input. Alternately, if the user circuitry has a low offset voltage such that the input signal is within ±50 mV of bipolar zero when no AC signal is present, the OFST pin on the CS5320/21 can be ac-tivated. When OFST = 1, +100 mV of input re-ferred offset will be added internal to the CS5320/21 and guarantee that any idle tones present will lie out-of-band. The user should be certain that when OFST is active (OFST =1) that the offset voltage generated by the user circuitry does not negate the offset added by the OFST pin.2.3 Input Range and Overrange Conditions The analog input is applied to the AIN+ and AINR pins with the AIN- pin connected to GND. The in-put is fully differential but for proper operation the AIN- pin must remain at GND potential.The analog input span is defined by the voltage ap-plied between the VREF+ and VREF- input pins. See the Voltage Reference section of this data sheet for voltage reference requirements.The modulator is a fourth order delta-sigma and is therefore conditionally stable. The modulator may go into an oscillatory condition if the analog input is overranged. Input signals which exceed either plus or minus full scale by more than 5 % can intro-duce instability in the modulator. If an unstable condition is detected, the modulator will be re-duced to a first order system until loop stability is achieved. If this occurs the MFLG pin will transi-tion from a low to a high will result in an error bit being set in the CS5322. The input signal must be reduced to within the full scale range of the con-verter for at least 32 MCLK cycles for the modula-tor to recover from this error condition.Figure 20. System Connection Diagram。

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AmPac and Asia Regions VersionFLUKE Corporation / FLUKE International Corporation / PO Box 9090 / Everett WA 98206-9090 USA.(206) 356 5500 / FAX (206) 356-5116Page 1产品发布多功能电气安全校准器利用单台仪器校准和计量各种电气安全测试设备福禄克精密仪器部（FPM ）发布了FLUKE5320A —— 一款多功能校准器，为各种各样的电气安全测试仪器的校准提供了齐全的功能和全面解决方案——高电压、大电流、大功率测量和驱动能力，所有这些都集成到了一台仪器内。

通过将多种功能集成到一台仪器，可以用一台校准器替代那些难以找得到的、高电压和大电流、大功率的电阻器和许多旧型号的仪器。

5320A 还包括一台精密数字多用表和电压校准器，可以完全校准多功能电气安装测试仪、兆欧表、环路测试仪、漏电保护测试仪、大地电阻测试、便携式电器设备测试仪、接地连接测试仪、医疗仪器电气安全测试仪，等等。

用户会对5320A 的精密度、可重复测量结果充满信心，并且会通过将5320A 与MET/CAL® Plus 校准管理软件相集成，实现自动化校准，从而实现生产力的大幅提高。

利用5320A 覆盖最多的被校准对象FLUKE 5320A 在单台仪器中集成了多种功能，可保证各种电气安全测试设备校准的产出效率和测量准确度。

谁是目标客户？主要的客户为直流/低频（DC/LF）校准实验室：第三方实验室内部校准实验室（公用事业部门、电信、电气制造厂商）部队/政府电气安全测试仪器制造商5320A的自动测试功能使其非常适合于生产测试和用于校准实验室。

被校准对象是什么？随着全球范围内电气安全标准的日益增多（包括英国的第16版测试标准和德国的VDE 0100及0700标准），电气安装和电器设备的测试成为电工和测试人员从事越来越多的常见任务。

MSI Cubi N ADL 商品说明说明书

© 2023 Micro-Star Int'l Co.Ltd. MSI is a registered trademark of Micro-Star Int'l Co.Ltd. All rights reserved.SPECIFICATIONSOperating System Windows 11 Home & Windows 11 Pro- MSI recommends Windows 11 Pro for businessCPU Intel ®Processor N200 (6M Cache, 1.0 GHz up to 3.7 GHz) Intel ®Processor N100 (6M Cache, 0.8 GHz up to 3.4 GHz)Chipset Intel ® SoCGraphics Intel ® UHD Graphics Storage 1x M.2 SSD (auto switch)1x 2.5”HDD/SSDSystem Memory 1x DDR4 3200MHz SO-DIMMs, up to 16GB I/O (Front)2x USB 3.2 Gen 2 Type A1x USB 3.2 Gen 2 Type-C (DP Alternate)1x Mic-in / Headphone-out combo I/O (Rear)2x USB 2.0 Type A 2x RJ451x DP-out(1.4)1x HDMI™-out (2.1)Bluetooth 4.2 (for AC 3168)5.1 (for AC 9462)Wireless LAN Intel Wireless AC 3168Intel Wireless AC 9462TPM Support dTPM 2.0LAN 2x Realtek ® RTL8111H Cooling SystemFan CoolerAC Adapter/ PSU 65WDimension (WxDxH)124 x 124 x 53.7 mm (4.88 x 4.88 x 2.11 inch)WEIGHT (N.W./G.W.)0.55 kg / 1.4 kgVESA Mount 100 x 100 mm & 75 x 75 mm Volume0.66 Liter / 1.39 ptAccessories1x User Manual (Optional)1x Quick Guide 1x Warranty Card1x Adpator 1x Power CordVESA Mount ScrewsCertiﬁcates FCC, CB/CE, UL & CUL, VCCI, RCM, ENERGY STAR Note*Upgrade timing may vary by device. Features and app availability may vary by region. Certain features require speciﬁc hardware (see https:///en-us/windows/windows-11-speciﬁcations).VESA MountableTo be mounted on the wall of your oﬃce & home with a VESAstandard design which can make it completely invisible on a desk.TPM SupportFW TPM design secures your conﬁdential data with encryption keys.Low NoiseWith an excellent thermal design and low noise fan, resulting in a low noise level as quiet as a forest.CONNECTIONS1. 1x Mic-in/ Headphone-out combo 3. 1x USB 3.2 Gen 2 Type C (DP Alternate)5. 1x Kensington Lock 7. 1x DP-out (1.4)9. 2x USB 2.0 Type A2. 2x USB3.2 Gen 2 Type A4. 1x Power Botton 6. 1x HDMI™ (2.1)8. 2x RJ45 (LAN)10. DC JackG e n e r a t e d 2023-06-21, c h e c k f o r t h e l a t e s t v e r s i o n w w w .m s i .c o m /d a t a s h e e t . T h e i n f o r m a t i o n p r o v i d e d i n t h i s d o c u m e n t i s i n t e n d e d f o r i n f o r m a t i o n a l p u r p o s e s o n l y a n d i s s u b j e c t t o c h a n g e w i t h o u t n o t i c e .。

5320A型多功能电气测试仪校准器测量不确定度评定

Ａｂｓｔｒａｃｔ：Ｒａｐｉｄｍｅａｓｕｉｎｒｇｒａｎｇｅｅｘｐａｎｓｉｏｎ，ｔｈｅｍｅａｓｕｒｅｍｅｎｔｕｎｃｅｒｔａｉｎｔｙｉｎｔｈｅｉｅｆｌｄｏｆｍｅａｓｕｒｅｍｅｎｔｏｆｔｈｅｗｏｒｌｄｈａｖｅｂｅｅｎｗｉｄｅｌｙｕｓｅｄ．Ｔｈｅｍｅａｓｕｒｅｍｅｎｔｕｎｃｅｒｔａｉｎｔｙｉｓｐｒｅｒｅｑｕｉｓｉｔｅｔｏｇｅｔｔｉｎｇｉｎｔｅｒｎａｔｉｏｎａｌａｎｄｏｔｈｅｒｉｎ — ｄｕｓｔｒｉｅｓｒｅｃｏｇｎｉｔｉｏｎ．Ｕｓｉｎｇｔｒａｄｉｔｉｏｎａｌｅｒｒｏｒｓｙｓｔｅｍｒｅｐｒｅｓｅｎｔｓｍｅａｓｕｒｅｍｅｎｔｒｅｓｕｌｔｓ，ｗｈｉｃｈｍａｙｌｅａｄｔｏｔｈｅｄｅ — ｆｅｃｔｓ．Ｉｎｏｒｄｅｒｔｏａｖｏｉｄｔｈｅｄｅｆｅｃｔｓ，ｕｎｃｅｒｔａｉｎｔｙｍｅａｓｕｒｅｍｅｎｔｉｓｅｍｐｌｏｙｅｄｉｎｔｈｅｓｃｉｅｎｔｉｉｃｆｌｉｔｅｒａｔｕｒｅａｔｈｏｍｅａｎｄａｂｒｏａｄ．Ｉｎｔｈｉｓｐａｐｅｒ，ａｃｃｏｒｄｉｎｇｔｏｔｈｅｍｅａｓｕｒｅｍｅｎｔｕｎｃｅｒｔａｉｎｔｙａｎｄｔｈｅｒｅｐｒｅｓｅｎｔａｔｉｏｎｍｅｔｈｏｄｏｆｅｖａｌｕａｔｉｏｎ，ｔｈｒｏｕｇｈｔｈｅａｎａｌｙｓｉｓｏｆ５３２０Ａｍｕｈｉｆｕｎｃｔｉｏｎｅｌｅｃｔｒｉｃａｌｔｅｓｔｅｒｃａｌｉｂｒａｔｏｒｕｎｃｅｒｔａｉｎｔｙｓｏｕｒｃｅｓ，ｔｈｅｍｅａｓｕｒｅｍｅｎｔｕｎ — ｃｅｒｔａｉｎｔｙｏｆ５３２０Ａｍｕｈｉｆｕｎｃｔｉｏｎｅｌｅｃｔｒｉｃａｌｔｅｓｔｅｒｃａｌｉｂｒａｔｏｒｉｓｅｖａｌｕａｔｅｄ．Ｋｅｙｗｏｒｄｓ：ＥｌｅｃｔｒｉｃａｌＳａｆｅｔｙＲｅｇｕｌａｔｉｏｎＴｅｓｔ；ＭｅａｓｕｒｅｍｅｎｔＵｎｃｅｒｔａｉｎｔｙ；Ｅｖａｌｕａｔｉｏｎ

MIC5320 1评估板高性能双150mAμCap ULDO说明书

MIC5320/1 Evaluation BoardHigh Performance Dual 150mAµCap ULDO™ULDO is a trademark of Micrel, Inc.MLF and Micro LeadFrame are registered trademarks of Amkor Technology, Inc.Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • General DescriptionThe MIC5320 and MIC5321 are tiny dual output, ultra low dropout linear regulators. The MIC5320 regulator provides two independent enable pins, to disable each output separately. The MIC5321 regulator provides a single enable pin for both outputs as well as a bypass pin to reduce the output voltage noise. The MIC5320/1 provides two high performance 150mA LDOs in a tiny 6 pin 1.6mm x 1.6mm Thin MLF ® package.The MIC5320/1 dual Ultra Low Dropout (ULDO™) linear regulator is easy to use. A small output capacitance of only 1µF for each of the outputs is required. A bypass capacitor of 0.01µF is included on the evaluation board for the MIC5321 to reduce the output voltage noise and improve the Power Supply Rejection Ratio (PSRR).An input capacitor may be required when the power supply is more than 4-inches away from the device. The evaluation board includes an input capacitor of 10µF to compensate for long inductive test leads.RequirementsThe MIC5320/1 evaluation board requires an input power source that is able to deliver at least 300mA at a voltage within the range of 2.3V to 5.5V. The output load can be either active or passive.PrecautionsThe evaluation board does not have reverse polarity protection. Applying a negative voltage to the V IN terminal may damage the device.The evaluation board is tailored for a Li-Ion range input supply voltage. It should not exceed 5.5V on the input.Getting Started1. Connect an external supply to V IN . Apply thedesired input voltage to the V IN (J1) and ground terminal (J2) of the evaluation board, paying careful attention to polarity and supply voltage (2.3V ≤ V IN ≤ 5.5V). An ammeter may be placed between the input supply and the V IN terminal to the evaluation board to accurately monitor the input current. The ammeter and/or power lead resistance can reduce the voltage supplied to the input so monitor the supply voltage at the V IN terminal.2. Enable/Disable the MIC5320. The evaluationboard is set up for “Default Enable” on both outputs with a 10k pull up resistor on each of the enable pins (EN1 and EN2) to V IN . To disable an output, simply jumper the EN terminal (J7 for LDO1, J3 for LDO2) to the GND terminal (J2 or J5). The enable pins must be either pulled high or low for proper operation. Removing the pull up resistors and leaving the pins floating will cause the regulators to operate in an indeterminate state . The MIC5321 has a single enable pin (J7) to control both outputs of the regulator. 3. Connect the loads to the V OUT terminals (J4 forLDO1, J6 for LDO2) and ground terminal (J5). The load can be either a passive (resistor) or active (electronic load). Be sure to monitor the output voltage at the V OUT (J4 and J6) terminals.Ordering InformationPart Number DescriptionMIC5320-XXYMT EV Evaluation board with the 150mA DualULDO™ device MIC5321-XXYMT EVEvaluation board with the 150mA DualULDO™ device with bypassEvaluation Board SchematicU1MIC5320/1-xxYMTJ1VINJ3EN2/BYPJ7EN1J2GND J4VOUT1J5GNDJ6VOUT2Bill of Materials MIC5320-XXYMTItem Part Number Manufacturer Description Qty C1 C1608X5R0J106M TDK (1)Capacitor, 10µF Ceramic, 6.3V, X5R, Size 0603 1 C2 OPEN Do not populateC3, C4 C1608X5R0J105M TDK (1)Capacitor, 1µF Ceramic, 6.3V, X5R, Size 06032 R1, R2 CRCW06031002FKEYE3Vishay (2) Resistor, 10k Ω, 1%, 1/16W, Size 0603 2U1MIC5320-XXYMTMicrel (3)UCAP LDO, Dual 150mA, Size 1.6mm x 1.6mm Thin MLF ®1Bill of Materials MIC5321-XXYMTItem Part Number Manufacturer Description Qty C1 C1608X5R0J106M TDK (1)Capacitor, 10µF Ceramic, 6.3V, X5R, Size 0603 1 C2 VJ0603Y103KXQ Vishay (2) Capacitor, 0.01µF Ceramic, 10V, X7R, Size 0603 1 C3, C4 C1608X5R0J105MTDK (1) Capacitor, 1µF Ceramic, 6.3V, X5R, Size 0603 2 R1OPENDo not populateR2 CRCW06031002FKEYE3 Vishay (2) Resistor, 10k Ω, 1%, 1/16W, Size 0603 1U1 MIC5321-XXYMT Micrel (3)UCAP LDO, Dual 150mA, Size 1.6mm x 1.6mm Thin MLF ®1Notes:1. TDK: 2. Vishay: 3.Micrel, Inc.: PCB Layout RecommendationsTop LayerBottom Layer。

常用的AD芯片

常用的A/D芯片1. AD公司AD/DA器件AD公司生产的各种模数转换器(ADC)和数模转换器(DAC)(统称数据转换器)一直保持市场领导地位，包括高速、高精度数据转换器和目前流行的微转换器系统（MicroConvertersTM )。

1.1带信号调理、1mW功耗、双通道16位AD转换器：AD7705AD7705是AD公司出品的适用于低频测量仪器的AD转换器。

它能将从传感器接收到的很弱的输入信号直接转换成串行数字信号输出，而无需外部仪表放大器。

采用Σ-Δ的ADC，实现16位无误码的良好性能，片内可编程放大器可设置输入信号增益。

通过片内控制寄存器调整内部数字滤波器的关闭时间和更新速率，可设置数字滤波器的第一个凹口。

在+3V电源和1MHz主时钟时， AD7705功耗仅是1mW。

AD7705是基于微控制器（MCU）、数字信号处理器（DSP）系统的理想电路，能够进一步节省成本、缩小体积、减小系统的复杂性。

应用于微处理器（MCU）、数字信号处理（DSP）系统，手持式仪器，分布式数据采集系统。

1.2 3V/5V CMOS信号调节AD转换器：AD7714AD7714是一个完整的用于低频测量应用场合的模拟前端，用于直接从传感器接收小信号并输出串行数字量。

它使用Σ-Δ转换技术实现高达24位精度的代码而不会丢失。

输入信号加至位于模拟调制器前端的专用可编程增益放大器。

调制器的输出经片内数字滤波器进行处理。

数字滤波器的第一次陷波通过片内控制寄存器来编程，此寄存器可以调节滤波的截止时间和建立时间。

AD7714有3个差分模拟输入（也可以是5个伪差分模拟输入）和一个差分基准输入。

单电源工作（+3V或+5V）。

因此，AD7714能够为含有多达5个通道的系统进行所有的信号调节和转换。

AD7714很适合于灵敏的基于微控制器或DSP的系统，它的串行接口可进行3线操作，通过串行端口可用软件设置增益、信号极性和通道选择。

AD7714具有自校准、系统和背景校准选择，也允许用户读写片内校准寄存器。

ADL5530中文资料

Rev. 0 | Page 2 of 12
元器件交易网
ADL5530
SPECIFICATIONS
VPOS = 5 V and TA = 25°C, unless otherwise noted.
Table 1.
Parameter
Conditions
OVERALL FUNCTION (See Table 2)
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700

Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
Frequency Range1
Gain (S21)
Input Return Loss (S11)
Output Return Loss (S22)
Reverse Isolation (S12)
FREQUENCY = 70 MHz
Gain
vs. Temperature
−40°C ≤ TA ≤ +85°C
The ADL5530 is fabricated on a GaAs pHEMPT process. The device is packaged in a 3 mm × 2 mm LFCSP that uses an exposed paddle for excellent thermal impedance. It operates from −40°C to +85°C. A fully populated evaluation board is also available.

ANALOG DEVICES ADL5320 说明书

400 MHz to 2700 MHzRF Driver AmplifierADL5320 Rev. 0Information furnished by Analog Devices is believed to be accurate and reliable. However, noresponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners. O ne Technology Way, P.O. Box 9106, Norwood, MA 02062−9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.FEATURESOperation: 400 MHz to 2700 MHz Gain of 17 dB at 880 MHzOIP3 of 45 dBm at 880 MHzP1dB of 25.4 dBm at 880 MHzNoise figure: 4 dB at 880 MHz Power supply: 5 VPower supply current: 104 mA typical Internal active biasingThermally efficient SOT-89 package ESD rating of ±4 kV (Class 3A) FUNCTIONAL BLOCK DIAGRAMIN OUT584Figure 1.GENERAL DESCRIPTIONThe ADL5320 is a broadband, linear driver RF amplifier that operates at frequencies from 400 MHz to 2700 MHz. The device can be used in a wide variety of wired and wireless applications, including ISM, WLL, PCS, GSM, CDMA, and W-CDMA.The ADL5320 operates with a 5 V supply voltage and a supply current of 104 mA. The ADL5320 is fabricated on a GaAs HBT process. The device is packaged in a low cost SOT-89 that uses an exposed paddle for excellent thermal impedance. It operates from −40°C to+85°C, and a fully populated evaluation board is available.ADL5320Rev. 0 | Page 2 of 16TABLE OF CONTENTSFeatures .............................................................................................. 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Typical Scattering Parameters ..................................................... 4 Absolute Maximum Ratings ............................................................ 5 ESD Caution .................................................................................. 5 Pin Configuration and Function Descriptions .. (6)Typical Performance Characteristics ..............................................7 Basic Layout Connections ............................................................. 11 Soldering Information and Recommended PCB LandPattern .......................................................................................... 11 Matching Procedure ................................................................... 12 W-CDMA ACPR Performance ................................................ 13 Evaluation Board ............................................................................ 14 Outline Dimensions ....................................................................... 16 Ordering Guide .. (16)REVISION HISTORY2/08—Revision 0: Initial VersionADL5320Rev. 0 | Page 3 of 16SPECIFICATIONSVSUP = 5 V and T A = 25°C, unless otherwise noted. Table 1.ParameterConditions Min Typ Max Unit OVERALL FUNCTION Frequency Range 400 2700 MHz FREQUENCY = 880 MHzGain 116.3 16.9 17.5 dB vs. Frequency ±50 MHz ±0.3 dB vs. Temperature −40°C ≤ T A ≤ +85°C ±0.6 dB vs. Supply4.75 V to5.25 V ±0.1 dB Output 1 dB Compression Point 25.4 dBm Output Third-Order Intercept ∆f = 1 MHz, P OUT = 10 dBm per tone 45 dBm Noise Figure4.1 dB FREQUENCY = 2140 MHzGain 112.4 13.2 14.0 dB vs. Frequency ±50 MHz ±0.33 dB vs. Temperature −40°C ≤ T A ≤ +85°C ±0.8 dB vs. Supply4.75 V to5.25 V ±0.06 dB Output 1 dB Compression Point 25.7 dBm Output Third-Order Intercept ∆f = 1 MHz, P OUT = 10 dBm per tone 42 dBm Noise Figure4.4 dB FREQUENCY = 2600 MHzGain 111.5 12.5 13.4 dB vs. Frequency ±100 MHz ±0.6 dB vs. Temperature −40°C ≤ T A ≤ +85°C ±1.1 dB vs. Supply4.75 V to5.25 V ±0.1 dB Output 1 dB Compression Point 27.4 dBm Output Third-Order Intercept ∆f = 1 MHz, P OUT = 10 dBm per tone 37 dBm Noise Figure 5.1 dB POWER INTERFACE Pin RF OUT Supply Voltage 4.5 5 5.5 V Supply Current 104 124 mA vs. Temperature −40°C ≤ T A ≤ +85°C ±6.0 mA Power DissipationVSUP = 5 V 520 mW1Guaranteed maximum and minimum specified limits on this parameter are based on 6 sigma calculations.ADL5320Rev. 0 | Page 4 of 16TYPICAL SCATTERING PARAMETERSVSUP = 5 V and T A = 25°C; the effects of the test fixture have been de-embedded up to the pins of the device. Table 2.Freq (MHz) S11 S21 S12 S22Magnitude (dB) Angle (°) Magnitude (dB) Angle (°) Magnitude (dB) Angle (°) Magnitude (dB) Angle (°) 400 −1.51 164.18 14.18 +128.37 −32.37 +6.77 −3.44 160.94 500 −1.38 155.33 14.03 +118.16 −31.75 +1.48 −3.70 156.73 550 −1.42 151.34 13.79 +112.76 −31.68 −3.93 −3.79 154.66 600 −1.46 147.66 13.72 +108.71 −31.46 −4.60 −3.83 152.89 650 −1.46 144.12 13.53 +104.05 −31.56 −6.81 −3.90 151.08 700 −1.50 140.66 13.45 +98.89 −31.13 −9.87 −3.99 149.38 750 −1.56 137.19 13.21 +95.44 −31.12 −11.14 −4.02 147.87 800 −1.61 133.97 13.29 +90.33 −31.00 −13.96 −4.07 146.36 850 −1.66 130.74 13.04 +86.67 −30.60 −14.90 −4.12 144.94 900 −1.72 127.65 13.03 +81.59 −30.72 −17.78 −4.21 143.60 950 −1.85 124.15 12.92 +77.91 −30.31 −20.23 −4.25 142.41 1000 −1.92 120.90 12.93 +73.13 −30.22 −22.21 −4.27 141.31 1050 −2.02 117.54 12.92 +68.80 −29.98 −24.19 −4.32 140.51 1100 −2.20 114.21 12.76 +64.12 −29.80 −28.18 −4.37 139.63 1150 −2.41 110.72 12.97 +59.95 −29.39 −29.56 −4.43 138.68 1200 −2.62 107.22 12.69 +54.62 −29.46 −33.00 −4.42 138.09 1250 −2.87 103.77 12.98 +50.95 −29.03 −37.13 −4.47 137.74 1300 −3.16 99.97 12.87 +44.96 −28.75 −38.18 −4.44 137.08 1350 −3.65 96.51 12.94 +40.47 −28.81 −44.64 −4.45 136.77 1400 −4.09 92.23 12.87 +35.36 −28.26 −46.78 −4.40 136.49 1450 −4.59 88.76 13.04 +30.47 −28.43 −49.56 −4.37 136.43 1500 −5.28 84.62 13.00 +24.40 −28.13 −56.47 −4.29 135.79 1550 −6.09 80.71 12.89 +19.39 −27.96 −59.31 −4.20 135.63 1600 −6.98 77.02 13.13 +14.80 −27.98 −62.71 −4.05 135.39 1650 −8.06 72.69 13.07 +7.27 −27.73 −69.93 −3.88 134.43 1700 −9.38 68.92 13.00 +2.17 −27.49 −73.80 −3.71 133.76 1750 −11.15 66.21 12.97 −3.27 −27.78 −77.79 −3.59 132.94 1800 −13.20 63.18 13.18 −9.57 −27.23 −85.28 −3.29 131.04 1850 −15.83 63.73 13.03 −17.27 −27.36 −89.22 −3.11 129.62 1900 −19.87 71.29 12.84 −22.35 −27.40 −96.30 −2.93 127.46 1950 −24.51 103.69 13.08 −29.10 −27.26 −102.96 −2.69 124.63 2000 −22.66 156.61 12.86 −36.58 −27.33 −109.25 −2.54 122.53 2050 −18.02 171.65 12.88 −43.14 −27.33 −117.37 −2.50 118.78 2100 −14.34 174.52 12.63 −51.83 −27.54 −124.60 −2.35 115.97 2150 −12.10 172.15 12.45 −55.83 −27.77 −132.56 −2.44 112.52 2200 −10.23 166.81 12.65 −67.28 −27.74 −141.32 −2.42 108.19 2250 −8.65 160.58 11.82 −73.99 −28.34 −149.30 −2.43 104.65 2300 −7.90 153.80 11.84 −79.82 −28.62 −161.50 −2.74 100.98 2350 −6.66 145.88 11.55 −91.28 −28.92 −165.89 −2.62 96.52 2400 −6.35 138.01 10.97 −96.39 −29.75 +179.97 −2.94 92.52 2450 −5.77 128.87 10.36 −108.43 −30.13 +170.82 −3.03 88.07 2500 −5.51 118.44 9.65 −110.92 −30.41 +163.00 −3.24 83.25 2550 −5.35 112.21 9.46 −122.10 −32.29 +152.20 −3.41 79.98 2600 −5.15 99.40 7.99 −130.39 −31.60 +138.60 −3.55 73.08 2650 −5.22 92.84 7.70 −132.72 −33.19 +135.12 −3.80 69.85 2700 −5.06 82.21 6.61 −143.64 −33.61 +120.22 −3.93 63.87ADL5320Rev. 0 | Page 5 of 16ABSOLUTE MAXIMUM RATINGSTable 3.Parameter RatingSupply Voltage, VSUP 6.5 V Input Power (50 Ω Impedance) 20 dBm Internal Power Dissipation (Paddle Soldered) 683 mW θJC (Junction to Paddle) 28.5°C/WMaximum Junction Temperature 150°C Operating Temperature Range −40°C to +85°CStorage Temperature Range −65°C to +150°CESD CAUTIONStresses above those listed under Absolute Maximum Ratingsmay cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operationalsection of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.ADL5320Rev. 0 | Page 6 of 16PIN CONFIGURATION AND FUNCTION DESCRIPTIONSRF IN GND RF OUT 123GND ADL5320TOP VIEW (Not to Scale)05840-002(2)Figure 2. Pin ConfigurationTable 4. Pin Function DescriptionsPin No. Mnemonic Description1 RF IN RF Input. Requires a dc blocking capacitor.2 GND Ground. Connect to a low impedance ground plane.3 RF OUT RF Output and Supply Voltage. DC bias is provided to this pin through an inductor that is connected to the external power supply. RF path requires a dc blocking capacitor.Exposed PaddleExpose Paddle. Internally connected to GND. Solder to a low impedance ground plane.ADL5320Rev. 0 | Page 7 of 16TYPICAL PERFORMANCE CHARACTERISTICS5045403530252015105005840-003G A I N , N F (d B ); P 1d B , O I P 3 (d B m )FREQUENCY (MHz)800820840860880900920940960Figure 3. Gain, P1dB, OIP3, and Noise Figure vs. Frequency,800 MHz to 960 MHz19.018.518.017.517.016.516.015.515.014.514.005840-004G A I N (d B )FREQUENCY (MHz)800820840860880900920940960Figure 4. Gain vs. Frequency and Temperature, 800 MHz to 960 MHz –25.0–25.5–26.0–26.5–27.0–27.5–28.0–28.5–29.00–5–10–15–20–25–30–35–4005840-005S 12 (d B )S 11 (d B ) A N D S 22 (d B )FREQUENCY (MHz)7007508008509009501000S12S11S22Figure 5. Input Return Loss (S11), Output Return Loss (S22), and ReverseIsolation (S12) vs. Frequency, 800 MHz to 960 MHz504540353025203029282726252405840-006O I P 3 (d B m )P 1d B (d B m )FREQUENCY (MHz)800820840860880900920940960Figure 6. OIP3 and P1dB vs. Frequency and Temperature,800 MHz to 960 MHz504642383430–2024681012141618202205870-007O I P 3 (d B m )P OUT(dBm)Figure 7. OIP3 vs. P OUT and Frequency, 800 MHz to 960 MHz7.06.56.05.55.04.54.03.53.02.52.005840-008N F (d B )FREQUENCY (MHz)7007508008509009501000Figure 8. Noise Figure vs. Frequency and Temperature, 800 MHz to 960 MHzADL5320Rev. 0 | Page 8 of 1620602080210021202140216021802200222045403530252015105005840-009FREQUENCY (MHz)G A I N , N F (d B ); P 1d B , O I P 3 (d B m )Figure 9. Gain, P1dB, OIP3, and Noise Figure vs. Frequency,2060 MHz to 2200 MHz2060208021002120214021602180220022201615141312111005840-010G A I N (d B )FREQUENCY (MHz)–40°C+85°C+25°C Figure 10. Gain vs. Frequency and Temperature, 2060 MHz to 2200 MHz –23–24–25–26–27–28–290–5–10–15–20–25–30–35–4005840-011S 12 (d B )S 11 (d B ) A N D S 22 (d B )FREQUENCY (MHz)190019502000210020502150220022502300S11S12S22Figure 11. Input Return Loss (S11), Output Return Loss (S22), and ReverseIsolation (S12) vs. Frequency, 2060 MHz to 2200 MHz 45434139373533312929.028.528.027.527.026.526.025.525.024.505840-012O I P 3 (d B M )P 1d B (d B m )FREQUENCY (MHz)206020802100212021402160218022002220Figure 12. OIP3 and P1dB vs. Frequency and Temperature,2060 MHz to 2200 MHz43413937353331–2024681012141618202205870-013O I P 3 (d B m )P OUT (dBm)Figure 13. OIP3 vs. P OUT and Frequency, 2060 MHz to 2200 MHz8.07.57.06.56.05.55.04.54.03.53.02.52.005840-014N F (d B )FREQUENCY (MHz)190019502000205021002150220022502300Figure 14. Noise Figure vs. Frequency and Temperature,2060 MHz to 2200 MHzADL5320Rev. 0 | Page 9 of 1640353025201510505840-015G A I N , N F (d B ); P 1d B , O I P 3 (d B m )FREQUENCY (MHz)25002520254025602580266026802600262026402700Figure 15. Gain, P1dB, OIP3, and Noise Figure vs. Frequency,2500 MHz to 2700 MHz25002550260026502700151413121110905840-016G A I N (d B )FREQUENCY (MHz)–40°C+85°C+25°CFigure 16. Gain vs. Frequency and Temperature, 2500 MHz to 2700 MHz–25.0–25.5–26.0–26.5–27.0–27.5–28.0–28.5–29.0–29.5–30.005840-017S 12 (d B )S 11 (d B ) A N D S 22 (d B )FREQUENCY (MHz)240024502500260025502700265027502800Figure 17. Input Return Loss (S11), Output Return Loss (S22), and ReverseIsolation (S12) vs. Frequency, 2500 MHz to 2700 MHz 25002550260026502700393837363534333231302905840-018O I P 3 (d B m )FREQUENCY (MHz)P1d B (d B m )Figure 18. OIP3 and P1dB vs. Frequency and Temperature,2500 MHz to 2700 MHz46444240383634323005840-019O I P 3 (d B m )P OUT (dBm)–3–11357911131517192123Figure 19. OIP3 vs. P OUT and Frequency, 2500 MHz to 2700 MHz8.07.57.06.56.05.55.04.54.03.53.02.52.005840-020N F (d B )FREQUENCY (MHz)240024502500255026002650270027502800–40°C+25°C+85°CFigure 20. Noise Figure vs. Frequency and Temperature,2500 MHz to 2700 MHzADL5320Rev. 0 | Page 10 of 1618161412108642042.042.843.644.445.246.046.847.605840-021P E R C E N T A G E (%)OIP3 (dBm)Figure 21. OIP3 Distribution at 880 MHz60504030201024.424.825.225.626.026.426.805840-022P E R C E N T A G E (%)P1dB (dBm)Figure 22. P1dB Distribution at 880 MHz3025201510505840-023P E R C E N T A G E (%)GAIN (dB)Figure 23. Gain Distribution at 880 MHz50403020103.80 3.88 3.964.04 4.12 4.20 4.2805840-024P E R C E N T A G E (%)NF (dB)Figure 24. Noise Figure Distribution at 880 MHz1201151101051009590858005840-025S U P P L YC U R R E N T (m A )TEMPERATURE (°C)–40–30–20–1001020304050607080Figure 25. Supply Current vs. Supply Voltage and Temperature (Using880 MHz Matching Components)BASIC LAYOUT CONNECTIONSThe basic connections for operating the ADL5320 are shown in Figure 26.Table 5 lists the required matching components. Capacitors C1, C2, C3, C4, and C7 are Murata GRM155 series (0402 size) and Inductor L1 is a Coilcraft 0603CS series (0603 size). For all frequency bands, the placement of C3 and C7 are critical. From 2300 MHz to 2700 MHz, the placement of C2 is also important. Table 6 lists the recommended component placement for various frequencies.A 5 V dc bias is supplied through L1 which is connected toRF OUT (Pin 3). In addition to C4, 10 nF and 10 μF power supply decoupling capacitors are also required. The typical current consumption for the ADL5320 is 110 mA.RFOUT1SEE TABLE 5 FOR FREQUENCY SPECIFIC COMPONENTS.2SEE TABLE 10 FOR RECOMMENDED COMPONENT SPACING.0 5 8 4 0 -0 2 6Figure 26. Basic Connections SOLDERING INFORMATION AND RECOMMENDED PCB LAND PATTERNFigure 27 shows the recommended land pattern for the ADL5320. To minimize thermal impedance, the exposed paddle on the SOT-89 package underside is soldered down to a ground plane along with Pin 2. If multiple ground layers exist, they should be stitched together using vias. For more information on land pattern design and layout, refer to the Application Note AN-772, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP).584-27Figure 27. Recommended Land PatternTable 5. Recommended Components for Basic ConnectionsFrequency (MHz) C1 (pF) C2 (pF) C3 (pF) C4 (pF) C7 (pF) L1 (nH) 450 to 500 100 100 18 100 6.8 47 800 to 960 47 47 6.8 100 2.2 47 1805 to 1880 22 22 0.5 22 1.5 15 1930 to 1990 22 22 0.5 22 1.5 15 2110 to 2170 22 22 0.5 22 1.5 15 2300 to 2400 12 2.2 1.2 12 1.0 15 2500 to 2700 12 1.0 1.8 12 0.5 15Table 6. Matching Component SpacingFrequency (MHz) λ1 (mils) λ2 (mils) λ3 (mils) λ4 (mils)450 to 500 391 75 364 50800 to 960 200 75 100 3501805 to 2170 300 75 175 2752300 to 2400 225 75 125 1252500 to 2700 142 75 89 75MATCHING PROCEDUREThe ADL5320 is designed to achieve excellent gain and IP3 performance. To achieve this, both input and output matching networks must present specific impedance to the device. The matching components listed in Table 6 were chosen to provide −10 dB input return loss while maximizing OIP3. The load-pull plots (Figure 28, Figure 29, and Figure 30) show the load impedance points on the Smith chart where optimum OIP3, gain, and output power can be achieved. These load impedance values (that is, the impedance that the device sees when looking into the output matching network) are listed in Table 7 and Table 8 for maximum gain and maximum OIP3, respectively. The contours show how each parameter degrades as it is movedaway from the optimum point.From the data shown in Table 7 and Table 8 it becomes clear that maximum gain and maximum OIP3 do not occur at the same impedance. This can also be seen on the load-pull contours in Figure 28 through Figure 30. Thus, output matching generally involves compromising between gain and OIP3. In addition, the load-pull plots demonstrate that the quality of the output impedance match must be compromised to optimize gainand/or OIP3. In most applications where line lengths are short and where the next device in the signal chain presents a low input return loss, compromising on the output match is acceptable.To adjust the output match for operation at a different frequency or if a different trade-off between OIP3, gain,and output impedance is desired, the following procedureis recommended.For example, to optimize the ADL5320 for optimum OIP3 and gain at 700 MHz use the following steps:1.Install the recommended tuning components for a 800 MHzto 960 MHz tuning band, but do not install C3 and C7. 2.Connect the evaluation board to a vector network analyzerso that input and output return loss can be viewed simulta-neously.3.Starting with the recommended values and positions forC3 and C7, adjust the positions of these capacitors alongthe transmission line until the return loss and gain areacceptable. Push-down capacitors that are mounted onsmall sticks can be used in this case as an alternative tosoldering. If moving the component positions does notyield satisfactory results, then the values of C3 and C7should be increased or decreased (most likely increasedin this case as the user is tuning for a lower frequency).Repeat the process.4.Once the desired gain and return loss are realized, OIP3should be measured. Most likely, it will be necessary togo back and forth between return loss/gain and OIP3measurements (probably compromising most on outputreturn loss) until an acceptable compromise is achieved.584-28 Figure 28. Load-Pull Contours, 880 MHz584-29 Figure 29. Load-Pull Contours, 2140 MHz584-30 Figure 30. Load-Pull Contours, 2600 MHzThe ADL5320 achieves an ACPR of −82 dBc at 0 dBm output, at which point device noise and not distortion is beginning to dominate the power in the adjacent channels. At an output power of 10 dBm, ACPR is still very low at −70 dBc making the device particularly suitable for PA driver applications.Table 7. Load Conditions for Gain MAXFrequency (MHz) ΓLoad(Magnitude) ΓLoad (°) Gain MAX (dB) 880 0.5147 159.88 17.76 2140 0.6611 134.40 13.78 26000.5835133.8012.36–30–40–50–60–70–80–9005840-031A C P R @ 5M H z C A R R IE R OF F S E T (d B c )P OUT (dBm)–20–15–10–505101520Table 8. Load Conditions for IP3 MAXFrequency (MHz) ΓLoad(Magnitude) ΓLoad (°) IP3 MAX (dBm) 880 0.4156 −138.22 46.29 2140 0.5035 +110.27 42.72 2600 0.4595 +102.48 43.01W-CDMA ACPR PERFORMANCEFigure 31 shows a plot of adjacent channel power ratio (ACPR) vs. P OUT for the ADL5320. The signal type being used is a single W-CDMA carrier (Test Model 1−64) at 2140 MHz. This signal is generated by a very low ACPR source. ACPR is measured at the output by a high dynamic range spectrum analyzer, which incorporates an instrument noise correction function. Figure 31. ACPR vs. P OUT , Single Carrier W-CDMA (Test Model 1−64) at 2140MHz Evaluation BoardEVALUATION BOARDThe schematic of the ADL5320 evaluation board is shown in Figure 32. This evaluation board uses 25 mil wide traces and is made from FR4 material. The evaluation board comes tuned for operation in the 1805 MHz to 2140 MHz tuning band. Tuning options for other frequency bands are also provided in Table 9. The recommended placement for these components is provided in Table 10. The inputs and outputs should be ac-coupled with appropriately sized capacitors. DC bias is provided to the amplifier via an inductor connected to the RF OUT pin. A bias voltage of 5 V is recommended.RF OUT05840-032Figure 32. Evaluation Board, 1805 MHz to 2170 MHz10uF C30.5pFC71.5pFC122pFC222pF10nF22pF15nH05840-033Figure 33. Evaluation Board Layout and Default Component Placement forOperation from 1805 MHz to 2170 MHzTable 9. Evaluation Board Configuration OptionsComponent Function 450 MHz to 500 MHz 800 MHz to 960 MHz 1805 MHz to 2170 MHz (DefaultConfiguration) 2300 MHz to 2400 MHz2500 MHz to 2700 MHzC1, C2AC coupling capacitors0402, 100 pF 0402, 47 pF 0402, 22pF C1= 0402 12 pF C2 = 0402 2.2 pF C1 = 0402 12 pF C2 = 0402 1.0 pF C4, C5, C6 Power supply bypassing capacitors C4 = 0603 100 pFC5 = 0603 10 nF C6 = 1206 10 μFC4 = 0603 100 pF C5 = 0603 10 nF C6 = 1206 10 μF C4 = 0402 22pF C5 = 0603 10 nF C6 = 1206 10 μF C4 = 0603 12 pF C5 = 0603 10 nF C6 = 1206 10 μF C4 = 0603 12 pF C5 = 0603 10 nF C6 = 1206 10 μF L1 DC bias inductor0603, 47 nH0603, 47 nH 0603, 15 nH 0603, 15 nH 0603, 15 nH C3, C7 Tuning capacitors C3 = 0402 18 pFC7 = 0402 6.8 pFC3 = 0402 6.8 pF C7 = 0402 2.2 pF C3 = 0402 0.5 pF C7 = 0402 1.5 pF C3 = 0402 1.2 pF C7 = 0402 1.0 pF C3 = 0402 1.8 pF C7 = 0402 0.5 pF R1R1 = 0402 0 Ω R1 = 0402 0 Ω VSUP, GND Power supply connections VSUP red testloop, GND black testloopVSUP red testloop, GND black test loopVSUP red test loop, GND black test loopVSUP red test loop, GND black test loopVSUP red test loop, GND black test loopTable 10. Recommended Component Spacing on Evaluation BoardFrequency (MHz) λ1 (mils) λ2 (mils) λ3 (mils) λ4 (mils) 450 to 500 391 75 364 50 800 to 960 200 75 100 350 1805 to 2170 300 75 175 275 2300 to 2400 225 75 125 125 2500 to 270014275897510uFC3 18pFC7 6.8pFC1 100pFC2100pF10nF100pF47nH584-37Figure 34. Evaluation Board Layout and Component Placement 450 MHz to 500 MHz Operation10uFC3 6.8pF C7 2.2pFC1 47pFC210nF100pF584-34Figure 35. Evaluation Board Layout and Component Placement 800 MHz to 960 MHz Operation10uF12pFC3C1C22.2pF10nF12pF15nH1.2pF C71pFR1 0Ω584-35Figure 36. Evaluation Board Layout and Component Placement 2300 MHz to 2400 MHz Operation10uFC31.8pFC70.5pFC1C21.0pF10nF12pF15nHR1 0Ω584-36Figure 37. Evaluation Board Layout and Component Placement 2500 MHz to 2700 MHz Operation040407-A*COMPLIANT TO JEDEC STANDARDS TO-243 WITHEXCEPTION TO DIMENSIONS INDICATED BY AN ASTERISK.OUTLINE DIMENSIONSFigure 38. 3−Lead Small Outline Transistor Package [SOT-89](RK-3)Dimensions shown in millimetersORDERING GUIDEModelTemperature Range Package Description Package Option ADL5320ARKZ-R71−40°C to +85°C 3-Lead SOT-89, 7“ Tape and Reel RK-3 ADL5320-EVALZ 1Evaluation Board1Z = RoHS Compliant Part.©2008 Analog Devices, Inc. All rights reserved. Trademarks andregistered trademarks are the property of their respective owners. D05840-0-2/08(0)。

ADISEVALZ;中文规格书,Datasheet资料

i Sensor™ PC Evaluation System Preliminary Technical Data ADISEVALRev. Pr.CInformation furnished by Analog Devices is believed to be accurate and reliable.However, no responsibility is assumed by Analog Devices for its use, nor for anyinfringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: Fax: 781.326.8703© 2008 Analog Devices, Inc. All rights reserved.GENERAL DESCRIPTIONThe ADISEV AL is a PC-based evaluation system for many of the i Sensor™ products. It comes with a Parallel Interface Board, parallel interface cable, 2 12-pin ribbon cables, and the i Sensor™ CD, which contains product documentation and evaluation software.GETTING STARTEDGetting started with this system requires four simple steps.1.Connect J2 of the Parallel Interface Board (see Figure 1) tothe appropriate power supply, using Table 1. For simplicity, connect pin 1 to pin 4 and connect pin 2 to pin 3. Set thevoltage on the power supply per Table 2. Turn power off.2.Install the ADIS16XXX/PCBZ evaluation board on theParallel Interface Board, using 2mm machine screws andthe two 12-pin ribbon cables, as shown in Figure 2. Make sure that these cables are aligned correctly on each header before applying power. Hook up the system to a PC using the parallel cable.3.Locate the product-specific evaluation software on thei Sensor™ CD or download it from:/isensor-evaluation. See Table 3 for a listof products supported by each installation package.4.Unpack the zip file and double click on the setup.exe file.Follow the prompts to install the software.5.Go to the created directory. In most cases, this will be asubdirectoy under “C:\ProgramFiles\Analog DevicesiSensors\.” Double-click on the giveio.exe. Follow theprompts to install this driver, which enables the parallelport communications in the PC.6.Double click on the ADIS*.exe file to start the software.7.Click on “Interface” and select, “Parallel.” Enter theaddress of the parallel port on the PC and click the “OK”button. The parallel port address can be found under theDevice Manager in Windows XP. The software contains help files that describe each function ofthe software. The right button on the mouse has the ability tospeed up changes when the Pointer is placed over titles, graphaxes and waveform data.See Figure 4 (ADIS16003, ADIS16006), Figure 5 (ADIS16080,ADIS16100), Figure 6 (ADIS16201), Figure 7 (ADIS16203),Figure 8 (ADIS16209) and Figure 9 (ADIS16250) for basicsoftware assistance.Table 1. Power Supply Hook-up – J2Pin Number Function1 Digital I/O Power Supply2 Common3 Common4 Sensor Power SupplyNOTE: No reverse polarity protection provided.Table 2. Power Supply VoltagesEvaluation Board Power Supply VoltageADIS16003/PCBZ +3.0 to +5.25VADIS16006/PCBZ +3.0 to +5.25VADIS16060/PCBZ +4.75 to +5.25VADIS16080/PCBZ +4.75 to +5.25VADIS16100/PCB +4.75 to +5.25VADIS1620x/PCBZ +3.0 to +3.6VADIS1625x/PCBZ +4.75 to +5.25VTable 3. Evaluation SoftwareInstallation Package Filename Supported Products003ES(x).zip ADIS16003ADIS16006ADIS16060 ADIS16080ADIS16100201ES(x).zip ADIS16201203ES(x).zip ADIS16203204ES(x).zip ADIS16024209ES(x).zip ADIS16209250ES(x).zip ADIS16250ADIS16251ADIS16255ORDERING GUIDEModelP ackageDescriptionADISEVAL i Sensor™ PC Evaluation SystemADISEVALPin 1Figure 1 – i Sensor™ PC Interface Board LayoutRev. PrC | Page 2 of 10Preliminary Technical DataADISEVALRev. PrC | Page 3 of 1112-pin ribbon cables are installed hereFigure 2 – i Sensor ™ PC Interface Board with ADIS16201/PCBZ installedADISEVALFigure 3 – i Sensor™PC Evaluation Board SchematicRev. PrC | Page 4 of 10Preliminary Technical DataADISEVALRev. PrC | Page 5 of 11FIGURE FLAG NOTES:1. Set the Device type to ADIS16003 or ADIS16006.2. Set the axis to measure. Test function exercises a self-test during a single sweep on the screen.3. Plot and log data to files.4. Set up data logging parameters.5. Right click over Y-Axis to adjust scale and offset of the plot.Figure 4. ADIS16003 and ADIS16006 Evaluation SoftwareADISEVALRev. PrC | Page 6 of 10FIGURE FLAG NOTES:1. Set the Device type to ADIS16060, ADIS16080 or ADIS16100.2. Set the output channel to measure. Test function exercises a self-test during a single sweep on the screen.3. Plot and log data to files.4. Set up data logging parameters.5. Right click over Y-Axis to adjust scale and offset of the plot.Figure 5. ADIS16060, ADIS16080 and ADIS16100 Evaluation Software ScreenPreliminary Technical DataADISEVALRev. PrC | Page 7 of 111234FIGURE FLAG NOTES:1. Perform a single read of the ADIS16201’s output data2. Start and stop continuous reading of the ADIS16201’s output data. The acquisition loop delay time provides rough control oversample times. Please note that this data will not have a high degree of coherence. 3. Select the file data logging option.4. Configure the ADIS16201’s internal sample rate and filter response.Figure 6. ADIS16201 Evaluation SoftwareADISEVALRev. PrC | Page 8 of 10FIGURE FLAG NOTES:1. Perform a single read of the ADIS16203’s output data2. Start and stop continuous reading of the ADIS16203’s output data. The acquisition loop delay time provides rough control oversample times. Please note that this data will not have a high degree of coherence. 3. Select the file data logging option.4. Configure the ADIS16203’s internal sample rate and filter response.5. Graphical orientation. Note that for incline angle - 0°, the corner dot would be in the lower, left hand corner.6. Alarm monitoring. Note that these turn red on alarm condition. They maintain their status until the Reset button is pressed,even if the error condition has cleared.Figure 7. ADIS16203 Evaluation SoftwarePreliminary Technical DataADISEVALRev. PrC | Page 9 of 11124536FIGURE FLAG NOTES:1. Perform a single read of the ADIS16209’s output data2. XINCL_OUT and YINCL_OUT are horizontal incline outputs. ROTATION is the vertical-oriented rotational positionmeasurement. This requires the X and Y axes to be in the vertical plane, with respect to the earth’s surface. 3. This graph displays the vertical oriented, rotational position. This requires the X and Y axes to be in the vertical plane, withrespect to the earth’s surface. 4. Start and stop continuous reading of the ADIS16209’s output data. The acquisition loop time provides rough control oversample times. Please note that this data will not have a high degree of coherence. 5. The acquisition loop time provides rough control over sample times. Please note that this data will not have a high degree ofcoherence.ADISEVALRev. PrC | Page 10 of 106. Configure the ADIS16209’s internal sample rate and filter response.Figure 8. ADIS16209 Evaluation Software4FIGURE FLAG NOTES:1. Perform a single read of the ADIS16250’s output data2. Start and stop continuous reading of the ADIS16250’s output data. The acquisition loop delay time provides rough control oversample times. Please note that this data will not have a high degree of coherence. 3. Select the file data logging option.4. Configure the ADIS16250’s internal sample rate and filter response.5. Set the measurement range from the three options available in the ADIS16250.6. Exercise the user calibration functions.7. Note, for the ADIS16251, divide the data by a factor of 4. The ADIS16255 data requires no scaling.Figure 9. ADIS16250 Evaluation Software©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. EB06335-0-7/08(P rC)分销商库存信息: ANALOG-DEVICES ADISEVALZ。

万讯5320e IP电话快速参考指南说明书

MITEL 5320e IP PHONE QUICK REFERENCE GUIDEDocument Part Number 835.3289-1, August 2013Mitel ® 5000 Communications Platform (CP)This guide provides information for frequently used features. For more information about these and other features, refer to the user guide. For voice mail information, refer to the voice mail user guide for your system.76543218 DescriptionHandset The handset is hearing aid compatible (HAC). If you are using a headset or if you are in Handsfree Mode, you do not need to use the handset.Programmable Buttons Provide 11 self-labeling, programmable buttons.Display Provides a 160 x 320 (pixels) high-resolution viewing area for selecting and using features and identifying callers.Ring/Message IndicatorFlashes or stays lit to indicate call, message, and feature activity.Feature Buttons Provide quick access to commonly used features. See “Feature Buttons” on page 2 for descriptions.Dialpad Buttons Use the dialpad buttons to dial phone numbers, enter feature codes, and to enter characters when using features that require text input.Navigation Buttons Use the navigation buttons to page through Display screens.External SpeakerProvides audio for handsfree calls and background music.1234Indicator Signals DescriptionRapidly flashing You have an incoming call.Slowly flashing You have a waiting message or callback message.On You are on a call or using a feature.OffYour IP phone is idle.5678Mitel 5320e Quick Reference Guide (Mitel 5000 Communications Platform)Feature ButtonsFeature buttons provide quick access to commonly used features. See the following table for descriptions.Commonly Used Feature CodesMost of the following feature codes work when your IP phone is idle. However, if you are on an active call or if the IP phone is off-hook, you may need to press(Special) to activate the feature before you enter the feature code.If you make a mistake when entering numbers or characters, you can press (Hold) to move the cursor to the left and delete the characters entered, or you can press * to cancel the feature.Contact your system administrator for more information about system features.Button Action(Up) (Down)Provides volume control.Scrolls through feature options. (Speaker)Activates Handsfree Mode.Activates features.(Mute)Mutes the microphone during a call.(Applications)Activates the Applications menu to use the conference unit or cordless devices, program various phone settings, and enable Clean Mode. (Special)Activates features while on a call.The (Special) button does not cancel features. To cancel features, press the Star button (*).(Redial)Calls the last external number dialed. You cannot redial internal numbers.(Hold)Places the current call on hold.Left/Backspace when entering dialpad characters.(Transfer)Transfers the current call. Right/Forward when entering dialpad characters.(Message)Allows you to view station messages.Toggles between Alpha Mode and Numeric Mode.FeatureCode ACD Agent – Log In/Out328Automatic IC Call Access – On/Off 361Automatic Trunk Call Access – On/Off 360Background Music – On/Off 313Call Forward – All Calls 355Call Logging 333Conference 5Default Station 394Directory307Display Time And Date 300Do-Not-Disturb – On/Off372Dynamic Extension Express – On/Off 364Dynamic Extension Express Handoff 388Handsfree – On/Off 319Headset – On/Off 317Hold – Individual 336Hold – System 335Hot Desk On/Off348Hunt Group – Remove/Replace 324Message – Cancel Left Message 366Message – Delete Message 368Message – Leave Message 367Message – View Messages Menu 365Microphone Mute – On/Off 314Page Receive – On/Off 325Program Buttons397Program Station Passcode 392Programmable Buttons – Default 395Queue (Callback) Request 6Record-A-Call385Reverse Transfer (Call Pick-Up)4Ring Tone Selection 398Station Speed Dial382Station Speed Dial – Programming 383Switch Keymap399System Forward – On/Off 354System Speed Dial 381View Button Assignments396Mitel 5320e Quick Reference Guide (Mitel 5000 Communications Platform)Answering CallsLift the handset, or press (Speaker) to answer a call while using a headset or to answer a call in Handsfree Mode.Placing Emergency CallsDial the emergency number (911 U.S. or999/112 Europe). The system immediately places theemergency call as soon as you dial the number, even if you do not select an outside line.Placing Internal (Intercom) CallsWith or without the handset lifted, dial the extensionnumber. If you enter incorrect digits, you can press(Hold) to move the cursor backward, deleting the last digits entered. If you are using Handsfree Mode, listen for the double tone, and then begin to speak.Placing External CallsPress the Outgoing button, an unlitCall button, orenter the Outgoing Call access code (8 is the defaultcode), and then dial the number.Redialing External NumbersWith or without the handset lifted, press the (Redial). The system automatically selects a line and dials the number.Transferring Calls to Other Extensions1. While on the call, press(Transfer), and thenenter the extension number.2. Do one of the following:•Wait for an answer, announce the call, and then hang up. If the extension is unavailable, press the flashing IC or Call button to return to the caller.•Hang up to transfer the call and disconnect the call from your IP phone.Forwarding Calls1. Press the Fwd button, and then enter the featurecode, if applicable. ENTER FORWARD DEST appears. 2. Enter the extension number, or press the Outgoingbutton or enter the Outgoing Call access code (8 is the default code), and then dial the telephone number.Placing Ad Hoc Conference Calls1. While on the first call, press the Conf button to placethe call on hold. CALL NEXT PARTY TO CNF appears.2. Place a call to the next conference party. For externalcalls, press the Outgoing button or enter theOutgoing Call access code (8 is the default code), and then dial the number.3. After the party answers, announce the conference,and then press the Conf button to place the call on hold. If necessary, repeat this step to add the remaining conference party.4. Press the Conf button again to start the conference.CNF IN PROGRESS appears.Viewing and Responding to Messages 1. With the handset on-hook, press (Message).Messages are displayed as first in/first out. If there ismore than one message, you can repeatedly press(Message) to scroll through the messages. 2. When the desired message is displayed, press #, orlift the handset for privacy, and then press # torespond. (If your handset is off-hook and you press[Message], you automatically place a call to the party or message center who left the message.)Using Do-Not-Disturb1. Press the DND button, and then do one of thefollowing:•Press (Up) or (Down) to scroll throughthe messages.•Enter the two-digit number for the DND message.2. If applicable , enter the additional text for the DNDdescription. 3. Press(Speaker), or lift and replace the handset.Placing a Page Announcement1. Press 7.2. Enter the page-zone number (0 to 9).3. After the tone, make your announcement, and thenhang up.。