计算机组成原理计算题设计题

1.IEEE 754 format of X is (41360000)16, what is its decimal value?

将十六进制数展开，可得二进制数格式为：

0 100 0001 0 011 0110 0000 0000 0000 0000

指数e=阶码－127=10000010－01111111= 00000011 =（3）10

包括隐藏位1的尾数1.M = 1.011 0110 0000 0000 0000 0000 = 1.011011

于是有：X = (-1)s * 1.M * 2e = +(1.011011)2 * 23 = + (1011.011)2= (11.375)10

2.Let the carry bits of an adder are C4, C3, C2, C1. C0 is the carry from the low bit. Please give the logic expressions of C4, C3, C2, C1 in ripple carry mode and carry look ahead mode respectively.

(1)串行进位

G1 = A1B1 , P1 = A1 ⊕ B1

G2 = A2B2 , P2 = A2 ⊕ B2

G3 = A3B3 , P3 = A3 ⊕ B3

G4 = A4B4 , P4 = A4 ⊕ B4

C1 = G1 + P1P0

C2 = G2 + P2C1

C3 = G3 + P3C2

C4 = G4 + P4C3

(2)并行进位

C1 = G1 + P1C0

C2 = G2 + P2G1 + P2P1C0

C3 = G3 + P3G2 + P3P2G1 + P3P2P1C0

G4 = G4 + P4G3 + P4G3G2 + P4P3P2G1 + P4P3P2P1C0

3.Suppose a computer with a clock frequency of 100 MHz as four types of instructions, and the frequency of usage and the CPI for each of them are given in table.

(1)Find the MIPS of the computer and the T (CPU time) required to run a program of 107 instructions.

(2) Combining comparing and branch instructions together so that compare instructions can be replaced and removed. Suppose each compare instruction was originally used with one branch instruction, and now each branch instruction is changed to a compare&branch instruction. Also suppose that the new proposal would decrease the clock frequency by 5%, because the new compare&branch instruction needs more time to execute. Find the new CPIave, MIPS, and T.

CPIave = (0.4*2+0.*4+0.22*3)/0.92 = 2.9

MIPS = f(MHz)/CPIave = (100*0.95)/2.9 = 32.76

T = IC ＊CPIave/f(Hz) = （0.92*10000000）*2.9/（0.95*100*1000000）= 0.28s

4 CPU has 16 address bus lines (A15-A0), 8 data bus lines (D7-D0), R/W (high

level represents Read, while low level represents Write), MREQ control line for accessing memory (low level represents accessible).

Memory space allocation: The minimal 8K are used for system program, which is composed of Read Only Memory chip; the following 24K are used for user program; the last 2K are used for system working.

Now we have: EPROM 8K * 8 (contains CS control line only);

SRAM 16K*1, 2K*8, 4K*8, 8K*8;

Decoder 74LS138;

and other logic gates

Questions:

(1) Select appropriate chips to form the required memory space. Which chips

are needed? How many chips are needed? Descript the corresponding data bus length, address bus length and control bus line.

(2) Descript the address distribution of memory.

(3) Descript select chip logic functions (片选逻辑函数) of each chip.

(4) Descript the connection way among CPU, memory chips and 74LS138.

解：（1）根据给定条件，选用

EPROM：8K×8位芯片1片，其地址线13根，数据线8根，片选控制信号CS，无读写控制信号。

SRAM：8K×8位芯片3片，地址线13根，数据线8根，片选控制线号CS，读写控制线号R/W；2K×8位芯片1片，地址线11根，数据线8根，片选控制线号CS，读写控制线号R/W。

（2）A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

CS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

8K 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1

CS1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0

8K 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1

CS2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0

8K 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1

CS3 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0

8K 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

CS4 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0

2K 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1-

(3) CS0 = (A15’*A14’*A13’)’ = Y0’

CS1 = (A15’*A14’*A13)’ = Y1’

CS2 = (A15’*A14*A13’)’ = Y2’

CS3 = (A15’*A14*A13)’ = Y3’

CS4 = (((A15*A14*A13)’)’*(A12*A11))’ =( (Y1’)’*A12*A11)’