IC datasheet pdf-CC1021,pdf(Single-Chip Low Power RF Transceiver for Narrow band Systems)

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IC datasheet pdf-MX25L1005C pdf,datasheet

MX25L1005C DATASHEET1M-BIT [x 1] CMOS SERIAL FLASH FEATURESGENERAL• Serial Peripheral Interface compatible -- Mode 0 and Mode 3• 1,048,576 x 1 bit structure• 32 Equal Sectors with 4K byte each- Any Sector can be erased individually• 2 Equal Blocks with 64K byte each- Any Block can be erased individually• Single Power Supply Operation- 2.7 to 3.6 volt for read, erase, and program operations• Latch-up protected to 100mA from -1V to Vcc +1VPERFORMANCE• High Performance- Fast access time: 85MHz serial clock- Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page)- Fast erase time: 60ms(typ.)/sector (4K-byte per sector) ; 1s(typ.) and 2s(max.)/block (64K-byte per block)• Low Power Consumption- Low active read current: 12mA(max.) at 85MHz and 4mA(max.) at 33MHz- Low active programming current: 15mA (max.)- Low active erase current: 15mA (max.)- Low standby current: 10uA (max.)• Minimum 100,000 erase/program cycles• 20 years data retentionSOFTWARE FEATURES• I nput Data Format- 1-byte Command code• Block Lock protection- The BP0~BP1 status bit defines the size of the area to be software protected against Program and Erase instructions.• A uto Erase and Auto Program Algorithm- Automatically erases and verifies data at selected sector- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (Any page to be programed should have page in the erased state first)• Status Register Feature• Electronic Identification- JEDEC 2-byte Device ID- RES command, 1-byte Device IDHARDWARE FEATURES• S CLK Input- Serial clock input• SI Input- Serial Data Input• SO Output- Serial Data Output• WP# pin- Hardware write protection• HOLD# pin- pause the chip without diselecting the chip• PACKAGE- 8-pin SOP (150mil)- 8-land USON (2x3x0.6mm)- All Pb-free devices are RoHS CompliantGENERAL DESCRIPTIONMX25L1005C is a CMOS 1,048,576 bit serial Flash memory, which is configured as 131,072 x 8 internally.The MX25L1005C feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input.The MX25L1005C provide sequential read operation on whole chip.After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the speci-fied page or sector/block locations will be executed. Program command is executed on page (256 bytes) basis, and erase command is executes on chip or sector(4K-bytes) or block(64K-bytes).To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit.When the device is not in operation and CS# is high, it is put in standby mode and draws less than 10uA DC cur-rent.The MX25L1005C utilize Macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles.PIN CONFIGURATIONSPIN DESCRIPTION8-PIN SOP (150mil)8-LAND USON (2x3mm)CS#SO WP#GNDVCC HOLD#SCLK SICS#SO WP#GNDVCC HOLD#SCLK SISYMBOL DESCRIPTION CS#Chip SelectSI Serial Data Input SO Serial Data Output SCLK Clock InputHOLD#Hold, to pause the device without deselecting the device VCC + 3.3V Power Supply GNDGroundDATA PROTECTIONThe MX25L1005C is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the standby mode. In addition, with its control register architecture, alteration of the memory con-tents only occurs after successful completion of specific command sequences. The device also incorporates sev-eral features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise.• Valid command length checking: The command length will be checked whether it is at byte base and completed on byte boundary.• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before other command to change data. The WEL bit will return to reset stage under following situation:- Power-up- Write Disable (WRDI) command completion- Write Status Register (WRSR) command completion- Page Program (PP) command completion- Sector Erase (SE) command completion- Block Erase (BE) command completion- Chip Erase (CE) command completion• Software Protection Mode (SPM): by using BP0-BP1 bits to set the part of Flash protected from data change.• Hardware Protection Mode (HPM): by using WP# going low to protect the BP0-BP1 bits and SRWD bit from data change.• Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from writing all commands except Release from deep power down mode command (RDP) and Read Electronic Sig-nature command (RES).Table 1. Protected Area SizesHOLD FEATUREHOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the operation of write status register, programming, or erasing in progress.The operation of HOLD requires Chip Select(CS#) keeping low and starts on falling edge of HOLD# pin signal while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start until Serial Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Se-rial Clock(SCLK) signal is being low( if Serial Clock signal is not being low, HOLD operation will not end until Serial Clock being low), see Figure 1.Figure 1. Hold Condition OperationThe Serial Data Output (SO) is high impedance, both Serial Data Input (SI) and Serial Clock (SCLK) are don't care during the HOLD operation. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and CS# must be at low.Status bitProtect level 1Mb BP1 BP00 0 0 (none) None 0 1 1 (1 block) Block 1 1 0 2 (2 blocks) All 113 (All)AllTable 2. COMMAND DEFINITION(1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first.(2) It is not allowed to adopt any other code which is not in the above command definition table.Command (byte)WREN (write enable)WRDI (write disable)RDID (read identification)RDSR (read status register)WRSR (write status register)READ (read data)FAST READ(fast readdata)SE (sectorerase)1st byte 06 (hex)04 (hex)9F (hex)05 (hex)01 (hex)03 (hex)0B (hex)20 (hex)2nd byte AD1 AD1AD13rd byte AD2 AD2AD24th byte AD3 AD3AD35th byte xAction sets the (WEL) write enable latch bit resets the (WEL) write enable latch bit outputs JEDEC ID: 1-byte Manufacturer ID & 2-byte Device IDto read out the values of the status register to write new values of the status registern bytes read out until CS# goes high n bytes read out until CS# goes high to erase the selected sectorCommand(byte)BE (block erase)CE (chip erase)PP (page program)DP (Deep power down)RDP (Releasefrom deeppower down)RES (read electronic ID)REMS (readelectronicmanufacturer &device ID)1st byte D8 (hex)60 or C7 (hex)02 (hex)B9 (hex)AB (hex)AB (hex)90 (hex)2nd byte AD1 AD1 x x 3rd byte AD2 AD2 x x 4th byteAD3 AD3x ADD (1)Actionto erase the selected block to erase whole chip to program the selected pageenters deeppower down moderelease from deep power down mode to read out 1-byte Device ID output the Manufacturer ID & Device IDTable 3. Memory OrganizationBlock Sector Address Range13101F000h01FFFFh ::: 16010000h010FFFh01500F000h00FFFFh ::: 3003000h003FFFh 2002000h002FFFh 1001000h001FFFh 0000000h000FFFhDEVICE OPERATION1. Before a command is issued, status register should be checked to ensure device is ready for the intended op-eration.2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z.3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until next CS# rising edge.4. Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK. The difference of Serial mode 0 and mode 3 is shown as Figure 2.5. For the following instructions: RDID, RDSR, READ, FAST_READ, RES and REMS the shifted-in instruction se-quence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE, CE, PP , RDP and DP the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglect-ed and not affect the current operation of Write Status Register, Program, Erase.Figure 2. Serial Modes SupportedNote:CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is supported.SCLKMSBCPHA shift inshift outSI 01CPOL(Serial mode 0)(Serial mode 3)1SO SCLKMSBCOMMAND DESCRIPTION(1) Write Enable (WREN)The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, SE, BE, CE, and WRSR, which are intended to change the device content, should be set every time after the WREN in-struction setting the WEL bit.The sequence of issuing WREN instruction is: CS# goes low→ sending WREN instruction code→ CS# goes high. (see Figure 11)(2) Write Disable (WRDI)The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.The sequence of issuing WRDI instruction is: CS# goes low→ sending WRDI instruction code→ CS# goes high. (see Figure 12)The WEL bit is reset by following situations:- Power-up- Write Disable (WRDI) instruction completion- Write Status Register (WRSR) instruction completion- Page Program (PP) instruction completion- Sector Erase (SE) instruction completion- Block Erase (BE) instruction completion- Chip Erase (CE) instruction completion(3) Read Identification (RDID)The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC Manufacturer ID is C2(hex), the memory type ID is 20(hex) as the first-byte device ID, and the individual device ID of second-byte ID is as followings: 11(hex) for MX25L1005C.The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code → 24-bits ID data out on SO→ to end RDID operation can use CS# to high at any time during data out. (see Figure. 13)While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cy-cle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage.(4) Read Status Register (RDSR)The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is in progress. The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register data out on SO (see Figure. 14)The definition of the status register bits is as below:WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle.WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the de-vice will not accept program/erase/write status register instruction.BP1, BP0 bits. The Block Protect (BP1, BP0) bits, non-volatile bits, indicate the protected area(as defined in table 1) of the device to against the program/erase instruction without hardware protection mode being set. To write the Block Protect (BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase (BE) and Chip Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed)SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protec-tion (WP#) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP# pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP1, BP0) are read only.Note: 1. See the table "Protected Area Sizes".2. The endurance cycles of protect bits are 100,000 cycles; however, the tW time out spec of protect bits isrelaxed as tW = N x 15ms (N is a multiple of 10,000 cycles, ex. N = 2 for 20,000 cycles) after 10,000 cycles on those bits.bit7bit6bit5bit4bit3bit2bit1bit0SRWD (status register write protect)00)BP1 (level of protected block)BP0 (level of protected block)WEL (write enable latch)WIP (write inprogress bit)1=status register write disable(note 1)(note 1)1=write enable 0=not write enable 1=write operation 0=not in write operation(5) Write Status Register (WRSR)The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in ad-vance. The WRSR instruction can change the value of Block Protect (BP1, BP0) bits to define the protected area of memory (as shown in table 1). The WRSR also can set or reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#) pin signal. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered.The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register data on SI→ CS# goes high. (see Figure 15)The WRSR instruction has no effect on b6, b5, b4, b1, b0 of the status register.The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset.Table 4. Protection ModesNote:1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 1.As the above table showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM). Software Protected Mode (SPM):- When SRWD bit=0, no matter WP# is low or high, the WREN instruction may set the WEL bit and can changethe values of SRWD, BP1, BP0. The protected area, which is defined by BP1, BP0, is at software protected mode (SPM).- When SRWD bit=1 and WP# is high, the WREN instruction may set the WEL bit can change the values ofSRWD, BP1, BP0. The protected area, which is defined by BP1, BP0, is at software protected mode (SPM)Note: If SRWD bit=1 but WP# is low, it is impossible to write the Status Register even if the WEL bit has previously been set. It is rejected to write the Status Register and not be executed.ModeStatus register condition WP# and SRWD bit status Memory Software protectionmode(SPM)Status register can be written in (WEL bit is set to "1") andthe SRWD, BP0-BP1bits can be changed WP#=1 and SRWD bit=0, or WP#=0 and SRWD bit=0, or WP#=1 and SRWD=1The protected areacannotbe program or erase.Hardware protectionmode (HPM)The SRWD, BP0-BP1 of status register bits cannot bechangedWP#=0, SRWD bit=1The protected areacannotbe program or erase.Hardware Protected Mode (HPM):- When SRWD bit=1, and then WP# is low (or WP# is low before SRWD bit=1), it enters the hardware protected mode (HPM). The data of the protected area is protected by software protected mode by BP1, BP0 and hard-ware protected mode by the WP# to against data modification.Note: to exit the hardware protected mode requires WP# driving high once the hardware protected mode is entered. If the WP# pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via BP1, BP0.(6) Read Data Bytes (READ)The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been reached.The sequence of issuing READ instruction is: CS# goes low→ sending READ instruction code→ 3-byte address on SI→data out on SO→ to end READ operation can use CS# to high at any time during data out. (see Figure. 16) (7) Read Data Bytes at Higher Speed (FAST_READ)The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has been reached.The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ instruction code→3-byte address on SI→1-dummy byte address on SI→data out on SO→ to end FAST_READ operation can use CS# to high at any time during data out. (see Figure. 17)While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any im-pact on the Program/Erase/Write Status Register current cycle.(8) Sector Erase (SE)The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". A Write Enable (WREN) in-struction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address of the sector (see table 3) is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed.Address bits [Am-A12] (Am is the most significant address) select the sector address.The sequence of issuing SE instruction is: CS# goes low→ sending SE instruction code→ 3-byte address on SI →CS# goes high. (see Figure 19)The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the page.(9) Block Erase (BE)The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". A Write Enable (WREN) in-struction must execute to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (see table 3) is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed.The sequence of issuing BE instruction is: CS# goes low→ sending BE instruction code→ 3-byte address on SI → CS# goes high. (see Figure 20)The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the page.(10) Chip Erase (CE)The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruc-tion must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). Any address of the sector (see table 3) is a valid address for Chip Erase (CE) instruction. The CS# must go high exactly at the byte boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not ex-ecuted.The sequence of issuing CE instruction is: CS# goes low→sending CE instruction code→ CS# goes high. (see Fig-ure 20)The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip is protected by BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed when BP1, BP0 all set to "0".(11) Page Program (PP)The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). If the eight least sig-nificant address bits (A7-A0) are not all 0, all transmitted data which goes beyond the end of the current page are programmed from the start address if the same page (from the address whose 8 least significant address bits (A7-A0) are all 0). The CS# must keep during the whole Page Program cycle. The CS# must go high exactly at the byte boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. If more than 256 bytes are sent to the device, the data of the last 256-byte is programmed at the request page and previous data will be disregarded. If less than 256 bytes are sent to the device, the data is programmed at the request address of the page without effect on other address of the same page.The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on SI→at least 1-byte on data on SI→CS# goes high. (see Figure 18)The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP1, BP0 bits, the Page Program (PP) instruction will not be executed.(12) Deep Power-down (DP)The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to enter-ing the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not ac-tive and all Write/Program/Erase instruction are ignored. When CS# goes high, it's only in standby mode not deep power-down mode. It's different from Standby mode.The sequence of issuing DP instruction is: CS# goes low→ sending DP instruction code→CS# goes high. (see Fig-ure 22)Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP) and Read Electronic Signature (RES) instruction. (RES instruction to allow the ID been read out). When Power-down, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2.(13) Release from Deep Power-down (RDP), Read Electronic Signature (RES)The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip Select (CS#) must remain High for at least tRES2(max), as specified in Table 6. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions.RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new deisng, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/ write cycle in progress.The sequence is shown as Figure 23,24.The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeat-edly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction.The RDP instruction is for releasing from Deep Power Down Mode.。

IC datasheet pdf-TAS5186A,pdf(6-Channel 210-W Digital Amplifier Power Stage)

TMFEATURESAPPLICATIONSDESCRIPTIONTHD+N–TotalHarmonicDistortion+Noise–%1070G0120.010.12010.110P O – Output Power – W1TAS5186ASLES156–OCTOBER2005 6-Channel,210-W,Digital-Amplifier Power StageThe TAS5186A requires only simple passivedemodulation filters on its outputs to deliver •Total Output Power@10%THD+Nhigh-quality,high-efficiency audio amplification.The –5×30W@6Ω+1×60W@3Ωdevice efficiency of the TAS5186A is greater than90%when driving6-Ωsatellites and a3-Ωsubwoofer •105-dB SNR(A-Weighted)speaker.•0.07%THD+N@1WThe TAS5186A has an innovative protection system •Power Stage Efficiency>90%Intointegrated on-chip,safeguarding the device against a Recommended Loads(SE)wide range of fault conditions that could damage the •Integrated Self-Protection Circuits system.These safeguards are short-circuit protection,–Undervoltage overload protection,undervoltage protection,andovertemperature protection.The TAS5186A has a –Overtemperaturenew proprietary current-limiting circuit that reduces –Overloadthe possibility of device shutdown during high-level –Short Circuit music transients.A new programmable overcurrentdetector allows the use of lower-cost inductors in the •Integrated Active-Bias Control to Avoid DCdemodulation output filter.Pop•Thermally Enhanced44-Pin HTSSOP Package TOTAL HARMONIC DISTORTION+NOISEvs•EMI-Compliant When Used WithOUTPUT POWER Recommended System Design•DVD Receiver•Home Theater in a BoxThe TAS5186A is a high-performance,six-channel,digital-amplifier power stage with an improvedprotection system.The TAS5186A is capable ofdriving a6-Ω,s ingleended load up to30W per eachfront/satellite channel and a3-Ω,single-endedsubwoofer greater than60W at10%THD+Nperformance.A low-cost,high-fidelity audio system can be builtusing a TI chipset comprising a modulator(e.g.,TAS5086)and the TAS5186A.This device does notrequire power-up sequencing because of the internalpower-on reset.Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PowerPAD is a trademark of Texas Instruments.PRODUCTION DATA information is current as of publication date.Copyright©2005,Texas Instruments Incorporated Products conform to specifications per the terms of the TexasInstruments standard warranty.Production processing does notnecessarily include testing of all parameters.DDV PACKAGE (TOP VIEW)P0016-03TAS5186ASLES156–OCTOBER 2005These devices have limited built-in ESD protection.The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.The TAS5186A is available in a thermally enhanced 44-pin HTSSOP PowerPAD™package.The heat slug is located on the top side of the device for convenient thermal coupling to a heatsink.2TAS5186ASLES156–OCTOBER 2005GENERAL INFORMATION (continued)TERMINAL FUNCTIONSTERMINAL TYPE (1)DESCRIPTIONNAME NO.AGND 12P Analog groundBST_A 23P HS bootstrap supply (BST),capacitor to OUT_A required BST_B 29P HS bootstrap supply (BST),external capacitor to OUT_B required BST_BIAS 21P BIAS bootstrap supply,external capacitor to OUT_BIAS required BST_C 30P HS bootstrap supply (BST),external capacitor to OUT_C required BST_D 37P HS bootstrap supply (BST),external capacitor to OUT_D required BST_E 38P HS bootstrap supply (BST),external capacitor to OUT_E required BST_F 44P HS bootstrap supply (BST),external capacitor to OUT_F required GND 11P Chip groundGVDD_ABC 20P Gate drive voltage supply GVDD_DEF 3P Gate drive voltage supply M110I Mode selection pin M29I Mode selection pin M38I Mode selection pinOC_ADJ 14O Overcurrent threshold programming pin,resistor to ground required OTW 16O Overtemperature warning open-drain output signal,active-low OUT_A 25O Output,half-bridge A,satellite OUT_B 27O Output,half-bridge B,satellite OUT_BIAS 22O BIAS half-bridge output pin OUT_C 32O Output,half-bridge C,subwoofer OUT_D 35O Output,half-bridge D,satellite OUT_E 40O Output,half-bridge E,satellite OUT_F42OOutput,half-bridge F,satellite1,26,PGND 33,P Power ground34,41PVDD_A 24P Power-supply input for half-bridge A PVDD_B 28P Power-supply input for half-bridge B PVDD_C 31P Power-supply input for half-bridge C PVDD_D 36P Power-supply input for half-bridge D PVDD_E 39P Power-supply input for half-bridge E PVDD_F 43P Power-supply input for half-bridge F PWM_A 19I PWM input signal for half-bridge A PWM_B 18I PWM input signal for half-bridge B PWM_C 17I PWM input signal for half-bridge C PWM_D 6I PWM input signal for half-bridge D PWM_E 5I PWM input signal for half-bridge E PWM_F 2I PWM input signal for half-bridge F RESET 7I Reset signal (active-low logic)SD 15O Shutdown open-drain output signal,active-low VDD 4P Power supply for digital voltage regulator VREG 13ODigital regulator supply filter pin,output(1)I =input;O =output;P =power3PACKAGE HEAT DISSIPATION RATINGS (1)ABSOLUTE MAXIMUM RATINGSTAS5186ASLES156–OCTOBER 2005Table 1.MODE Selection PinsMODE PINS (1)MODEM2M3NAMEDESCRIPTION00 2.1mode Channels A,B,and C enabled;channels D,E,and F disabled01 5.1mode All channels enabled10/1Reserved(1)M1must always be connected to GND.0indicates a pin connected to GND;1indicates a pin connected to VREG.PARAMETERTAS5186ADDVR θJC (°C/W)—1satellite (sat.)FET only 10.3R θJC (°C/W)—1subwoofer (sub.)FET only5.2R θJC (°C/W)—1sat.half-bridge 5.2R θJC (°C/W)—1sub.half-bridge 2.6R θJC (°C/W)—5sat.half-bridges +1sub.1.74Typical pad area (2)34.9mm 2(1)JC is junction-to-case,CH is case-to-heatsink.(2)R θCH is an important consideration.Assume a 2-mil thickness of typical thermal grease between the pad area and the heatsink.The R θCH with this condition is typically 2°C/W for this package.over operating free-air temperature range (unless otherwise noted)(1)TAS5186AVDD to AGND –0.3V to 13.2V GVDD_X to AGND –0.3V to 13.2V PVDD_X to PGND_X (2)–0.3V to 50V OUT_X to PGND_X (2)–0.3V to 50V BST_X to PGND_X (2)–0.3V to 63.2V VREG to AGND –0.3V to 4.2V PGND to GND –0.3V to 0.3V PGND to AGND –0.3V to 0.3V GND to AGND–0.3V to 0.3V PWM_X,OC_ADJ,M1,M2,M3to AGND –0.3V to 4.2V RESET,SD,OTW to AGND–0.3V to 7V Maximum operating junction temperature range (T J )0to 125°C Storage temperature–40°C to 125°CLead temperature –1,6mm (1/16inch)from case for 10seconds 260°C Minimum PWM pulse duration,low 30ns(1)Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.These are stress ratings only,and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2)These voltages represent the dc voltage +peak ac waveform measured at the terminal of the device in all conditions.4M1M2RESETSD OTWAGND OC_ADJVREG VDDGVDD_DEF M3GNDPWM_FOUT_F PGND PVDD_FBST_FPWM_EOUT_E PGND PVDD_E BST_EPWM_DOUT_D PGND PVDD_D BST_DPWM_COUT_C PGND PVDD_C BST_CPWM_BOUT_B PGND PVDD_B BST_BPWM_AOUT_APVDD_A BST_AOUT_BIASBST_BIASB0034-03GVDD_ABC TAS5186ASLES156–OCTOBER 2005TYPICAL SYSTEM DIAGRAMA schematic diagram for a typical system is appended at the end of the data sheet.FUNCTIONAL BLOCK DIAGRAM5RECOMMENDED OPERATING CONDITIONSAUDIO SPECIFICATIONTAS5186ASLES156–OCTOBER 2005MINTYPMAX UNIT PVDD_X Half-bridge supply,SEDC supply voltage at pin(s)040V GVDD Gate drive and guard ring supply voltage DC voltage at pin(s)10.81213.2V VDD Digital regulator supply DC supply voltage at pin 10.81213.2V Any value of R PU,EXT within VPU Pullup voltage supply35 5.5V recommended rangeResistive load impedance,satellite Recommended demodulation filter R L,SAT 46Ωchannels (1)Resistive load impedance,subwoofer Recommended demodulation filter R L,SUB 2.253ΩchannelMinimum output inductance under L output Demodulation filter inductance 522µH short-circuit conditionC output,sat Demodulation filter capacitance 1µF C output,sub Demodulation filter capacitance 1µF F PWM PWM frame rate192384432kHz(1)Load impedance outside range listed might cause shutdown due to OLP,OTE,or NLP.PVDD_X =40V,GVDD =12V,audio frequency =1kHz,AES17measurement filter,F PWM =384kHz,case temperature =75°C.Audio performance is recorded as a chipset,using TAS5086PWM processor with an effective modulation index limit of 97%.All performance is in accordance with the foregoing specifications and recommended operating conditions unless otherwise specified.PARAMETERCONDITIONSMINTYP MAXUNITR L =6Ω,10%THD,clipped input signal30R L =8Ω,10%THD,clipped input signal 25P O,satPower output per satellite channelWR L =6Ω,0dBFS,unclipped input signal 25R L =8Ω,0dBFS,unclipped input signal 20R L =3Ω,10%THD,clipped input signal60R L =4Ω,10%THD,clipped input signal 52P O,subPower output,subwooferW R L =3Ω,0dBFS,unclipped input signal 50R L =4Ω,0dBFS,unclipped input signal40R L =6Ω,P O =25W 0.3%Total harmonic distortion +noise,satelliteR L =6Ω,1W 0.07%THD +NR L =3Ω,P O =50W 0.5%Total harmonic distortion +noise,subwooferR L =3Ω,1W 0.05%Output integrated noise,satellite A-weighted 55V n µV Output integrated noise,subwoofer A-weighted 60SNR System signal-to-noise ratio A-weighted105dB Dynamic range (1)A-weighted,–60dBFS input signal,105DNRdB measured with TAS5086PWM processor P O =0W,all channels running 5.1mode (2).22-µH Kwang-Sung inductors (see 4.5W Power dissipation due to idle losses schematic for information)P idle(IPVDDX)P O =0W,2.1mode.22-µH Kwang-Sung 2.2W inductors (see schematic for information)(1)SNR is calculated relative to 0-dBFS input level.(2)Actual system idle losses are affected by core losses of output inductors.6ELECTRICAL CHARACTERISTICSTAS5186ASLES156–OCTOBER 2005F PWM =384kHz,GVDD =12V,VDD =12V,T C (case temperature)=75°C,unless otherwise noted.All performance is in accordance with recommended operating conditions,unless otherwise specified.SYMBOL PARAMETERCONDITIONSMIN TYP MAX UNIT INTERNAL VOLTAGE REGULATOR ANDCURRENT CONSUMPTIONVREG Voltage regulator,only used as reference node VDD =12V33.3 3.6V Operating,50%duty cycle 720IVDD VDD supply currentmA Idle,reset mode 61650%duty cycle 522IGVDD_XGate supply current per half-bridgemAIdle,reset mode1350%duty cycle,without output filter or load,5.1110mode.22-µH Kwang-Sung inductorsIPVDD_X Half-bridge idle currentmA50%duty cycle,without output filter or load,2.160mode.22-µH Kwang-Sung inductors OUTPUT STAGE MOSFETs R DSon ,LS Sat Drain-to-source resistance,low side,satellite T J =25°C,includes metallization resistance 210m ΩR DSon ,HS Sat Drain-to-source resistance,high side,satellite T J =25°C,includes metallization resistance 210m ΩR Dson ,LS Sub Drain-to-source resistance,low side,subwoofer T J =25°C,includes metallization resistance 110m ΩR Dson ,HS Sub Drain-to-source resistance,high side,subwooferT J =25°C,includes metallization resistance110m ΩI/O PROTECTION V UVP,G Undervoltage protection limit GVDD_X 10V V UVP,hyst (1)Undervoltage protection hysteresis 250mV OTW (1)Overtemperature warning125°C Temperature drop needed below OTW temp.for OTW hyst (1)25°C OTW to be inactive after the OTW event OTE (1)Overtemperature error155°C Temperature drop needed below OTE temp.for SD OTE HYST (1)25°C to be released after the OTE event OLCP Overload protection counter 1.25ms Overcurrent limit protection,satellite Rocp =18k Ω 4.5A I OC Overcurrent limit protection,subwoofer Rocp =18k Ω8A I OCT Overcurrent response time 210ns Rocp OC programming resistor range Resistor tolerance =5%18k ΩSTATIC DIGITAL SPECIFICATIONV IH High-level input voltage 2PWM_X,M1,M2,M3,RESET V V IL Low-level input voltage 0.8I LEAKInput leakage currentStatic condition–8080µAOTW/SHUTDOWN (SD)Internal pullup resistor to DREG (3.3V)for SD and R INT_PU 26k ΩOTWInternal pullup resistor only3 3.33.6V OH High-level output voltage External pullup:4.7-k Ωresistor to 5V 4.55V V OL Low-level output voltage I O =4mA 0.20.4FANOUTDevice fanout OTW,SDNo external pullup30Devices (1)Specified by design.7TYPICAL CHARACTERISTICS,5.1MODET H D +N – T o t a l H a r m o n i c D i s t o r t i o n + N o i s e – %1040G0010.010.12010.110P O – Output Power – W1T H D +N – T o t a l H a r m o n i c D i s t o r t i o n + N o i s e – %1070G0020.010.12010.110P O – Output Power – W1PVDD – Supply Voltage – V 024681012141618202224262830323436P O – O u t p u t P o w e r – WG003PVDD – Supply Voltage – V510152025303540455055606570G004P O – O u t p u t P o w e r – WTAS5186ASLES156–OCTOBER 2005TOTAL HARMONIC DISTORTION +NOISETOTAL HARMONIC DISTORTION +NOISEvsvsOUTPUT POWEROUTPUT POWERFigure 1.Figure 2.OUTPUT POWEROUTPUT POWERvsvsSUPPLY VOLTAGESUPPLY VOLTAGEFigure 3.Figure 4.8PVDD – Supply Voltage – V 0246810121416182022242628G005P O – O u t p u t P o w e r – WPVDD – Supply Voltage – V0510152025303540455055G006P O – O u t p u t P o w e r – W20406080100120140160180200220240S y s t e m E f f i c i e n c y – %G007P O – Total Output Power – W051015202530354020406080100120140160180200220240S y s t e m P o w e r L o s s – WG008P O – Total Output Power – WTAS5186ASLES156–OCTOBER 2005TYPICAL CHARACTERISTICS,5.1MODE (continued)OUTPUT POWEROUTPUT POWERvsvsSUPPLY VOLTAGESUPPLY VOLTAGEFigure 5.Figure 6.SYSTEM EFFICIENCYSYSTEM POWER LOSSvsvsTOTAL OUTPUT POWERTOTAL OUTPUT POWERFigure 7.Figure 8.9T C – Case Temperature – °C 0510********35402030405060708090100110G009P O – O u t p u t P o w e r – WT C – Case Temperature – °C010203040506070802030405060708090100110G010P O – O u t p u t P o w e r – Wf – Frequency – kHz−150−140−130−120−110−100−90−80−70−60−50−40−30−20−1000246810121416182022A m p l i t u d e – d BG011TAS5186ASLES156–OCTOBER 2005TYPICAL CHARACTERISTICS,5.1MODE (continued)OUTPUT POWEROUTPUT POWERvsvsCASE TEMPERATURECASE TEMPERATUREFigure 9.Figure 10.AMPLITUDEvsFREQUENCYFigure 11.10 THEORY OF OPERATIONPOWER SUPPLIESSYSTEM POWER-UP/DOWN SEQUENCE Powering Down Error Reporting TAS5186ASLES156–OCTOBER 2005reliability,it is important that each PVDD_X pin is decoupled with a 100-nF ceramic capacitor placed as close as possible to each supply pin on the same To facilitate system design,the TAS5186A needsside of the PCB as the TAS5186A.It is only a 12-V supply in addition to a typical 39-Vrecommended to follow the PCB layout of the power-stage supply.An internal voltage regulatorTAS5186A reference design.For additional provides suitable voltage levels for the digital andinformation on the recommended power supply and low-voltage analog circuitry.Additionally,all circuitryrequired components,see the application diagrams requiring a floating voltage supply,e.g.,the high-sidegiven in this data sheet.The 12-V supply should be gate drive,is accommodated by built-in bootstrappowered from a low-noise,low-output-impedance circuitry requiring only a few external capacitors.voltage regulator.Likewise,the 39-V power-stage supply is assumed to have low output impedance and In order to provide outstanding electrical and acousticlow noise.The power-supply sequence is not critical characteristics,the PWM signal path including gatedue to the internal power-on-reset circuit.Moreover,drive and output stage is designed as identical,the TAS5186A is fully protected against erroneous independent half-bridges.For this reason,eachpower-stage turnon due to parasitic gate charging.half-bridge has separate bootstrap pins (BST_X)andThus,voltage-supply ramp rates (dv/dt)are typically power-stage supply pins (PVDD_X).Furthermore,annoncritical.additional pin (VDD)is provided as power supply forall common circuits.Although supplied from the same12-V source,it is highly recommended to separateGVDD_X and VDD on the printed-circuit board (PCB)The TAS5186A does not require a power-up by RC filters (see application diagram for details).sequence.The outputs of the H-bridge remain in a These RC filters provide the recommendedhigh-impedance state until the gate-drive supply high-frequency isolation.Special attention should bevoltage (GVDD_X)and VDD voltage are above the paid to placing all decoupling capacitors as close toundervoltage protection (UVP)voltage threshold (see their associated pins as possible.In general,the Electrical Characteristics section of this data inductance between the power-supply pins andsheet).Although not specifically required,it is decoupling capacitors must be avoided.(Seerecommended to hold RESET in a low state while reference board documentation for additionalpowering up the rmation.)When the TAS5186A is being used with TI PWM For a properly functioning bootstrap circuit,a smallmodulators such as the TAS5086,no special ceramic capacitor must be connected from eachattention to the state of RESET is required,provided bootstrap pin (BST_X)to the power-stage output pinthat the chipset is configured as recommended.(OUT_X).When the power-stage output is low,thebootstrap capacitor is charged through an internaldiode connected between the gate-drivepower-supply pin (GVDD_X)and the bootstrap pin.The TAS5186A does not require a power-down When the power-stage output voltage is high,thesequence.The device remains fully operational as bootstrap capacitor voltage is shifted above thelong as the gate-drive supply (GVDD_X)voltage and output voltage potential and thus provides a suitableVDD voltage are above the undervoltage protection voltage supply for the high-side gate driver.In an(UVP)threshold level (see the Electrical application with PWM switching frequencies in theCharacteristics section of this data sheet).Although range 352kHz to 384kHz,it is recommended to usenot specifically required,it is a good practice to hold 33-nF ceramic capacitors,size 0603or 0805,for theRESET low during power down,thus preventing bootstrap capacitor.These 33-nF capacitors ensureaudible artifacts including pops and clicks sufficient energy storage,even during minimal PWMWhen the TAS5186A is being used with TI PWM duty cycles,to keep the high-side power stage FETmodulators such as the TAS5086,no special (LDMOS)fully started during all of the remaining partattention to the state of RESET is required,provided of the PWM cycle.In an application running at athat the chipset is configured as recommended.reduced switching frequency,generally 250kHz to192kHz,the bootstrap capacitor might need to beincreased in value.Special attention should be paidto the power-stage power supply;this includesThe SD and OTW pins are both active-low,component selection,PCB placement and routing.Asopen-drain outputs.Their function is for indicated,each half-bridge has independentprotection-mode signaling to a PWM controller or power-stage supply pins (PVDD_X).For optimalother system-control device.electrical performance,EMI compliance,and systemDevice Protection SystemOVERCURRENT (OC)PROTECTION WITH TAS5186ASLES156–OCTOBER 2005Any fault resulting in device shutdown is signaled bytwo protection systems.The first protection system the SD pin going low.Likewise,OTW goes low whencontrols the power stage in order to prevent the the device junction temperature exceeds 125°C (seeoutput current from further increasing.i.e.,it performs the following table).a current-limiting function rather than prematurely shutting down during combinations of high-level music transients and extreme speaker SDOTW DESCRIPTION load-impedance drops.If the high-current situation persists,i.e.,the power stage is being overloaded,a 00Overtemperature (OTE)or overload (OLP)or undervoltage (UVP)second protection system triggers a latching shutdown,resulting in the power stage being set in 01Overload (OLP)or undervoltage (UVP)the high-impedance (Hi-Z)state.10Overtemperature warning.Junction temperature higher than 125°C,typical For added flexibility,the OC threshold is 11Normal operation.Junction temperature lower thanprogrammable within a limited range using a single 125°C,typical external resistor connected between the OC_ADJ pinand AGND.It should be noted that asserting RESET low forces OC-Adjust Resistor ValuesMaximum Peak Current Before the SD and OTW signals high independently of faults (k Ω)OC Occurs (A)being present.It is recommended to monitor the 18 4.5(sat.),8(sub.)OTW signal using the system microcontroller and torespond to an overtemperature warning signal by,It should be noted that a properly functioning e.g.,turning down the volume to prevent furtherovercurrent detector assumes the presence of a heating of the device that would result in deviceproperly designed demodulation filter at the shutdown (OTE).To reduce external componentpower-stage output.Short-circuit protection is not count,an internal pullup resistor to 3.3V is providedprovided directly at the output pins of the power stage on both the SD and OTW outputs.Level compliancebut only on the speaker terminals (after the for 5-V logic can be obtained by adding externaldemodulation filter).It is required to follow certain pullup resistors to 5V (see the Electricalguidelines when selecting the OC threshold and an Characteristics section of this data sheet for furtherappropriate demodulation inductor.specifications).•For the lowest-cost bill of materials in terms of component selection,the OC threshold current should be limited,considering the power output The TAS5186A contains advanced protection circuitryrequirement and minimum load impedance.carefully designed to facilitate system integration andHigher-impedance loads require a lower OC ease of use,as well as safeguarding the device fromthreshold.permanent failure due to a wide range of fault•The demodulation filter inductor must retain at conditions such as short circuit,overload,andleast 5µH of inductance at twice the OC undervoltage.The TAS5186A responds to a fault bythreshold setting.immediately setting the power stage in ahigh-impedance state (Hi-Z)and asserting the SD pinMost inductors have decreasing inductance with low.In situations other than overload,the deviceincreasing temperature and increasing current automatically recovers when the fault condition has(saturation).To some degree,an increase in been removed,e.g.,the supply voltage has increasedtemperature naturally occurs when operating at high or the temperature has dropped.For highest possibleoutput currents,due to inductor core losses and the reliability,recovering from an overload fault requiresdc resistance of the inductor copper winding.A external reset of the device no sooner than 1secondthorough analysis of inductor saturation and thermal after the shutdown (see the Device Reset section ofproperties is strongly recommended.this data sheet).Setting the OC threshold too low might cause issuessuch as lack of output power and/or unexpectedshutdowns due to sensitive overload detection.CURRENT LIMITING AND OVERLOAD DETECTION In general,it is recommended to follow closely theexternal component selection and PCB layout asThe device has independent,fast-reacting currentgiven in the application section.detectors with programmable trip threshold (OCthreshold)on all high-side and low-side power-stageFETs.See the following table for OC-adjust resistorvalues.The detector outputs are closely monitored by Overtemperature ProtectionUNDERVOLTAGE PROTECTION (UVP)AND DEVICE RESET ACTIVE-BIAS CONTROL (ABC)TAS5186ASLES156–OCTOBER 2005element in the audio path,i.e.,split-cap capacitors or series capacitor,to the desired potential before The TAS5186A has a two-levelswitching is started on the PWM outputs.(For temperature-protection system that asserts anrecommended configuration,see the typical active-low warning signal (OTW)when the deviceapplication schematic included in this data sheet).junction temperature exceeds 125°C (typical),and Ifthe device junction temperature exceeds 155°CThe start-up sequence can be controlled through (typical),the device is put into thermal shutdown,sequencing the M3and RESET pins according to resulting in all half-bridge outputs being set in theTable 2and Table 3.high-impedance state (Hi-Z)and SD being assertedlow.Table 2.5.1Mode—All Output Channels ActiveM3RESET OUT_BIAS OUT_A,OUT_D,COMMENT _B,_C _E,_FPOWER-ON RESET (POR)00Hi-Z Hi-Z Hi-Z All outputsdisabled,The UVP and POR circuits of the TAS5186A fully nothing isprotect the device in any power-up/down and switching.brownout situation.While powering up,the POR 10Active Hi-Z Hi-Z OUT_BIAScircuit resets the overload circuit (OLP)and ensures enabled,allthat all circuits are fully operational when the other outputsdisabledGVDD_X and VDD supply voltages reach 10V (typical).Although GVDD_X and VDD are 11Hi-Z Active Active OUT_BIASdisabled,allindependently monitored,a supply voltage drop other outputsbelow the UVP threshold on any VDD or GVDD_Xswitching pin results in all half-bridge outputs immediately beingset in the high-impedance (Hi-Z)state and SD beingTable 3.2.1Mode—Only Output Channels A,B,asserted low.The device automatically resumesand C Active operation when all supply voltages have increasedabove the UVP threshold.M3RESET OUT_BIAS OUT_A,OUT_D,COMMENT _B,_C _E,_F00Hi-Z Hi-Z Hi-Z All outputsdisabled,When RESET is asserted low,the output FETs in all nothing ishalf-bridges are forced into a high-impedance (Hi-Z)switching.state.10Active Hi-Z Hi-Z OUT_BIASenabled,allAsserting the RESET input low removes any fault other outputsinformation to be signaled on the SD output,i.e.,SD disabledis forced high.01Hi-Z Active Hi-ZOUT_BIASdisabled,allA rising-edge transition on the RESET input allows other outputsthe device to resume operation after an overloadswitching fault.When the TAS5186A is used with the TAS5086PWM modulator,no special attention to start-up sequencing is required,provided that the chipset is configured as Audible pop noises are often associated withrecommended.single-rail,single-ended power stages at power-up orat the start of switching.This commonly knownproblem has been virtually eliminated byincorporating a proprietary active-bias control circuitryas part of the TAS5186A feature set.By the use ofonly a few passive external components (typicallyresistors),the ABC can pre-charge the dc-blocking。

IC datasheet pdf-LT3652HV PDF DATASHEET

13652hvfT YPICAL APPLICATIOND ESCRIPTION ChargerThe LT ®3652HV is a complete monolithic step-down bat-tery charger that operates over a 4.95V to 34V input range. The LT3652HV provides a constant-current/constant-voltage charge characteristic, with maximum charge current externally programmable up to 2A. The charger employs a 3.3V ﬂ oat voltage feedback reference, so any desired battery ﬂ oat voltage up to 18V can be programmed with a resistor divider.The LT3652HV employs an input voltage regulation loop, which reduces charge current if the input voltage falls below a programmed level, set with a resistor divider. When the LT3652HV is powered by a solar panel, the input regulation loop is used to maintain the panel at peak output power.The L T3652HV c an b e c onﬁ gured t o t erminate c harging w hen charge c urrent f alls b elow 1/10 o f t he p rogrammed m aximum (C/10). Once charging is terminated, the LT3652HV enters a low-current (85μA) standby mode. An auto-recharge feature starts a new charging cycle if the battery voltage falls 2.5% below the programmed ﬂ oat voltage. The LT3652HV also contains a programmable safety timer, used to terminate charging after a desired time is reached. This allows top-off charging at currents less than C/10.F EATURESA PPLICATIONS nInput Supply Voltage Regulation Loop for Peak Power T racking in (MPPT) Solar Applicationsn Wide Input Voltage Range: 4.95V to 34V (40V Abs Max)n Programmable Charge Rate Up to 2An User Selectable Termination: C/10 or On-Board Termination Timern Resistor Programmable Float Voltage Up to 18V Accommodates 4-Cell Li-Ion/Polymer , 5-Cell LiFePO 4, Lead-Acid Chemistriesn Parallelable for Higher Output Current n 1MHz Fixed Frequencyn 0.5% Float Voltage Reference Accuracy n 5% Charge Current Accuracy n 2.5% C/10 Detection Accuracyn Binary-Coded Open-Collector Status PinsnSolar Powered Applications n Remote Monitoring Stations n Portable Handheld Instruments n 12V to 24V Automotive SystemsnBattery Charging from Current Limited AdapterL , L T , L TC, L TM, Linear Technology and the Linear logo are registered trademarks and PowerPath is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners.V IN_REG Loop Servos Maximum Charge Current to Prevent AC Adapter Output from Drooping Lower Than 24V 5-Cell LiFePO 4 Charger (18V at 1.5A) with C/10 TerminationPowered by Inexpensive 24VDC/1A Unregulated Wall Adapter.SYSTEM LOADD3ADAPTER OUTPUT CURRENT (A)00.2A D A P T E R O U T P U T V O L T A G E (V )12151833302724210.61 1.23652 TA01b360.40.8 1.61.421.81A/24VDC Unregulated AdapterI vs V CharacteristicLT3652HV23652hvfP IN CONFIGURATIONA BSOLUTE MAXIMUM RATINGS Voltages:V IN ........................................................................40V V IN_REG , SHDN , CHRG , FAUL T ............V IN + 0.5V , 40V SW ........................................................................40V SW-V IN .................................................................4.5V BOOST ...................................................SW+10V , 50V BAT , SENSE .. (20V)(Note 1)ORDER INFORMATIONLEAD FREE FINISH TAPE AND REEL PART MARKING*PACKAGE DESCRIPTION TEMPERATURE RANGE LT3652HVEDD#PBF LT3652HVEDD#TRPBF LFRG 12-Lead Plastic DFN 3mm × 3mm –40°C to 125°C LT3652HVIDD#PBF LT3652HVIDD#TRPBF LFRG 12-Lead Plastic DFN 3mm × 3mm –40°C to 125°C LT3652HVEMSE#PBF LT3652HVEMSE#TRPBF 3652HV 12-Lead Plastic MSOP –40°C to 125°C LT3652HVIMSE#PBFLT3652HVIMSE#TRPBF3652HV12-Lead Plastic MSOP–40°C to 125°CConsult LTC Marketing for parts speciﬁ ed with wider operating temperature ranges. *The temperature grade is identiﬁ ed by a label on the shipping container.Consult LTC Marketing for information on non-standard lead based ﬁ nish parts.For more information on lead free part marking, go to: /leadfree/ For more information on tape and reel speciﬁ cations, go to: /tapeandreel/TOP VIEWDD PACKAGE12-LEAD (3mm × 3mm) PLASTIC DFN1211891045321SW BOOST SENSE BAT NTCV FBV IN V IN_REG SHDN CHRG FAUL T TIMER6713123456V IN V IN_REG SHDN CHRG FAUL T TIMER 121110987SW BOOST SENSE BAT NTC V FBTOP VIEW13MSE PACKAGE12-LEAD PLASTIC MSOPT JMAX = 125°C, θJA = 43°C/W , θJC = 3°C/WEXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCBT JMAX = 125°C, θJA = 43°C/W , θJC = 3°C/WEXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCBBAT-SENSE .........................................–0.5V to +0.5VNTC, TIMER, ........................................................2.5V V FB ..........................................................................5V Operating Junction Temperature Range(Note 2) .............................................–40°C to 125°C Storage Temperature Range ...................–65°C to 150°CLT3652HV33652hvfE LECTRICAL CHARACTERISTICSSYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITSV IN V IN Operating RangeV IN Start Voltage V BAT = 4.2 (Notes 3, 4)V BAT = 4.2 (Note 4)l l 4.957.534V V V IN(OVLO)OVLO Threshold OVLO Hysteresis V IN Rising l3435140V V V IN(UVLO)UVLO Threshold UVLO Hysteresis V IN Rising 4.60.24.95V V V FB(FL T)Float Voltage Reference (Note 6)l 3.2823.263.3 3.3183.34V V ΔV RECHARGE Recharge Reference Threshold Voltage Relative to V FB(FL T) (Note 6)82.5mV V FB(PRE)Reference Precondition Threshold V FB Rising (Note 6)2.3V V FB(PREHYST)Reference Precondition Threshold HysteresisVoltage Relative to V FB(PRE) (Note 6)70mVV IN_REG(TH)Input Regulation Reference V FB = 3V; V SENSE – V BAT = 50mV l 2.65 2.7 2.75V I IN_REG Input Regulation Reference Bias Current V IN_REG = V IN_REG(TH)l 35100nA I VINOperating Input Supply CurrentCC/CV Mode, I SW = 0Standby ModeShutdown (SHDN = 0)l 2.58515 3.5mA μA μA I BOOST BOOST Supply Current Switch On, I SW = 0,2.5 < V (BOOST – SW) < 8.520mA I BOOST/I SW BOOST Switch Drive I SW = 2A30mA/A V SW(ON)Switch-On Voltage Drop V IN – V SW , I SW = 2A350mV I SW(MAX)Switch Current Limit l 2.53A V SENSE(PRE)Precondition Sense Voltage V SENSE – V BAT ; V FB = 2V 15mVV SENSE(DC)Maximum Sense Voltage V SENSE – V BAT ; V FB = 3V (Note 7)l 95100105mV V SENSE(C/10)C/10 T rigger Sense Voltage V SENSE – V BAT , Falling l7.51012.5mV I BAT BAT Input Bias Current Charging Terminated 0.11μA I SENSE SENSE Input Bias Current Charging Terminated 0.11μA I VFB V FB Input Bias Current Charging Terminated 65nA I VFB V FB Input Bias Current CV Operation (Note 5)110nAV NTC(H)NTC Range Limit (High)V NTC Rising l 1.25 1.36 1.45V V NTC(L)NTC Range Limit (Low)V NTC Falling l 0.270.290.315V V NTC(HYST)NTC Threshold Hysteresis % of threshold 20%R NTC(DIS)NTC Disable Impedance Impedance to ground l 250500kΩI NTC NTC Bias Current V NTC = 0.8V l 47.55052.5μA V SHDN Shutdown Threshold Risingl 1.151.2 1.25V V SHDN (HYST)Shutdown Hysteresis 120mV I SHDN SHDN Input Bias Current –10nAV CHRG , V FAUL T Status Low Voltage 10mA Load l 0.4V I TIMER Charge/Discharge Current 25μA V TIMER(DIS)Timer Disable Thresholdl0.10.25VThe l denotes the speciﬁ cations which apply over the full operating junction temperature range, otherwise speciﬁ cations are at T A = 25°C. V IN = 20V, Boost – SW = 4V, SHDN = 2V, V FB = 3.3V, C TIMER= 0.68μF.LT3652HV43652hvfSYMBOL PARAMETERCONDITIONS MIN TYP MAX UNITSt TIMERFull Charge Cycle Timeout 3hr Precondition Timeout 22.5minTimer Accuracyl–1010%f O Operating Frequency 1MHz DCDuty Cycle RangeContinuous Operationl 1590%E LECTRICAL CHARACTERISTICS The l denotes the speciﬁ cations which apply over the full operating junction temperature range, otherwise speciﬁ cations are at T A = 25°C. V IN = 20V, Boost – SW = 4V, SHDN = 2V, V FB = 3.3V, C TIMER = 0.68μF.Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.Note 2: The L T3652HV is tested under pulsed load conditions such that T J ≅ T A . The L T3652HVE is guaranteed to meet performance speciﬁ cations from 0°C to 85°C junction temperature. Speciﬁ cations over the –40°C to 125°C operating junction temperature range are assured by design, characterization, and correlation with statistical process controls. The L T3652HVI speciﬁ cations are guaranteed over the full –40°C to 125°C operating junction temperature range. High junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125°C.Note 3: V IN minimum voltages below the start threshold are only supported if (V BOOST -V SW ) > 2V .Note 4: This parameter is valid for programmed output battery ﬂ oat voltages ≤ 4.2V . V IN operating range minimum is 0.75V above the programmed output battery ﬂ oat voltage (V BAT(FL T) + 0.75V). V IN Start Voltage is 3.3V above the programmed output battery ﬂ oat voltage (V BAT(FL T) + 3.3V).Note 5: Output battery ﬂ oat voltage (V BAT(FL T)) programming resistor divider equivalent resistance = 250k compensates for input bias current. Note 6: All V FB voltages measured through 250k series resistance.Note 7: V SENSE(DC) is reduced by thermal foldback as junction temperature approaches 125°C.LT3652HV53652hvfT YPICAL PERFORMANCE CHARACTERISTICS Switch Forward Drop (V IN – V SW ) vs TemperatureCC/CV Charging; SENSE Pin Bias Current vs V SENSEC/10 Threshold (V SENSE –V BAT ) vs TemperatureV FB Reference Voltage vs TemperatureV IN Standby Mode Current vs TemperatureSwitch Drive (I SW /I BOOST ) vs Switch CurrentT J = 25°C, unless otherwise noted.TEMPERATURE (°C)–50V F B (F L T )3.2963.2983.3003.302050753652 G01a3.304–2525100125TEMPERATURE (°C)–5065I V I N C U R R E N T (μA )70758010090050753652 G029585–2525100SWITCH CURRENT (A)I S W /I B O O S T18243036 1.6126021273315930.40.8 1.20.2 1.80.6 1.0 1.4 2.03652 G03TEMPERATURE (°C)–50320V S W (O N ) (m V )340360380480420050753652 G04440460400–2525100125V SENSE (V)–350I S E N S E (μA )–250–150–5010050–300–200–10003652 G05TEMPERATURE (°C)–508V S E N S E (C /10) (m V )9101112050753652 G06–2525100125TEMPERATURE (°C)–50V I N _R E G (T H ) (V )2.6802.6852.6902.7152.7102.7052.7002.695050753652 G012.720–2525100125V IN_REG Thresholdvs Temperature: I CHG at 50%LT3652HV63652hvfTYPICAL PERFORMANCE CHARACTERISTICSMaximum Charge Current (V SENSE –V BAT ) vs TemperatureThermal Foldback – Maximum Charge Current (V SENSE –V BAT ) vs TemperatureCC/CV Charging; BAT Pin Bias Current vs V BATT A = 25°C, unless otherwise noted.TEMPERATURE (°C)–5099.0V S E N S E (D C ) (m V )99.299.699.8100.0101.0100.4050753652 G0799.4100.6100.8100.2–2525100125TEMPERATURE (°C)V S E N S E (D C )(m V )4080206010012045658510512535135255575951153652 G08V BAT (V)–0.4I B A T (m A )0.00.40.82.21.62.01.2–0.20.20.61.01.81.43652 G09V IN_REG (V)2.65V S E N S E (D C ) (m V )208060402.67 2.692.73652 G101002.66 2.682.722.71 2.732.742.75V BAT(FL T) (V)020I R F B (μA )861012183652 G114264810121614TIME (MINUTES)EFFICIENCY (%)C H A R G E C U R R E N T (A ); P OW E R L O S S (W )0.52.02.51.51.040801003652 G123.0354575655595852060140120160180200Maximum Charge Current(V SENSE –V BAT ) vs V IN_REG VoltageV FLOAT Programming Resistor Current vs V FLOAT for 2-Resistor NetworkCharge Current, Efﬁ ciency, and Power Loss vs Time(I CHG(MAX) = 2A; V FLOAT = 8.2V)Charger Efﬁ ciency vs Battery Voltage (I CHG= 2A)V BAT (V)70E F F I C I E N C Y (%)7680828486887472789057911134141536810123652 G13LT3652HV73652hvfP IN FUNCTIONS V IN (Pin 1): Charger Input Supply. V IN operating range is 4.95V to 34V. V IN must be 3.3V greater than the pro-grammed output battery ﬂ oat voltage (V BAT(FLT)) for reli-able start-up. (V IN – V BAT(FLT)) ≥ 0.75V is the minimum operating voltage, provided (V BOOST – V SW ) ≥ 2V. I VIN ~ 85μA after charge termination. This pin is typically con-nected to the cathode of a blocking diode.V IN_REG (Pin 2): Input Voltage Regulation Reference. Maxi-mum charge current is reduced when this pin is below 2.7V. Connecting a resistor divider from V IN to this pin enables programming of minimum operational V IN voltage. This is typically used to program the peak power voltage for a solar panel. The LT3652HV servos the maximum charge current required to maintain the programmed operational V IN voltage, through maintaining the voltage on V IN_REG at or above 2.7V. If the voltage regulation feature is not used, connect the pin to V IN .SHDN (Pin 3): Precision Threshold Shutdown Pin. The enable threshold is 1.2V (rising), with 120mV of input hysteresis. When in shutdown mode, all charging functions are disabled. The precision threshold allows use of the SHDN pin to incorporate UVLO functions. If the SHDN pin is pulled below 0.4V, the IC enters a low current shutdown mode where V IN current is reduced to 15μA. Typical SHDN pin input bias current is 10nA. If the shutdown function is not desired, connect the pin to V IN .CHRG (Pin 4): Open-Collector Charger Status Output; typically pulled up through a resistor to a reference volt-age. This status pin can be pulled up to voltages as high as V IN when disabled, and can sink currents up to 10mA when enabled. During a battery charging cycle, if required charge current is greater than 1/10 of the programmed maximum current (C/10), CHRG is pulled low. A tem-perature fault also causes this pin to be pulled low. After C/10 charge termination or, if the internal timer is used for termination and charge current is less than C/10, the CHRG pin remains high-impedance.FAULT (Pin 5): Open-Collector Charger Status Output; typically pulled up through a resistor to a reference volt-age. This status pin can be pulled up to voltages as high as V IN when disabled, and can sink currents up to 10mA when enabled. This pin indicates fault conditions during abattery charging cycle. A temperature fault causes this pin to be pulled low. If the internal timer is used for termina-tion, a bad battery fault also causes this pin to be pulled low. If no fault conditions exist, the FAULT pin remains high-impedance.TIMER (Pin 6): End-Of-Cycle Timer Programming Pin. If a timer-based charge termination is desired, connect a capacitor from this pin to ground. Full charge end-of-cycle time (in hours) is programmed with this capacitor following the equation: t EOC = C TIMER • 4.4 • 106A bad battery fault is generated if the battery does not achieve the precondition threshold voltage within one-eighth of t EOC , or: t PRE = C TIMER • 5.5 • 105A 0.68μF capacitor is typically used, which generates a timer EOC at three hours, and a precondition limit time of 22.5 minutes. If a timer-based termination is not desired, the timer function is disabled by connecting the TIMER pin to ground. With the timer function disabled, charging terminates when the charge current drops below a C/10 threshold, or I CHG(MAX)/10V FB (Pin 7): Battery Float Voltage Feedback Reference. The charge function operates to achieve a ﬁ nal ﬂ oat voltage of 3.3V on this pin. Output battery ﬂ oat voltage (V BAT(FLT)) is programmed using a resistor divider. V BAT(FLT) can be programmed up to 18V.The auto-restart feature initiates a new charging cyclewhen the voltage at the V FB pin falls 2.5% below the ﬂoat voltage reference.The V FB pin input bias current is 110nA. Using a resistor divider with an equivalent input resistance at the V FB pin of 250k compensates for input bias current error.Required resistor values to program desired V BAT(FLT) follow the equations:R1 = (V BAT(FLT) • 2.5 • 105)/3.3 (Ω) R2 = (R1 • 2.5 • 105)/(R1 - (2.5 • 105))(Ω)R1 is connected from BAT to V FB , and R2 is connected from V FBto ground.LT3652HV 83652hvfNTC (Pin 8): Battery Temperature Monitor Pin. This pin is the input to the NTC (Negative Temperature Coefﬁ cient) thermistor temperature monitoring circuit. This function is enabled by connecting a 10kΩ, B = 3380 NTC thermistor from the NTC pin to ground. The pin sources 50μA, and monitors the voltage across the 10kΩ thermistor. When the voltage on this pin is above 1.36 (T < 0°C) or below 0.29V (T > 40°C), charging is disabled and the CHRG and FAULT pins are both pulled low. If internal timer termina-tion is being used, the timer is paused, suspending the charging cycle. Charging resumes when the voltage on NTC returns to within the 0.29V to 1.36V active region. There is approximately 5°C of temperature hysteresis associated with each of the temperature thresholds. The temperature monitoring function remains enabled while the thermistor resistance to ground is less than 250k, so if this function is not desired, leave the NTC pin unconnected.BAT (Pin 9): Charger Output Monitor Pin. Connect a 10μF decoupling capacitance (C BAT ) to ground. Depend-ing on application requirements, larger value decoupling capacitors may be required. The charge function operates to achieve the programmed output battery ﬂ oat voltage (V BAT(FLT)) at this pin. This pin is also the reference for the current sense voltage. Once a charge cycle is termi-nated, the input bias current of the BAT pin is reduced to < 0.1μA, to minimize battery discharge while the charger remains connected.SENSE (Pin 10): Charge Current Sense Pin. Connect the inductor sense resistor (R SENSE ) from the SENSE pin to the BAT pin. The voltage across this resistor sets the averagecharge current. The maximum charge current (I CHG(MAX)) corresponds to 100mV across the sense resistor. This resistor can be set to program maximum charge cur-rent as high as 2A. The sense resistor value follows the relation:R SENSE = 0.1/I CHG(MAX) (Ω)Once a charge cycle is terminated, the input bias current of the SENSE pin is reduced to < 0.1μA, to minimize battery discharge while the charger remains connected.BOOST (Pin 11): Bootstrapped Supply Rail for Switch D rive. This pin facilitates saturation of the switch transistor. Connect a 1μF or greater capacitor from the BOOST pin to the SW pin. Operating range of this pin is 0V to 8.5V, referenced to the SW pin. The voltage on the decoupling capacitor is refreshed through a rectifying diode, with the anode connected to either the battery output voltage or an external source, and the cathode connected to the BOOST pin.SW (Pin 12): Switch Output Pin. This pin is the output of the charger switch, and corresponds to the emitter of the switch transistor. When enabled, the switch shorts the SW pin to the V IN supply. The drive circuitry for this switch is bootstrapped above the V IN supply using the BOOST supply pin, allowing saturation of the switch for maximum efﬁ ciency. The effective on-resistance of the boosted switch is 0.175Ω.SGND (Pin 13): Ground Reference and Backside Exposed Lead Frame Thermal Connection. Solder the exposed lead frame to the PCB ground plane.P IN FUNCTIONSLT3652HV93652hvfB LOCK DIAGRAM+–LT3652HV103652hvfA PPLICATIONS INFORMATION OverviewL T3652HV is a complete monolithic, mid-power , multi-chemistry buck battery charger , addressing high input voltage applications with solutions that require a minimum of external components. The IC uses a 1MHz constant fre-quency, average-current mode step-down architecture.The L T3652HV incorporates a 2A switch that is driven by a bootstrapped supply to maximize efficiency during charging cycles. Wide input range allows operation to full charge from voltages as high as 34V . A precision threshold shutdown pin allows incorporation of UVLO functionality using a simple resistor divider . The IC can also be put into a low-current shutdown mode, in which the input supply bias is reduced to only 15μA.The L T3652HV employs an input voltage regulation loop, which reduces charge current if a monitored input voltage falls below a programmed level. When the L T3652HV is powered by a solar panel, the input regulation loop is used to maintain the panel at peak output power .The L T3652HV automatically enters a battery precondition mode if the sensed battery voltage is very low. In this mode, the charge current is reduced to 15% of the programmed maximum, as set by the inductor sense resistor , R SENSE . Once the battery voltage reaches 70% of the fully charged float voltage, the IC automatically increases maximum charge current to the full programmed value.The L T3652HV can use a charge-current based C/10 termination scheme, which ends a charge cycle when the battery charge current falls to one tenth of the pro-grammed maximum charge current. The L T3652HV also contains an internal charge cycle control timer , for timer-based termination. When using the internal timer , the IC combines C/10 detection with a programmable time constraint, during which the charging cycle can continue beyond the C/10 level to top-off a battery. The charge cycle terminates when a specific time elapses, typically 3 hours. When the timer-based scheme is used, the IC also supports bad battery detection, which triggers a system fault if a battery stays in precondition mode for more than one eighth of the total charge cycle time.Once charging is terminated, the L T3652HV automati-cally enters a low-current standby mode where supply bias currents are reduced to 85μA. The IC continues tomonitor the battery voltage while in standby, and if that voltage falls 2.5% from the full-charge float voltage, the L T3652HV engages an automatic charge cycle restart. The IC also automatically restarts a new charge cycle after a bad battery fault once the failed battery is removed and replaced with another battery.The L T3652HV contains provisions for a battery tem-perature monitoring circuit. This feature monitors battery temperature using a thermistor during the charging cycle. If the battery temperature moves outside a safe charg-ing range of 0°C to 40°C, the IC suspends charging and signals a fault condition until the temperature returns to the safe charging range.The L T3652HV contains two digital open-collector outputs, which provide charger status and signal fault conditions. These binary-coded pins signal battery charging, standby or shutdown modes, battery temperature faults, and bad battery faults.General Operation (See Block Diagram)The L T3652HV uses average current mode control loop architecture, such that the IC servos directly to average charge current. The L T3652HV senses charger output voltage through a resistor divider via the V FB pin. The difference between the voltage on this pin and an internal 3.3V voltage reference is integrated by the voltage error amplifier (V-EA). This amplifier generates an error volt-age on its output (I TH ), which corresponds to the average current sensed across the inductor current sense resistor , R SENSE , which is connected between the SENSE and BAT pins. The I TH voltage is then divided down by a factor of 10, and imposed on the input of the current error amplifier (C-EA). The difference between this imposed voltage and the current sense resistor voltage is integrated, with the resulting voltage (V C ) used as a threshold that is compared against an internally generated ramp. The output of this comparison controls the charger’s switch.The I TH error voltage corresponds linearly to average current sensed across the inductor current sense resistor , allowing maximum charge current control by limiting the effective voltage range of I TH . A clamp limits this voltage to 1V which, in turn, limits the current sense voltage to 100mV . This sets the maximum charge current, or the current delivered while the charger is operating in con-A PPLICATIONS INFORMATIONstant-current (CC) mode, which corresponds to 100mV across R SENSE. The I TH voltage is pulled down to reduce this maximum charge current should the voltage on the V IN_REG pin falls below 2.7V (V IN_REG(TH)) or the die tem-perature approaches 125°C.If the voltage on the V FB pin is below 2.3V (V FB(PRE)), the L T3652HV engages precondition mode. D uring the precondition interval, the charger continues to operate in constant-current mode, but the maximum charge current is reduced to 15% of the maximum programmed value as set by R SENSE.When the charger output voltage approaches the float volt-age, or the voltage on the V FB pin approaches 3.3V (V FB(FL T)), the charger transitions into constant-voltage (CV) mode and charge current is reduced from the maximum value. As this occurs, the I TH voltage falls from the limit clamp and servos to lower voltages. The IC monitors the I TH volt-age as it is reduced, and detection of C/10 charge current is achieved when I TH = 0.1V. If the charger is configured for C/10 termination, this threshold is used to terminate the charge cycle. Once the charge cycle is terminated, the CHRG status pin becomes high-impedance and the charger enters low-current standby mode.The L T3652HV contains an internal charge cycle timer that terminates a successful charge cycle after a programmed amount of time. This timer is typically programmed to achieve end-of-cycle (EOC) in 3 hours, but can be con-figured for any amount of time by setting an appropriate timing capacitor value (C TIMER). When timer termination is used, the charge cycle does not terminate when C/10 is achieved. Because the CHRG status pin responds to the C/10 current level, the IC will indicate a fully-charged battery status, but the charger continues to source low currents into the battery until the programmed EOC time has elapsed, at which time the charge cycle will terminate. At EOC when the charging cycle terminates, if the battery did not achieve at least 97.5% of the full float voltage, charging is deemed unsuccessful, the L T3652HV re-initiates, and charging continues for another full timer cycle.Use of the timer function also enables bad-battery detec-tion. This fault condition is achieved if the battery does not respond to preconditioning, such that the charger remains in (or enters) precondition mode after 1/8th of the programmed charge cycle time. A bad battery fault halts the charging cycle, the CHRG status pin goes high-impedance, and the FAUL T pin is pulled low.When the L T3652HV terminates a charging cycle, whether through C/10 detection or by reaching timer EOC, the average current mode analog loop remains active, but the internal float voltage reference is reduced by 2.5%. Because the voltage on a successfully charged battery is at the full float voltage, the voltage error amp detects an over-voltage condition and I TH is pulled low. When the voltage error amp output drops below 0.3V, the IC enters standby mode, where most of the internal circuitry is dis-abled, and the V IN bias current is reduced to 85μA. When the voltage on the V FB pin drops below the reduced float reference level, the output of the voltage error amp will climb, at which point the IC comes out of standby mode and a new charging cycle is initiated.V IN Input SupplyThe L T3652HV is biased through a reverse-current block-ing element from the charger input supply to the V IN pin. This supply provides large switched currents, so a high-quality, low ESR decoupling capacitor is recommended to minimize voltage glitches on V IN. The V IN decoupling capacitor (C VIN) absorbs all input switching ripple current in the charger, so it must have an adequate ripple current rating. RMS ripple current (I CVIN(RMS)) is:I CVIN(RMS)≅ I CHG(MAX) • (V BAT / V IN)•([V IN / V BAT] – 1)1/2,where I CHG(MAX) is the maximum average charge current (100mV/R SENSE). The above relation has a maximum at V IN = 2 • V BAT, where:I CVIN(RMS) = I CHG(MAX)/2.The simple worst-case of ½ • I CHG(MAX) is commonly used for design.。

IC datasheet pdf-DS1921G,pdf,datasheet,Thermochron iButton

General Description The DS1921G Thermochron ®iButton ®is a rugged, self-sufficient system that measures temperature and records the result in a protected memory section. The recording is done at a user-defined rate, both as a direct storage of temperature values as well as in the form of a histogram.Up to 2048 temperature values taken at equidistant inter-vals ranging from 1 to 255min can be stored. The his-togram provides 63 data bins with a resolution of 2.0°C.If the temperature leaves a user-programmable range,the DS1921G also records when this happened, for how long the temperature stayed outside the permitted range,and if the temperature was too high or too low. An addi-tional 512 bytes of read/write nonvolatile (NV) memory allows storing information pertaining to the object to which the DS1921G is associated. Data is transferred serially through the 1-Wire ®protocol, which requires only a single data lead and a ground return. Every DS1921G is factory lasered with a guaranteed unique, electrically readable, 64-bit registration number that allows for abso-lute traceability. The durable stainless steel package is highly resistant to environmental hazards such as dirt,moisture, and shock. Accessories permit the DS1921G to be mounted on almost any object including contain-ers, pallets, and bags.ApplicationsFeatures♦Digital Thermometer Measures Temperature in 0.5°C Increments♦Accuracy ±1°C from -30°C to +70°C (See the Electrical Characteristics for Accuracy Specification)♦Built-In Real-Time Clock (RTC) and Timer HasAccuracy of ±2 Minutes per Month from 0°C to +45°C ♦Water Resistant or Waterproof if Placed Inside DS9107 iButton Capsule (Exceeds Water Resistant 3 ATM Requirements)♦Automatically Wakes Up and Measures Temperature at User-Programmable Intervals from 1Minute to 255 Minutes♦Logs Up to 2048 Consecutive Temperature Measurements in Protected NV RAM♦Records a Long-Term Temperature Histogram with 2.0°C Resolution♦Programmable Temperature High and Temperature Low Alarm Trip Points♦Records Up to 24 Timestamps and Durations When Temperature Leaves the Range Specified by the Trip Points♦512 Bytes of General-Purpose Read/Write NV RAM ♦Communicates to Host with a Single Digital Signal at 15.4kbps or 125kbps Using 1-Wire ProtocolCommon iButton Features♦Digital Identification and Information by Momentary Contact♦Unique, Factory-Lasered, and Tested 64-BitRegistration Number (8-Bit Family Code + 48-BitSerial Number + 8-Bit CRC Tester) AssuresAbsolute Traceability Because No Two Parts areAlike ♦Multidrop Controller for 1-Wire Net ♦Chip-Based Data Carrier Compactly Stores Information♦Data Can Be Accessed While Affixed to Object♦Button Shape is Self-Aligning with Cup-ShapedProbes♦Durable Stainless-Steel Case Engraved withRegistration Number Withstands HarshEnvironments ♦Easily Affixed with Self-Stick Adhesive Backing,Latched by Its Flange, or Locked with a Ring Pressed Onto Its Rim♦Presence Detector Acknowledges When Reader First Applies Voltage ♦Meets UL 913 (4th Edit.); Intrinsically SafeApparatus: Approved Under Entity Concept for Usein Class I, Division 1, Group A, B, C and D LocationsDS1921GThermochron iButton________________________________________________________________Maxim Integrated Products1Ordering Information 19-5101; Rev 3; 4/10For pricing, delivery, and ordering information,please contact Maxim Direct at 1-888-629-4642,or visit Maxim’s website at .PART TEMP RANGE PIN-PACKAGEDS1921G-F5# -40°C to +85°C F5 iButton Examples of Accessories PART ACCESS ORY DS9096P Self-Stick AdhesivePadDS9101 Multipurpose Clip DS9093RA Mounting Lock RingDS9093A Snap-In FobDS9092 iButton ProbePin Configuration appears at end of data sheet.Thermochron, iButton, and 1-Wire are registered trademarks of Maxim Integrated Products, Inc.#Denotes a RoHS-compliant device that may include lead(Pb)that is exempt under the RoHS requirements.Temperature Logging in Cold Chain, Food Safety,Pharmaceutical, and Medical ProductsD S 1921GThermochron iButton 2_______________________________________________________________________________________ABSOLUTE MAXIMUM RATINGSELECTRICAL CHARACTERISTICSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.IO Voltage Range Relative to GND..........................-0.5V to +6V IO Sink Current....................................................................20mA Operating Temperature Range..........................-40°C to +85°C*Storage Temperature Range..............................-40°C to +50°C**Storage or operation above +50°C significantly reduces battery life.DS1921GThermochron iButton_______________________________________________________________________________________3times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily loaded systems, an active pullup such as that found in the DS2480B may be required.Note 3:Capacitance on IO could be 800pF when power is first applied. If a 2.2k Ωresistor is used to pull up the data line, 2.5µs after V PUP has been applied, the parasite capacitor does not affect normal communication.Note 4:These values are derived from simulation across process, voltage, and temperature and are not production tested.Note 5:Input load is to ground.Note 6:All voltages are referenced to ground.Note 7:V TL , V TH are a function of the internal supply voltage.Note 8:Voltage below which, during a falling edge of IO, a logic 0 is detected.Note 9:The voltage on IO must be less than or equal to V ILMAX whenever the master drives the line low.Note 10:Voltage above which, during a rising edge on IO, a logic 1 is detected.Note 11:The I-V characteristic is linear for voltages less than 1V.Note 12:Numbers in bold are not in compliance with the published iButton standards. See the Comparison Table .Note 13:εin Figure 15 represents the time required for the pullup circuitry to pull the voltage on the IO pin up from V IL to V TH .Note 14:δin Figure 15 represents the time required for the pullup circuitry to pull the voltage on the IO pin up from V IL to the input high threshold of the bus master.Note 15:This number was derived from a test conducted by Cemagref in Antony, France, in July 2000.http://www.cemagref.fr/English/index.htm Test Report No. E42Note 16:Total accuracy is Δϑplus 0.25°C quantization due to the 0.5°C digital resolution of the device.ELECTRICAL CHARACTERISTICS (continued)D S 1921GNote 17:WARNING:Not for use as the sole method of measuring or tracking temperature in products and articles that could affectthe health or safety of persons, plants, animals, or other living organisms, including but not limited to foods, beverages,pharmaceuticals, medications, blood and blood products, organs, flammable, and combustible products. User shallassure that redundant (or other primary) methods of testing and determining the handling methods, quality, and fitness of the articles and products should be implemented. Temperature tracking with this product, where the health or safety of the aforementioned persons or things could be adversely affected, is only recommended when supplemental or redundant information sources are used. Data-logger products are 100% tested and calibrated at time of manufacture by Maxim to ensure that they meet all data sheet parameters, including temperature accuracy. User shall be responsible for proper use and storage of this product. As with any sensor-based product, user shall also be responsible for occasionally rechecking the temperature accuracy of the product to ensure it is still operating properly.Note 18:The number of temperature conversions (= samples) possible with the built-in energy source depends on the operating andstorage temperature of the device. When not in use for a mission, the RTC oscillator should be turned off and the device should be stored at a temperature not exceeding +25°C. Under this condition the shelf life time is 10 years minimum.Thermochron iButton 4_______________________________________________________________________________________Note:Numbers in bold are not in compliance with the published iButton standards.ELECTRICAL CHARACTERISTICS (continued)(V PUP = +2.8V to +5.25V, T A = -40°C to +85°C.)DS1921GThermochron iButton_______________________________________________________________________________________5RTC Deviation vs. TemperatureMinimum Product Lifetime vs. Temperature at Different Sample RatesD S 1921GThermochron iButtonMinimum Product Lifetime vs. Sample Rate at Different TemperaturesAccuracy LimitsDetailed DescriptionThe DS1921G Thermochron iButton is an ideal device to monitor the temperature of any object it is attached to or shipped with, such as perishable goods or con-tainers of temperature-sensitive chemicals. The read/write NV memory can store an electronic copy of shipping information, date of manufacture and other important data written as clear as well as encrypted files. Note that the initial sealing level of the DS1921G achieves IP56. Aging and use conditions can degrade the integrity of the seal over time, therefore, for applica-tions with significant exposure to liquids, sprays, or other similar environments, it is recommended to placethe Thermochron in the DS9107 iButton capsule. The DS9107 provides a watertight enclosure that has been rated to IP68 (refer to Application Note 4126:Understanding the IP (Ingress Protection) Ratings of iButton Data Loggers and Capsule ).OverviewFigure 1 shows the relationships between the major control and memory sections of the DS1921G. The device has seven main data components: 64-bit lasered ROM; 256-bit scratchpad; 4096-bit general-purpose SRAM; 256-bit register page of timekeeping,control, and counter registers; 96 bytes of alarm time-stamp and duration logging memory; 126bytes ofDS1921GThermochron iButton_______________________________________________________________________________________7Figure 1. Block DiagramD S 1921GThermochron iButton8_______________________________________________________________________________________Figure 2. Hierarchical Structure for 1-Wire Protocolhistogram memory; and 2048 bytes of data-logging memory. Except for the ROM and the scratchpad, all other memory is arranged in a single linear address space. All memory reserved for logging purposes,including counter registers and several other regis-ters, is read-only for the user. The timekeeping and control registers are write protected while the device is programmed for a mission.The hierarchical structure of the 1-Wire protocol is shown in Figure 2. The bus master must first provide one of the seven ROM function commands: Read ROM,Match ROM, Search ROM, Conditional Search ROM,Skip ROM, Overdrive-Skip ROM, or Overdrive-Match ROM. Upon completion of an Overdrive ROM com-mand byte executed at standard speed, the device enters overdrive mode, where all subsequent communi-cation occurs at a higher speed. The protocol required for these ROM function commands is described in Figure 13. After a ROM function command is success-fully executed, the memory functions become accessi-ble and the master can provide any one of the sevenavailable commands. The protocol for these memory function commands is described in Figure 10. All data is read and written least significant bit first.Parasite PowerFigure 1 shows the parasite-powered circuitry. This cir-cuitry “steals” power whenever the IO input is high. IO provides sufficient power as long as the specified tim-ing and voltage requirements are met. The advantages of parasite power are two-fold: 1) By parasiting off this input, battery power is not consumed for 1-Wire ROM function commands, and 2) if the battery is exhausted for any reason, the ROM may still be read normally. The remaining circuitry of the DS1921G is solely operated by battery energy.64-Bit Lasered ROMEach DS1921G contains a unique ROM code that is 64bits long. The first 8 bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last 8 bits are a cyclic redundancy check (CRC) of the first 56 bits (see Figure 3 for details). The 1-Wire CRC is generatedDS1921GThermochron iButton_______________________________________________________________________________________9MSB8-BIT CRC CODE48-BIT SERIAL NUMBERMSBMSBLSB LSBLSB 8-BIT FAMILY CODE(21h)MSBLSB Figure 3. 64-Bit Lasered ROMFigure 4. 1-Wire CRC Generatorusing a polynomial generator consisting of a shift regis-ter and XOR gates as shown in Figure 4. The polynomi-al is X 8+ X 5 + X 4+ 1. Additional information about the 1-Wire CRC is available in Application Note 27:Understanding and Using Cyclic Redundancy Checks with Maxim iButton Products .The Shift register bits are initialized to 0. Then, starting with the least significant bit of the family code, one bit at a time is shifted in. After the 8th bit of the family code has been entered, the serial number is then entered.After the 48th bit of the serial number has been entered, the Shift register contains the CRC value.Shifting in the 8 bits of CRC returns the Shift register to all zeros.MemoryFigure 5 shows the DS1921G memory map. The 4096-bit general-purpose SRAM makes up pages 0 to 15.The timekeeping, control, and counter registers fill page 16, called register page (see Figure 6). Pages 17,18, and 19 are assigned to storing the alarm time-stamps and durations. The temperature histogram bins begin at page 64 and use up to four pages. The tem-perature-logging memory covers pages 128 to 191.Memory pages 20 to 63, 68 to 127, and 192 to 255 are reserved for future extensions. The scratchpad is an additional page that acts as a buffer when writing to the SRAM memory or the register page. The memory pages 17 and higher are read only for the user. They are written to or erased solely under the supervision of the on-chip control logic.D S 1921GThermochron iButton 10______________________________________________________________________________________32-BYTE INTERMEDIATE STORAGE SCRATCHPADADDRESS0000h to 01FFh GENERAL-PURPOSE SRAM (16 PAGES)PAGES 0 to 15 0200h to 021Fh 32-BYTE REGISTER PAGEPAGE 16 0220h to 027Fh ALARM TIMESTAMPS AND DURATIONS PAGES 17 to 19 0280h to 07FFh (RESERVED FOR FUTURE EXTENSIONS) PAGES 20 to 63 0800h to 087Fh TEMPERATURE HISTOGRAM MEMORY PAGES 64 to 67 0880h to 0FFFh (RESERVED FOR FUTURE EXTENSIONS) PAGES 68 to 127 1000h to 17FFh DATA-LOG MEMORY (64 PAGES) PAGES128 to 191 1800h to 1FFFh(RESERVED FOR FUTURE EXTENSIONS)PAGES 192 to 255Figure 5. Memory MapADDRESS BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0FUNCTION ACCESS*0200h 0 10 Seconds Single Seconds 0201h10 MinutesSingle Minutes 0202h 0 12/2420 HourAM/PM 10 Hour Single Hours0203h 0 0 0 0 0Day of Week0204h10 Date Single Date 0205h CENT 0 010 MonthsSingle Months 0206h 10 YearsSingle Years RTCRegistersR/W R/W**0207h MS 10 Seconds Alarm Single Seconds Alarm 0208hMM10 Minutes AlarmSingle Minutes Alarm 0209h MH 12/24 20 HourAM/PMAlarm 10 HourAlarmSingle Hours Alarm020Ah MD 0 0 0 0 Day of Week AlarmRTC Alarm RegistersR/W R/W**020Bh Temperature Low Alarm Threshold 020Ch Temperature High Alarm ThresholdTemperatureAlarms R/W R/W** 020Dh Number of Minutes Between Temperature ConversionsSample RateR/W R** 020Eh EOSC EMCLREM RO TLS THS TAS Control R/W R/W**020Fh(No function, reads 00h)—RR**Figure 6. Register Pages Map *The left entry in the ACCESS column is valid between missions. The right entry shows the applicable access mode while amission is in progress.**While a mission is in progress, these addresses can be read. The first attempt to write to these registers (even read-only ones), however, ends the mission and overwrites selected writable registers.DS1921GThermochron iButtonADDRESS BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0FUNCTIONACCESS*0210h(No function, reads 00h)—RR**0211h Temperature Read-Out (Forced Conversion) Temperature RR** 0212h Low Byte 0213h High Byte Mission Start Delay R/W R/W** 0214hTCB MEMCLR MIPSIPTLFTHFTAFStatusR/W R/W0215h Minutes 0216h Hours0217h Date0218h Month 0219h YearMission TimestampR R 021Ah Low Byte 021Bh Center Byte 021Ch High Byte Mission Samples Counter R R 021Dh Low Byte 021Eh Center Byte 021Fh High Byte Device Samples CounterR RFigure 6. Register Pages Map (continued)*The left entry in the ACCESS column is valid between missions. The right entry shows the applicable access mode while a mission is in progress.**While a mission is in progress, these addresses can be read. The first attempt to write to these registers (even read-only ones), however, ends the mission and overwrites selected writable registers.Detailed Register DescriptionsTimekeepingThe RTC/alarm and calendar information is accessed by reading/writing the appropriate bytes in the register page, address 0200h to 0206h. Note that some bits are set to 0. These bits always read 0 regardless of how they are written. The contents of the time, calendar, and alarm registers are in the binary-coded decimal (BCD)format.RTC/CalendarThe RTC of the DS1921G can run in either 12hr or 24hr mode. Bit 6 of the Hours register (address 0202h) is defined as the 12hr or 24hr mode select bit. When high,the 12hr mode is selected. In the 12hr mode, bit 5 is the AM/PM bit with logic 1 being PM. In the 24hr mode, bit 5 is the 20hr bit (20hr to 23hr).To distinguish between the days of the week, the DS1921G includes a counter with a range from 1 to 7.The assignment of a counter value to the day of week is arbitrary. Typically, the number 1 is assigned to a Sunday (U.S. standard) or to a Monday (European stan-dard).The calendar logic is designed to automatically com-pensate for leap years. For every year value that is either 00 or a multiple of four, the device adds a 29th of February. This works correctly up to (but not including)the year 2100.The DS1921G is Y2K compliant. Bit 7 (CE NT) of the Months register at address 0205h serves as a century flag. When the Year register rolls over from 99 to 00, the century flag toggles. It is recommended to write the century bit to a 1 when setting the RTC to a time/date between the years 2000 and 2099.D S 1921GRTC AlarmsThe DS1921G also contains an RTC alarm function. The RTC Alarm registers are located in registers 0207h to 020Ah. The most significant bit of each of the alarm registers is a mask bit. When all the mask bits are logic 0, an alarm occurs once per week when the values stored in timekeeping registers 0200h to 0203h match the values stored in the RTC Alarm registers. Any alarm sets the timer alarm flag (TAF) in the device’s Status register (address 214h). The bus master can set the search conditions in the Control register (address 20Eh) to identify devices with timer alarms by means of the conditional search function (see the ROM Function Commands section).Thermochron iButtonTemperature Conversion The DS1921G measures temperatures with a resolution of 0.5°C. Temperature values are represented in a sin-gle byte as an unsigned binary number, which trans-lates into a theoretical range of 128°C. The range, however, has been limited to values from 0000 0000 (00h) through 1111 1010 (FAh). The codes 01h to F9h are considered valid temperature readings.If a temperature conversion yields a temperature that is out of range, it is recorded as 00h (if too low) or FAh (if too high). Since out-of-range results are accumulated in histogram bins 0 and 62 (see the Temperature Logging and Histogram section), the data in these bins is of lim-ited value. For this reason the specified temperature range of the DS1921G is considered to begin at code 04h and end at code F7h, which corresponds to his-togram bins 1 to 61.With T[7…0] representing the decimal equivalent of a tem-perature reading, the temperature value is calculated asϑ(°C) = T[7…0]/2 - 40.0This equation is valid for converting temperature read-ings stored in the data-log memory as well as for data read from the Forced Temperature Conversion Readout register (address 0211h).To specify the temperature alarm thresholds, this equa-tion needs to be resolved toT[7…0] = 2 x ϑ(°C) + 80.0A value of 23°C, for example, thus translates into 126 decimal or 7Eh. This corresponds to the binary patterns0111 1110, which could be written to a TemperatureAlarm register (address 020Bh and 020Ch, respectively).Sample RateThe content of the Sample Rate register (address020Dh) determines how many minutes the temperature conversions are apart from each other during a mission.The sample rate can be any value from 1 to 255, codedas an unsigned 8-bit binary number. If the memory hasbeen cleared (Status register bit ME MCLR = 1) and a mission is enabled (Control register bit EM= 0), writinga nonzero value to the Sample Rate register starts a mis-sion. For a full description of the correct sequence ofsteps to start a temperature-logging mission, see the Missioning or Mission E xample: Prepare and Start aNew Mission sections.DS1921G Thermochron iButtonD S 1921GControl RegisterThe DS1921G is set up for its operation by writing appropriate data to its special function registers that are located in the register page. Several functions that are controlled by a single bit only are combined into a single byte called the Control register (address 020Eh).This register can be read and written. If the device is programmed for a mission, writing to the Control regis-ter ends the mission and changes the register contents.The functional assignments of the individual bits are explained below. Bit 5 has no function. It always reads 0 and cannot be written to 1.Bit 7: Enable Oscillator (EOSC ). This bit controls the crystal oscillator of the RTC. When set to logic 0, the oscillator starts operation. When written to logic 1, the oscillator stops and the device is in a low-power data-retention mode. This bit must be 0 for normal opera-tion.The RTC must have advanced at least 1 second before a Mission Start is accepted.Bit 6: Memory Clear Enable (EMCLR). This bit needs to be set to logic 1 to enable the Clear Memory func-tion, which is invoked as a memory function command.The timestamp, histogram memory as well as the Mission Timestamp, Mission Samples Counter, Mission Start Delay, and Sample Rate are cleared only if the Clear Memory command is issued with the next access to the device . The E MCLR bit returns to 0 as the next memory function command is executed.Bit 4: Enable Mission (EM ). This bit controls whether the DS1921G begins a mission as soon as the sample rate is written. To enable the device for a mission, this bit must be 0.Bit 3: Rollover Enable/Disable (RO). This bit controls whether the temperature logging memory is overwritten with new data or whether data logging is stopped once the memory is filled with data during a mission. Setting this bit to a 1 enables the rollover and data logging continues at the beginning, overwriting previously col-lected data. Clearing this bit to 0 disables the rolloverand no further temperature values are stored in the temperature logging memory once it is filled with data.This does not stop the mission. The device continues measuring temperatures and updating the histogram and alarm timestamps and durations.Bit 2: Temperature L ow Alarm Search (TL S). If this bit is 1, the device responds to a Conditional Search ROM command if, during a mission, the temperature has reached or is lower than the Low Temperature Threshold stored at address 020Bh.Bit 1: Temperature High Alarm Search (THS). If this bit is 1, the device responds to a Conditional Search ROM command if, during a mission, the temperature has reached or is higher than the High Temperature Threshold stored at address 020Ch.Bit 0: Timer Alarm Search (TAS). If this bit is 1, the device responds to a Conditional Search ROM com-mand if, during a mission, a timer alarm has occurred.Since a timer alarm cannot be disabled, the TAF flag usually reads 1 during a mission. Therefore, it is advis-able to set the TAS bit to a 0, in most cases.Mission Start Delay CounterThe content of the Mission Start Delay Counter register determines how many minutes the device waits before starting the logging process. The Mission Start Delay value is stored as an unsigned 16-bit integer number at addresses 0212h (low byte) and 0213h (high byte). The maximum delay is 65,535 minutes, equivalent to 45days, 12 hours, and 15 minutes.For a typical mission, the Mission Start Delay is 0. If a mission is too long for a single DS1921G to store all temperature readings at the selected sample rate, one can use several devices, staggering the Mission Start Delay to record the full period. In this case, the rollover enable (RO) bit in the Control register (address 020Eh)must be set to 0 to prevent overwriting of the recorded temperature log after the data-log memory is full. See the Mission Start and Logging Process section and Figure 11 for details.Thermochron iButtonStatus Register The Status register holds device status information and alarm flags. The register is located at address 0214h. Writing to this register does not necessarily end a mission.The functional assignments of the individual bits are explained below. The bits MIP, TLF, THF, and TAF can only be written to 0. All other bits are read-only. Bit 3 has no function.Bit 7: Temperature Core Busy (TCB). If this bit reads 0, the DS1921G is currently performing a temperature conversion. This temperature conversion is either self-initiated because of a mission being in progress or initi-ated by a command when a mission is not in progress. The TCB bit goes low just before a conversion starts and returns to high just after the result is latched into the Read-Out register at address 0211h.Bit 6: Memory Cleared (MEMCLR). If this bit reads 1, the memory pages 17 and higher (alarm timestamps/ durations, temperature histogram, excluding data-log memory), as well as the Mission Timestamp, Mission Samples Counter, Mission Start Delay, and Sample Rate have been cleared to 0 from executing a Clear Memory function command. The MEMCLR bit returns to 0 as soon as writing a nonzero value to the Sample Rate register starts a new mission, provided that the EM bit is also 0. The memory has to be cleared in order for a mission to start.Bit 5: Mission in Progress (MIP). If this bit reads 1, the DS1921G has been set up for a mission and this mis-sion is still in progress. A mission is started if the EM bit of the Control register (address 20Eh) is 0 and a nonze-ro value is written to the Sample Rate register, address 20Dh. The MIP bit returns from logic 1 to logic 0 when a mission is ended. A mission ends with the first write attempt (Copy Scratchpad command) to any register in the address range of 200h to 213h. Alternatively, a mis-sion can be ended by directly writing to the Status reg-ister and setting the MIP bit to 0. The MIP bit cannot beset to 1 by writing to the Status register.BIT 4: Sample in Progress (SIP). If this bit reads 1, theDS1921G is currently performing a temperature conver-sion as part of a mission in progress. The mission sam-ples occur on the seconds rollover from 59 to 00. TheSIP bit changes from 0 to 1 approximately 250ms before the actual temperature conversion begins allow-ing the circuitry of the chip to wake up. A temperature conversion including a wake-up phase takes maximum875ms. During this time, read accesses to the memorypages 17 and higher are permissible but can reveal invalid data.Bit 2: Temperature L ow Flag (TL F). Logic 1 in the temperature low flag bit indicates that a temperature measurement during a mission revealed a temperatureequal to or lower than the value in the Temperature Low Threshold register. The temperature low flag can be cleared at any time by writing this bit to 0. This flagmust be cleared before starting a new mission.Bit 1: Temperature High Flag (THF). Logic 1 in the temperature high flag bit indicates that a temperature measurement during a mission revealed a temperatureequal to or higher than the value in the TemperatureHigh Threshold register. The temperature high flag canbe cleared at any time by writing this bit to 0. This flagmust be cleared before starting a new mission.Bit 0: Timer Alarm Flag (TAF). If this bit reads 1, aRTC alarm has occurred (see the Timekeeping sectionfor details). The timer alarm flag can be cleared at anytime by writing this bit to logic 0. Since the timer alarm cannot be disabled, the TAF flag usually reads 1 duringa mission. This flag should be cleared before starting anew mission.DS1921G Thermochron iButton。

IC datasheet pdf-THS5661A,pdf(12-Bit, 125 MSPS, CommsDAC Digital-to-Analog Converter)

SLAS247B − NOVEMBER 1999 REVISED SEPTEMBER 2002
THS5661A 12ĆBIT, 125 MSPS, CommsDAC DIGITALĆTOĆANALOG CONVERTER
D Member of the Pin-Compatible D D D D D D D D D D
CommsDAC Product Family 125 MSPS Update Rate 12-Bit Resolution Spurious Free Dynamic Range (SFDR) to Nyquist at 40 MHz Output: 60 dBc 1 ns Setup/Hold Time Differential Scalable Current Outputs: 2 mA to 20 mA On-Chip 1.2 V Reference 3 V and 5 V CMOS-Compatible Digital Interface Straight Binary or Twos Complement Input Power Dissipation: 175 mW at 5 V, Sleep Mode: 25 mW at 5 V Package: 28-Pin SOIC and TSSOP
Copyright 2002, Texas Instruments Incorporated
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SLAS247B − NOVEMBER 1999 REVISED SEPTEMBER 2002
THS5661A 12ĆBIT, 125 MSPS, CommsDAC DIGITALĆTOĆANALOG CONVERTER

IC datasheet pdf-TPIC8101,pdf(Knock Sensor Interface)

KNOCKKNOCKKNOCKInput SignalInt/Hold SignalOutput SignalFigure 3. Amplified Input Signal ProcessInput SignalInt/Hold SignalOutput SignalFigure 4. Input Signal ProcessingKNOCKPACKAGE OPTION ADDENDUM 16-Jul-2010Addendum-Page 1PACKAGING INFORMATION Orderable DeviceStatus (1)Package Type Package Drawing Pins Package Qty Eco Plan (2)Lead/Ball Finish MSL Peak Temp (3)Samples (Requires Login)TPIC8101DWACTIVE SOIC DW 2025Green (RoHS & no Sb/Br)CU NIPDAU Level-3-260C-168 HR/Level-1-235C-UNLIM Contact TI Distributor or Sales Office TPIC8101DWG4ACTIVE SOIC DW 20TBD Call TI Call TI Purchase Samples TPIC8101DWRACTIVE SOIC DW 202000Green (RoHS & no Sb/Br)CU NIPDAU Level-3-260C-168 HR/Level-1-235C-UNLIM Request Free Samples TPIC8101DWRG4ACTIVE SOIC DW 20TBD Call TI Call TI Purchase Samples (1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check /productcontent for the latest availability information and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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IC datasheet pdf-CD54AC245,CD74AC245,CD54ACT245,CD74ACT245,pdf(Octal-Bus Transceiver,Three-State, No

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA DC Output Source or Sink Current per Output Pin, IO
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC (Note 4)
AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Slew Rate, dt/dv AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max) AC Types, 3.6V to 5.5V . . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max) ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)

IC datasheet pdf-MAXQ2010评估套件

BIT 3 COM3 1A 1H 2A 2H 3A 3H 4A 4H 5A 5H 6A 6H 7A 7H 8A 8H
BIT 2 COM2 1B 1G 2B 2G 3B 3G 4B 4G 5B 5G 6B 6G 7B 7G 8B 8G
BIT 1 COM1 1C 1N 2C 2N 3C 3N 4C 4N 5C 5N 6C 6N 7C 7N 8C 8N
QTY
DESCRIPTION 100nF ±10%, 10V ceramic capacitors (0805) Murata GRM219R71C104KA01D 10nF ±5%, 10V ceramic capacitors (0805) Murata GRM21BR72A103KA01L 22pF ±5%, 10V ceramic capacitors (0805) Murata GRM2195C2A220JZ01D 4.7μF ±10%, 10V ceramic capacitors (0805) Murata GRM219R61A475KE19D 10μF ±10%, 10V capacitors (0805) Murata GRM21BR61A106KE19L Empty capacitor footprint (0805) 1μF ±10%, 10V ceramic capacitors (0805) Murata GRM21BR71C105KA01L Green surface-mount LEDs Lumex SML-LX0805SUGC-TR Red surface-mount LED Lumex SML-LX0805SIC-TR
BIT 6 COM2 1F 1J 2F 2J 3F 3J 4F 4J 5F 5J 6F 6J 7F 7J 8F 8J

tpic1021中文

TPIC1021中文版 DATASHEET翻译: Nforver of WEE特征l遵守LIN物理层规范2.0版本,符合SAEJ2602标准l LIN总线速率达到20kbpsl LIN口静电保护电压达12kV(人体放电)l LIN口处理电压范围为-40V到+40Vl短暂损害试验抗扰动能力强l工作电压范围为直流7V-27V之间l两种工作模式:正常模式和睡眠模式l睡眠模式低电流消耗l可以通过LIN总线或唤醒开关及微控制器(MCU)来唤醒l与MCU的接口为5V或3.3V I\O口l TXD口显性状态超时保护l RXD口唤醒请求l外部电压调节器控制（INH口）l整合上拉电阻和串联二极管以配合LIN从机应用l低电磁干扰,抗干扰能力强l总线终端短路保护以保护总线对电源对地的短路l热地保护l系统水平地线隔离l系统水平地线移位操作l未工作节点不影响网络描述TPIC1021是串行工作LIN物理接口器件,具有唤醒和保护功能。

LIN总线的单一的双向总线用于低速波特率网络速度在2.4到20kbps之间。

LIN总线有两种逻辑状态：显性状态(电压近地)代表了逻辑0。

隐性状态(近电源电压)逻辑1 。

在隐性状态由于TPIC1021内部上拉电阻(3 KΩ)和串联二极管LIN总线会被拉高，所以作为从机应用时无需额外的上拉组件，作为主机时需加上拉电阻（1KΩ）并串联二极管。

LIN协议数据流通过TXD口经TPIC1021内部限流整流低边驱动器转换成符合LIN物理层规范2.0版的LIN总线信号。

接收器通过RXD口来接收经TPIC1021转换的从LIN总线过来的数据流。

在低功率模式,TPIC1021需要非常低的静态电流即使唤醒电路保持活跃，允许来自LIN总线远程唤醒、本地NWake唤醒或EN口唤醒。

TPIC1021被设计成可操作于严酷的汽车环境中。

该器件可处理LIN总线从40v~-40v的电压摆动，还可以防止由于地线移位或电源断开导致的LIN口到芯片供电端的电流回流。

IC datasheet pdf-24LCS22A pdf datasheet

—
400
4.5V ≤ VCC ≤ 5.5V
2
THIGH
Clock high time
4000 600
—
ns 2.5V ≤ VCC ≤ 5.5V
—
4.5V ≤ VCC ≤ 5.5V
3Leabharlann TLOWClock low time
4700 1300
—
ns 2.5V ≤ VCC ≤ 5.5V
—
4.5V ≤ VCC ≤ 5.5V
for monitor identification, including recovery to DDC1
• 2 Kbit Serial EEPROM Low-power CMOS technology:
- 1 mA active current, typical - 10 μA standby current, typical at 5.5V • 2-wire serial interface bus, I2C™ compatible
—
V VCC ≥ 2.7V (Note)
D4
VIL
Low-level input voltage
—
0.2 VCC V VCC ≤ 2.7V (Note)
D5
VHYS
Hysteresis of Schmitt Trigger .05 VCC
—
Inputs
V (Note)
D6
VOL1
Low-level output voltage
TABLE 1-1: DC CHARACTERISTICS
DC CHARACTERISTICS
Vcc = +2.5V to 5.5V Industrial (I): TA = -40°C to +85°C

YC1021 datasheet-易兆微电子最新多模蓝牙芯片规格书

Yichip Microelectronics1 / 3YC1021Bluetooth 4.1 + 3.0 (EDR) + 2.4GHz-ProprietaryPreliminary BriefYichip Microelectronics©2013Yichip Microelectronics2 / 3General DescriptionThe YC1021 is a very low power, high performance and highly integrated Bluetooth 4.1 BR/EDR + BLE +2.4G Proprietary triple-mode solution, designed for operation over the 2400MHz to 2483.5Mhz ISM frequency band.YC1021 is manufactured using advanced 55nm CMOS low leakage process, which offers highest integration, lowest power consumption, lowest leakage current and reduced BOM cost while simplifying the overall system design. Rich peripherals including an 8 channel general purpose ADC, power-on-reset (POR), Arithmetic Accelerators, USB2.0, 3axis Q-decoder, ISO7816, UART/SPI/I2C and up to 32 GPIOs, which further reduce overall system cost and size.YC1021 operates with a power supply range from 1.8 to 5.5V and has very low power consumption in both Tx and Rx modes, enabling long lifetimes in battery-operated systems while maintaining excellent RF performance. The device can enter an ultra low power sleep mode in which the registers and retention memory content are retained while low power Oscillator and sleep timer is ON.Different package from QFN4x4_32L(upto 17 GPIOs) to QFN7x7_56L (upto 32 GPIOs) is available.Key Features ● Bluetooth 4.1 BR/EDR+BLE+2.4GHz-Proprietary triple-mode RF SOC ● Very Low Power Consumption ● 10nA shut down mode (external interrupts) ● 620nA sleep mode ( 32kHz RC OSC, sleep timer and register ON) ● 2uA retention mode ( 32kHz RC OSC, sleep timer, 2k retention memory and register ON) ● Rx peak current @3V (ideal DCDC) ⏹ 6.75mA in BLE/2.4G mode⏹ 7.25mA in in 3.0(EDR) mode ● Tx peak current @3V (-2dBm, ideal DCDC) ⏹ 16.5mA in BLE/2.4G mode ⏹ 17mA in in 3.0(EDR) mode ● Rx peak current w/o DCDC ⏹ 16mA in BLE/2.4G mode ⏹ 17mA in 3.0(EDR) mode ● Tx peak current w/o DCDC @ -2dBm ⏹ 22mA in BLE/2.4G mode ⏹ 23mA in 3.0(EDR) mode ● <25uA avg, 500ms sniff hold connection ● 2.4GHz Transceiver ● Single-end RFIO ● -93dBm in BLE mode ● support 250kbps, 1/2/3Mbps data rates ● Tx Power upto +6dBm● Oscillators ● 16M/24M/32M XTAL supported (default 24M)● 50M RC oscillator● Low Jitter 32K RC oscillator● Dual Core Digital Architecture● 8051 Core for application⏹ 16kB code RAM● 32bit-Risc Core for link management⏹ 80kB code ROM⏹ 8kB code RAM⏹ All RAMs can be set to retention mode● Arithmetic Accelerators [Accuracy : (sign, 15b.16b)] ● sin/cos/tan/sin -1/cos -1/tan -1/ multi/div/sqrt● Analog Peripherals● 8 channel ADC with 10 bit accuracy/3Msps● Digital Peripherals● USB 2.0 full speed (12Mbps)● Two-wire Master (I2C compatible), upto 400kbps; UART(RTS/CTS) with HCI-H5 protocol, upto 3.25Mbps; SPI Master, upto24Mbps● ISO7816● AES128 HW encryption● LED drive capability● PWM● 20x8 keyscan● 3 axis Q-decoderYichip Microelectronics 3 / 3Package Variants●QFN 7x7 56L ●QFN 6x6 48L ●QFN 4x4 32L ●Die Applications ● Sports & Fitness ● Healthcare & medical ● Remote control ● PC peripherals (mouse, keyboard) ●Game control ● Mobile phone accessories● TV Setup Boxs● SPP● 3D Glasses。

IC datasheet pdf-TPA6203A1,pdf(1.25-W Mono Fully Differential Audio Power Amplifier)

RECOMMENDED OPERATING CONDITIONS
MIN Supply voltage, VDD High-level input voltage, VIH Low-level input voltage, VIL Common-mode input voltage, VIC Operating free-air temperature, TA Load impedance, ZL SHUTDOWN SHUTDOWN VDD = 2.5 V, 5.5 V, CMRR ≤ -60 dB 0.5 -40 6.4 8 2.5 2 0.8 VDD-0.8 85 TYP MAX 5.5 UNIT V V V V °C Ω
1.25-W MONO FULLY DIFFERENTIAL AUDIO POWER AMPLIFIER
1
FEATURES
APPLICATIONS
• Designed for Wireless or Cellular Handsets and PDAs
• 1.25 W Into 8 Ω From a 5-V Supply at THD = 1% (Typical) • Low Supply Current: 1.7 mA Typical • Shutdown Control < 10 µA • Only Five External Components – Improved PSRR (90 dB) and Wide Supply Voltage (2.5 V to 5.5 V) for Direct Battery Operation – Fully Differential Design Reduces RF Rectification – Improved CMRR Eliminates Two Input Coupling Capacitors – C(BYPASS) Is Optional Due to Fully Differential Design and High PSRR • Avaliable in a 2 mm x 2 mm MicroStar Junior ™ BGA Package (GQV, ZQV) • Available in 3 mm x 3 mm QFN Package (DRB) • Available in an 8-Pin PowerPAD™ MSOP (DGN)

IC datasheet pdf-ATA6140 pdf,datasheet

Features•Temperature and Voltage Compensated Frequency (Fully Integrated Oscillator)•Warning Indication of Lamp Failure by Means of Frequency Doubling•Voltage Dependence of the Indicator Lamps also Compensated for Lamp Failure •Relay Output with High Current Capability and Low Saturation Voltage •Frequency Doubling only During Direction Mode•Temperature Compensated Threshold for Lamp Failure Detection •Overvoltage and Undervoltage Shut Down of the Relay Outputs •Quiescent Current I ≤ 10 µA (Switches Open)•EMI Protection According to ISO TR 7637/1, Test Level 4 (Exclusive Load Dump)•Reversed Battery Protection by Means of a Serial Resistor and Relay Coil Connected •Load Dump Protection 80V with External Protection Components •12V/24V Application •Package: SO16Electrostatic sensitive device.Observe precautions for handling.1.DescriptionThe integrated circuit ATA6140 is used in relay-controlled automotive flashers. With two output stages, each side of the vehicle is controlled separately. A left and a right direction indicator input with only a small control current makes switch contacts for small loads possible. The separate hazard warning input simplifies the construction ofthe hazard switch. Lamp outage is indicated by frequency doubling during direction mode. Thanks to the extreme low current consumption the ATA6140 can be con-nected to the battery directly.24560E–AUTO–09/05ATA6140Figure 1-1.Block Diagram34560E–AUTO–09/05ATA61402.Pin ConfigurationFigure 2-1.Pinning SO16Table 2-1.Pin DescriptionPin Symbol DirectionFunction1TS1G In Input left turn switch to ground (1)2TS1B In Input left turn switch to battery (1)3TS2G In Input right turn switch to ground 4TS2B In Input right turn switch to battery 5OUTPUT RIGHTOut Relay driver right side 6BA TT Supply Power battery voltage Battery force 7OUTPUT LEFTOut Relay driver left side 8IGN In Ignition input9LEDInOpen: regular frequencySwitch to IC-ground: LED outage left side, external signal frequency doubling left side (2)10LED In Open: normal workSwitch to IC-ground: LED outage right side, external signal frequency doubling right side (2)11HAZIn Input switch to hazard warning 12MEASURE INPUTIn Voltage drop at the shunt resistor1324VIn Switch to 24V version:Open enables overvoltage shut down function, connecting to IC-ground disables overvoltage shut down function14BA TTERY SENSEInSense battery voltage for the internal comparator with high precision 15TEST PIN Either not connected or connected to IC-ground16IC-GROUNDSupplyIC-groundNote:e either switches to ground pin 1 and 3 or switches to battery pin 2 and 42.These pins can be connected optional by using LED flashlights to indicate outage. If a LED pin is on low level, frequencydoubling is active, independent of pin MEASURE INPUT.44560E–AUTO–09/05ATA61403.Absolute Maximum RatingsStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Parameters Symbol Value Unit Supply voltage, pin 6V VS 6 to 40V Ambient temperature range T amb –40 to +105°C Junction temperature range T j –40 to +150°C Storage temperature rangeT stg–55 to +150°C4.Thermal ResistanceParametersSymbol Value Unit Maximum thermal resistance SO16R thJA110K/W5.Operating RangeParameters Symbol Value Unit Supply voltage, pin 6V VS 6 to 24V Supply voltage, pin 6(24V version, pin 13 to GND)V VS18 to 33V6.Noise and Surge ImmunityParametersTest Conditions Value Conducted interferences (1)ISO 7637-1Level 4ESD (Human Body Model)MIL-STD-883D Method 3015.7(2)2 kV MIL-STD-883D Method 3015.7 (pin 12 and pin 14) 1 kV ESD FCDM (Field induced Charge Device Model)ESD - S. 5.3500VNote:1.At both outputs a relay of minimum 130 Ω should be added (for details see application circuits Figure 11-2 on page 8 toFigure 11-9 on page 12).2.Exclusive pin 12 and pin 14.54560E–AUTO–09/05ATA61407.Electrical CharacteristicsNo.ParametersTest ConditionsPinSymbolMin.Typ.Max.UnitType*1Supply Voltage Range1.1Supply voltage 6V VS 816V C 1.1Supply voltage (24V version)6V VS1833VC2Current Consumption 2.1Quiescent current (V S )V VS < 16V switches open 6I VS 10µA A 2.1Quiescent current (V S , 24V version)V VS < 33V switches open 6I VS 20µA A 2.2Supply current (V S )V VS < 16V6I VS 6mA A 2.2Supply current(V S , 24V version)V VS < 33V6I VS8mAA3Under and Overvoltage Detection 3.1Undervoltage detection threshold6V VU 68V A 3.2Undervoltage detection delay timet dUV2.510ms A3.3Overvoltage detection threshold6V VO 1822V A 3.3Overvoltage detection threshold (24V version)Disabled in 24V version (pin 13 to GND)6V VOVA4RelayOutputs 4.1Current output right 5I I5170mA A 4.2Current output left7I I7170mA A 4.3Saturation voltage right 170 mA at 23°C 5V SATR 1V A 4.4Saturation voltage left 170 mA at 23°C 7V SA TL 1V A 4.5Leakage current right 5I LEAKR 3µA A 4.5Leakage current right (24V version)5I LEAKR 6µA A 4.6Leakage current left 7I LEAKL 3µA A 4.6Leakage current left (24V version)7I LEAKL 6µA A 4.7Start delay time right 5T DR 1040ms A 4.8Start delay time left 7T DL 1040ms A 5Control Signal Thresholds 5.1Frequency doubling V S = 9V 12V THFD9424548mV A 5.2Frequency doubling V S = 15V 12V THFD15505357mV A 5.2Frequency doubling (24V version)V S = 24V 12V THFD2465mVA 5.3Short circuit detection V S = 13.5V 12V THSC 425475525mVB 5.3Short circuit detection (24V version)V S = 24V 12V THSC650mVB*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter64560E–AUTO–09/05ATA61408.Short Circuit or Overload Detection DelayDirection mode:100 ms during the first bright phase, 50 ms during all following bright phases Hazard mode: 100 ms during all bright phasesIn case of overload the relay output switches off (not stored)9.Bulb Outage DetectionThe detection of bulb outage takes place during the bright phase. There is a delay time of typi-cally 128 ms before ATA6140 measures the bulb current with a debounce period of 5 ms. After this time the inrush current dropped significantly.Application hint:It has to be considered that a slow relay contact may shorten the inrush current decay time and too high current would be measured and falsely an outage may not be detected. If operated with low supply voltage (e.g., 8V) the relay speed could be even slower.5.4Temperature coefficient –40°C to +105°C12C TH 30µV/K C 5.5Input current V S = 13.5 V 12I TH 2µA A 5.5Input current (24V version)V S = 24V12I TH4µAA6LED Inputs 6.1Threshold left V S = 13.5V 9V LEDL 1 4.5V A 6.2Threshold right V S = 13.5V10V LEDR 1 4.5V A 6.3Pull-up resistor left 9R LEDL 1075k ΩA 6.4Pull-up resistor right 10R LEDR1075k ΩA7Timing 7.1Basic frequency 1/f = 706 msF B–10.5+12%A 7.2Bright period50%A 7.3Bright period in failure mode40%A 7.4Failure frequency F F2.2 × F BA7.5Debounce timeBulb outage detection123.656.2ms7.Electrical Characteristics (Continued)No.Parameters Test Conditions Pin Symbol Min.Typ.Max.Unit Type**) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter74560E–AUTO–09/05ATA614010.Flasher Operating ModeIgnition Input Left Ground Input Right Ground Input Left Ignition Input Right Ignition Input Hazard Left Lamps (1)Right Lamps (1)Frequency in Case of Lamp Failure (1)Off Open Open IC-ground IC-ground Open x x x Off Ground Open IC-ground IC-ground Open x x x Off Open Ground IC-ground IC-ground Open x x x Off Open Open IC-ground IC-ground Ground Flash Flash Normal Off Ground Open IC-ground IC-ground Ground Flash Flash Normal Off Open Ground IC-ground IC-ground Ground Flash Flash Normal Off Ground Ground IC-ground IC-ground Ground Flash Flash Normal Off Ground Ground IC-ground IC-ground Open x x x (2)On Open Open IC-ground IC-ground Open x x x On Ground Open IC-ground IC-ground Open Flash x Double On Open Ground IC-ground IC-ground Open x Flash Double On Open Open IC-ground IC-ground Ground Flash Flash Normal On Ground Open IC-ground IC-ground Ground Flash Flash Normal On Open Ground IC-ground IC-ground Ground Flash Flash Normal On Ground Ground IC-ground IC-ground Ground Flash Flash Normal On Ground Ground IC-ground IC-ground Open Flash Flash Normal Off V BATT V BATT Open Open Open x x x Off V BATT V BATT Ignition Open Open x x x Off V BATT V BATT Open Ignition Open x x x Off V BATT V BATT Open Open Ground Flash Flash Normal Off V BATT V BATT Ignition Open Ground Flash Flash Normal Off V BATT V BATT Open Ignition Ground Flash Flash Normal Off V BATT V BATT Ignition Ignition Ground Flash Flash Normal Off V BATT V BATT Ignition Ignition Open x x x (3)On V BATT V BATT Open Open Open x x x On V BATT V BATT Ignition Open Open Flash x Double On V BATT V BATT Open Ignition Open x Flash Double On V BATT V BATT Open Open Ground Flash Flash Normal On V BATT V BATT Ignition Open Ground Flash Flash Normal On V BATT V BATT Open Ignition Ground Flash Flash Normal On V BATT V BATT Ignition Ignition Ground Flash Flash Normal On V BATTV BATTIgnitionIgnitionOpenFlashFlashNormalNotes:1.x = no flashing2.If ignition is OFF , the input level cannot be sensed (the IC is in the sleep mode). For hazard mode use the input hazard.3.For hazard mode use input hazard or switch to battery as shown in Figure 11-4 on page 9 and Figure 11-8 on page 11.84560E–AUTO–09/05ATA614011.DiagramsFigure 11-1.Timing DiagramFigure 11-2.Application 1: 12V Version, Turn Signal Switches to GND, Hazard Switch to GND94560E–AUTO–09/05ATA6140Figure 11-3.Application 2: 12V Version, Turn Signal Switches to Ignition, Hazard Switch to GNDFigure 11-4.Application 3: 12V Version, Turn Signal Switches to Ignition, Hazard Switch to Battery104560E–AUTO–09/05ATA6140Figure 11-5.Application 4: 12V Version, Turn Signal Switches to Ignition, Hazard Switch to GND, additional LED OutageFigure 11-6.Application 1: 24V Version, Turn Signal Switches to GND, Hazard Switch to GND114560E–AUTO–09/05ATA6140Figure 11-7.Application 2: 24V Version, Turn Signal Switches to Ignition, Hazard Switch to GNDFigure 11-8.Application 3: 24V Version, Turn Signal Switches to Ignition, Hazard Switch to Battery124560E–AUTO–09/05ATA6140Figure 11-9.Application 4: 24V Version, Turn Signal Switches to Ignition, Hazard Switch to GND, additional LED Outage134560E–AUTO–09/05ATA614013.Package Information14.Revision History12.Ordering InformationExtended Type Number Package RemarksA T A6140-TBQYSO16Taped and reeled, Pb-freePlease note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document.Revision No.History4560E-AUTO-09/05• Put datasheet in a new template • Pb-free logo on page 1 added• Ordering Information on page 13 changed4560E–AUTO–09/05© Atmel Corporation 2005. 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单片机数字电压表论文中英文资料对照外文翻译

单片机数字电压表论文中英文资料对照外文翻译中英文资料对照外文翻译文献综述外文资料digital voltage meter Based on single-chip technologySingle chip is an integrated on a single chip a complete computer system. Even though most of his features in a small chip, but it has a need to complete the majority of computer components: CPU, memory, internal and external bus system, most will have the Core. At the same time, such as integrated communication interfaces, timers, real-time clock and other peripheral equipment. And now the most powerful single-chip microcomputer system can even voice, image, networking, input and output complex system integration on a single chip.Also known as single-chip microprocessor, first because it was used in the field of industrial control. Only by the single-chip CPU chip developed from the dedicated processor. The design concept is the first by a large number of peripherals and CPU in a single chip, the computer system so that smaller, more easily integrated into the complex and demanding on the volume control devices. INTEL the Z80 is one of the first design in accordance with the idea of the processor, From then on, the MCU and the development of a dedicated processor parted ways.At present, single-chip to infiltrate all areas of our lives, which is very difficult to find the area of almost no traces of single-chip microcomputer. Missile navigation equipment, aircraft control on a variety of instruments, computer network communications and data transmission, industrial automation, real-time process control and data processing, are widely used in a variety of smart IC card, limousine civilian security systems, video recorders, cameras, the control of automatic washing machines, as well as program-controlled toys, electronic pet, etc., which are inseparable from the single-chip microcomputer. Not to mention the field of robot automation, intelligent instrumentation, medical equipment has been.Throughout the development process of single-chip, you can indicate the development trend of single-chip, generally are: 1. Of low-power CMOSMCS-51 series of 8031 introduced the power consumption of 630mW, and now widespread in the single-chip 100mW or so, with the growing demand for low-powersingle-chip, and now all the basic single-chip manufacturers are use of CMOS (complementary metal oxide semiconductor process). As the 80C51 on the use of HMOS (high density metal oxide semiconductor process) and CHMOS (high-density complementary metal oxide semiconductor process). Although the CMOS low power consumption, but because of its physical characteristics to determine its speed is not high enough, and then CHMOS with high-speed and low power consumption characteristics of these features, it is more suitable in low power consumption, as battery-powered applications . Therefore, the process for some time to come will be the main way to develop single-chip microcomputer. 2.Singal-chip of micro-chipNow generally in conventional single-chip will be the central processing unit (CPU), random access data storage (RAM), read-only program memory (ROM), parallel and serial communication interface, system interruption, timing circuits, integrated circuit clock in a single chip, enhanced single-chip integration, such as A / D converter, PMW (pulse width modulation circuit), WDT (watchdog), and some will be single-chip LCD (LCD) driver integrated circuits are in a single chip, this unit includes single-chip circuits on more and more powerful features. Even single-chip manufacturers can also betailored in accordance with the requirements of users, to create a single chip with its own chip characteristics. 3. Mainstream and multi-species coexistenceAlthough a wide variety of single-chip, unique, but still single-chip microcomputer 80C51 prevailing at the core, compatible with its structure and command system of PHILIPS products, ATMEL company's products and ChinaTaiwan's Winbond Series single-chip machine. Therefore, single-chip microcomputer as the core C8051 occupied the half. Microchip's PIC and reduced instruction set (RISC) has a strong development momentum of China Taiwan HOLTEK single-chip companies in recent years, increasing production, with its high quality low-cost advantages, to occupy a certain market share. MOTOROLA addition to the company's products, several large companies in Japan's exclusive single-chip microcomputer. A certain period of time, this situation will continue to be upheld, there will not be a single-chip monopoly domination, taking the complementary interdependence, complementarity and common development.AT89C51 is a flicker with 4K bytes EEPROM-programmable low-voltage, high-performance digital microprocessors CMOS8, commonly known as single-chip microcomputer. AT89C2051 is a flicker with 2K bytes EEPROM programmablemicrocontroller. MCU EEPROM erasure can be repeated 100 times. The device ATMEL manufacture high-density nonvolatile memory technology with industry-standard MCS-51 instruction set and pin compatible output. Owing to the multi-purpose 8-bit CPU and flash memory chips in a single portfolio, ATMEL'sAT89C51 microcontroller is a highly efficient, AT89C2051 is a streamlined version of it. AT89C single-chip embedded control system for many provides a flexible and inexpensive program. AT89C51 performance : 1. And MCS-51 compatible2.4K bytes of programmable Flash Memory3. Life expectancy: 1000 write / wipe cycle4. Data retention time: 10 years5. Static work of the whole:0Hz-24MHz 6. Three-level Program Memory Lock 7.128 × 8-bit internal RAM8.32 Programmable I / O lines 9. Two 16-bit timer / counter 10.5 Interrupt Sources11. Programmable Serial Channel 12. Low-power idle and power-down mode 13. Chip oscillator and clock circuitryReferred to as digital voltage meter DVM, it is a digital measurement technology, the continuous analog (DC input voltage) into a non-continuous, discrete digital form and the instrument display. The characteristics ofdigital voltage meter： 1.Show a clear intuitive, accurate readingsTraditional analogue instruments through the use of indicators must be carried out and dial readings in the reading process will be introduced to the inevitable human error. Digital voltage meter is the use of advanced digital display technology, so that the measurement results at a glance, as long asthe meter jump phenomenon does not occur, the measurement results is unique. 2.Show that the medianShow that the median is usually 31 / 2, 32 / 3, 33 / 4 / spaces, 41 / 2, 43 / 4, 51 / 2, 61 / 2, 71 / 2, 81 / 2 A total of 9. Determine the median number of instruments there are two principles:1. can display all the numbers 0 to 9 are the integer-bit; Score-bitnumerical value is based on the largest show the highest number of elements, with the highest number of full-scale as the denominator . 3.High accuracyAccuracy of results is a measure of systematic error and random error ofthe integrated. 4. High resolutionDigital voltage meter at the lowest voltage range on the bottom of a character represented by the voltage value, known as the instrument of the resolution, which reflects the level of instrument sensitivity. With thedisplay resolution increases the median. Resolution refers to the smallest can be shown in the figures (except zero) and the largest percentage of the number. For example, 31 / 2 DVM of a resolution of 1 / 1999 ≈ 0.05%. Be noted thatthe resolution and accuracy are two different concepts. From the measurement point of view, the resolution is \indicators (with measurement error hasnothing to do), the accuracy is the \target (on behalf of the size of measurement error). 5. Wide measuring rangeDVM generally more measurable range 0 ~ 1000V DC voltage, high voltage probe can be measured with the million-volt high-pressure.A / D converter [4] is a digital voltage meter, digital multimeter and measuring system the \hundreds of species can be broadly divided into fivemain categories: 1. monolithic A / D converter; 2. DMM dedicated single-chip IC; 3. dedicated multi-display meter IC; 4. for digital the use of special instrumentation IC (ASIC); 5. other general-purpose A / D converter, the chip can only complete A / D converter, not directly with the number of instruments.Digital voltage meter digital meter is a great core and foundation of the digital voltage meter as a continuous analog DC voltage to a discrete form of non-sequential numbers, which is different from traditional dial indicator readings to increase the ways to avoid errors in reading and visual fatigue.At present, the digital multimeter is a core component of the internal A / D converter, converter, to a large extent affect the accuracy of the accuracy of the design of digital multimeter - Digital Voltage Meter A / D converter for converting analog signals ADC0804 input, AT89C51 controls the heart of the transformation and processing the results of operations, the final output device driver number of voltage signal. Digital voltage meter digital meter is a great core and foundation of the digital voltage meter as a continuousanalog DC voltage to a discrete form of non-sequential numbers, which is different from traditional dial indicator readings to increase the ways to avoid errors in reading and visual fatigue. At present, the digital multimeter is a core component of the internal A / D converter, converter, to a large extent affect the accuracy of the accuracy of the design of digital multimeter - Digital Voltage Meter A / D converter for converting analog signals ADC0804 input, AT89C51 controls the heart of the transformation and processing the results of operations, the final output device driver number of voltage signal. LED display can be carried out will be displayed after the decimal pointvoltage value of one.Adoption of new technologies, new processes, from LSI and VLSI constitutea new type of digital instrumentation and a large number of high-end smart devices available, the field of electronic devices marked a revolution in creating a modern pioneer of electronic measurement technology.感谢您的阅读，祝您生活愉快。