0.18μm CMOS and beyond-1

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1.
INTRODUCTION
ቤተ መጻሕፍቲ ባይዱ
With 0.18~m, we are seeing widespread use of Cu interconnect, rapid reductions in V,, and the rapid introduction of embedded modules for system-on-chip. As we move beyond the 0.18pm node, the SIA Roadmap continues to accelerate. Some proposals put the 35nm node in only 2009 (Figure I), leading to renewed examination of the limits to simple scaling rules for the transistor performance. In particular, there are serious questions on the sustainability of voltage scaling, and how the breakdown of this crucial rule will affect circuit performance. This paper will review the various impending disasters in the transistor performance, and conclude that the most serious challenges lie in the properties that have never scaled. Lithography is expected to be the gating item in the Roadmap, and in reality the availability of suitable tools will control how rapidly the minimum dimensions can be reduced. The further acceleration that has been proposed will probably be constrained by the absence of commercial lithographic processes. The most likely solution to this new challenge involves rapid deployment of enhancement technologies in optical lithography, followed by insertion of a post-optical lithography at the earliest possible point. Currently, this is likely to occur at the lOOnm and 70nm nodes, making SCALPEL much the likeliest NextGeneration Lithography.
Given the required gate dimension, traditional scaling reduces all lengthscales and voltages while increasing the doping level in order to achieve comparable fields everywhere. This has greatly simplified approach to design in successive technologies, and departure from this rule would vastly complicate the design. With an accelerating Roadmap, a breakdown in simple scaling is widely feared once the thermal limit (Vt B 0.3V) is approached. Potential solutions discussed in the literature include SoI, as well as more radical departures such as dual-gate transistors, and lowering the operating temperature. At this point there is good reason to believe that these approaches will not be economically necessary for several more technology nodes. However, design challenges continue to be dominated by circuit-level features that have never scaled appropriately. Power densities will continue to increase, and power management will become an increasingly important part of system design. Similarly, the history of interconnect management is of a long fight against the unfavourable scaling of the resistance and interconnect delay. By default, RC time-constants increase very rapidly as the L,ff scales down, a problem which is exacerbated if it is viewed in terms of clock-cycles. Traditionally, this has been tackled by adding more layers of metal. Over the next few years, most process flows will migrate to Cu metallisation, with a transition point dictated by process cost and chip dimensions. However, the ultimate solution requires explicitly handling latency at the system level.
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0.18p.m CMOS and beyond
D.J. Eaglesham Bell Labs, Lucent Technologies, 600 Mountain Avenue, Murray Hill, NJ 07974
deaglesham@
ABSTRACT
As we move to the 0.18pm node and beyond, the dominant trend in device and process technology is a simple continuation of several decades of scaling. However, some serious challenges to straightforward scaling are on the horizon. This paper will review the present status of process technology and examine the likely departures from scaling in the various areas. The 0.18pm node is seeing the first major new materials introduced into the Si process for many years in the interconnect, and major departures from the traditional process are being actively considered for the transistor. However, it is probable that continued scaling will continue to dominate advanced processes for several generations to come.
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