S2551中文资料

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CS42L51中文资料

Advance Product InformationThis document contains information for a new product.Cirrus Logic reserves the right to modify this product without notice.Low Power, Stereo CODEC with Headphone AmpDIGITAL to ANALOG FEATURES!98 dB Dynamic Range (A-wtd) !-86 dB THD+N!Headphone Amplifier - GND Centered–On-Chip Charge Pump Provides -VA_HP –No DC-Blocking Capacitor Required –46mW Power Into Stereo 16Ω @ 1.8V –88mW Power Into Stereo 16Ω @ 2.5V –-75 dB THD+N!Digital Signal Processing Engine–Bass & Treble Tone Control, De-Emphasis –PCM + ADC Mix w/Independent Vol Control –Master Digital Volume Control–Soft Ramp & Zero Cross Transitions ! Beep Generator–Tone Selections Across Two Octaves –Separate Volume Control–Programmable On & Off Time Intervals –Continuous, Periodic or One-Shot Beep Selections!Programmable Peak-Detect and Limiter !Pop and Click SuppressionANALOG to DIGITAL FEATURES!98 dB Dynamic Range (A-wtd)! -88 dB THD+N !Analog Gain Controls–+32 dB or +16 dB MIC Pre-Amplifiers –Analog Programmable Gain Amplifier (PGA)!+20 dB Digital Boost!Programmable Automatic Level Control (ALC)–Noise Gate for Noise Suppression –Programmable Threshold and Attack/Release Rates!Independent Channel Control !Digital Volume Control!High-Pass Filter Disable for DC Measurements !Stereo 3:1 Analog Input MUX !Dual MIC Inputs–Programmable, Low Noise MIC Bias Levels –Differential MIC Mix for Common Mode Noise Rejection!Very Low 64 Fs Oversampling Clock ReducesPower ConsumptionCS42L51SYSTEM FEATURES!24-bit Converters! 4 kHz to 96kHz Sample Rate!Multi-bit Delta Sigma Architecture!Low Power Operation–Stereo Playback: 12.93 mW @ 1.8 V–Stereo Record and Playback: 20.18 mW @1.8 V!Variable Power Supplies– 1.8 V to 2.5 V Digital & Analog– 1.8 V to 3.3V Interface Logic!Power Down Management–ADC, DAC, CODEC, MIC Pre-Amplifier, PGA!Software Mode (I²C & SPI™ Control)!Hardware Mode (Stand-Alone Control)!Digital Routing/Mixes:–Analog Out=ADC+Digital In–Digital Out=ADC+Digital In–Internal Digital Loopback–Mono Mixes!Flexible Clocking Options–Master or Slave Operation–High-Impedance Digital Output Option (for easy MUXing between CODEC and OtherData Sources)–Quarter-Speed Mode - (i.e. Allows 8 kHz Fs while maintaining a flat noise floor up to16kHz)APPLICATIONS!HDD & Flash-Based Portable Audio Players !MD Players/Recorders!PDAs!Personal Media Players!Portable Game Consoles!Digital Voice Recorders!Digital Camcorders!Digital Cameras!Smart Phones GENERAL DESCRIPTIONThe CS42L51 is a highly integrated, 24-bit, 96kHz, low power stereo CODEC. Based on multi-bit, delta-sigma modulation, it allows infinite sample rate adjustment be-tween 4 kHz and 96 kHz. Both the ADC and DAC offer many features suitable for low power, portable system applications.The ADC input path allows independent channel control of a number of features. An input multiplexer selects be-tween line-level or microphone level inputs for each channel. The microphone input path includes a select-able programmable-gain pre-amplifier stage and a low noise MIC bias voltage supply. A PGA is available for line or microphone inputs and provides analog gain with soft ramp and zero cross transitions. The ADC also fea-tures a digital volume attenuator with soft ramp transitions. A programmable ALC and Noise Gate mon-itor the input signals and adjust the volume levels appropriately.The DAC output path includes a digital signal process-ing engine. Tone Control provides bass and treble adjustment of four selectable corner frequencies. The Mixer allows independent volume control for both the ADC mix and the PCM mix, as well as a master digital volume control for the analog output. All volume level changes may be configured to occur on soft ramp and zero cross transitions. The DAC also includes de-em-phasis, limiting functions and a beep generator delivering tones selectable across a range of two full octaves.The stereo headphone amplifier is powered from a sep-arate positive supply and the integrated charge pump provides a negative supply. This allows a ground-cen-tered analog output with a wide signal swing and eliminates external DC-blocking capacitors.In addition to its many features, the CS42L51 operates from a low-voltage analog and digital core, making this CODEC ideal for portable systems that require ex-tremely low power consumption in a minimal amount of space.The CS42L51 is available in a 32-pin QFN package in both Commercial (-10 to +70° C) and Automotive grades (-40 to +85° C). The CDB42L51 Customer Dem-onstration board is also available for device evaluation and implementation suggestions. Please see “Ordering Information” on page81 for complete details.TABLE OF CONTENTS1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE (7)1.1 Digital I/O Pin Characteristics (9)2. TYPICAL CONNECTION DIAGRAMS (10)3. CHARACTERISTIC AND SPECIFICATION TABLES (12)SPECIFIED OPERATING CONDITIONS (12)ABSOLUTE MAXIMUM RATINGS (12)ANALOG INPUT CHARACTERISTICS (COMMERCIAL - CNZ) (13)ANALOG INPUT CHARACTERISTICS (AUTOMOTIVE - DNZ) (14)ADC DIGITAL FILTER CHARACTERISTICS (15)ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL - CNZ) (16)ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE - DNZ) (17)LINE OUTPUT VOLTAGE CHARACTERISTICS (18)HEADPHONE OUTPUT POWER CHARACTERISTICS (19)COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (20)SWITCHING SPECIFICATIONS - SERIAL PORT (20)SWITCHING SPECIFICATIONS - I²C CONTROL PORT (22)SWITCHING CHARACTERISTICS - SPI CONTROL PORT (23)DC ELECTRICAL CHARACTERISTICS (24)DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS (24)POWER CONSUMPTION (25)4. APPLICATIONS (26)4.1 Overview (26)4.1.1 Architecture (26)4.1.2 Line & MIC Inputs (26)4.1.3 Line & Headphone Outputs (26)4.1.4 Signal Processing Engine (26)4.1.5 Beep Generator (26)4.1.6 Device Control (Hardware or Software Mode) (26)4.1.7 Power Management (26)4.2 Hardware Mode (27)4.3 Analog Inputs (28)4.3.1 Digital Code, Offset & DC Measurement (28)4.3.2 High-Pass Filter and DC Offset Calibration (29)4.3.3 Digital Routing (29)4.3.4 Differential Inputs (29)4.3.4.1 External Passive Components (29)4.3.5 Analog Input Multiplexer (30)4.3.6 MIC & PGA Gain (31)4.3.7 Automatic Level Control (ALC) (31)4.3.8 Noise Gate (32)4.4 Analog Outputs (33)4.4.1 De-Emphasis Filter (33)4.4.2 Volume Controls (34)4.4.3 Mono Channel Mixer (34)4.4.4 Beep Generator (34)4.4.5 Tone Control (35)4.4.6 Limiter (35)4.4.7 Line-Level Outputs and Filtering (36)4.4.8 On-Chip Charge Pump (36)4.5 Serial Port Clocking (37)4.5.1 Slave (37)4.5.2 Master (38)4.5.3 High-Impedance Digital Output (38)4.5.4 Quarter- and Half-Speed Mode (39)4.6 Digital Interface Formats (39)4.7 Initialization (40)4.8 Recommended Power-Up Sequence (40)4.9 Recommended Power-Down Sequence (41)4.10 Software Mode (42)4.10.1 SPI Control (42)4.10.2 I²C Control (42)4.10.3 Memory Address Pointer (MAP) (44)4.10.3.1 Map Increment (INCR) (44)5. REGISTER QUICK REFERENCE (45)6. REGISTER DESCRIPTION (47)6.1 Chip I.D. and Revision Register (Address 01h) (Read Only) (47)6.2 Power Control 1 (Address 02h) (47)6.3 MIC Power Control & Speed Control (Address 03h) (48)6.4 Interface Control (Address 04h) (49)6.5 MIC Control (Address 05h) (51)6.6 ADC Control (Address 06h) (52)6.7 ADCx Input Select, Invert & Mute (Address 07h) (53)6.8 DAC Output Control (Address 08h) (54)6.9 DAC Control (Address 09h) (55)6.10 ALCX & PGAX Control:ALCA, PGAA (Address 0Ah) & ALCB, PGAB (Address 0Bh) (56)6.11 ADCx Attenuator:ADCA (Address 0Ch) & ADCB (Address 0Dh) (57)6.12 ADCx Mixer Volume Control:ADCA (Address 0Eh) & ADCB (Address 0Fh) (58)6.13 PCMX Mixer Volume Control:PCMA (Address 10h) & PCMB (Address 11h) (59)6.14 Beep Frequency & Timing Configuration (Address 12h) (60)6.15 Beep Off Time & Volume (Address 13h) (61)6.16 Beep Configuration & Tone Configuration (Address 14h) (62)6.17 Tone Control (Address 15h) (63)6.18 AOUTx Volume Control:AOUTA (Address 16h) & AOUTB (Address 17h) (64)6.20 Limiter Threshold SZC Disable (Address 19h) (65)6.21 Limiter Release Rate Register (Address 1Ah) (66)6.22 Limiter Attack Rate Register (Address 1Bh) (67)6.23 ALC Enable & Attack Rate (Address 1Ch) (67)6.24 ALC Release Rate (Address 1Dh) (68)6.25 ALC Threshold (Address 1Eh) (69)6.26 Noise Gate Configuration & Misc. (Address 1Fh) (70)6.27 Status (Address 20h) (Read Only) (71)6.28 Charge Pump Frequency (Address 21h) (71)7. ANALOG PERFORMANCE PLOTS (72)7.1 Headphone THD+N versus Output Power Plots (72)7.2 ADC_FILT+ Capacitor Effects on THD+N (74)8. EXAMPLE SYSTEM CLOCK FREQUENCIES (75)8.1 Auto Detect Enabled (75)8.2 Auto Detect Disabled (76)9. PCB LAYOUT CONSIDERATIONS (77)9.1 Power Supply, Grounding (77)9.2 QFN Thermal Pad (77)10. ADC & DAC DIGITAL FILTERS (78)11. PARAMETER DEFINITIONS (79)12. PACKAGE DIMENSIONS (80)THERMAL CHARACTERISTICS (80)13. ORDERING INFORMATION (81)14. REFERENCES (81)15. REVISION HISTORY (82)LIST OF FIGURESFigure 1. Typical Connection Diagram (Software Mode) (10)Figure 2. Typical Connection Diagram (Hardware Mode) (11)Figure 3. Headphone Output Test Load (19)Figure 4. Serial Audio Interface Slave Mode Timing (21)Figure 5. TDM Serial Audio Interface Timing (21)Figure 6. Serial Audio Interface Master Mode Timing (21)Figure 7. Control Port Timing - I²C (22)Figure 8. Control Port Timing - SPI Format (23)Figure 9. Analog Input Architecture (28)Figure 10. MIC Input Mix w/Common Mode Rejection (30)Figure 11. Differential Input (30)Figure 12. ALC (31)Figure 13. Noise Gate Attenuation (32)Figure 14. Output Architecture (33)Figure 15. De-Emphasis Curve (33)Figure 16. Beep Configuration Options (34)Figure 17. Peak Detect & Limiter (35)Figure 18. Master Mode Timing (38)Figure 19. Tri-State Serial Port (38)Figure 20. I²S Format (39)Figure 21. Left-Justified Format (39)Figure 22. Right-Justified Format (DAC only) (39)Figure 23. Initialization Flow Chart (41)Figure 24. Control Port Timing in SPI Mode (42)Figure 25. Control Port Timing, I²C Write (43)Figure 26. Control Port Timing, I²C Read (43)Figure 27. AIN & PGA Selection (53)Figure 28. THD+N vs. Ouput Power per Channel at 1.8V (16 Ω load) (72)Figure 29. THD+N vs. Ouput Power per Channel at 2.5V (16 Ω load) (72)Figure 30. THD+N vs. Ouput Power per Channel at 1.8V (32 Ω load) (73)Figure 31. THD+N vs. Ouput Power per Channel at 2.5V (32 Ω load) (73)Figure 32. ADC THD+N vs. Frequency w/Capacitor Effects (74)Figure 33. ADC Passband Ripple (78)Figure 34. ADC Stopband Rejection (78)Figure 35. DAC Passband Ripple (78)Figure 36. DAC Stopband (78)Figure 35. DAC Transition Band (78)Figure 36. DAC Transition Band (Detail) (78)Figure 35. ADC Transition Band (78)Figure 36. ADC Transition Band (Detail) (78)1.PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODEPin Name#Pin DescriptionLRCK 1Left Right Clock (Input/Output ) - Determines which channel, Left or Right, is currently active on the serial audio data line.SDA/CDIN 2Serial Control Data (Input /Output ) - SDA is a data I/O in I²C mode. CDIN is the input data line for the control port interface in SPI mode.(MCLKDIV2)MCLK Divide by 2 (Input ) - Hardware Mode: Divides the MCLK by 2 prior to all internal circuitry.SCL/CCLK 3Serial Control Port Clock (Input ) - Serial clock for the serial control port.(I²S/LJ)Interface Format Selection (Input ) - Hardware Mode: Selects between I²S & Left-Justified interface for-mats for the ADC & DAC.AD0/CS 4Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C mode; CS is the chip select signal for SPI format.(DEM)De-Emphasis (Input) - Hardware Mode: Enables/disables the de-emphasis filter.VA_HP 5Analog Power For Headphone (Input) - Positive power for the internal analog headphone section.FLYP 6Charge Pump Cap Positive Node (Input) - Positive node for the external charge pump capacitor.GNDHP 7Analog Ground (Input ) - Ground reference for the internal headphone/charge pump section.FLYN 8Charge Pump Cap Negative Node (Input) - Negative node for the external charge pump capacitor.VSS_HP 9Negative Voltage From Charge Pump (Output) - Negative voltage rail for the internal analog head-phone section.AOUTB AOUTA 1011Analog Audio Output (Output ) - The full-scale output level is specified in the DAC Analog Characteris-tics specification table.VA 12Analog Power (Input) - Positive power for the internal analog section.AGND13Analog Ground (Input) - Ground reference for the internal analog section.M /S )V S S _H A O U T BA O U T V A G N D A C _F I L T A D C _F I L T VDAC_FILT+ ADC_FILT+1416Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.VQ15Quiescent Voltage (Output) - Filter connection for internal quiescent voltage.MICIN1/ AIN3A 17Microphone Input 1 (Input) - The full-scale level is specified in the ADC Analog Characteristics specifi-cation table.MICIN2/ BIAS/AIN3B 18Microphone Input 2 (Input/Output) - The full-scale level is specified in the ADC Analog Characteristics specification table. This pin can also be configured as an output to provide a low noise bias supply for an external microphone. Electrical characteristics are specified in the DC Electrical Characteristics table.AIN2A19Analog Input (Input) - The full-scale level is specified in the ADC Analog Characteristics specification table.AIN2B/BIAS20Analog Input (Input/Output) - The full-scale level is specified in the ADC Analog Characteristics specifi-cation table. This pin can also be configured as an output to provide a low noise bias supply for an exter-nal microphone. Electrical characteristics are specified in the DC Electrical Characteristics table.AFILTA AFILTB 2122Filter Connection (Output) - Filter connection for the ADC inputs.AIN1A AIN1B 2324Analog Input (Input) - The full-scale level is specified in the ADC Analog Characteristics specification table.RESET25Reset (Input) - The device enters a low power mode when this pin is driven low.VL26Digital Interface Power (Input) - Determines the required signal level for the serial audio interface and host control port. Refer to the Recommended Operating Conditions for appropriate voltages.VD27Digital Power (Input) - Positive power for the internal digital section.DGND28Digital Ground (Input) - Ground reference for the internal digital section.SDOUT29Serial Audio Data Output (Output) - Output for two’s complement serial audio data.(M/S)Serial Port Master/Slave (Input/Output) - Hardware Mode Startup Option: Selects between master and slave mode for the serial port.MCLK30Master Clock (Input) -Clock source for the delta-sigma modulators.SCLK31Serial Clock (Input/Output) - Serial clock for the serial audio interface.SDIN32Serial Audio Data Input (Input) - Input for two’s complement serial audio data.Thermal Pad-Thermal relief pad for optimized heat dissipation. See “QFN Thermal Pad” on page77.1.1Digital I/O Pin CharacteristicsThe logic level for each input should adhere to the corresponding power rail and should not exceed the maximum ratings.Power Rail Pin NameSW/(HW)I/O Driver ReceiverVL RESET Input- 1.8 V - 3.3 V SCL/CCLK(I²S/LJ)Input- 1.8 V - 3.3 V, with HysteresisSDA/CDIN(MCLKDIV2)Input/Output 1.8 V - 3.3 V, CMOS/Open Drain 1.8 V - 3.3 V, with HysteresisAD0/CS(DEM)Input- 1.8 V - 3.3 V MCLK Input- 1.8 V - 3.3 VLRCK Input/Output 1.8 V - 3.3 V, CMOS 1.8 V - 3.3 VSCLK Input/Output 1.8 V - 3.3 V, CMOS 1.8 V - 3.3 VSDOUT(M/S)Input/Output 1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V SDIN Input- 1.8 V - 3.3 VTable 1. I/O Power Rails2.TYPICAL CONNECTION DIAGRAMSFigure 1. Typical Connection Diagram (Software Mode)Figure 2. Typical Connection Diagram (Hardware Mode)3.CHARACTERISTIC AND SPECIFICATION TABLES(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and T A = 25° C.)SPECIFIED OPERATING CONDITIONS(AGND=DGND=0 V, all voltages with respect to ground.)ABSOLUTE MAXIMUM RATINGS(AGND = DGND = 0 V; all voltages with respect to ground.)WARNING:Operation at or beyond these limits may result in permanent damage to the device. Normal operationis not guaranteed at these extremes.Notes:1.The device will operate properly over the full range of the analog, headphone amplifier, digital core andserial/control port interface supplies.2.Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not causeSCR latch-up.3.The maximum over/under voltage is limited by the input current.ParametersSymbol Min NomMaxUnitsDC Power Supply (Note 1)Analog Core VA 1.712.37 1.82.5 1.892.63V V Headphone Amplifier VA_HP 1.712.37 1.82.5 1.892.63V V Digital CoreVD 1.712.37 1.82.5 1.892.63V V Serial/Control Port InterfaceVL1.712.373.14 1.82.53.3 1.892.633.47V V V Ambient TemperatureCommercial - CNZ Automotive - DNZT A-10-40--+70+85°C °CParametersSymbol MinMaxUnitsDC Power SupplyAnalog Digital Serial/Control Port Interface VA, VA_HP VDVL-0.3-0.3-0.3 3.03.04.0V V V Input Current(Note 2)I in -±10mAAnalog Input Voltage(Note 3)V INAGND-0.7VA+0.7VDigital Input Voltage (Note 3))V IND-0.3VL+ 0.4V Ambient Operating Temperature Commercial - CNZ(power applied)Automotive - DNZT A -20-50+85+95°C °C Storage TemperatureT stg-65+150°C(Test Conditions (unless otherwise specified): All supplies = VA = 2.5 V and 1.8 V; Input sine wave (relative to dig-ital full-scale): 1kHz through passive input filter; Measurement Bandwidth is 10Hz to 20kHz unless otherwise specified. Sample Frequency = 48kHz)VA = 2.5V VA = 1.8VParameter (Note 4)Min Typ Max Min Typ Max Unit Analog In to ADC (PGA bypassed)Dynamic Range A-weightedunweighted 93909996--90879693--dBdBTotal Harmonic Distortion + Noise -1dBFS-20dBFS-60dBFS ----86-76-36-80------84-73-33-78--dBdBdBAnalog In to PGA to ADC Dynamic RangePGA Setting: 0 dB A-weightedunweighted 92899895--89869592--dBdBPGA Setting: +12 dB A-weightedunweighted 85829188--82798885--dBdBTotal Harmonic Distortion + NoisePGA Setting: 0 dB -1dBFS -60dBFS ---88-35-82----86-32-80-dBdBPGA Setting: +12 dB -1dBFS--85-79--83-77dB Analog In to MIC Pre-Amp(+16 dB) to PGA to ADCDynamic RangePGA Setting: 0 dB A-weightedunweighted --8683----8380--dBdBTotal Harmonic Distortion + NoisePGA Setting: 0 dB -1dBFS--76---74-dB Analog In to MIC Pre-Amp(+32 dB) to PGA to ADCDynamic RangePGA Setting: 0 dB A-weightedunweighted --7874----7571--dBdBTotal Harmonic Distortion + NoisePGA Setting: 0 dB -1dBFS--74---71-dB Other CharacteristicsDC AccuracyInterchannel Gain Mismatch-0.1--0.1-dB Gain Drift-±100--±100-ppm/°C InputInterchannel Isolation-90--90-dB DAC Isolation (Note 5)-70--70-dB Full-scale Input Voltage (x•VA) (Note 7)0.70•VA0.72•VA0.75•VA0.70•VA0.72•VA0.75•VA VppInput Impedance (Note 6)ADCPGAMIC 184050------184050------kΩkΩkΩ(Test Conditions (unless otherwise specified): All supplies = VA = 2.5 V and 1.8 V; Input sine wave (relative to full-scale): 1 kHz through passive input filter; Measurement Bandwidth is 10Hz to 20kHz unless otherwise specified. Sample Frequency = 48kHz)Notes:4.Referred to the typical full-scale voltage.5.Measured with DAC delivering full-scale output power into 16 Ω.VA = 2.5V VA = 1.8V Parameter (Note 4)MinTypMaxMinTypMaxUnitAnalog In to ADCDynamic RangeA-weighted unweighted91789996--88859693--dB dB Total Harmonic Distortion + Noise -1dB -20dB-60dB ----86-76-36-78------84-73-33-76--dB dB dBAnalog In to PGA to ADC Dynamic RangePGA Setting: 0 dB A-weighted unweighted 90879895--87849592--dB dB PGA Setting: +12 dBA-weighted unweighted83809188--80778885--dB dB Total Harmonic Distortion + Noise PGA Setting: 0 dB -1dB -60dB ---88-35-80----86-32-78-dB dB PGA Setting: +12 dB -1dB--85-77--83-75dBAnalog In to MIC Pre-Amp (+16 dB) to PGA to ADC Dynamic RangePGA Setting: 0 dBA-weighted unweighted--8683----8380--dB dB Total Harmonic Distortion + Noise PGA Setting: 0 dB-1dB--76---74-dBAnalog In to MIC Pre-Amp (+32 dB) to PGA to ADC Dynamic RangePGA Setting: 0 dBA-weighted unweighted--7874----7571--dB dB Total Harmonic Distortion + Noise PGA Setting: 0 dB-1dB--74---71-dBOther CharacteristicsDC AccuracyInterchannel Gain Mismatch -0.1--0.1-dB Gain Drift-±100--±100-ppm/°C InputInterchannel Isolation -90--90-dB DAC Isolation (Note 5)-70--70-dB Full-scale Input Voltage (Note 7) 0.70•VA 0.72•VA0.75•VA0.70•VA 0.72•VA0.75•VAVpp Input Impedance (Note 6)ADC PGA MIC 184050------184050------k Ωk Ωk ΩNotes:6.Measured between AINxx and AGND.7.Full-scale input voltage characteristics for the PGA and Microphone inputs are scaled based on the gainsetting for each.ADC DIGITAL FILTER CHARACTERISTICSNotes:8.Response is clock dependent and will scale with Fs. Note that the response plots (Figures 33to 36 onpage 78) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.Parameter (Note 8)MinTypMaxUnitPassband (Frequency Response) to -0.1 dB corner0-0.4948Fs Passband Ripple -0.09-0dB Stopband0.6677--Fs Stopband Attenuation 48.4--dB Total Group Delay-2.7/Fs -s High-Pass Filter CharacteristicsFrequency Response -3.0 dB -0.13 dB -- 3.724.2--Hz Hz Phase Deviation @ 20Hz-10-Deg Passband Ripple --0.17dB Filter Settling Time-105/Fss(Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz; test load R L = 10 kΩ, C L = 10 pF for the line output (see Figure3), and test load R L = 16 Ω, C L = 10 pF (see Figure3) for the headphone output. HP_GAIN[2:0] = 011.)Parameter(Note 9)VA = 2.5VMin Typ MaxVA = 1.8VMin Typ Max UnitR L = 10 kΩDynamic Range18 to 24-Bit A-weighted unweighted 16-Bit A-weightedunweighted 9289--98959693----8986--95929390----dBdBdBdBTotal Harmonic Distortion + Noise18 to 24-Bit0 dB-20 dB-60 dB 16-Bit0 dB-20 dB-60 dB -------86-75-35-86-73-33-80------------88-72-32-88-70-30-82-----dBdBdBdBdBdBR L = 16 ΩDynamic Range18 to 24-Bit A-weightedunweighted 16-Bit A-weightedunweighted 9289--98959693----8986--95929390----dBdBdBdBTotal Harmonic Distortion + Noise18 to 24-Bit0 dB-20 dB-60 dB 16-Bit0 dB-20 dB-60 dB -------75-75-35-75-73-33-69------------75-72-32-75-70-30-69-----dBdBdBdBdBdBOther Characteristics for R L = 16 Ω or 10 kΩOutput Parameters Modulation Index (MI) (Note 10)Analog Gain Multiplier (G)-0.67870.6047--0.67870.6047-Full-scale Output Voltage (2•G•MI•VA) (Note 10)Refer to Table“Line Output Voltage Characteristics” onpage18VppFull-scale Output Power (Note 10)Refer to Table“Headphone Output Power Characteristics” onpage19Interchannel Isolation (1 kHz)16 Ω10 kΩ--8095----8093--dBdBInterchannel Gain Mismatch-0.10.25-0.10.25dB Gain Drift-±100--±100-ppm/°C AC-Load Resistance (R L)(Note 11)16--16--ΩLoad Capacitance (C L)(Note 11)--150--150pF(Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz and 96 kHz; test load R L = 10 kΩ, C L = 10 pF for the line output (see Figure3), and test load R L = 16 Ω, C L = 10 pF (see Figure3) for the headphone output.HP_GAIN[2:0] = 011.)Parameter(Note 9)VA = 2.5VMin Typ MaxVA = 1.8VMin Typ Max UnitR L = 10 kΩDynamic Range18 to 24-Bit A-weighted unweighted 16-Bit A-weightedunweighted 9087--98959693----8784--95929390----dBdBdBdBTotal Harmonic Distortion + Noise18 to 24-Bit0 dB-20 dB-60 dB 16-Bit0 dB-20 dB-60 dB -------86-75-35-86-73-33-78------------88-72-32-88-70-30-80-----dBdBdBdBdBdBR L = 16 ΩDynamic Range18 to 24-Bit A-weightedunweighted 16-Bit A-weightedunweighted 9087--98959693----8784--95929390----dBdBdBdBTotal Harmonic Distortion + Noise18 to 24-Bit0 dB-20 dB-60 dB 16-Bit0 dB-20 dB-60 dB -------75-75-35-75-73-33-67------------75-72-32-75-70-30-67-----dBdBdBdBdBdBOther Characteristics for R L = 16 Ω or 10 kΩOutput Parameters Modulation Index (MI) (Note 10)Analog Gain Multiplier (G)-0.67870.6047--0.67870.6047-Full-scale Output Voltage (2•G•MI•VA) (Note 10)Refer to Table “Line Output Voltage Characteristics” onpage18VppFull-scale Output Power (Note 10)Refer to Table “Headphone Output Power Characteristics” onpage19Interchannel Isolation (1 kHz)16 Ω10 kΩ--8095----8093--dBdBInterchannel Gain Mismatch-0.10.25-0.10.25dB Gain Drift-±100--±100-ppm/°C AC-Load Resistance (R L)(Note 11)16--16--ΩLoad Capacitance (C L)(Note 11)--150--150pF。

TPS2551DBVR;TPS2550DBVT;TPS2550DRVT;TPS2551DRVT;TPS2550DBVR;中文规格书,Datasheet资料

Copyright © 2008, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments.
5 V USB INPUT RFAULT 100 kW FAULT Signal Control Signal FAULT EN ILIM GND PowerPAD RILIM 15 kW 0.1 mF IN OUT 120 mF * TPS2550/51 USB Data USB Port
• • • • • • •
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TPS2550 TPS2551
SLVS736B – FEBRUARY 2008 – REVISED NOVEMBER 2008 ........................................................................................................................................

u盘量产工具量产后出现cdrom驱动器,怎样去掉,下面我来分享一下经验

U盘用量产工具有的人会出现一个CD-ROM启动器，这是一种只读磁碟，写入信息后永久保存，利用光碟驱动器读取信息。

但很多时候我们用不到。

还浪费内存。

当时我的u盘损坏上网搜了一下教程。

制作好之后出现了CDROM。

虽然是一个启动盘，但是没有自己直接制作的好用。

所以现在教大家怎么把CDROM驱动器删除。

当然，还是要用到量产工具。

下面入正题。

如果你忘了自己是用的哪一个量产工具，可以用ChipEasy检测一下。

这是我做过启动盘之后的u盘，占用了三百多兆的内存。

找到自己u盘芯片相配的量产工具。

我的是金士顿的u盘，芯片型号PS2251-61 然后下载量产工具。

（u盘之家可以下载）我用的是MPALL v3.29.0B工具。

解压好下载文件，首先打开GetInfo。

打开之后就是然后输入自己u盘的盘符，就是下图这个。

输入盘符,点read这就是你u盘的详细信息了。

然后打开MPParamEdit_F1.exe 出现setting type 选择basic setting new setting 然后ok按照下图输入首先选择语言。

主控就是你的芯片型号我的是ps2551-61 分区数量一定选择1.不然就会出现很多盘符了。

然后点保存。

然后打开MPALL_F1_9000_v329_00.exe在MP.ini前打对号。

然后点update 程序会检测到u盘信息。

最后点start。

之后会出现英文提示，点确定就行。

之后就等着变绿就表示成功了。

这时你u盘上的CDROM驱动器就没有了，原来的内存又可以用了。

当然如果你需要CDROM，网上有教程，跟这个差不多的。

文案编辑词条B 添加义项?文案，原指放书的桌子，后来指在桌子上写字的人。

现在指的是公司或企业中从事文字工作的职位，就是以文字来表现已经制定的创意策略。

文案它不同于设计师用画面或其他手段的表现手法，它是一个与广告创意先后相继的表现的过程、发展的过程、深化的过程，多存在于广告公司，企业宣传，新闻策划等。

RFC2511

要求的证书值域，以及与登记过程相连系的控制ห้องสมุดไป่ตู้息。
2) 可以通过计算CertRequest的值来证明拥有与所请求的证书的公钥相连系的私钥，即可
计算出POP（proof of possession，拥有私钥的证明）的值。
3) 以上两项所需要的其他登记信息，这些信息和POP值，CertRequest结构组成证书请求
--签名signature（使用algorithmIdentifier所指的算法）是基于poposkInput 的DER
编码值。
--注意：如果certReq中的 CertTemplate结构包含主体和公钥值，那么
--poposkInput必须省略掉，并且signature必须通过certReq 的DER编码值计算出来。
DoD
March 1999
只要CA已经有了DH证书，这个证书已经被终端实体知道，并且终端实体愿意使用CA的
DH参数，这个选项就可以使用。
4．4 POP语法
ProofOfPossession ::= CHOICE {
raVerified [0] NULL,
-- 用于是否RA已经证明请求者拥有私钥
忘录的发布是不受限制的。
版权通知
版权所属因特网社会（1999），保留全部权力。
目录
1 摘要 2
2 略读 2
3 证书请求信息(CertReqMessage)的语法 2
4 拥有私钥的证明(POP) 3
4．1 签名密钥 3
4．2 加密密钥 3
4．3 协议密钥 4
4．4 POP语法 4
Entrust Technologies
D. Solo

TSL2561中文资料

Chipscale Package
D Automatically Rejects 50/60-Hz Lighting
Ripple
D Low Active Power (0.75 mW Typical) with
Power Down Mode
D RoHS Compliant
TSL2560, TSL2561 LIGHT-TO-DIGITAL CON61 LIGHT-TO-DIGITAL CONVERTER
TAOS059K − APRIL 2007
Functional Block Diagram
VDD = 2.7 V to 3.5 V
Channel 0 Visible and IR
The TSL256x devices also support an interrupt feature that simplifies and improves system efficiency by eliminating the need to poll a sensor for a light intensity value. The primary purpose of the interrupt function is to detect a meaningful change in light intensity. The concept of a meaningful change can be defined by the user both in terms of light intensity and time, or persistence, of that change in intensity. The TSL256x devices have the ability to define a threshold above and below the current light level. An interrupt is generated when the value of a conversion exceeds either of these limits.

PC机与单片机之间的串行通讯、数据的发送和接收

PC机与单片机之间的串行通讯、数据的发送和接收【摘要】本文以MCS-51单片机为例，详细介绍了PC机与单片机之间的串行通讯、数据的发送和接收。

在Windows98下利用VB的串行通讯控件可实现PC机与单片机之间的通讯。

其数据的发送和接收采用红外线通信方式，其优点是：省去了有线通信信号线的直接连接，使用简单，移动方便,微机与单片机无直接连接，属完全隔离状态，两者间不会因为电平的不同而造成数据传输的失误，抗干扰能力强。

本设计主要应用AT89C51作为控制核心，并与LED数码显示管、双向可控硅、红外发射与接收相结合的系统，充分发挥了单片机的性能。

其优点硬件电路简单，软件功能完善，控制系统可靠，性价比较高等特点，具有一定的使用和参考价值。

【关键字】MSC-51（单片机），红外，RS-232，电平转换器，串行通信半双工【Abstract】This text take one-chip computer MCS-51 for example , introduce a serial communication, data’s sending and receiving . Under the Windows98 we make use of a communication control of VB to achieve the communication of the machine of PC and one-chip computer. Its data’s sending and receiving adopts the method of the infrared ray communication, its advantage is that it exclude the direct link of signal line of with-wired communication ,and usage are simple, and move is convenience etc. The tiny machine have no direct conjunction with single a machine, belonging to the complete insulation appearance, can't result in the error that data deliver both because give or get an electric shock even and different, the antijam ability is strong.This design is a system that it applies AT89C51 as control core and combine the LED figures manifestation tube, MAX232CPE level changer, infrared’s sending and receiving. The system completely exerts the function of one-chip computer. Its advantage is that the hardware circuit is simple; the software function is perfect; the control system is dependable; the rate of price and function is high etc. So the system has certainly consult value.【Keyword】MSC-51(One-chip computer), infrared, RS-232, Level changer, serial communication，half duplex目录前言3第一章系统分析4 1．1 系统功能的概述 5 1．2 系统要求及主要内容 5 1．3 系统技术指标 5第二章系统总体设计6 2．1硬件设计思路 6 2．2软件设计思路 7第三章硬件电路设计7 3．1 单片机模块设计 8 3．2 红外通信（发射与接收）电路的设计 14 3．3 PC机模块的设计 17第四章串行口通信技术20 4．1 单片机串行口通信 21 4．2 PC机串口通信 24第五章软件设计25 5．1 单片机通信程序设计 25 5．2 PC机通信程序设计 29第六章系统调试30 6．1 硬件调试 30 6．2 软件调试 31 6．3 综合调试 33 6．4 故障分析及解决方案 33 6．5 结论与经验 34结束语35附录36 附录1 电路原理图 36 附录2程序流程图 38 附录3程序清单 41 附录4元器件清单 44 附录5 英文资料 45 附录6 中文翻译 52参考文献56前言单片机的英文名称是Micro Controller unit,缩写为MCU，又称为微控制器，它是一种面向控制的大规模集成电路芯片。

TSES_255(电镀锌)

3.Green chromate will experience the generation of minute pit – like spot color fading but these are not considered as corrosion.绿色铬酸盐处理会经过微小的凹陷的产生，如专色的褪色，但是这些将不被认为是腐蚀。
2.Code and Category of Plating电镀标准和范畴
Code and Category of plating shall be as per the following Tables.其标准和范畴必须按照下列表格进行
Table 1:表1Specifies the symbol of base material规定了基底材料的象征
Reviewed completely全部复审
Zn-Fe Alloy plating bright, Zn-Ni alloy plating and note added增加了锌铁合金光亮电镀，锌镍合金电镀，以及注释
Reviewed completely on 18.08.2007 and no change required 18.08.2007全部复审，无变化要求
Issue No.
Sheet No.
Revision No.
Reason for Change
Date
1
1
1
2
2
1-8
7
8
1-8
8
1-8
1-8
0
a
b
0
00
01
02
New Release新发布
Zn-Fe alloy plating has been added添加锌铁（Zn-Fe）合金电镀

CS5451资料

LIST OF FIGURES
Figure 1. Serial Port Timing............................................................................................................. 6 Figure 2. Typical Connection Diagram ............................................................................................ 7 Figure 3. Serial Port Data Transfer ................................................................................................. 8 Figure 4. Close-up of One Data Frame ........................................................................................... 9 Figure 5. Generating VA- with a Charge Pump............................................................................. 10
Decimation Filter
IIN2+ IIN2VIN2+ VIN2-
x1, 20
4th Order ∆Σ Modulator
Decimation Filter

FPGA可编程逻辑器件芯片XC6SLX9-2CSG225I中文规格书

Spartan-6 FPGA Electrical CharacteristicsSpartan®-6 LX and LXT FPGAs are available in various speed grades, with -3 having the highest performance. The DC and AC electrical parameters of the Automotive XA Spartan-6 FPGAs and Defense-grade Spartan-6Q FPGAs devices are equivalent to the commercial specifications except where noted. The timing characteristics of the commercial (XC) -2 speed grade industrial device are the same as for a -2 speed grade commercial device. The -2Q and -3Q speed grades areexclusively for the expanded (Q) temperature range. The timing characteristics are equivalent to those shown for the -2 and -3 speed grades for the Automotive and Defense-grade devices.Spartan-6FPGA DC and AC characteristics are specified for commercial (C), industrial (I), and expanded (Q) temperature ranges. Only selected speed grades and/or devices might be available in the industrial or expanded temperature ranges for Automotive and Defense-grade devices. References to device names refer to all available variations of that part number (for example, LX75 could denote XC6SLX75, XA6SLX75, or XQ6SLX75). The Spartan-6 FPGA -3N speed grade designates devices that do not support MCB functionality.All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications. Available device and package combinations can be found at:•DS160: Spartan-6 Family Overview•DS170: Automotive XA Spartan-6 Family Overview •DS172: Defense-Grade Spartan-6Q Family OverviewSpartan-6 FPGA DC CharacteristicsSpartan-6 FPGA Data Sheet:DC and Switching CharacteristicsDS162 (v3.1.1) January 30, 2015Product SpecificationTable 1:Absolute Maximum Ratings (1)Symbol DescriptionUnits V CCINT Internal supply voltage relative to GND –0.5 to 1.32V V CCAUX Auxiliary supply voltage relative to GND –0.5 to 3.75V V CCO Output drivers supply voltage relative to GND–0.5 to 3.75V V BATT Key memory battery backup supply (LX75, LX75T, LX100, LX100T , LX150, and LX150T only)–0.5 to 4.05V V FS External voltage supply for eFUSE programming (LX75, LX75T , LX100, LX100T, LX150, and LX150T only)(2)–0.5 to 3.75V V REFInput reference voltage–0.5 to 3.75VeFUSE Read EnduranceTable11 lists the minimum guaranteed number of read cycle operations for Device DNA and for the AES eFUSE key. For more information, see UG380: Spartan-6 FPGA Configuration User Guide.Table 11:eFUSE Read EnduranceSymbol DescriptionSpeed Grade Units(Min) -3-3N-2-1LDNA_CYCLES Number of DNA_PORT READ operations or JT AG ISC_DNA read command operations. Unaffected by SHIFT operations.30,000,000ReadCyclesAES_CYCLES Number of JTAG FUSE_KEY or FUSE_CNTL read command operations.Unaffected by SHIFT operations.30,000,000ReadCyclesSSTL, Class II, 2.5V SSTL2_II 250V REF 1.25SSTL, Class II, 1.5VSSTL15_II250V REF 0.75LVDS (Low-Voltage Differential Signaling), 2.5V & 3.3V LVDS_25, LVDS_3310000(3)–BLVDS (Bus LVDS), 2.5V BLVDS_25Note 400(3)–Mini-LVDS, 2.5V & 3.3VMINI_LVDS_25, MINI_LVDS_3310000(3)–RSDS (Reduced Swing Differential Signaling), 2.5V & 3.3V RSDS_25, RSDS_3310000(3)–TMDS (Transition Minimized Differential Signaling), 3.3V TMDS_33Note 500(3)–PPDS (Point-to-Point Differential Signaling, 2.5V & 3.3VPPDS_25, PPDS_331000(3)–DescriptionI/O Standard Attribute R REF (Ω)C REF (1)(pF)V MEAS (V)V REF (V)Table 33:Spartan-6 FPGA V CCO/GND Pairs per BankPackage Devices Description Bank 0Bank 1Bank 2Bank 3Bank 4Bank 5TQG144LX V CCO/GND Pairs3323N/A N/A Maximum I/O per Pair88138N/A N/ACPG196LX VCCO/GND Pairs4646N/A N/A Maximum I/O per Pair6474N/A N/ACSG225LX V CCO/GND Pairs4444N/A N/A Maximum I/O per Pair1010910N/A N/AFT(G)256LX V CCO/GND Pairs5645N/A N/A Maximum I/O per Pair89910N/A N/ACSG324LXV CCO/GND Pairs6666N/A N/AMaximum I/O per Pair109109N/A N/A LXTV CCO/GND Pairs4666N/A N/AMaximum I/O per Pair49109N/A N/ACS(G)484LXV CCO/GND Pairs813813N/A N/AMaximum I/O per Pair7878N/A N/A LXTV CCO/GND Pairs712813N/A N/AMaximum I/O per Pair5868N/A N/AFG(G)484LXV CCO/GND Pairs10101111N/A N/AMaximum I/O per Pair6898N/A N/A LXTV CCO/GND Pairs6101110N/A N/AMaximum I/O per Pair7878N/A N/AFG(G)676LX45V CCO/GND Pairs12151016N/A N/AMaximum I/O per Pair3787N/A N/A LX75, LX100, LX150V CCO/GND Pairs129101066Maximum I/O per Pair9109989 LXTV CCO/GND Pairs10810877Maximum I/O per Pair878877FG(G)900LXV CCO/GND Pairs1714171478Maximum I/O per Pair767876 LXTV CCO/GND Pairs1514131478Maximum I/O per Pair768876VCCOI/O StandardDriveSlewSSO Limit per V CCO /GND PairAll TQG144, CPG196, CSG225, FT(G)256, and LX devices in CSG324All CS(G)484, FG(G)484, FG(G)676, FG(G)900, and LXT devices in CSG324Bank 0/2Bank 1/3Bank 0/2Bank 1/3/4/51.2VLVCMOS12, LVCMOS12_JEDEC2Fast30 (1)353035Slow 51555152QuietIO 715871704Fast17171719Slow 23252322QuietIO 353235326Fast13151314Slow 19201917QuietIO 262426248FastN/A 12N/A 12Slow N/A 15N/A 13QuietIO N/A 20N/A 1912FastN/A 5N/A 4Slow N/A 8N/A 5QuietION/A11N/A10。

V54C3256164VBS中文资料

All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock.
Operating the four memory banks in an interleaved fashion allows random access operation to occur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 166 MHz is possible depending on burst length, CAS latency and speed grade of the device.
referenced to clock rising edge ■ Single Pulsed RAS Interface ■ Data Mask for Read/Write Control ■ Four Banks controlled by BA0 & BA1 ■ Programmable CAS Latency: 2, 3 ■ Programmable Wrap Sequence: Sequential or
TSOP TSOP TSOP
WBGA WBGA WBGA
SOC BGA SOC BGA SOC BGA
V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002
2
元器件交易网
MOSEL VITELIC

CC2541中文数据手册

POWER-ON RESET BROWN OUT
VDD (2 V–3.6 V) DCOUPL
SFR bus
SLEEP TIMER
HIGH SPEED RC-OSC
32-kHz RC-OSC
POWER MGT. CONTROLLER
8051 CPU CORE
DMA
PDATA XRAM IRAM
SFR
UNIFIED
true
为片上系统（SoC）解决方案
蓝牙
low
能源和专有的2.4-GHz应用.它使建立强大的网络节点
,同时降低总体材料清单成本. CC2541结合了领先的
RF收发器,业界标准的增强型8051 MCU,性能优良的系统内可编程闪存,8 KB RAM和许多其他强大的支持功能和外设
. CC2541是非常适合需要超低功耗的系统.这是指
ADC,转换时
MIN TYP MAX单位 17.9
20.2 mA
16.8
18.2
270
1
µA
0.5
6.7
mA
90
90
60
μA
70
0.6
1.2
mA
4
提交文档反馈
产品文件夹链接（s）： CC2541
Copyright © 2012, Texas Instruments Incorporated
CC2541
1Mbps的GFSK,250 kHz的偏差,
蓝牙
A = 25°C和VDD = 3 V, 低能量模式,和0.1％BER
参数
测试条件
RX模式,标准模式,没有外设活跃,低MCU 活动
高增益模式下,RX模式,没有外设活跃,低MCU 活动

国家机场代码

ATH
摩尔多瓦
基希讷乌
CHISINAU
KIV
立陶宛
维尔纽斯
VILNIUS
VNO
斯洛文尼亚YU
卢布尔雅那
LJUBLAJANA
LJU
波黑
萨拉热窝
SARAJEVO
SJJ
卢森堡LU
卢森堡
LUXEMBOURG
LUX
阿尔巴尼亚RO
地拉那
TIRANA
TIA
摩纳哥
摩纳哥
MONACO
XMM
克罗地亚
萨格勒布
ZAGREB
DUB
科克
CORK
ORK
香农
SHANNON
SNN
奥地利AT
维也纳
VIENNA
VIE
格拉茨
GRAZ
GRZ
林茨
LINZ
LNZ
茵斯布鲁克
INNSBRUCK
INN
萨尔茨堡
SALZBURG
SZG
英国UK
阿伯丁
ABERDEEN
ABZ
贝尔法斯特
BELFAST
BFS
伯明翰
BIRMINHAM
BHX
布里斯托尔
BRISTOL
CALVI
CLY
尚贝里
CHAMBERY
CMF
克莱蒙费朗
CLERMONT-FERRAND
CFE
格勒诺布尔
GRENOBLE
GNB
勒阿弗尔
LE HAVRE
LEH
里摩日
LIMOGES
LIG
洛里昂
LORIENT
LRT
卢尔德塔布
LOURDES-TARBES
LDE

2SC3356中文资料(RENESAS)中文数据手册「EasyDatasheet - 矽搜」

芯片中文手册,看全文,戳
2SC3356
电气特性（T
参数直流特性集电极截止电流发射极截止电流
DC电流增益
射频特性增益带宽产品插入功率增益噪声系数反向传输电容
A = +25°C)
符号
测试条件
ICBO IE B O h Note 1
FE
VCB = 10 V, I E = 0 mA时 VEB = 1.0 V, I C = 0 mA时 VCE = 10 V, I C 能力= 20 mA
和信息.瑞萨电电子不承担由您或因使用上述电路,软件以及相关信息而引起任何损失承担任何责任.
5. 当导出本文档中描述产品或技术,您应遵守适用出口管制法律,法规,并按照这些法律和法规规定程序.你不应该使用瑞萨电子产品或技术本文档中描述由军方关于军事应用或使用任何用途,包括但不限于大规模杀伤武器发展.瑞萨电子产品和技术不得用于或纳入任何产品或系统制造,使用,销售或根据任何适用国内或外国法律或法规禁止.
防止它们之间物理损伤一个故障情况下所造成火灾可能性,和伤害或损害瑞萨电子产品,如安全设计硬件和软件,包括但不限于冗余度,防火和防故障,老化退化或其他任何适当措施,适当治疗.因为单独微机软件评价是非常困难,请评价您所生产最终产品或系统安全性.
10. 请联系瑞萨电子销售处细节,以环境问题,如环境每个瑞萨电子产品兼容性.请使用瑞萨电子产品符合所有适用调控受控物质列入或使用,包括但不限于欧盟RoHS法规指示.瑞萨电子承担对于因您不遵守适用法律法规而导致损害或损失不承担任何责任.
50 100
15 (dB)
2
|21e 10
插入功率增益主场迎战集电极电流
VCE = 10 V F = 1 GHz的

TSL2561传感器中文资料

TSL2561是光-数字转换器，它将光强转换成数字信号输出，具有直接I2C接口或者SMBus接口。

每个设备都连接一个带宽的光敏二极管和在单独CMOS集成电路上的一个红外响应的光敏二极管，这个集成电路具有提供20bit动态范围的近-适光响应的能力。

两个集成的ADCs将光敏电流转换成一个数字输出，这个数字输出表示测量每一个通道的发光。

这个数字输出可以是一个微处理器的输入。

在这个微处理器里亮度（周围光的水平）使用试验化公式来得到。

TSL2560设备允许SNBTSL256x是TAOS公司推出的一种高速、低功耗、宽量程、可编程灵活配置的光强传感器芯片。

本文简要介绍了TSL256x的基本特点、引脚功能、内部结构和工作原理，给出了TSL2561的实用电路、软件设计流程连同核心程式。

关键词光强传感器 TSL256x I2C总线积分式A/D转换器1TSL256x简介TSL2560和TSL2561是TAOS公司推出的一种高速、低功耗、宽量程、可编程灵活配置的光强度数字转换芯片。

该芯片可广泛应用于各类显示屏的监控，目的是在多变的光照条件下，使得显示屏提供最好的显示亮度并尽可能降低电源功耗；还能够用于街道光照控制、安全照明等众多场合。

该芯片的主要特点如下：◇可编程配置许可的光强度上下阈值，当实际光照度超过该阈值时给出中断信号；◇数字输出符合标准的SMBus(TSL2560)和I2C(TSL2561)总线协议；◇模拟增益和数字输出时间可编程控制；◇1.25 mm×1.75 mm超小封装，在低功耗模式下，功耗仅为0.75 mW；◇自动抑制50 Hz/60 Hz的光照波动。

2TSL256x的引脚功能TSL256x有2种封装形式： 6LEAD CHIPSCALE和6LEAD TMB。

封装形式不同，相应的光照度计算公式也不同。

图1为这两种封装形式的引脚分布图。

图1TSL256x封装各引脚的功能如下：脚1和脚3：分别是电源引脚和信号地。

霍尼韦尔(Honeywell)Signature 2551无显示电磁流量计(用户手册) 中文说明书

*3-2552.090*3-2551.090 Rev. 18 06/19Signet 2551无显示电磁流量计中文...................................................................8...........................................................10-12操作说明书• English• 中文22551无显示电磁流量计32551无显示电磁流量计42551无显示电磁流量计52551无显示电磁流量计62551无显示电磁流量计72551无显示电磁流量计82551无显示电磁流量计92551无显示电磁流量计102551无显示电磁流量计112551无显示电磁流量计金属安装件：碳钢三通和焊接式安装件, 不锈钢三通和焊接式安装件，镀锌钢制三通金属安装件：铜制三通和焊接式安装件管径(英寸)安装件型号脉冲/美国加仑脉冲/升“出厂设置为对应20mA的流量，单位为GPM”“出厂设置为对应20mA的流量，单位为LPM”用于SCH40管路的碳钢三通1/2CS4T0051572.66415.501558 3/4CS4T0071086.73287.1127102 1CS4T010582.34153.8644168 1-1/4CS4T012377.4899.7376289 1-1/2CS4T015267.7970.75104394 2CS4T020167.8544.35172651用于SCH40管路的不锈钢三通1/2CR4T0051601.26423.051558 3/4CR4T007937.78247.7627102 1CR4T010606.18160.1544168 1-1/4CR4T012279.6873.8976289 1-1/2CR4T015147.6539.01104394 2CR4T020111.9029.56172651用于SCH40管路的不锈钢焊接式安装件2-1/2CR4W025106.3128.09245927 3CR4W03072.2719.093781433 4CR4W04036.849.736522469 5CR4W05029.287.7310243877 6CR4W06020.29 5.3614805601 8CR4W08011.73 3.1025579680 10CR4W1007.45 1.97403215262 12CR4W120 5.24 1.39572521671用于SCH40管路的碳钢焊接式安装件2-1/2CS4W025105.7027.93245927 3CS4W03070.6818.673781433 4CS4W04036.389.616522469 5CS4W05029.287.7310243877 6CS4W06020.29 5.3614805601 8CS4W08011.73 3.1025579680 10CS4W1007.45 1.97403215262 12CS4W120 5.24 1.39572521671用于SCH40管路的镀锌钢制三通1IR4T010558.50147.5644168 1-1/4IR4T012334.4588.3676289 1-1/2IR4T015248.9765.78104394 2IR4T020146.0038.57172651管径(英寸)安装件型号脉冲/美国加仑脉冲/升“出厂设置为对应20mA的流量，单位为GPM”“出厂设置为对应20mA的流量，单位为LPM”用于SCH40管路的铜制三通1BR4T010582.34153.8644168 1-1/4BR4T012330.5487.3376289 1-1/2BR4T015254.7667.31104394 2BR4T020157.3641.58172651用于SCH K铜管的铜制三通1/2CUKT0052459.19649.721142 3/4CUKT0071108.02292.742284 1CUKT010649.87171.7040150 1-1/4CUKT012422.03111.5062236 1-1/2CUKT015281.4374.3588333 2CUKT020136.0235.94154583用于SCH L铜管的铜制三通1/2CUKT0052406.30635.751142 3/4CUKT0071174.77310.372284 1CUKT010672.28177.6240150 1-1/4CUKT012402.84106.4362236 1-1/2CUKT015294.9977.9488333 2CUKT020149.6339.53154583用于SCH 40管路的铜制焊接式安装件2-1/2BR4B025117.3130.99245927 3BR4B03078.6220.773781433 4BR4B04045.1311.926522469 5BR4B05032.798.6610243877 6BR4B06022.73 6.0114805601 8BR4B08013.14 3.4725579680 10BR4B1008.34 2.20403215262 12BR4B120 5.87 1.55572521671132551无显示电磁流量计142551无显示电磁流量计152551无显示电磁流量计乔治费歇尔•中国上海 021 3899 3899 北京 010 5682 1599 深圳 0755 8228 0172/73 成都 028 8608 8556 西安 029 8819 3-2551.090 Rev. 18 06/19 English© Georg Fischer Signet LLC 2019制造商部件号订货代码描述3-2551-P0-12159 001 110DN15-DN100，PP和316L不锈钢3-2551-T0-12159 001 113DN15-DN100，PVDF和钛3-2551-V0-12159 001 259DN15-DN100，PVDF和哈氏合金C 3-2551-P1-12159 001 111DN125-DN200，PP和316L不锈钢3-2551-T1-12159 001 114DN125-DN200，PVDF和钛3-2551-V1-12159 001 260DN125-DN200，PVDF和哈氏合金C 3-2551-P2-12159 001 112DN250-DN900，PP和316L不锈钢3-2551-T2-12159 001 449DN250-DN900，PVDF和钛3-2551-V2-12159 001 451DN250-DN900，PVDF和哈氏合金C制造商部件号订货代码描述3-2551-P0-11159 001 105DN15-DN100，PP和316L不锈钢3-2551-T0-11159 001 108DN15-DN100，PVDF和钛3-2551-V0-11159 001 257DN15-DN100，PVDF和哈氏合金C 3-2551-P1-11159 001 106DN125-DN200，PP和316L不锈钢3-2551-T1-11159 001 109DN125-DN200，PVDF和钛3-2551-V1-11159 001 258DN125-DN200，PVDF和哈氏合金C 3-2551-P2-11159 001 107DN250-DN900，PP和316L不锈钢3-2551-T2-11159 001 448DN250-DN900，PVDF和钛3-2551-V2-11159 001 450DN250-DN900，PVDF和哈氏合金C4-20mA输出频率或数字（S³L）输出。

六氟化硫安全技术说明书MSDS

第一部分化学品及企业标识化学品中文名：六氟化硫化学品英文名：sulphurhexafluorideCAS No.：2551-62-4EC No.：219-854-2分子式：SF6第二部分危险性概述紧急情况概述气体。

高压，遇热有爆炸危险。

气体可能会引起头晕或窒息。

GHS危险性类别根据GB30000-2013化学品分类和标签规范系列标准（参阅第十六部分），该产品分类如下：高压气体，压缩气体；特定目标器官毒性-单次接触：麻醉效应，类别3。

标签要素象形图警示词：警告危险信息：内装高压气体；遇热可能爆炸，可能造成昏睡或眩晕。

预防措施：避免吸入粉尘/烟/气体/烟雾/蒸气/喷雾。

受沾染的工作服不得带出工作场地。

事故响应：求医/就诊。

如误吸入：将受人转移到空气新鲜处，保持呼吸舒适的体位。

安全储存：存放在通风良好的地方。

保持容器密闭。

防日晒。

存放于通风良好处。

废弃处置：按照地方/区域/国家/国际规章处置内装物/容器。

物理化学危险：高压压缩气体，遇热有爆炸危险。

健康危害：吸入本品可能引起瞌睡和头昏眼花，可能伴随嗜睡、警惕性下降、反射作用消失、失去协调性并感到眩晕。

吸入该物质可能会引起对健康有害的影响或呼吸道不适。

由于本品的物理状态，一般没有危害。

在商业/工业场合中，认为本品不太可能进入体内。

通过割伤、擦伤或病变处进入血液，可能产生全身损伤的有害作用。

眼睛直接接触本品可导致暂时不适。

环境危害：请参阅SDS第十二部分。

第三部分成分/组成信息√物质混合物第四部分急救措施急救措施描述一般性建议：急救措施通常是需要的，请将本SDS出示给到达现场的医生。

皮肤接触：立即脱去污染的衣物。

用大量肥皂水和清水冲洗皮肤。

如有不适，就医。

眼睛接触：用大量水彻底冲洗至少15分钟。

如有不适，就医。

吸入：立即将患者移到新鲜空气处，保持呼吸畅通。

如果呼吸困难，给于吸氧。

如患者食入或吸入本物质，不得进行口对口人工呼吸。

如果呼吸停止。

立即进行心肺复苏术。

TSL2561CS资料

D Approximates Human Eye Response toControl Display Backlight and Keyboard IlluminationD Precisely Measures Illuminance in Diverse Lighting Conditions Providing Exposure Control in CamerasD Programmable Interrupt Function with User-Defined Upper and Lower Threshold SettingsD 16-Bit Digital Output with SMBus (TSL2560)or I 2C (TSL2561) Fast-Mode at 400 KHzD Programmable Analog Gain and Integration Time Supporting 1,000,000-to-1 Dynamic RangeD Available in Ultra-Small 1.25 mm y 1.75 mm Chipscale PackageD Automatically Rejects 50/60-Hz Lighting RippleDLow Active Power (0.75 mW Typical) with Power Down Mode DRoHS CompliantDescriptionThe TSL2560 and TSL2561 are light-to-digital converters that transform light intensity to a digital signal output capable of direct I 2C (TSL2561) or SMBus (TSL2560) interface. Each device combines one broadband photodiode (visible plus infrared) and one infrared-responding photodiode on a single CMOS integrated circuit capable of providing a near-photopic response over an effective 20-bit dynamic range (16-bit resolution). Two 6 SDA 5 INT 4 SCLPACKAGE T 6-LEAD TMB (TOP VIEW)V DD 1ADDR SEL 2GND 3PACKAGE CS 6-LEAD CHIPSCALE(TOP VIEW)V DD 1ADDR SEL 2GND 36 SDA 5 INT 4 SCLPackage Drawings are Not to ScaleTSL2560, TSL2561LIGHT-TO-DIGITAL CONVERTERFunctional Block DiagramV DD Detailed DescriptionThe TSL2560 and TSL2561 are second-generation ambient light sensor devices. Each contains two integrating analog-to-digital converters (ADC) that integrate currents from two photodiodes. Integration of both channels occurs simultaneously. Upon completion of the conversion cycle, the conversion result is transferred to the Channel 0 and Channel 1 data registers, respectively. The transfers are double-buffered to ensure that the integrity of the data is maintained. After the transfer, the device automatically begins the next integration munication to the device is accomplished through a standard, two-wire SMBus or I 2C serial bus.Consequently, the TSL256x device can be easily connected to a microcontroller or embedded controller. No external circuitry is required for signal conditioning, thereby saving PCB real estate as well. Since the output of the TSL256x device is digital, the output is effectively immune to noise when compared to an analog signal.The TSL256x devices also support an interrupt feature that simplifies and improves system efficiency by eliminating the need to poll a sensor for a light intensity value. The primary purpose of the interrupt function is to detect a meaningful change in light intensity. The concept of a meaningful change can be defined by the user both in terms of light intensity and time, or persistence, of that change in intensity. The TSL256x devices have the ability to define a threshold above and below the current light level. An interrupt is generated when the value of a conversion exceeds either of these limits.TSL2560, TSL2561LIGHT-TO-DIGITAL CONVERTERTAOS059K − APRIL 2007Terminal FunctionsTERMINALNAME CS PKG NO.T PKG NO.TYPE DESCRIPTIONADDR SEL 22ISMBus device select — three-stateGND 33Power supply ground. All voltages are referenced to GND.INT 55O Level or SMB Alert interrupt — open drain.SCL 44I SMBus serial clock input terminal — clock signal for SMBus serial data.SDA 66I/O SMBus serial data I/O terminal — serial data I/O for SMBus.V DD11Supply voltage.Available OptionsDEVICE INTERFACE PACKAGE − LEADSPACKAGE DESIGNATORORDERING NUMBERTSL2560SMBus Chipscale CS TSL2560CS TSL2560SMBus TMB-6T TSL2560T TSL2561I 2C Chipscale CS TSL2561CS TSL2561I 2CTMB-6TTSL2561TAbsolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)†Supply voltage, V DD (see Note 1) 3.8 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital output voltage range, V O −0.5 V to 3.8 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital output current, I O −1 mA to 20 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage temperature range, T stg −40°C to 85°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESD tolerance, human body model 2000 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.NOTE 1:All voltages are with respect to GND.Recommended Operating ConditionsMINNOMMAX UNIT Supply voltage, V DD2.733.6V Operating free-air temperature, T A −3070°C SCL, SDA input low voltage, V IL −0.50.8V SCL, SDA input high voltage, V IH2.13.6VElectrical Characteristics over recommended operating free-air temperature range (unless otherwise noted)PARAMETERTEST CONDITIONSMINTYP MAX UNIT Active 0.240.6mA I DD Supply currentPower down 3.215μA INT SDA output low voltage 3 mA sink current 00.4V V OL INT, SDA output low voltage 6 mA sink current00.6V I LEAKLeakage current−55μATSL2560, TSL2561LIGHT-TO-DIGITAL CONVERTERTAOS059K − APRIL 2007Operating Characteristics, High Gain (16 ), V DD = 3 V, T A = 255C, (unless otherwise noted) (see Notes 2, 3, 4, 5)TSL2560T, TSL2561T TSL2560CS, TSL2561CSPARAMETERTEST CONDITIONSCHANNELMIN TYP MAX MIN TYP MAX UNIT f oscOscillator frequency 690735780690735780kHz 0 T 402 ms Ch00404Dark ADC count valueE e = 0, T int = 402 ms Ch10404counts178 msCh06553565535T int > 178 ms Ch16553565535Full scale ADC count101 ms Ch0371*******value (Note 6)T int = 101 ms Ch137********counts 137 msCh050475047T int = 13.7 ms Ch150475047λCh075010001250p = 640 nm, T int = 101 ms E e = 36.3 μW/cm 2Ch1200λCh070010001300countsp = 940 nm, T int = 101 ms E e = 119 μW/cm 2Ch1820ADC count valueCh075010001250λp = 640 nm, T int = 101 ms E e = 41 μW/cm 2Ch1190λCh070010001300countsp = 940 nm, T int = 101 ms E e = 135 μW/cm 2Ch1850ADC t l ti 640 nm T 101 ms 015020025014019024ADC count value ratio:λp = 640 nm, T int = 101 ms 0.150.200.250.140.190.24 940 nm T 101 ms 069082095070085Ch1/Ch0λp = 940 nm, T int = 101 ms 0.690.820.950.700.851 640 nm T 101 msCh027.524.4λp = 640 nm, T int = 101 ms Ch1 5.5 4.6counts/R eIrradiance responsivity940 nm T 101 ms Ch08.47.4(μW/λp = 940 nm, T int = 101 ms Ch1 6.9 6.3cm 2)Fluorescent light source: Ch03635T int = 402 msCh14 3.8counts/R vIlluminance responsivityIncandescent light source: Ch0144129lux T int = 402 msCh17267ADC count value ratio:Fluorescent light source: T int = 402 ms0.110.11Incandescent light source: 05052Ch1/Ch0T int = 402 ms0.50.52Fluorescent light source: Ch0 2.3 2.2Illuminance responsivity,T int = 402 msCh10.250.24counts/R vlow gain mode (Note 7)Incandescent light source: Ch098.1lux T int = 402 msCh14.5 4.2(Sensor Lux) /(actual Lux) high gain Fluorescent light source: T int = 402 ms0.651 1.350.651 1.35(actual Lux), high gain mode (Note 8)Incandescent light source: T int = 402 ms0.6011.400.6011.40TSL2560, TSL2561LIGHT-TO-DIGITAL CONVERTERTAOS059K − APRIL 2007NOTES: 2.Optical measurements are made using small-angle incident radiation from light-emitting diode optical sources. Visible 640 nm LEDsand infrared 940 nm LEDs are used for final product testing for compatibility with high-volume production.3.The 640 nm irradiance E e is supplied by an Al I nGaP light-emitting diode with the following characteristics: peak wavelengthλp = 640 nm and spectral halfwidth Δλ½ = 17 nm.4.The 940 nm irradiance E e is supplied by a GaAs light-emitting diode with the following characteristics: peak wavelengthλp = 940 nm and spectral halfwidth Δλ½ = 40 nm.5.Integration time T int , is dependent on internal oscillator frequency (f osc ) and on the integration field value in the timing register asdescribed in the Register Set section. For nominal f osc = 735 kHz, nominal T int = (number of clock cycles)/f osc . Field value 00: T int = (11 × 918)/f osc = 13.7 ms Field value 01: T int = (81 × 918)/f osc = 101 ms Field value 10: T int = (322 × 918)/f osc = 402 msScaling between integration times vary proportionally as follows: 11/322 = 0.034 (field value 00), 81/322 = 0.252 (field value 01),and 322/322 = 1 (field value 10).6.Full scale ADC count value is limited by the fact that there is a maximum of one count per two oscillator frequency periods and alsoby a 2-count offset.Full scale ADC count value = ((number of clock cycles)/2 − 2)Field value 00: Full scale ADC count value = ((11 × 918)/2 − 2) = 5047Field value 01: Full scale ADC count value = ((81 × 918)/2 − 2) = 37177Field value 10: Full scale ADC count value = 65535, which is limited by 16 bit register. This full scale ADC count value is reached for 131074 clock cycles, which occurs for T int = 178 ms for nominal f osc = 735 kHz.7.Low gain mode has 16y lower gain than high gain mode: (1/16 = 0.0625).8.The sensor Lux is calculated using the empirical formula shown on p. 22 of this data sheet based on measured Ch0 and Ch1 ADCcount values for the light source specified. Actual Lux is obtained with a commercial luxmeter. The range of the (sensor Lux) / (actual Lux) ratio is estimated based on the variation of the 640 nm and 940 nm optical parameters. Devices are not 100% tested with fluorescent or incandescent light sources.TSL2560, TSL2561LIGHT-TO-DIGITAL CONVERTERTAOS059K − APRIL 2007AC Electrical Characteristics, V DD = 3 V, T A = 255C (unless otherwise noted)PARAMETER †TEST CONDITIONS MIN TYP MAX UNIT t (CONV)Conversion time 12100400ms f (SCL)Clock frequency400kHz t (BUF)Bus free time between start and stop condition 1.3μs t (HDSTA)Hold time after (repeated) start condition. After this period, the first clock is generated.0.6μs t (SUSTA)Repeated start condition setup time 0.6μs t (SUSTO)Stop condition setup time 0.6μst (HDDAT)Data hold time 00.9μs t (SUDAT)Data setup time 100ns t (LOW)SCL clock low period 1.3μs t (HIGH)SCL clock high period0.6μst (TIMEOUT)Detect clock/data low timeout (SMBus only)2535ms t F Clock/data fall time 300ns t R Clock/data rise time 300ns C iInput pin capacitance10pF†Specified by design and characterization; not production tested.TSL2560, TSL2561LIGHT-TO-DIGITAL CONVERTERTAOS059K − APRIL 2007PARAMETER MEASUREMENT INFORMATIONSDASCLStartConditionStopConditionPSDAtSCLPSSFigure 1. Timing DiagramsSCLStart bySDAFrame 1 SMBus Slave Address Byte Frame 2 Command ByteACK by Stop by ACK by Figure 2. Example Timing Diagram for SMBus Send Byte FormatSCLStart by MasterSDAFrame 1 SMBus Slave Address Byte Frame 2 Data Byte From TSL256xACK by Stop by MasterNACK by Figure 3. Example Timing Diagram for SMBus Receive Byte FormatTSL2560, TSL2561LIGHT-TO-DIGITAL CONVERTERTAOS059K − APRIL 2007TYPICAL CHARACTERISTICSFigure 4SPECTRAL RESPONSIVITYλ − Wavelength − nm04000.20.40.60.8150060070080090010001100N o r m a l i z e d R e s p o n s i v i t y300Figure 5NORMALIZED RESPONSIVITYvs.ANGULAR DISPLACEMENT — CS PACKAGEQ − Angular Displacement − °N o r m a l i z e d R e s p o n s i v i t y00.20.40.60.81.0−90−60−300306090Figure 6NORMALIZED RESPONSIVITYvs.ANGULAR DISPLACEMENT — TMB PACKAGEQ − Angular Displacement − °N o r m a l i z e d R e s p o n s i v i t y00.20.40.60.81.0−90−60−300306090TSL2560, TSL2561LIGHT-TO-DIGITAL CONVERTERTAOS059K − APRIL 2007PRINCIPLES OF OPERATIONAnalog-to-Digital ConverterThe TSL256x contains two integrating analog-to-digital converters (ADC) that integrate the currents from the channel 0 and channel 1 photodiodes. Integration of both channels occurs simultaneously, and upon completion of the conversion cycle the conversion result is transferred to the channel 0 and channel 1 data registers,respectively. The transfers are double buffered to ensure that invalid data is not read during the transfer. After the transfer, the device automatically begins the next integration cycle.Digital InterfaceInterface and control of the TSL256x is accomplished through a two-wire serial interface to a set of registers that provide access to device control functions and output data. The serial interface is compatible with System Management Bus (SMBus) versions 1.1 and 2.0, and I 2C bus Fast-Mode. The TSL256x offers three slave addresses that are selectable via an external pin (ADDR SEL). The slave address options are shown in T able 1.Table 1. Slave Address SelectionADDR SEL TERMINAL LEVELSLAVE ADDRESSSMB ALERT ADDRESSGND 01010010001100Float 01110010001100VDD10010010001100NOTE:The Slave and SMB Alert Addresses are 7 bits. Please note the SMBus and I 2C protocols on pages 9 through 12. A read/write bit shouldbe appended to the slave address by the master device to properly communicate with the TSL256X device.SMBus and I 2C ProtocolsEach Send and Write protocol is, essentially, a series of bytes. A byte sent to the TSL256x with the most significant bit (MSB) equal to 1 will be interpreted as a COMMAND byte. The lower four bits of the COMMAND byte form the register select address (see Table 2), which is used to select the destination for the subsequent byte(s) received. The TSL256x responds to any Receive Byte requests with the contents of the register specified by the stored register select address.The TSL256X implements the following protocols of the SMB 2.0 specification:D Send Byte Protocol D Receive Byte Protocol D Write Byte Protocol D Write Word Protocol D Read Word Protocol D Block Write Protocol DBlock Read ProtocolThe TSL256X implements the following protocols of the Philips Semiconductor I 2C specification:D I 2C Write ProtocolD I 2C Read (Combined Format) ProtocolTSL2560, TSL2561LIGHT-TO-DIGITAL CONVERTERTAOS059K − APRIL 2007When an SMBus Block Write or Block Read is initiated (see description of COMMAND Register), the byte following the COMMAND byte is ignored but is a requirement of the SMBus specification. This field contains the byte count (i.e. the number of bytes to be transferred). The TSL2560 (SMBus) device ignores this field and extracts this information by counting the actual number of bytes transferred before the Stop condition is detected.When an I 2C Write or I 2C Read (Combined Format) is initiated, the byte count is also ignored but follows the SMBus protocol specification. Data bytes continue to be transferred from the TSL2561 (I 2C) device to Master until a NACK is sent by the Master.The data formats supported by the TSL2560 and TSL2561 devices are:D Master transmitter transmits to slave receiver (SMBus and I 2C):−The transfer direction in this case is not changed.D Master reads slave immediately after the first byte (SMBus only):−At the moment of the first acknowledgment (provided by the slave receiver) the master transmitter becomes a master receiver and the slave receiver becomes a slave transmitter.D Combined format (SMBus and I 2C):−During a change of direction within a transfer, the master repeats both a START condition and the slave address but with the R/W bit reversed. In this case, the master receiver terminates the transfer by generating a NACK on the last byte of the transfer and a STOP condition.For a complete description of SMBus protocols, please review the SMBus Specification at /specs. For a complete description of I 2C protocols, please review the I 2C Specification at .XXA Acknowledge (this bit position may be 0 for an ACK or 1 for a NACK)P Stop Condition RdRead (bit value of 1)S Start ConditionSr Repeated Start Condition Wr Write (bit value of 0)XShown under a field indicates that that field is required to have a value of X ...Continuation of protocolFigure 7. SMBus and I 2C Packet Protocol Element KeyTAOS059K − APRIL 2007Figure 8. SMBus Send Byte Protocol1Figure 9. SMBus Receive Byte ProtocolFigure 10. SMBus Write Byte Protocol1Figure 11. SMBus Read Byte ProtocolFigure 12. SMBus Write Word Protocol...1Figure 13. SMBus Read Word ProtocolTAOS059K − APRIL 2007......Figure 14. SMBus Block Write or I2C Write ProtocolsNOTE:The I 2C write protocol does not use the Byte Count packet, and the Master will continue sending Data Bytes until the Master initiates aStop condition. See the Command Register on page 13 for additional information regarding the Block Read/Write protocol.......1Figure 15. SMBus Block Read or I 2C Read (Combined Format) ProtocolsNOTE:The I 2C read protocol does not use the Byte Count packet, and the Master will continue receiving Data Bytes until the Master initiatesa Stop Condition. See the Command Register on page 13 for additional information regarding the Block Read/Write protocol.Register SetThe TSL256x is controlled and monitored by sixteen registers (three are reserved) and a command register accessed through the serial interface. These registers provide for a variety of control functions and can be read to determine results of the ADC conversions. The register set is summarized in Table 2.Table 2. Register AddressADDRESSRESISTER NAME REGISTER FUNCTION−−COMMAND Specifies register address 0h CONTROL Control of basic functions 1h TIMING Integration time/gain control 2h THRESHLOWLOW Low byte of low interrupt threshold 3h THRESHLOWHIGH High byte of low interrupt threshold 4h THRESHHIGHLOW Low byte of high interrupt threshold 5h THRESHHIGHHIGHHigh byte of high interrupt threshold 6h INTERRUPTInterrupt control 7h −−Reserved8h CRC Factory test — not a user register 9h −−ReservedAh ID Part number/ Rev ID Bh −−ReservedCh DATA0LOW Low byte of ADC channel 0Dh DATA0HIGH High byte of ADC channel 0Eh DATA1LOW Low byte of ADC channel 1FhDATA1HIGHHigh byte of ADC channel 1The mechanics of accessing a specific register depends on the specific SMB protocol used. Refer to the section on SMBus protocols. In general, the COMMAND register is written first to specify the specific control/status register for following read/write operations.TAOS059K − APRIL 2007Command RegisterThe command register specifies the address of the target register for subsequent read and write operations.The Send Byte protocol is used to configure the COMMAND register. The command register contains eight bits as described in Table 3. The command register defaults to 00h at power on.Table 3. Command Register675423100Reset Value:COMMANDFIELD BIT DESCRIPTIONCMD 7Select command register. Must write as 1.CLEAR 6Interrupt clear. Clears any pending interrupt. This bit is a write-one-to-clear bit. It is self clearing.WORD 5SMB Write/Read Word Protocol. 1 indicates that this SMB transaction is using either the SMB Write Word or Read Word protocol.BLOCK 4Block Write/Read Protocol. 1 indicates that this transaction is using either the Block Write or the Block Readprotocol. See Note below.ADDRESS3:0Register Address. This field selects the specific control or status register for following write and read commands according to Table 2.NOTE:An I 2C block transaction will continue until the Master sends a stop condition. See Figure 14 and Figure 15. Unlike the I2C protocol, theSMBus read/write protocol requires a Byte Count. All four ADC Channel Data Registers (Ch through Fh) can be read simultaneously in a single SMBus transaction. This is the only 32-bit data block supported by the TSL2560 SMBus protocol. The BLOCK bit must be set to 1, and a read condition should be initiated with a COMMAND CODE of 9Bh. By using a COMMAND CODE of 9Bh during an SMBus Block Read Protocol, the TSL2560 device will automatically insert the appropriate Byte Count (Byte Count = 4) as illustrated in Figure 15.A write condition should not be used in conjunction with the Bh register.Control Register (0h)The CONTROL register contains two bits and is primarily used to power the TSL256x device up and down as shown in Table 4.Table 4. Control Register67542310000Reset Value:CONTROL0h FIELD BIT DESCRIPTIONResv7:2Reserved. Write as 0.POWER 1:0Power up/power down. By writing a 03h to this register, the device is powered up. By writing a 00h to this register, the device is powered down.NOTE: If a value of 03h is written, the value returned during a read cycle will be 03h. This feature can be used to verify that the device is communicating properly.TAOS059K − APRIL 2007Timing Register (1h)The TIMING register controls both the integration time and the gain of the ADC channels. A common set of control bits is provided that controls both ADC channels. The TIMING register defaults to 02h at power on.Table 5. Timing Register67542310010Reset Value:TIMING1h FIELD BIT DESCRIPTIONResv 7−5Reserved. Write as 0.GAIN 4Switches gain between low gain and high gain modes. Writing a 0 selects low gain (1×); writing a 1 selects high gain (16×).Manual 3Manual timing control. Writing a 1 begins an integration cycle. Writing a 0 stops an integration cycle.NOTE: This field only has meaning when INTEG = 11. It is ignored at all other times.Resv 2Reserved. Write as 0.INTEG1:0Integrate time. This field selects the integration time for each conversion.Integration time is dependent on the INTEG FIELD VALUE and the internal clock frequency. Nominal integration times and respective scaling between integration times scale proportionally as shown in Table 6. See Note 5and Note 6 on page 5 for detailed information regarding how the scale values were obtained; see page 22 for further information on how to calculate lux.Table 6. Integration TimeINTEG FIELD VALUESCALE NOMINAL INTEGRATION TIME000.03413.7 ms 010.252101 ms 101402 ms 11−−N/AThe manual timing control feature is used to manually start and stop the integration time period. If a particular integration time period is required that is not listed in Table 6, then this feature can be used. For example, the manual timing control can be used to synchronize the TSL256x device with an external light source (e.g. LED).A start command to begin integration can be initiated by writing a 1 to this bit field. Correspondingly, the integration can be stopped by simply writing a 0 to the same bit field.Interrupt Threshold Register (2h − 5h)The interrupt threshold registers store the values to be used as the high and low trigger points for the comparison function for interrupt generation. If the value generated by channel 0 crosses below or is equal to the low threshold specified, an interrupt is asserted on the interrupt pin. If the value generated by channel 0 crosses above the high threshold specified, an interrupt is asserted on the interrupt pin. Registers THRESHLOWLOW and THRESHLOWHIGH provide the low byte and high byte, respectively, of the lower interrupt threshold.Registers THRESHHIGHLOW and THRESHHIGHHIGH provide the low and high bytes, respectively, of the upper interrupt threshold. The high and low bytes from each set of registers are combined to form a 16-bit threshold value. The interrupt threshold registers default to 00h on power up.TAOS059K − APRIL 2007Table 7. Interrupt Threshold RegisterREGISTER ADDRESSBITS DESCRIPTIONTHRESHLOWLOW 2h 7:0ADC channel 0 lower byte of the low threshold THRESHLOWHIGH 3h 7:0ADC channel 0 upper byte of the low threshold THRESHHIGHLOW 4h 7:0ADC channel 0 lower byte of the high threshold THRESHHIGHHIGH5h7:0ADC channel 0 upper byte of the high thresholdNOTE:Since two 8-bit values are combined for a single 16-bit value for each of the high and low interrupt thresholds, the Send Byte protocol shouldnot be used to write to these registers. Any values transferred by the Send Byte protocol with the MSB set would be interpreted as the COMMAND field and stored as an address for subsequent read/write operations and not as the interrupt threshold information as desired.The Write Word protocol should be used to write byte-paired registers. For example, the THRESHLOWLOW and THRESHLOWHIGH registers (as well as the THRESHHIGHLOW and THRESHHIGHHIGH registers) can be written together to set the 16-bit ADC value in a single transaction.Interrupt Control Register (6h)The INTERRUPT register controls the extensive interrupt capabilities of the TSL256x. The TSL256x permits both SMB-Alert style interrupts as well as traditional level-style interrupts. The interrupt persist bit field (PERSIST) provides control over when interrupts occur. A value of 0 causes an interrupt to occur after every integration cycle regardless of the threshold settings. A value of 1 results in an interrupt after one integration time period outside the threshold window. A value of N (where N is 2 through15) results in an interrupt only if the value remains outside the threshold window for N consecutive integration cycles. For example, if N is equal to 10 and the integration time is 402 ms, then the total time is approximately 4 seconds.When a level Interrupt is selected, an interrupt is generated whenever the last conversion results in a value outside of the programmed threshold window. The interrupt is active-low and remains asserted until cleared by writing the COMMAND register with the CLEAR bit set.In SMBAlert mode, the interrupt is similar to the traditional level style and the interrupt line is asserted low. To clear the interrupt, the host responds to the SMBAlert by performing a modified Receive Byte operation, in which the Alert Response Address (ARA) is placed in the slave address field, and the TSL256x that generated the interrupt responds by returning its own address in the seven most significant bits of the receive data byte. If more than one device connected on the bus has pulled the SMBAlert line low, the highest priority (lowest address)device will win communication rights via standard arbitration during the slave address transfer. If the device loses this arbitration, the interrupt will not be cleared. The Alert Response Address is 0Ch.When INTR = 11, the interrupt is generated immediately following the SMBus write operation. Operation then behaves in an SMBAlert mode, and the software set interrupt may be cleared by an SMBAlert cycle.NOTE:Interrupts are based on the value of Channel 0 only.Table 8. Interrupt Control Register675423100000000Reset Value:INTERRUPT6h FIELD BITS DESCRIPTIONResv 7:6Reserved. Write as 0.INTR 5:4INTR Control Select. This field determines mode of interrupt logic according to Table 9, below.PERSIST3:0Interrupt persistence. Controls rate of interrupts to the host processor as shown in Table 10, below.。

RF基本概念剖析

GPRS test item
1.Output Avg Power 2.BurstMatching 3.Modulation&Switching Spectrum 4.Phase&Frequency Error 5.Block Error Rate
EDGE(2.75G)
• EGPRS（也称为EDGE）是英文Enhanced Data Rate for GSM Evolution 的缩写，即增强型数据速率GSM演进技术。
技术（Packet Binary Convolutional Code）在IEEE 802.11b（2.4GHz频段）基础上提供22Mbit/s的数据传输速率。但这事实上并不是一个IEEE的公开标准，而是一项产权私有的技术，产权属于美国德州仪器公司。
Wifi 测试仪器
• IQVIEW和IQFLEX
2. 无需直线传播传输范围为室外最大300米，室内有障碍的情况下最大100米，是现在使用的最多的传输协议。
802.11协议
• 802.11协议组是国际电工电子工程学会（IEEE）为无线局域网络制定的标准。
• *IEEE 802.11，1997年，原始标准（2Mbit/s，工作在2.4GHz）。 • * IEEE802.11a，1999年，物理层补充（54Mbit/s，工作在5GHz）。 • *IEEE 802.11b，1999年，物理层补充（11Mbit/s工作在2.4GHz）。 • * IEEE802.11g，2003年，物理层补充（54Mbit/s，工作在2.4GHz）。 • * IEEE 802.11n，2009年9月通过正式标准，WLAN的传输速率由802.11a及
BT
• Bluetooth 取自中世纪北欧丹麦维京国王： Harald Blaatand “Bluetooth” II(940-981)，统一当时的丹麦和挪威。