CD4013BCMX_NL中文资料

© 2002 Fairchild Semiconductor Corporation DS005946October 1987Revised March 2002CD4013BC Dual D-Type Flip-FlopCD4013BCDual D-Type Flip-FlopGeneral DescriptionThe CD4013B dual D-type flip-flop is a monolithic comple-mentary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement mode transistors. Each flip-flop has independent data, set, reset, and clock inputs and “Q” and “Q” outputs. These devices can be used for shift register applications, and by connecting “Q” output to the data input, for counter and toggle applications. The logic level present at the “D” input is transferred to the Q output during the positive-going transition of the clock pulse. Setting or resetting is independent of the clock and is accomplished by a high level on the set or reset line respectively.Featuress Wide supply voltage range: 3.0V to 15V s High noise immunity:0.45 V DD (typ.)s Low power TTL:fan out of 2 driving 74Lcompatibility:or 1 driving 74LSApplications•Automotive •Data terminals •Instrumentation •Medical electronics •Alarm system •Industrial electronics •Remote metering •ComputersOrdering Code:Devices also available in T ape and Reel. Specify by appending the suffix letter “X ” to the ordering code.Connection Diagram Top ViewTruth TableNo Changex = Don't Care CaseNote 1: Level ChangeOrder Number Package NumberPackage DescriptionCD4013BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow CD4013BCSJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide CD4013BCNN14A14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" WideCL (Note 1)D R S Q Q 00001 10010 x 00Q Q x x 1001x x 0110xx1111 2C D 4013B CSchematic DiagramsLogic DiagramCD4013BCAbsolute Maximum Ratings (Note 2)(Note 3)Recommended Operating Conditions (Note 3)Note 2: “Absolute Maximum Ratings ” are those values beyond which the safety of the device cannot be guaranteed, they are not meant to imply that the devices should be operated at these limits. The tables of “Recom-mended Operating Conditions ” and “Electrical Characteristics ” provide con-ditions for actual device operation.Note 3: V SS = 0V unless otherwise specified.DC Electrical Characteristics (Note 3)Note 4: I OH and I OL are measured one output at a time.DC Supply Voltage (V DD )−0.5 V DC to +18 V DC Input Voltage (V IN )−0.5 V DC to V DD +0.5 V DCStorage Temperature Range (T S )−65°C to +150°CPower Dissipation (P D )Dual-In-Line 700 mW Small Outline 500 mWLead Temperature (T L )(Soldering, 10 seconds)260°C DC Supply Voltage (V DD )+3 V DC to +15 V DC Input Voltage (V IN )V DC to V DD V DCOperating Temperature Range (T A )−55°C to +125°CSymbol ParameterConditions−55°C +25°C +125°C UnitsMinMax MinTypMax MinMax I DDQuiescent Device V DD = 5V, V IN = V DD or V SS 1.0 1.030µACurrentV DD = 10V, V IN = V DD or V SS 2.0 2.060V DD = 15V, V IN = V DD or V SS 4.0 4.0120V OLLOW Level |I O | < 1.0 µA VOutput VoltageV DD = 5V 0.050.050.05V DD = 10V 0.050.050.05V DD = 15V0.050.050.05V OHHIGH Level |I O | < 1.0 µA VOutput VoltageV DD = 5V 4.95 4.95 4.95V DD = 10V 9.959.959.95V DD = 15V14.9514.9514.95V ILLOW Level |I O | < 1.0 µAVInput VoltageV DD = 5V, V O = 0.5V or 4.5V 1.5 1.5 1.5V DD = 10V, V O = 1.0V or 9.0V 3.0 3.0 3.0V DD = 15V, V O = 1.5V or 13.5V4.04.04.0V IHHIGH Level |I O | < 1.0 µAVInput VoltageV DD = 5V, V O = 0.5V or 4.5V 3.5 3.5 3.5V DD = 10V, V O = 1.0V or 9.0V 7.07.07.0V DD = 15V, V O = 1.5V or 13.5V11.011.011.0I OLLOW Level Output V DD = 5V, V O = 0.4V 0.640.510.880.36mACurrent (Note 4)V DD = 10V, V O = 0.5V 1.6 1.3 2.250.9V DD = 15V, V O = 1.5V 4.2 3.48.8 2.4I OHHIGH Level Output V DD = 5V, V O = 4.6V −0.64−0.51−0.88−0.36mACurrent (Note 4)V DD = 10V, V O = 9.5V −1.6−1.3−2.25−0.9V DD = 15V, V O = 13.5V −4.2−3.4−8.8−2.4I INInput CurrentV DD = 15V, V IN = 0V −0.1−10−5−0.1−1.0µAV DD = 15V, V IN = 15V0.110−50.11.0 4C D 4013B CAC Electrical Characteristics (Note 5)T A = 25°C, C L = 50 pF, R L = 200k, unless otherwise notedNote 5: AC Parameters are guaranteed by DC correlated testing.Switching Time WaveformsSymbol Parameter Conditions Min Typ Max UnitsCLOCK OPERATION t PHL , t PLHPropagation Delay TimeV DD = 5V 200350nsV DD = 10V 80160V DD = 15V65120t THL , t TLHTransition TimeV DD = 5V 100200nsV DD = 10V 50100V DD = 15V4080t WL , t WHMinimum Clock V DD = 5V 100200nsPulse WidthV DD = 10V 4080V DD = 15V 3265t RCL , t FCLMaximum Clock Rise and V DD = 5V 15µsFall TimeV DD = 10V 10V DD = 15V 5t SUMinimum Set-Up TimeV DD = 5V 2040nsV DD = 10V 1530V DD = 15V1225f CLMaximum Clock V DD = 5V 2.55MHz FrequencyV DD = 10V 6.212.5V DD = 15V7.615.5SET AND RESET OPERATION t PHL(R),Propagation Delay TimeV DD = 5V 150300nst PLH(S)V DD = 10V 65130V DD = 15V 4590t WH(R),Minimum Set and V DD = 5V 90180ns t WH(S)Reset Pulse Width V DD = 10V 4080V DD = 15V 2550C INAverage Input Capacitance Any Input57.5pF CD4013BCPhysical Dimensions inches (millimeters) unless otherwise noted14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" NarrowPackage Number M14A 6C D 4013B CPhysical Dimensionsinches (millimeters) unless otherwise noted (Continued)14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm WidePackage Number M14D7CD4013BC Dual D-Type Flip-FlopPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" WidePackage Number N14AFairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICYFAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to the user.2. A critical component in any component of a life support device or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.。