TSM3424中文资料

合集下载

一种谐振式无线电能传输技术的研究

岬究与裸索第I FUJIAN NONGJI 一种谐振式无线电能传输技术的研究郑志聪(福建农林大学金山学院，福建福州350002)摘要:谐振式无线电能传输技术是一种利用发射线圈与接收线圈之间的强磁耦合实现无线电能传输的技术。

文章介绍了一种谐振式无线电能传输系统，主要由直流电源、驱动电路、发射线圈、接收线圈和负载5个部分所组成。

该系统可点亮传输距离为10cm的9 W节能灯，具有一定的应用价值。

关键词:谐振式；强磁耦合;传输距离;传输功率;传输效率中图分类号:TM724文献标识码:A随着社会的进步和科学技术的发展，无线电能传输技术因其安全、可靠和便捷等优点逐渐被人们认识和了解。

无线电能传输（Wireless Power Transfer,WPT)是通过发射器将电能转换为其他形式的中继能量（如电磁场能、激光、微波及机械波等），隔空传输一段距离后，再通过接收器将中继能量转换为电能，实现电能无线传输[1]。

本文介绍一种电磁耦合谐振式无线电能传输技术，利用近区非辐射磁场的耦合实现无线电能传输。

随着研究的深入,无线电能传输技术越来越完善，在交通运输、便携式电子产品、医疗器械、航空航天、水下探测等领域崭露头角，是未来研究热点之一'1总体结构与设计1.1总体结构谐振式无线电能传输系统主要由直流电源、驱动电路、发射线圈、接收线圈和负载5个部分组成，如图1所示。

电源由直流稳压电源提供。

驱动电路由E 类功率放大器模块和uc3842电路模块构成,uc3842 电路模块产生高频的MOS管驱动信号，经功率放大为发射线圈提供高频的交流电流信号。

发射线圈将作者简介:郑志聪(1982 —)，男，讲师，研究方向：电机与电器。

电能转变为磁能,接收线圈将接收到的磁能转为电能供给负载。

其中发射线圈和接收线圈设置为相同谐振频率的LC电路，当驱动信号频率与两线圈的固有谐振频率相同时，发射线圈和接收线圈发生谐振，两线圈之间产生强耦合,从而实现电能的无线传输。

MCP3422A0-ESN;MCP3422A0-EMS;MCP3422A0-EMC;MCP3423-EUN;MCP3424-ESL;中文规格书,Datasheet资料

• Differential Input Full Scale Range: -VREF to +VREF
• Self Calibration of Internal Offset and Gain per Each Conversion
• On-Board Voltage Reference (VREF): - Accuracy: 2.048V ± 0.05% - Drift: 15 ppm/°C
MCP3422/3/4
Functional Block Diagram
MCP3423
CH1+ CH1CH2+
MUX
VSS
VDD
PGA
Voltage Reference (2.048V) VREF
ΔΣ ADC Converter
I2C Interface
CH2-
Gain = 1,2,4, or 8
Clock Oscillator
The devices operate from a single 2.7V to 5.5V power supply and have a two-wire I2C compatible serial interface for a standard (100 kHz), fast (400 kHz), or high-speed (3.4 MHz) mode.
The user can select the PGA gain of x1, x2, x4, or x8 before the analog-to-digital conversion takes place. This allows the MCP3422/3/4 devices to convert a very weak input signal with high resolution.

TSM-材料规格

TSM规格
5514G-2 5514G-3A 5515G-1BV 5516G-1 5514G-3B 5608G-5L/5 5515G-1V 5514G-3/3A 5527G-1 5608G-1 5601G-3B 5608G-7 5601G-4C 5515G-1AL 5608G-5LS 5515G-1AL 5516G-1 5516G-1B 5514G-2 5512G-2C 5513G-1 5603G-5A TSM5512G-2C 5603G-2A 5515G-1BV 5513G-1L 5527G-1 5526G-1 5512G-2B TSM5514G-2N
客户名称
M规格
中山中山日本日本中山三井日本 5514G-2 5514G-3A 5515G-1BV 5516G-1 5514G-3B 5608G-5L 5515G-1V 5514G-3/3A 5527G-1
材料规格
PPTJ530S PPJ717QS POMM9045XAP PA6CM1017 PPTJ911S PPLA880C POMM9045XAP PPJ717QS PBT1401X06
TSM5608G-6
5608G-5L 5608G-6/7 5608G-1 5514G-2
PPCN-IP1 PPCN-BP7S PPCN-BP1 PPCN2015
聚菱燕聚菱燕聚菱燕聚菱燕
客户名称
中山
5608G-1 5601G-3B 5608G-7 5601G-4C 5515G-1AL 5608G-5LS 5515G-1AL 5516G-1 5516G-1B 5514G-2
TSM5608G-6 TSM5608G-6B TSM5608G-7 TSM5608G-5 TSM5608G-5L TSM5608G-1 TSM5608G-5W TSM5512G-2B TSM5512G-2A TSM5518G-2 TSM5514G-2 TSM5603G-2B

LMV342中文资料

LMV341/LMV342/LMV344Single with Shutdown/Dual/Quad General Purpose,2.7V,Rail-to-Rail Output,125˚C,Operational AmplifiersGeneral DescriptionThe LMV341/342/344are single,dual,and quad low volt-age,and low power Operational Amplifiers.They are de-signed specifically for low voltage portable applications.Other important product characteristics are low input biascurrent,rail-to-rail output,and wide temperature range.The patented class AB turnaround stage significantly re-duces the noise at higher frequencies,power consumption,and offset voltage.The PMOS input stage provides the userwith ultra-low input bias current of20fA(typical)and highinput impedance.The industrial-plus temperature range of-40˚C to125˚Callows the LMV341/342/344to accommodate a broad rangeof extended environment applications.LMV341expands Na-tional Semiconductor’s Silicon Dust™amplifier portfolio of-fering enhancements in size,speed,and power savings.TheLMV341/342/344are guaranteed to operate over the voltagerange of2.7V to5.0V and all have rail-to-rail output.The LMV341offers a shutdown pin that can be used todisable the device.Once in shutdown mode,the supplycurrent is reduced to45pA(typical).The LMV341/342/344have29nV Voltage Noise at10KHz,1MHz GBW,1.0V/µsSlew Rate,0.25mVos,and0.1µA shutdown current(LMV341.)The LMV341is offered in the tiny SC70-6L package,theLMV342in space saving MSOP-8and SOIC-8,and theLMV344in TSSOP-14and SOIC-14.These small packageamplifiers offer an ideal solution for applications requiringminimum PC board footprint.Applications with area con-strained PC board requirements include portable electronicssuch as cellular handsets and PDAs.Features(Typical2.7V Supply Values;Unless Otherwise Noted)n Guaranteed2.7V and5V specificationsn Input referred voltage noise(@10kHz)29nV/n Supply current(per amplifier)100µAn Gain bandwidth product 1.0MHzn Slew rate 1.0V/µsn Shutdown Current(LMV341)45pAn Turn-on time from shutdown(LMV341)5µsn Input bias current20fAApplicationsn Cordless/cellular phonesn Laptopsn PDAsn PCMCIA/Audion Portable/battery-powered electronic equipmentn Supply current monitoringn Battery monitoringn Buffern Filtern DriverConnection DiagramSC70-6L20030441Top ViewOrder NumberLMV341MG,LMV341MGXLMV342MM,LMV342MMXLMV342MA,LMV342MAXLMV344MT,LMV344MTXLMV344MA,LMV344MAXSample and Hold Circuit20030444March2003LMV341/LMV342/LMV344SinglewithShutdown/Dual/QuadGeneralPurpose,2.7V,Rail-to-RailOutput,125˚C,OperationalAmplifiers ©2003National Semiconductor Corporation Absolute Maximum Ratings(Note 1)If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.ESD Tolerance (Note 2)Machine Model 200V Human Body Model 2000VDifferential Input Voltage ±Supply VoltageSupply Voltage (V+-V −)5.5VOutput Short Circuit to V +(Note 3)Output Short Circuit to V−(Note 4)Storage Temperature Range −65˚C to 150˚CJunction Temperature (Note 5)150˚CMounting TemperatureInfrared or Convection Reflow (20sec.)235˚C Wave Soldering Lead Temp.(10sec.)260˚COperating Ratings (Note 1)Temperature Range −40˚C to 125˚CThermal Resistance (θJA )6-Pin SC70414˚C/W 8-Pin SOIC 190˚C/W 8-Pin MSOP 235˚C/W 14-Pin TSSOP 155˚C/W 14-Pin SOIC145˚C/W2.7V DC Electrical Characteristics(Note 10)Unless otherwise specified,all limits guaranteed for T J =25˚C,V +=2.7V,V −=0V,V CM =V +/2,V O =V +/2and R L >1M Ω.Boldface limits apply at the temperature extremes.Symbol ParameterConditionsMin (Note 7)Typ (Note 6)Max (Note 7)UnitsV OSInput Offset VoltageLMV3410.2544.5mVLMV342/LMV3440.5555.5TCV OS Input Offset Voltage Average Drift1.7µV/˚C I B Input Bias Current 0.02120250pA I OS Input Offset Current 6.6fA I SSupply CurrentPer Amplifier100170230µAShutdown Mode,V SD =0V (LMV341)45pA 1µA 1.5µACMRR Common Mode Rejection Ratio0V ≤V CM ≤1.7V 0V ≤V CM ≤1.6V 565080dB PSRR Power Supply Rejection Ratio 2.7V ≤V +≤5V 656082dB V CM Input Common Mode Voltage For CMRR ≥50dB 0−0.2to 1.9(Range)1.7VA VLarge Signal Voltage GainR L =10k Ωto 1.35V 7870113dBR L =2k Ωto 1.35V7264103V OOutput SwingR L =2k Ωto 1.35V246095mV609526R L =10k Ωto 1.35V5.030403040 5.3L M V 341/L M V 342/L M V 344 22.7V DC Electrical Characteristics(Note 10)(Continued)Unless otherwise specified,all limits guaranteed for T J =25˚C,V +=2.7V,V −=0V,V CM =V +/2,V O =V +/2and R L >1M Ω.Boldface limits apply at the temperature extremes.Symbol ParameterConditionsMin (Note 7)Typ (Note 6)Max (Note 7)UnitsI OOutput Short Circuit CurrentSourcingLMV341/LMV3422032mASourcing LMV3441824Sinking1524t on Turn-on Time from Shutdown (LMV341)5µs V SDShutdown Pin Voltage RangeON Mode (LMV341) 1.7to 2.7 2.4to 2.7V Shutdown Mode (LMV341)0to 10to 0.82.7V AC Electrical Characteristics(Note 10)Unless otherwise specified,all limits guaranteed for T J =25˚C,V +=2.7V,V −=0V,V CM =V +/2,V O =V +/2and R L >1M Ω.Boldface limits apply at the temperature extremes.Symbol ParameterConditionsMin (Note 7)Typ (Note 6)Max (Note 7)Units SR Slew RateR L =10k Ω,(Note 9) 1.0V/µs GBW Gain Bandwidth Product R L =100k Ω,C L =200pF 1.0MHz Φm Phase Margin R L =100k Ω72deg G m Gain MarginR L =100k Ω20dB e n Input-Referred Voltage Noise f =1kHz 40nV/i n Input-Referred Current Noise f =1kHz0.001pA/THDTotal Harmonic Distortionf =1kHz,A V =+1R L =600Ω,V IN =1V PP0.017%5V DC Electrical Characteristics(Note 10)Unless otherwise specified,all limits guaranteed for T J =25˚C,V +=5V,V −=0V,V CM =V +/2,V O =V +/2and R L>1M Ω.Boldface limits apply at the temperature extremes.Symbol ParameterConditionsMin (Note 7)Typ (Note 6)Max (Note 7)UnitsV OSInput Offset VoltageLMV3410.02544.5mVLMV342/LMV3440.7055.5TCV OS Input Offset Voltage Average Drift1.9µV/˚C I B Input Bias Current 0.02200375pA I OS Input Offset Current 6.6fA I SSupply CurrentPer Amplifier107200260µA Shutdown Mode,V SD =0V (LMV341)0.03311.5µA CMRR Common Mode Rejection Ratio0V ≤V CM ≤4.0V 0V ≤V CM ≤3.9V 565086dB PSRR Power Supply Rejection Ratio 2.7V ≤V +≤5V 656082dB V CMInput Common Mode VoltageFor CMRR ≥50dB0−0.2to 4.2(Range)4VLMV341/LMV342/LMV34435V DC Electrical Characteristics(Note 10)(Continued)Unless otherwise specified,all limits guaranteed for T J =25˚C,V +=5V,V −=0V,V CM =V +/2,V O =V +/2and R L>1M Ω.Boldface limits apply at the temperature extremes.Symbol ParameterConditionsMin (Note 7)Typ (Note 6)Max (Note 7)UnitsA VLarge Signal Voltage Gain (Note 8)R L =10k Ωto 2.5V 7870116dBR L =2k Ωto 2.5V7264107V OOutput SwingR L =2k Ωto 2.5V326095mV609534R L =10k Ωto 2.5V73040mV30407I O Output Short Circuit Current Sourcing 85113mA Sinking 5075t on Turn-on Time from Shutdown (LMV341)5µs V SDShutdown Pin Voltage RangeON Mode (LMV341) 3.1to 5 4.5to 5.0VShutdown Mode (LMV341)0to 10to 0.85V AC Electrical Characteristics(Note 10)Unless otherwise specified,all limits guaranteed for T J =25˚C,V +=5V,V −=0V,V CM =V +/2,V O =V +/2and R L>1M Ω.Boldface limits apply at the temperature extremes.Symbol ParameterConditionsMin (Note 7)Typ (Note 6)Max (Note 7)Units SR Slew RateR L =10k Ω,(Note 9) 1.0V/µs GBW Gain-Bandwidth Product R L =10k Ω,C L =200pF 1.0MHz Φm Phase Margin R L =100k Ω70deg G m Gain MarginR L =100k Ω20dB e n Input-Referred Voltage Noise f =1kHz 39nV/i n Input-Referred Current Noise f =1kHz0.001pA/THDTotal Harmonic Distortionf =1kHz,A V =+1R L =600Ω,V IN =1V PP0.012%Note 1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.Operating Ratings indicate conditions for which the device is intended to be functional,but specific performance is not guaranteed.For guaranteed specifications and the test conditions,see the Electrical Characteristics.Note 2:Human body model,1.5k Ωin series with 100pF.Machine model,0Ωin series with 200pF.Note 3:Shorting output to V +will adversely affect reliability.Note 4:Shorting output to V -will adversely affect reliability.Note 5:The maximum power dissipation is a function of T J(MAX),θJA ,and T A .The maximum allowable power dissipation at any ambient temperature is P D =(T J(MAX)–T A )/θJA .All numbers apply for packages soldered directly into a PC board.Note 6:Typical values represent the most likely parametric norm.Note 7:All limits are guaranteed by testing or statistical analysis.Note 8:R L is connected to mid-supply.The output voltage is GND +0.2V ≤V O ≤V +−0.2VNote 9:Connected as voltage follower with 2V PP step input.Number specified is the slower of the positive and negative slew rates.Note 10:Electrical Table values apply only for factory testing conditions at the temperature indicated.Factory testing conditions result in very limited self-heating of the device such that T J =T A .No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self heating where T J >T A .L M V 341/L M V 342/L M V 344 4Connection DiagramsSC70-6L8-Pin MSOP/SOIC14-Pin TSSOP/SOIC20030441 Top View20030451Top View20030452Top ViewOrdering InformationPackage Part Number Package Marking Transport Media NSC Drawing6-Pin SC70LMV341MGA781k Units Tape and ReelMAA06A LMV341MGX3k Units Tape and Reel8-Pin MSOPLMV342MMA82A1k Units Tape and ReelMUA08A LMV342MMX 3.5k Units Tape and Reel8-Pin SOICLMV342MALMV342MA95Units/RailM08A LMV342MAX 2.5k Units Tape and Reel14-Pin TSSOPLMV344MTLMV344MTRailsMTC14 LMV344MTX 2.5k Units Tape and Reel14-Pin SOICLMV344MALMV344MA55Units/RailM14ALMV344MAX 2.5k Units Tape and ReelLMV341/LMV342/LMV3445Typical Performance CharacteristicsSupply Current vs.Supply Voltage (LMV341)Input Current vs.Temperature2003042820030446Output Voltage Swing vs.Supply Voltage Output Voltage Swing vs.Supply Voltage2003042620030427I SOURCE vs.V OUT I SOURCE vs.V OUT2003042920030430L M V 341/L M V 342/L M V 344 6Typical Performance Characteristics(Continued)I SINK vs.V OUTI SINK vs.V OUT2003043120030432V OS vs.V CM V OS vs.V CM2003043320030434V IN vs.V OUT V IN vs.V OUT2003043520030436LMV341/LMV342/LMV3447Typical Performance Characteristics(Continued)CMRR vs.FrequencyPSRR vs.Frequency2003040320030401Input Voltage Noise vs.frequencySlew Rate vs.V SUPPLY2003040420030402Slew Rate vs.Temperature Slew Rate vs.Temperature2003042220030423L M V 341/L M V 342/L M V 344 8Typical Performance Characteristics(Continued)THD+N vs.FrequencyTHD+N vs.V OUT2003042520030424Open Loop Frequency Over Temperature Open Loop Frequency Response2003042120030420Open Loop Frequency ResponseGain &Phase vs.C L2003041920030417LMV341/LMV342/LMV3449Typical Performance Characteristics(Continued)Gain &Phase vs.C LStability vs.Capacitive Load2003041820030448Stability vs.Capacitive Load Non-Inverting Small Signal Pulse Response2003044920030405Non-Inverting Large Signal Pulse Response Non-Inverting Small Signal Pulse Response2003040820030406L M V 341/L M V 342/L M V 344 10Typical Performance Characteristics(Continued)Non-Inverting Large Signal Pulse ResponseNon-Inverting Small Signal Pulse Response2003040920030407Non-Inverting Large Signal Pulse Response Inverting Small Signal Pulse Response2003041020030411Inverting Large Signal Pulse Response Inverting Small Signal Pulse Response2003041420030412LMV341/LMV342/LMV34411Typical Performance Characteristics(Continued)Inverting Large Signal Pulse ResponseInverting Small Signal Pulse Response2003041520030413Inverting Large Signal Pulse Response Crosstalk Rejection vs.Frequency2003041620030454L M V 341/L M V 342/L M V 344 12Application SectionLMV341/342/344The LMV341/342/344family of amplifiers features low volt-age,low power,and rail-to-rail output operational amplifiers designed for low voltage portable applications.The family is designed using all CMOS technology.This results in an ultra low input bias current.The LMV341has a shutdown option, which can be used in portable devices to increase battery life.A simplified schematic of the LMV341/342/344family of amplifiers is shown in Figure1.The PMOS input differential pair allows the input to include ground.The output of this differential pair is connected to the Class AB turnaround stage.This Class AB turnaround has a lower quiescent current,compared to regular turnaround stages.This results in lower offset,noise,and power dissipation,while slew rate equals that of a conventional turnaround stage.The output of the Class AB turnaround stage provides gate voltage to the complementary common-source transistors at the output stage.These transistors enable the device to have rail-to-rail output.CLASS AB TURNAROUND STAGE AMPLIFIERThis patented folded cascode stage has a combined class AB amplifier stage,which replaces the conventional folded cascode stage.Therefore,the class AB folded cascode stage runs at a much lower quiescent current compared to conventional folded cascode stages.This results in signifi-cantly smaller offset and noise contributions.The reduced offset and noise contributions in turn reduce the offset volt-age level and the voltage noise level at the input of the LMV341/342/344.Also the lower quiescent current results in a high open-loop gain for the amplifier.The lower quiescent current does not affect the slew rate of the amplifier nor its ability to handle the total current swing coming from the input stage.The input voltage noise of the device at low frequencies, below1kHz,is slightly higher than devices with a BJT input stage;However the PMOS input stage results in a much lower input bias current and the input voltage noise drops at frequencies above1kHz.SAMPLE AND HOLD CIRCUITThe lower input bias current of the LMV341results in a very high input impedance.The output impedance when the de-vice is in shutdown mode is quite high.These high imped-ances,along with the ability of the shutdown pin to be derived from a separate power source,make LMV341a good choice for sample and hold circuits.The sample clock should be connected to the shutdown pin of the amplifier to rapidly turn the device on or off.Figure2shows the schematic of a simple sample and hold circuit.When the sample clock is high the first amplifier is in normal operation mode and the second amplifier acts as a buffer.The capacitor,which appears as a load on the first amplifier,will be charging at this time.The voltage across the capacitor is that of the non-inverting input of the first amplifier since it is connected as a voltage-follower.When the sample clock is low the first amplifier is shut off,bringing the output impedance to a high value.The high impedance of this output,along with the very high impedance on the input of the second amplifier,prevents the capacitor from discharg-ing.There is very little voltage droop while the first amplifier is in shutdown mode.The second amplifier,which is still in normal operation mode and is connected as a voltage fol-lower,also provides the voltage sampled on the capacitor at its output.SHUTDOWN FEATUREThe LMV341is capable of being turned off in order to conserve power and increase battery life in portable devices. Once in shutdown mode the supply current is drastically reduced,1µA maximum,and the output will be"tri-stated." The device will be disabled when the shutdown pin voltage is pulled low.The shutdown pin should never be left uncon-nected.Leaving the pin floating will result in an undefined operation mode and the device may oscillate between shut-down and active modes.The LMV341typically turns on2.8µs after the shutdown voltage is pulled high.The device turns off in less than400ns after shutdown voltage is pulled low.Figure3and Figure4 show the turn-on and turn-off time of the LMV341,respec-tively.In order to reduce the effect of the capacitance added to the circuit by the scope probe,in the turn-off time circuit a resistive load of600Ωis added.Figure5and Figure6show the test circuits used to obtain the two plots.20030453 FIGURE1.Simplified Schematic20030444FIGURE2.Sample and Hold CircuitLMV341/LMV342/LMV34413Application Section(Continued)LOW INPUT BIAS CURRENTThe LMV341/LMV342/LMV344Amplifiers have a PMOS in-put stage.As a result,they will have a much lower input bias current than devices with BJT input stages.This feature makes these devices ideal for sensor circuits.A typical curve of the input bias current of the LMV341is shown in Figure 7.20030440FIGURE 3.Turn-on Time20030439FIGURE 4.Turn-off Time20030442FIGURE 5.Turn-on Time20030443FIGURE 6.Turn-off Time20030447FIGURE 7.Input Bias Current vs.V CML M V 341/L M V 342/L M V 344 14Physical Dimensionsinches (millimeters)unless otherwise noted6-Pin SC70NS Package Number MAA06A8-Pin MSOPNS Package Number MUA08ALMV341/LMV342/LMV34415Physical Dimensionsinches (millimeters)unless otherwise noted (Continued)8-Pin SOICNS Package Number M08A14-Pin TSSOPNS Package Number MTC14L M V 341/L M V 342/L M V 344 16Physical Dimensionsinches (millimeters)unless otherwise noted (Continued)14-Pin SOICNS Package Number M14ALIFE SUPPORT POLICYNATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION.As used herein:1.Life support devices or systems are devices or systems which,(a)are intended for surgical implant into the body,or (b)support or sustain life,and whose failure to perform when properly used in accordance with instructions for use provided in the labeling,can be reasonably expected to result in a significant injury to the user.2.A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,or to affect its safety or effectiveness.National Semiconductor Americas Customer Support CenterEmail:new.feedback@ Tel:1-800-272-9959National SemiconductorEurope Customer Support CenterFax:+49(0)180-5308586Email:europe.support@Deutsch Tel:+49(0)6995086208English Tel:+44(0)8702402171Français Tel:+33(0)141918790National Semiconductor Asia Pacific Customer Support Center Fax:+65-62504466Email:ap.support@ Tel:+65-62544466National SemiconductorJapan Customer Support Center Fax:81-3-5639-7507Email:jpn.feedback@ Tel:81-3-5639-7560LMV341/LMV342/LMV344Single with Shutdown/Dual/Quad General Purpose,2.7V,Rail-to-Rail Output,125˚C,Operational AmplifiersNational does not assume any responsibility for use of any circuitry described,no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.。

342工业滑升门部分技术手册

A Company in the Cardo Group2005年5月阔福342工业滑升门工作原理：平衡系统（弹簧或配重）平衡门体的重量，通过外力（电机的扭力或手动拉力）来改变这个平衡，使门体在轨道内滑动。

平衡系统门板轨道A Company in the Cardo Group2005年5月阔福342工业滑升门各个部件名称：（注：因为门的安装及控制方式不同，有不同的部件，但主要部件名称都是相同的。

）请了解各个部件的名称，在与阔福沟通或参阅阔福资料的时候将会有极大的方便。

阔福342工业滑升门基本的技术参数：➢最小尺寸：2000X1500➢最大尺寸：8000X5500（弹簧平衡）*1➢表面材料：0.5mm厚的压花钢板铝板。

20微米厚的复合聚脂漆涂层，颜色可选➢门板厚度：42mm➢门板高度：500mm➢门板中间填充48kg/m3的无氟聚氨温发泡材料，含固定螺丝用钢带*2➢门板重量：铝门板10kg/m2钢门板16kg/m2 *3➢密闭性：2.5m3/m2/h(50P的压力下），最小可达到0.43m3/m2/h➢保温性：钢板门U值为0.84W/m2/℃，铝板门U值为0.9W/m2℃。

通过门板的U值为0.4W/m2 ℃➢抗风压：450N/M 2。

➢安全性：防弹簧断裂装置（SBD门标准配置），防钢丝绳断裂装置（CBD 选配），门底部安全防夹装置（电动门标准配置）。

*1 如果用配重平衡，门的尺寸可以做的更大。

*2 在门板边缘部分埋装有1mm厚的加强钢带，所有门板的铰链部分（如折页、支架等）的固定螺丝都是固定在此钢带上的。

*3 此重量为实际门体的重量（包括所有门板上的五金件）。

342工业门的门板结构：阔福342工业门门板特有的结构使门有优良的保温、密封、隔音性能。

门板中间密封门板外板（压花铝板或压花钢板内部加强钢带（固定螺丝用）彩光窗（可选）窗框抗风压加强型材（如需要）保温层（无氟聚胺脂）门把手底部型材底部密封342工业门可选部分：➢通行小门通行小门的选择，可以大大减少大门的使用频率，延长大门的使用寿命。

脉宽调制开关电源控制IC汇总

脉宽调制开关电源控制IC开关电源这个名字我们大家都不会感到很陌生。

常见的计算系统电源录象机、电视机电源都使用了这种电源技术。

但是常常会觉得这种电源技术好象很复杂根本不可能自已制作此类电源，当然早期的开关电源控制部份集成电路使得开关电源的外围变得如此简单以至于简单过一线性稳压电源。

这里介绍的是 sgs T开关电源这个名字我们大家都不会感到很陌生。

常见的计算系统电源录象机、电视机电源都使用了这种电源技术。

这里介绍的是 sgs Thomson 公司生产的新型系列集成稳压IC:UCX84X 之中的 UC1842 与系列中的其它 IC 相比，它们的内部电路结构基本上是一致的，只在某些参数如工作环境温度内部基准电压精度，最大占空比系数等方面有所区别所以原则上此类IC的外围电路是可以通用的。

UC1842 为脉冲调制 (PCM) 的开关电源控制 IC。

其封装为 8 脚，可谓简洁说明了。

其内部方框图如下：现介绍各脚功能：1脚为内部误差放大器输出端；2脚为误差放大输入端；1与2 脚之间接有反馈网络以确定反馈放大器增益与频响；2脚输入的反馈电压将与基准2.5V电压比较以产生控制电压；3脚为电流传感器输入引脚，当由电流传感器送来的电压超过1V时及当开关管过流时调宽脉冲就停止输出这样就保护了开关管防止意外损坏。

4脚为接定时电阻电容端口。

由外接的电容电阻决定内部振荡器振荡频率：f=1.8/Rt*Ct；5脚为接地端；6脚为输出调宽脉冲端口，输出的脉冲是推动后的开关管。

其驱动很强，达到 +1A 或 -1A 。

在负载叫容为 1000pF 时上升下降时间仅为 500S，所以很适合于推动VMOS管7脚为电源电压输入端，供电电压可在10V-30V，当电压低于10V时停止工作，工作电流 15mA，功耗是非常小的，因此工作稳定。

2SK3424-ZK中文资料

©1999, 2000Document No.D14640EJ2V0DS00 (2nd edition)Date Published May 2001 NS CP(K)Printed in JapanDATA SHEETThe mark 5 shows major revised points.The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.DESCRIPTIONThe 2SK3424 is N-Channel MOS FET device that features a low on-state resistance and excellent switching characteristics,designed for low voltage high current applications such as DC/DC converter with synchronous rectifier.FEATURES•4.5 V drive available •Low on-state resistanceR DS(on)1 = 11.5 m Ω MAX. (V GS = 10 V, I D = 24 A)•Low gate chargeQ G = 34 nC TYP. (I D = 48 A, V DD = 24 V, V GS = 10 V)•Built-in gate protection diode •Surface mount device availableABSOLUTE MAXIMUM RATINGS (T A = 25°C )Drain to Source Voltage (V GS = 0 V)V DSS 30V Gate to Source Voltage (V DS = 0 V)V GSS ±20V Drain Current (DC) (T C = 25°C)I D(DC)±48A Drain Current (Pulse)NoteI D(pulse)±192A Total Power Dissipation (T A = 25°C)P T1 1.5W Total Power Dissipation (T C = 25°C)P T250W Channel Temperature T ch 150°C Storage TemperatureT stg−55 to +150°CNote PW ≤ 10 µs, Duty Cycle ≤ 1%ORDERING INFORMATIONPART NUMBERPACKAGE 2SK3424TO-220AB 2SK3424-ZK TO-263(MP-25ZK)2SK3424-ZJTO-263(MP-25ZJ)Data Sheet D14640EJ2V0DS2ELECTRICAL CHARACTERISTICS(T A = 25°C)CHARACTERISTICSSYMBOL TEST CONDITIONS MIN.TYP.MAX.UNITDrain Leakage Current I DSS VDS = 30 V, V GS = 0 V 10µA Gate Leakage Current I GSS V GS = ±20 V, V DS = 0 V ±10µA Gate Cut-off Voltage V GS(off)V DS = 10 V, I D = 1 mA 1.5 2.5V Forward Transfer Admittance | y fs |V DS = 10 V, I D= 24 A 13S Drain to Source On-state ResistanceR DS(on)1V GS = 10 V, I D = 24 A 7.711.5mΩR DS(on)2V GS = 4.5 V, I D = 24 A 10.517.0m ΩInput Capacitance C iss V DS = 10 V 1900pF Output CapacitanceC oss V GS = 0 V 580pF Reverse Transfer Capacitance C rss f = 1 MHz270pF Turn-on Delay Time t d(on)V DD = 15 V , I D = 24 A 14ns Rise Timet r V GS(on) = 10 V 13ns Turn-off Delay Time t d(off)R G = 10 Ω61ns Fall Timet f 22ns Total Gate Charge Q G V DD = 24 V 34nC Gate to Source Charge Q GS V GS = 10 V 6.4nC Gate to Drain Charge Q GD I D = 48 A9.1nC Diode Forward Voltage V F(S-D)I F = 48 A, V GS = 0 V 1.0V Reverse Recovery Time t rr I F = 48 A, V GS = 0 V 34ns Reverse Recovery ChargeQ rrdi/dt = 100 A/µs26nCTEST CIRCUIT 2 GATE CHARGETEST CIRCUIT 1 SWITCHING TIME PG.V LDDτ = 1 s µDuty Cycle ≤ 1%L DDData Sheet D14640EJ2V0DS3TYPICAL CHARACTERISTICS (T A = 25°C)DRAIN CURRENT vs.DRAIN TO SOURCE VOLTAGEV DS - Drain to Source Voltage - V I D - D r a i n C u r r e n t - AFORWARD TRANSFER CHARACTERISTICS V GS - Gate to Source Voltage - VI D - D r a i n C u r r e n t - A1010.11001000GATE TO SOURCE CUT-OFF VOLTAGE vs.CHANNEL TEMPERATURE T ch - Channel Temperature - ˚CV G S (o f f ) - G a t e t o S o u r c e C u t -o f f V o l t a g e - VV DS = 10 V I D = 1 mA1.01.50.52.02.53.0−500501001500 | y f s | - F o r w a r d T r a n s f e r A d m i t t a n c e- SFORWARD TRANSFER ADMITTANCE vs.DRAIN CURRENT I D - Drain Current - A101100DRAIN TO SOURCE ON-STATE RESISTANCE vs. GATE TO SOURCE VOLTAGE V GS - Gate to Source Voltage - VR D S (o n ) - D r a i n t o S o u r c e O n -s t a t eR e s i s t a n c e - m Ω1520510DRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN CURRENTI D - Drain Current - AR D S (o n ) - D r a i n t o S o ur c e O n -s t a t e R e s i s t a n c e - m Ω10Data Sheet D14640EJ2V0DS4DRAIN TO SOURCE ON-STATE RESISTANCE vs.CHANNEL TEMPERATURE T ch - Channel Temperature - ˚C R D S (o n ) - D r a i n t o S o u r c e O n -s t a t e R e s i s t a n c e - m Ω0−4501001508162012SOURCE TO DRAIN DIODE FORWARD VOLTAGEI S D - D i o d e F o r w a r d C u r r e n t - AV SD - Source to Drain Voltage - VCAPACITANCE vs. DRAIN TO SOURCE VOLTAGEV DS- Drain to Source Voltage - V C i s s , C o s s , C r s s - C a p a c i t a n c e - p F100100010000SWITCHING CHARACTERISTICSI D - Drain Current - At d (o n ), t r , t d (o f f ), t f - S w i t c h i n g T i m e - n sREVERSE RECOVERY TIME vs.DIODE FORWARD CURRENTI SD - Diode Forward Current - At r r - R e v e r s e R e c o v e r y T i m e - n sdi/dt = 100 A/ sV GS = 0 V10.1101101001000100µDYNAMIC INPUT/OUTPUT CHARACTERISTICS V G S - G a t e t o S o u r c e V o l t a g e - VQ G - Gate Charge - nCV D S - D r a i n t o S o u r c e V ol t a g e - V105152025304812Data Sheet D14640EJ2V0DS5DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREAT ch - Channel Temperature - ˚C d T - P e r c e n t a g e o f R a t e d P o w e r - %40206010014080120160020406080100T C - Case Temperature - ˚CP T - T o t a l P o w e r D i s s i p a t i o n - W0080204060100140120160TOTAL POWER DISSIPATION vs.CASE TEMPERATURE10203040605070FORWARD BIAS SAFE OPERATING AREA110100I D - D r a i n C u r r e n t - A0.1V DS - Drain to Source Voltage - V5Data Sheet D14640EJ2V0DS6PACKAGE DRAWINGS (Unit : mm)1)TO-220AB (MP-25)2)TO-263 (MP-25ZK)3)TO-263 (MP-25ZJ)EQUIVALENT CIRCUITRemark The diode connected between the gate and source of the transistor serves as a protector against ESD.When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device.55[MEMO]Data Sheet D14640EJ2V0DS7M8E 00. 4The information in this document is current as of May, 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information.No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others.Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information.While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features.NEC semiconductor products are classified into the following three quality grades:"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application."Standard":Computers, office equipment, communications equipment, test and measurement equipment, audioand visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots"Special":Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disastersystems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support)"Specific":Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, lifesupport systems and medical equipment for life support, etc.The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application.(Note)(1)"NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.(2)"NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).••••••。

UC3824中文资料

UC3842芯片资料各管脚功能简介如下。

---1脚COMP是内部误差放大器的输出端，通常此脚与2脚之间接有反馈网络，以确定误差放大器的增益和频响。

---2脚FEED BACK是反馈电压输入端，此脚与内部误差放大器同向输入端的基准电压(一般为+2.5V)进行比较，产生控制电压，控制脉冲的宽度。

---3脚ISENSE是电流传感端。

在外围电路中，在功率开关管(如VMos管)的源极串接一个小阻值的取样电阻，将脉冲变压器的电流转换成电压，此电压送入3脚，控制脉宽。

此外，当电源电压异常时，功率开关管的电流增大，当取样电阻上的电压超过1V 时，UC3842就停止输出，有效地保护了功率开关管。

---4脚RT/CT是定时端。

锯齿波振荡器外接定时电容C和定时电阻R的公共端。

5脚GND是接地。

6脚OUT是输出端，此脚为图滕柱式输出，驱动能力是±lA。

这种图腾柱结构对被驱动的功率管的关断有利，因为当三极管VTl截止时，VT2导通，为功率管关断时提供了低阻抗的反向抽取电流回路，加速功率管的关断。

7脚Vcc是电源。

当供电电压低于＋16V时，UC3824不工作，此时耗电在1mA以下。

输入电压可以通过一个大阻值电阻从高压降压获得。

芯片工作后，输入电压可在+10～+30V之间波动，低于+10V停止工作。

工作时耗电约为15mA，此电流可通过反馈电阻提供。

8脚VREF是基准电压输出，可输出精确的+5V基准电压，电流可达50mA。

UV3842的电压调整率可达0.01%，工作频率为500kHz，启动电流小于1mA，输入电压为10～30V，基准电压为4.9～5.1V，工作温度为0～70℃，输出电流为1A。

TSM4中文资料

Document Number: 51009 Revision: 20-Oct-04
For technical questions, contact: sfer@
23
DIMENSIONS in millimeters
TSM4 YL TSM4 YJ TSM4 ZL TSM4 ZJ
4.8 1
4.8 1
0.2 0.2
2 2
5.3
1 2 3
5.1
5.3
1 2 3
5.1
2.3 min.
6.2
1 3
4.6
1.2 min. 4.6 0.8 1.25
1 3
5.1 max.
1.25 1.25 0.2 3 leads 0.6 x 0.15
1.3
Ø 1.5 slot 0.5 x 0.4
0.7
Ø 1.5 slot 0.5 x 0.4
RECOMMENDED SOLDERING AREAS
1.8
1.8 1.8
1.8 1.6 2 4 2.3 2 1.3 2.3
1.6
2 3.8 2
2.9
1.6 1.3
5.3
1.3 2.54
2.54
2.3
1.3
CIRCUIT DIAGRAM
Vishay Sfernice
Surface Mount Miniature Trimmers Multi-Turn Cermet Sealed
ELECTRICAL SPECIFICATIONS
Resistive Element Electrical Travel Resistance Range Standard Series Tolerance Standard Power Rating Temperature Coefﬁcient Limiting Element Voltage (Linear Law) Contact Resistance Variation End Resistance (Typical) Dielectric Strength (RMS) Insulation Resistance Linear Logarithmic Cermet 11 turns ± 2 10W to 1MW 1-2-5 ±10% 0.25W at + 85°C not applicable See Standard Resistance Element Table 200V 1% or 3W 1W 600V 106MW

AO3424中文资料

SymbolTyp Max 17.4305060R θJC 47.5Maximum Junction-to-Case BSteady-State°C/WThermal Characteristics ParameterUnits Maximum Junction-to-Ambient A t ≤ 10s R θJA °C/W Maximum Junction-to-Ambient A Steady-State °C/W AOD454AOD454SymbolMin TypMaxUnits BV DSS 40V 1T J =55°C5I GSS ±100nA V GS(th)1 2.33V I D(ON)30A 2533T J =125°C39523447m Ωg FS 25S V SD 0.761V I S12A C iss 404500pF C oss 95150pF C rss 3760pF R g 2.7ΩQ g (10V)9.2nC Q g (4.5V) 4.5nC Q gs 1.6nC Q gd 2.6nC t D(on) 3.5ns t r 6ns t D(off)13.2ns t f 3.5ns t rr 22.9ns Q rr 18.3nCTHIS PRODUCT HAS BEEN DESIGNED AND QUALIFIED FOR THE CONSUMER MARKET. APPLICATIONS OR USES AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS ARE NOT AUTHORIZED. AOS DOES NOT ASSUME ANY LIABILITY ARISING OUT OF SUCH APPLICATIONS OR USES OF ITS PRODUCTS. AOS RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN,FUNCTIONS AND RELIABILITY WITHOUT NOTICE.Body Diode Reverse Recovery Time Drain-Source Breakdown Voltage On state drain currentI D =10mA, V GS =0V V GS =10V, V DS =5V V GS =10V, I D =12AReverse Transfer Capacitance I F =12A, dI/dt=100A/µs V GS =0V, V DS =20V, f=1MHz SWITCHING PARAMETERS Electrical Characteristics (T J =25°C unless otherwise noted)STATIC PARAMETERS Parameter Conditions I DSS µA Gate Threshold Voltage V DS =V GS , I D =250µA V DS =32V, V GS =0VV DS =0V, V GS =±20V Zero Gate Voltage Drain Current Gate-Body leakage current R DS(ON)Static Drain-Source On-ResistanceForward Transconductance Diode Forward Voltage m ΩV GS =4.5V, I D =6AI S =1A, V GS =0V V DS =5V, I D =12A Gate resistance V GS =0V, V DS =0V, f=1MHzTurn-Off Fall Time Total Gate Charge V GS =10V, V DS =20V, I D =12AGate Source Charge Gate Drain Charge Total Gate Charge Body Diode Reverse Recovery ChargeI F =12A, dI/dt=100A/µsMaximum Body-Diode Continuous CurrentInput Capacitance Output Capacitance Turn-On DelayTime DYNAMIC PARAMETERS Turn-On Rise Time Turn-Off DelayTime V GS =10V, V DS =20V, R L =1.7Ω, R GEN =3ΩA: The value of R θJA is measured with the device mounted on 1in 2 FR-4 board with 2oz. Copper, in a still air environment with T A =25°C. The Power dissipation P DSM is based on R θJA and the maximum allowed junction temperature of 150°C. The value in any given application depends on the user's specific board design, and the maximum temperature of 175°C may be used if the PCB allows it.B. The power dissipation P D is based on T J(MAX)=175°C, using junction-to-case thermal resistance, and is more useful in setting the upper dissipation limit for cases where additional heatsinking is used.C: Repetitive rating, pulse width limited by junction temperature T J(MAX)=175°C.D. The R θJA is the sum of the thermal impedence from junction to case R θJC and case to ambient.E. The static characteristics in Figures 1 to 6 are obtained using <300 µs pulses, duty cycle 0.5% max.F. These curves are based on the junction-to-case thermal impedence which is measured with the device mounted to a large heatsink, assuming a maximum junction temperature of T J(MAX)=175°C.G. The maximum current rating is limited by bond-wires.H. These tests are performed with the device mounted on 1 in 2 FR-4 board with 2oz. Copper, in a still air environment with T A =25°C. The SOA curve provides a single pulse rating. Rev 3: Jan. 2006AOD454AOD454AOD454。

lm3424数据手册

LM3424August 22, 2009Constant Current N-Channel Controller with Thermal Foldback for Driving LEDsGeneral DescriptionThe LM3424 is a versatile high voltage N-channel MosFET controller for LED drivers . It can be easily configured in buck, boost, buck-boost and SEPIC topologies. In addition, the LM3424 includes a thermal foldback feature for temperature management of the LEDs. This flexibility, along with an input voltage rating of 75V, makes the LM3424 ideal for illuminating LEDs in a very diverse, large family of applications. Adjustable high-side current sense voltage allows for tight regulation of the LED current with the highest efficiency pos-sible. The LM3424 uses standard peak current-mode control providing inherent input voltage feed-forward compensation for better noise immunity. It is designed to provide accurate thermal foldback with a programmable foldback breakpoint and slope. In addition, a 2.45V reference is provided.The LM3424 includes a high-voltage startup regulator that operates over a wide input range of 4.5V to 75V. The internal PWM controller is designed for adjustable switching frequen-cies of up to 2.0 MHz and external synchronization is possible. The controller is capable of high speed PWM dimming and analog dimming. Additional features include slope compen-sation, softstart, over-voltage and under-voltage lock-out, cy-cle-by-cycle current limit, and thermal shutdown.Features■V IN range from 4.5V to 75V■High-side adjustable current sense■2Ω, 1A Peak MosFET gate driver■Input under-voltage and output over-voltage protection ■PWM and analog dimming■Cycle-by-cycle current limit■Programmable slope compensation■Programmable, synchronizable switching frequency ■Programmable thermal foldback■Programmable softstart■Precision voltage reference■Low power shutdown and thermal shutdown Applications■LED Drivers - Buck, Boost, Buck-Boost, and SEPIC ■Indoor and Outdoor Area SSL■Automotive■General Illumination■Constant-Current RegulatorsTypical Application Circuit300857k9300857b6© 2009 National Semiconductor LM3424 Constant Current N-Channel Controller with Thermal Foldback for Driving LEDsConnection Diagram3008570420-Lead TSSOP EPOrdering InformationOrder Number Spec.Package Type NSC Package Drawing Supplied AsLM3424MH NOPB TSSOP-20 EP MXA20A 73 Units, RailLM3424MHXNOPBTSSOP-20 EPMXA20A2500 Units, Tape and ReelPin DescriptionsPin Name Description Application Information1V IN Input Voltage Bypass with 100 nF capacitor to GND as close to the device as possible.2EN Enable Connect to > 2.4V to enable the device or to < 0.8V for low power shutdown.3COMP Compensation Connect a capacitor to GND to compensate control loop.4CSH Current Sense High Connect a resistor to GND to set the signal current. Can also be used to analog dim as explained in the Thermal Foldback / Analog Dimming section.5RT Resistor Timing Connect a resistor to GND to set the switching frequency. Can also be used to synchronize external clock as explained in the Switching Frequency section.6nDIM Dimming Input /Under-Voltage ProtectionConnect a PWM signal for dimming as detailed in the PWM Dimming section and/or a resistor divider from V IN to program input under-voltage lockout.7SS Soft-start Connect a capacitor to GND to extend start-up time.8TGAIN Temp Foldback Gain Connect a resistor to GND to set the foldback slope.9TSENSE Temp Sense Input Connect a resistor/ thermistor divider from V S to sense the temperature as explained in the Thermal Foldback / Analog Dimming section.10TREF Temp Foldback ReferenceConnect a resistor divider from V S to set the foldback reference voltage.11V S Voltage Reference 2.45V reference for temperature foldback circuit and other external circuitry.12OVP Over-Voltage Protection Connect a resistor divider from V O to program output over-voltage lockout.13DDRV Dimming Gate Drive OutputConnect to gate of dimming MosFET.14GND GroundConnect to DAP to provide proper system GND 15GATE Main Gate Drive Output Connect to gate of main switching MosFET.16V CC Internal Regulator Output Bypass with a 2.2 µF – 3.3 µF, ceramic capacitor to GND.17IS Main Switch Current Sense Connect to the drain of the main N-channel MosFET switch for R DS-ON sensing or to a sense resistor installed in the source of the same device.18SLOPE Slope Compensation Connect a resistor to GND to set slope of additional ramp.19HSN LED Current Sense Negative Connect through a series resistor to LED current sense resistor (negative).20HSP LED Current Sense Positive Connect through a series resistor to LED current sense resistor (positive).DAPDAPThermal pad on bottom of ICConnect to GND. Refer to (Note 4) for thermal considerations. 2L M 3424Absolute Maximum Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.V IN , EN, nDIM-0.3V to 76.0V-1 mA continuousOVP, HSP, HSN-0.3V to 76.0V-100 µA continuous IS-0.3V to 76.0V-2V for 100 ns-1 mA continuous VCC-0.3V to 8.0VV S , TREF, TSENSE, TGAIN,COMP, CSH, RT, SLOPE, SS-0.3V to 6.0V SS-30 µA to +30 µAcontinuous GATE, DDRV-0.3V to VCC-2.5V for 100 nsV CC +2.5V for 100 ns-1 mA to +1 mA continuousGND-0.3V to 0.3V-2.5V to 2.5V for 100 nsJunction Temperature150°C Storage Temperature Range−65°C to +150°C Maximum Lead Temperature(Reflow and Solder)260°C Continuous Power Dissipation Internally Limited ESD SusceptibilityHuman Body Model 2 kV Operating Conditions (Notes 1, 2) Operating JunctionTemperature Range−40°C to +125°CInput Voltage VIN4.5V to 75VElectrical Characteristics (Note 2)Specifications in standard type face are for TJ = 25°C and those with boldface type apply over the full Operating TemperatureRange ( TJ = −40°C to +125°C). Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typicalvalues represent the most likely parametric norm at TJ = +25°C, and are provided for reference purposes only. Unless otherwisestated the following condition applies: VIN= +14V.Symbol Parameter ConditionsMin(Note 7)Typ(Note 8)Max(Note 7)UnitsSTARTUP REGULATOR (VCC)VCC-REG VCCRegulation ICC= 0 mA 6.30 6.907.35VICC-LIM VCCCurrent Limit VCC= 0V2025mAIQQuiescent Current EN = 3.0V, Static 2.0 3.0ISDShutdown Current EN = 0V0.1 1.0µAVCC-UVLO VCCUVLO Threshold VCCIncreasing 4.17 4.50VVCCDecreasing 3.70 4.08VCC-HYS VCCUVLO Hysteresis0.1ENABLE (EN)VEN-STEN Startup Threshold EN Increasing 1.75 2.40VEN decreasing0.80 1.63VEN-HYSEN Startup Hysteresis0.1RENEN Pull-down Resistance0.450.82 1.30MΩOVER-VOLTAGE PROTECTION (OVP)VTH-OVPOVP OVLO Threshold OVP Increasing 1.185 1.240 1.285VIHYS-OVPOVP Hysteresis SourceCurrent OVP Active (high)132027µAERROR AMPLIFIERVCSHCSH Reference Voltage With Respect to GND 1.210 1.235 1.260VError Amplifier Input Bias Current -0.600.6µACOMP Sink / Source Current172635 Transconductance100µA/V Linear Input Range(Note 9)±125mVTransconductance Bandwidth -6dB Unloaded Response (Note 9)1.0MHzLM3424Symbol Parameter ConditionsMin (Note 7)Typ (Note 8)Max (Note 7)UnitsOSCILLATOR (RT)f SW Switching FrequencyR T = 36 k Ω164207250kHz R T = 12 k Ω525597669V RT-SYNC Sync Threshold3.5VPWM COMPARATORV CP-BASECOMP to PWM Offset - No Slope Compensation7509001050mVSLOPE COMPENSATION (SLOPE)ΔV CPSlope Compensation AmplitudeAdditional COMP to PWM Offset -SLOPE sinking 100 µA85mVCURRENT LIMIT (IS)V LIM Current Limit Threshold 215245275mV V LIM Delay to Output3575nst ON-MIN Leading Edge Blanking Time 140240340HIGH SIDE TRANSCONDUCTANCE AMPLIFIERInput Bias Current 10 µA Transconductance20 mA/V Input Offset Current -1.50 1.5µA Input Offset Voltage-505mVTransconductance BandwidthI CSH = 100 µA (Note 9)500kHzGATE DRIVER (GATE)R SRC-GATE GATE Sourcing Resistance GATE = High 2.0 6.0ΩR SNK-GATE GATE Sinking Resistance GATE = Low 1.3 4.5UNDER-VOLTAGE LOCKOUT and DIM INPUT (nDIM)V TH-nDIM nDIM / UVLO Threshold 1.185 1.240 1.285V I HYS-nDIM nDIM Hysteresis Current132027µADIM DRIVER (DDRV)R SRC-DDRV DDRV Sourcing Resistance DDRV = High 13.530.0ΩR SNK-DDRV DDRV Sinking Resistance DDRV = Low 3.510.0 nDIM rising to DDRV rising 700 nsnDIM rising to DDRV falling 360 SOFT-START (SS)I SS Soft-start current10µATHERMAL CONTROLV S V S VoltageI VS = 0A 2.40 2.45 2.50VI VS = 1 mA TREF input bias currentV TREF = 1.5V V TSENSE = 1.5V0.1 µATSENSE Input Bias Current V TREF = 1.5VV TSENSE = 1.5V0.1 I TGAIN-MAX TGAIN Maximum Sourcing CurrentV TGAIN = 2V200600I TFCSH Current with High-side Amplifier Disabled R TGAIN = 10k ΩV TREF = 1.5V V TSENSE = 0.5V 100 V TREF = 1.5VV TSENSE = 1.4V 10 V TREF = 1.5V V TSENSE = 1.5V2 4L M 3424SymbolParameter ConditionsMin (Note 7)Typ (Note 8)Max (Note 7)UnitsTHERMAL SHUTDOWN T SD Thermal Shutdown Threshold (Notes 3, 9) 165°CT HYSThermal Shutdown Hysteresis(Notes 3, 9)25THERMAL RESISTANCE θJAJunction to Ambient20L TSSOP EP (Note 4)34°C/WNote 1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Operating Ratings is not implied. The recommended Operating Ratings indicate conditions at which the device is functional and the device should not be operated beyond such conditions.Note 2:All voltages are with respect to the potential at the GND pin, unless otherwise specified.Note 3:Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T J =165°C (typical) and disengages at T J =140°C (typical).Note 4:Junction-to-ambient thermal resistance is highly board-layout dependent. The numbers listed in the table are given for a reference layout wherein the 20L TSSOP EP package has its DAP pad populated with 9 vias. In applications where high maximum power dissipation exists, namely driving a large MosFET at high switching frequency from a high input voltage, special care must be paid to thermal dissipation issues during board design. In high-power dissipation applications, the maximum ambient temperature may have to be derated. Maximum ambient temperature (T A-MAX ) is dependent on the maximum operating junction temperature (T J-MAX-OP = 125°C), the maximum power dissipation of the device in the application (P D-MAX ), and the junction-to ambient thermal resistance of the package in the application (θJA ), as given by the following equation: T A-MAX = T J-MAX-OP – (θJA × P D-MAX ). In most applications there is little need for the full power dissipation capability of this advanced package. Under these circumstances, no vias would be required and the thermal resistances would be 104 °C/W for the 20L TSSOP EP. It is possible to conservatively interpolate between the full via count thermal resistance and the no via count thermal resistance with a straight line to get a thermal resistance for any number of vias in between these two limits.Note 5:Refer to National’s packaging website for more detailed information and mounting techniques. /analog/packaging/Note 6:Human Body Model, applicable std. JESD22-A114-C.Note 7:All limits guaranteed at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are 100%production tested. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).Note 8:Typical numbers are at 25°C and represent the most likely norm.Note 9:These electrical parameters are guaranteed by design, and are not verified by test.Note 10:The measurements were made using the standard buck-boost evaluation board from AN-1967.Note 11:The measurements were made using the standard boost evaluation board from AN-1969.LM3424Typical Performance CharacteristicsT A =+25°C and V IN = 14V unless otherwise specifiedBoost Efficiency vs. Input Voltage V O = 32V (9 LEDs) (Note 11)300857b6Buck-Boost Efficiency vs. Input VoltageV O = 21V (6 LEDs) (Note 10)300857b5Boost LED Current vs. Input VoltageV O = 32V (9 LEDs) (Note 11)300857b8Buck-Boost LED Current vs. Input VoltageV O = 21V (6 LEDs) (Note 10)300857b7Analog DimmingV O = 21V (6 LEDs); V IN = 24V (Note 10)300857b9PWM DimmingV O = 32V (9 LEDs); V IN = 24V (Note 11)300857c0 6L M 3424V CSH vs. Junction Temperature 300857b0V CC vs. Junction Temperature300857b1V S vs. Junction Temperature 300857b2V LIM vs. Junction Temperature300857b3t ON-MIN vs. Junction Temperature 300857b4f SW vs. Junction Temperature30085701LM3424ITFvs. Junction TemperatureRGAIN= 10 kΩ; VTSENSE= 0.5V; VTREF= 1.5V30085702fSWvs. RT30085705Ideal Thermal Foldback - Varied SlopeRREF1= RREF2= 49.9 kΩ; RNTC-BK= RBIAS= 43.2 kΩ300857k4Ideal Thermal Foldback - Varied BreakpointRREF1= RREF2= 49.9 kΩ; RGAIN= 10 kΩ300857k5 8LM3424Block Diagram30085703Theory of OperationThe LM3424 is an N-channel MosFET (NFET) controller for buck, boost and buck-boost current regulators which are ideal for driving LED loads. The controller has wide input voltage range allowing for regulation of a variety of LED loads. The high-side differential current sense, with low adjustable threshold voltage, provides an excellent method for regulating output current while maintaining high system efficiency. The LM3424 uses peak current mode control providing good noise immunity and an inherent cycle-by-cycle current limit. The adjustable current sense threshold provides the capability toamplitude (analog) dim the LED current and the thermal fold-back circuitry allows for precise temperature management ofthe LEDs. Tthe output enable/disable function coupled withan internal dimming drive circuit provides high speed PWMdimming through the use of an external MosFET placed at theLED load. When designing, the maximum attainable LED cur-rent is not internally limited because the LM3424 is a con-troller. Instead it is a function of the system operating point,component choices, and switching frequency allowing theLM3424 to easily provide constant currents up to 5A. Thissimple controller contains all the features necessary to im-plement a high efficiency versatile LED driver.LM342430085798FIGURE 1. Ideal CCM Regulator Inductor Current iL(t)CURRENT REGULATORSCurrent regulators can be designed to accomplish three basicfunctions: buck, boost, and buck-boost. All three topologiesin their most basic form contain a main switching MosFET, arecirculating diode, an inductor and capacitors. The LM3424is designed to drive a ground referenced NFET which is per-fect for a standard boost regulator. Buck and buck-boostregulators, on the other hand, usually have a high-side switch.When driving an LED load, a ground referenced load is oftennot necessary, therefore a ground referenced switch can beused to drive a floating load instead. The LM3424 can thenbe used to drive all three basic topologies as shown in theBasic Topology Schematics section. Other topologies suchas the SEPIC and flyback converter (both derivatives of thebuck-boost) can be implemented as well.Looking at the buck-boost design, the basic operation of acurrent regulator can be analyzed. During the time that theNFET (Q1) is turned on (tON), the input voltage source storesenergy in the inductor (L1) while the output capacitor (CO)provides energy to the LED load. When Q1 is turned off(tOFF), the re-circulating diode (D1) becomes forward biasedand L1 provides energy to both COand the LED load. Figure1 shows the inductor current (iL(t)) waveform for a regulatoroperating in CCM.The average output LED current (ILED) is proportional to theaverage inductor current (IL) , therefore if ILis tightly con-trolled, ILEDwill be well regulated. As the system changesinput voltage or output voltage, the ideal duty cycle (D) is var-ied to regulate ILand ultimately ILED. For any current regulator,D is a function of the conversion ratio:BuckBoostBuck-boostPEAK CURRENT MODE CONTROLPeak current mode control is used by the LM3424 to regulatethe average LED current through an array of HBLEDs. Thismethod of control uses a series resistor in the LED path tosense LED current and can use either a series resistor in theMosFET path or the MosFET RDS-ONfor both cycle-by-cyclecurrent limit and input voltage feed forward. The controller hasa fixed switching frequency set by an internal programmableoscillator which means current mode instability can occur atduty cycles higher than 50%. To mitigate this standard prob-lem, an aritifical ramp is added to the control signal internally.The slope of this ramp is programmable to allow for a widerrange of component choices for a given design. A detailedexplanation of this control method is presented in the follow-ing sections.SWITCHING FREQUENCYThe switching frequency of the LM3424 is programmed usingan external resistor (RT) connected from the RT pin to GNDas shown in Figure 2.Alternatively, an external PWM signal can be applied to theRT pin through a filter (RFLTand CFLT) and an AC couplingcapacitor (CAC) to synchronize the part to an external clockas shown in Figure 2. If the external PWM signal is applied ata frequency higher than the base frequency set by the RTre-sistor, the internal oscillator is bypassed and the switchingfrequency becomes the synchronized frequency. The exter-nal synchronization signal should have a pulse width of100ns, an amplitude between 3V and 6V, and be AC coupledto the RT pin with a ceramic capacitor (CAC= 100pF). A10MHz RC filter (RFLT= 150Ω and C FLT = 100 pF) should beplaced between the PWM signal and CACto eliminate un-wanted high frequency noise from coupling into the RT pin.The switching frequency is defined:See the Typical Performance Characteristics section for a plotof RTvs. fSW.10LM342430085799FIGURE 2. Timing CircuitryAVERAGE LED CURRENTTo first understand how the LM3424 regulates LED current,the thermal foldback functionality will be ignored. Figure 3shows the physical implementation of the LED current sensecircuitry assuming the thermal foldback circuitry is a simplecurrent source which, for now, will be set to zero (ITF= 0A).The LM3424 uses an external current sense resistor (RSNS)placed in series with the LED load to convert the LED current(ILED) into a voltage (VSNS). The HSP and HSN pins are theinputs to the high-side sense amplifier which are forced to beequal potential (VHSP=VHSN) through negative feedback. Be-cause of this, the VSNSvoltage is forced across RHSPwhichgenerates a current that is summed with the thermal foldbackcurrent (ITF) to generate the signal current (ICSH) which flowsout of the CSH pin and through the RCSHresistor. The erroramplifier will regulate the CSH pin to 1.24V and assumingITF= 0A, ICSHcan be calculated:This means VSNSwill be regulated as follows:ILEDcan then be calculated:The selection of the three resistors (RSNS, RCSH, and RHSP) isnot arbitrary. For matching and noise performance, the sug-gested signal current ICSHis approximately 100 µA. Thiscurrent does not flow in the LEDs and will not affect either theoff-state LED current or the regulated LED current. ICSHcanbe above or below this value, but the high-side amplifier offsetcharacteristics may be affected slightly. In addition, to mini-mize the effect of the high-side amplifier voltage offset on LEDcurrent accuracy, the minimum VSNSis suggested to be50 mV. Finally, a resistor (RHSN= RHSP) should be placed inseries with the HSN pin to cancel out the effects of the inputbias current (~10 µA) of both inputs of the high-side senseamplifier.Note that he CSH pin can also be used as a low-side currentsense input regulated to 1.24V. The high-side sense amplifieris disabled if HSP and HSN are tied to GND.30085757FIGURE 3. LED Current Sense CircuitryLM3424300857a1FIGURE 4. Thermal Foldback CircuitryTHERMAL FOLDBACK / ANALOG DIMMINGThermal foldback is necessary in many applications due tothe extreme temperatures created in LED environments. Ingeneral, two functions are necessary: a temperature break-point (TBK) after which the nominal operating current needs tobe reduced, and a slope corresponding to the amount of LEDcurrent decrease per temperature increase as shown in Fig-ure 5. The LM3424 allows the user to program both thebreakpoint and slope of the thermal foldback profile.300857c2FIGURE 5. Ideal Thermal Foldback ProfileFoldback is accomplished by adding current (ITF) to the CSHsumming node. As more current is added, less current isneeded from the high side amplifier and correspondingly, theLED current is regulated to a lower value. The final tempera-ture (TEND) is reached when ITF= ICSHcausing no current tobe needed from the high-side amplifier, yielding ILED= 0A.Figure 4 shows how the thermal foldback circuitry is physicallyimplemented in the system. ITFis set by placing a differentialvoltage (VDIF= VTREF– VTSENSE) across TSENSE and TREF.VTREFcan be set with a simple resistor divider (RREF1andRREF2) supplied from the VSvoltage reference (typical 2.45V).VTSENSEis set with a temperature dependant voltage (as tem-perature increases, voltage should decrease).An NTC thermistor is the most cost effective device used tosense temperature. As the temperature of the thermistor in-creases, its resistance decreases (albeit non-linearly). Usu-ally, the NTC manufacturer's datasheet will detail theresistance-temperature characteristic of the thermistor. Thethermistor will have a different resistance (RNTC) at each tem-perature. The nominal resistance of an NTC is the resistancewhen the temperature is 25°C (R25) and in many datasheetsthis will be given a multiplier of 1. Then the resistance at ahigher temperature will have a multiplier less than 1 (i.e. R85multiplier is 0.161 therefore R85= 0.161 x R25). Given a de-sired TBKand TEND, the corresponding resistances at thosetemperatures (RNTC-BKand RNTC-END) can be found.Using the NTC method, a resistor divider from VScan be im-plemented with a resistor connected between VSandTSENSE and the NTC thermistor placed at the desired loca-tion and connected from TSENSE to GND. This will ensurethat the desired temperature-voltage characteristic occurs atTSENSE.If a linear decrease over the foldback range is necessary, aprecision temperature sensor such as the LM94022 can beused instead as shown in Figure 4. Either method can be usedto set VTSENSEaccording to the temperature. However, for therest of this datasheet, the NTC method will be used for thermalfoldback calculations.During operation, if VDIF< 0V, then the sensed temperatureis less than TBKand the differential sense amplifier will regu-late its output to zero forcing ITF= 0. This maintains thenominal LED current and no foldback is observed.At TBK, VDIF= 0V exactly and ITFis still zero. Looking at themanufacturer's datasheet for the NTC thermistor, RNTC-BKcanbe obtained for the desired TBKand the voltage relationshipat the breakpoint (VTSENSE-BK= VTREF) can be defined:A general rule of thumb is to set RREF1= RREF2simplifying thebreakpoint relationship to RBIAS= RNTC-BK.If VDIF> 0V (temperature is above TBK), then the amplifier willregulate its output equal to the input forcing VDIFacross theresistor (RGAIN) connected from TGAIN to GND. RGAINulti-mately sets the slope of the LED current decrease with re-spect to increasing temperature by changing ITF:LM3424If an analog temperature sensor such as the LM94022 isused, then RBIASand the NTC are not necessary andVTENSEwill be the direct voltage output of the sensor.Since the NTC is not usually local to the controller, a bypasscapacitor (CNTC) is suggested from TSENSE to GND. If a ca-pacitor is used at TSENSE, then a capacitor (CREF) of equalor greater value should be placed from TREF to GND in orderto ensure the controller does not start-up in foldback. Alter-natively, a smaller CREFcan be used to create a fade-upfunction at start-up (see Application Information section).Thermal foldback is simply analog dimming according to aspecific profile, therefore any method of controlling the differ-ential voltage between TREF and TSENSE can be use toanalog dim the LED current. The corresponding LED currentfor any VDIF> 0V is defined:The CSH pin can also be used to analog dim the LED currentby adjusting the current sense voltage (VSNS), similar to ther-mal foldback. There are several different methods to adjustVSNSusing the CSH pin:1.External variable resistance : Adjust a potentiometerplaced in series with RCSHto vary VSNS.2.External variable current source: Source current (0 µA toICSH) into the CSH pin to adjust VSNS.300857k3FIGURE 6. Analog Dimming CircuitryIn general, analog dimming applications require a lowerswitching frequency to minimize the effect of the leading edgeblanking circuit. As the LED current is reduced, the outputvoltage and the duty cycle decreases. Eventually, the mini-mum on-time is reached. The lower the switching frequency,the wider the linear dimming range. Figure 6 shows how bothCSH methods are physically implemented.Method 1 uses an external potentiometer in the CSH pathwhich is a simple addition to the existing circuitry. However,the LEDs cannot dim completely because there is alwayssome resistance causing signal current to flow. This methodis also susceptible to noise coupling at the CSH pin since thepotentiometer increases the size of the signal current loop.Method 2 provides a complete dimming range and betternoise performance, though it is more complex. Like thermalfoldback, it simply sources current into the CSH pin, decreas-ing the amount of signal current that is necessary. Thismethod consists of a PNP current mirror and a bias networkconsisting of an NPN, 2 resistors and a potentiometer(RADJ), where RADJcontrols the amount of current sourcedinto the CSH pin. A higher resistance value will source morecurrent into the CSH pin causing less regulated signal currentthrough RHSP, effectively dimming the LEDs. Q7 and Q8should be a dual pair PNP for best matching and perfor-mance. The additional current (IADD) sourced into the CSH pincan be calculated:The corresponding ILEDfor a specific IADDis:THERMAL SHUTDOWNThe LM3424 includes thermal shutdown. If the die tempera-ture reaches approximately 165°C the device will shut down(GATE pin low), until it reaches approximately 140°C whereit turns on again.LM3424。

intersil HFA3424 数据手册

HFA34242.4GHz - 2.5GHz Low Noise AmpliﬁerThe Intersil 2.4GHz PRISM™chip set is a highly integrated five-chip solution for RF modems employing DirectSequence Spread Spectrum (DSSS)signaling. The HFA3424 2.4GHz -2.5GHz low noise amplifier is an optional chip that can be added to the five chips in the PRISM™ chip set. TheHFA3424 offers increased sensitivity for systems targeting 802.11 specifications. (See Figure 1, the T ypical Application Diagram.)The Intersil HFA3424 PRISM™ is a high performance low noise ampliﬁer in a low cost SOIC 8 lead surface mount plastic package. The HFA3424 employs a fully monolithic design which eliminates the need for external tuningnetworks. It can be biased using 3V or 5V supplies and has an option for biasing at higher currents for increased dynamic range.The HFA3424 is ideally suited for use where low noise ﬁgure, high gain, high dynamic range and low powerconsumption required. Typical applications include receiver front ends in the Wireless Local Area Network (WLAN) and wireless data collection markets in the 2.4GHz Industrial,Scientiﬁc and Medical (ISM) band, as well as standard gain blocks, buffer amps, driver amps and IF amps in both ﬁxed and portable systems.Features•Low Noise Figure . . . . . . . . . . . . . . . . . . . . . . . . . .1.90dB •High Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14dB •Low Power Consumption . . . . . . . . . . . . . .3V to 5V , 5mA •High Dynamic Range•DC Decoupled RF Input and Output •No External RF Tuning Elements Necessary •Low Cost SOIC 8 Lead Plastic PackageApplications•Systems T argeting IEEE 802.11 Standard •TDD Quadrature-Modulated Communication Systems •Wireless Local Area Networks •PCMCIA Wireless T ransceivers •ISM Systems•TDMA Packet Protocol Radios •PCS/Wireless PBX •Wireless Local LoopPinoutHFA3424(SOIC)TOP VIEWFunctional Block Diagram™Ordering InformationPART NUMBER TEMP.RANGE (o C)PACKAGE PKG.NO.HFA3424IB -40 to 858 Ld SOIC M8.15HFA3424IB96-40 to 85Tape and ReelGND V BIAS RF IN GND12348765GND V DD RF OUT GNDV DDRF INLNA 1RF OUTEXTENDEDBIASData SheetJanuary 1997File Number4131.2查询HFA3424供应商Typical Application DiagramFor additional information on the PRISM™ chip set, call (407)724-7800to access Intersil’AnswerFAX system.When prompted, key in the four-digit document number (File #) of the datasheets you wish to receive.The four-digit ﬁle numbers are shown in T ypical Application Diagram, and correspond to the appropriate circuit.FIGURE 1.TYPICAL TRANSCEIVER AMPLIFIER APPLICATIONS CIRCUIT USING THE HFA3424NOTE:Required for systems targeting 802.11 speciﬁcations.QUAD IF MODULATORRFPAHFA3925HFA3724DSSS BASEBAND PROCESSORD A T A T O M A C C T R LHSP3824TUNE/SELECTHFA35240o /90oVCO A/DA/D MAC-PHY INTERFACE802.11VCODUAL SYNTHESIZERHFA3624UP/DOWN CONVERTERA/D (FILE# 4067)(FILE# 4064)(FILE# 4062)(FILE# 4066)(FILE# 4132)PRISM™ CHIP SET FILE #4063M U XM U XDPSK DEMODDPSK MOD.DE-SPREADSPREADQIHFA3424(NOTE)(FILE# 4131)CCARXIRXQ RSSITXITXQ÷2Absolute Maximum RatingsThermal InformationSupply Voltage, V DD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+10V DC Input Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+17dBm Supply Current (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30mAOperating ConditionsTemperature Range. . . . . . . . . . . . . . . . . . . . . . . . . .-40o C to 85o CThermal Resistance (T ypical, Note 2)θJA (o C/W)SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165Maximum Storage Temperature Range. . . . . . . . . .-65o C to 150o CMaximum Lead T emperature (Soldering 10s) . . . . . . . . . . . . .300o C (SOIC - Lead Tips Only)CAUTION:Stresses above those listed in “Absolute Maximum Ratings”may cause permanent damage to the device.This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.NOTES:1.Only if Pin 2 is used to increase current.2.θJA is measured with the component mounted on an evaluation PC board in free air.Electrical SpeciﬁcationsT A =25o C,Z 0=50Ω,V DD =+5V ,P IN =-30dBm,f =2.45GHz,V BIAS =Open Circuit Unless Otherwise Speciﬁed PARAMETERMIN TYP MAX UNITS LNA Input Frequency Range 2.4- 2.5GHz Gain 121416dB Noise Figure - 1.90 2.30dBInput VSWR - 1.5:1-Output VSWR - 1.5:1-Input Return Loss --14.0-dB Output Return Loss --14.0-dB Output 1dB Compression -3-dBm Input IP 3-1-dBm Reverse Isolation-30-dB Supply Current at V DD = 5V 357mA Supply Range2.7- 5.5V Typical Performance CurvesFIGURE 2.GAIN vs FREQUENCY FIGURE 3.NOISE FIGURE vs FREQUENCYT A = 25o C3V, 5mA5V, 20mA5V, 5mA2.22.32.4 2.5 2.6 2.71816141210FREQUENCY (GHz)G A I N (d B )T A = 25o C3V, 5mA5V , 20mA5V , 5mA2.402.422.44 2.46 2.48 2.502.01.91.81.71.6FREQUENCY (GHz)N O I S E F I G U R E (d B )FIGURE 4.VSWR vs FREQUENCYFIGURE 5.INPUT IP 3 vs FREQUENCYFIGURE 6.GAIN vs FREQUENCY FIGURE 7.NOISE FIGURE vs FREQUENCYTypical Performance Curves(Continued)OUTPUTINPUT2.22.32.4 2.5 2.6 2.73.02.52.01.51.0FREQUENCY (GHz)V S W R 5V, 5mA, T A = 25o CT A = 25o C5V, 20mA5V, 5mA2.402.422.44 2.46 2.48 2.5042-2-4FREQUENCY (GHz)I N P U T I P 3 (d B m )3V, 5mA5V , 5mA-40o C2.22.32.4 2.5 2.6 2.71816141210FREQUENCY (GHz)G A I N (d B )85o C25o C25o C5V, 5mA2.62.32.01.71.4FREQUENCY (GHz)N O I S E F I G U R E (d B )85o C-40o C2.402.422.44 2.46 2.48 2.50All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation.Intersil semiconductor products are sold by description only.Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-out notice.Accordingly,the reader is cautioned to verify that data sheets are current before placing rmation furnished by Intersil is believed to be accurate and reliable.However,no responsibility is assumed by Intersil or its subsidiaries for its use;nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.For information regarding Intersil Corporation and its products, see web site Sales Ofﬁce HeadquartersNORTH AMERICA Intersil CorporationP. O. Box 883, Mail Stop 53-204Melbourne, FL 32902TEL:(407) 724-7000FAX: (407) 724-7240EUROPE Intersil SAMercure Center100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111FAX: (32) 2.724.22.05ASIAIntersil (Taiwan) Ltd.7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of ChinaTEL: (886) 2 2716 9310FAX: (886) 2 2715 3029Typical Application CircuitR BB12348765+V DDRF SIGNAL OUTPUT 2.4GHz 15nH(50Ω TRANSMISSION LINE)500pFPIN 2 ALLOWS FOR AN EXTERNAL RESISTOR R BB TO BE USED TO GROUND FOR AN OPTIONAL20mA CURRENT OPERATION. RECOMMENDED VALUES FOR THE CHIP RESISTOR ARE 30Ω TO 35Ω.V BIAS (PIN 2)NORMAL BIASEXTENDED BIAS Open30Ω To 35Ω To GroundSEE NOTE 2RF SIGNAL INPUT 2.4GHz (50Ω TRANSMISSION LINE)SEE NOTE 2NOTE:3.No DC blocking capacitor required on LNA input or output transmission lines.FIGURE 8.REFERENCE APPLICATION/TEST DESIGN SETUP SCHEMATIC: LOW NOISE AMPLIFIER。

MEG 342C QD-OLED (3DC4) 用户指南说明书

MEG Series OLED Monitor MEG 342C QD-OLED (3DC4)User GuideContentsGetting Started (3)Package Contents (3)Installing the Monitor Stand (4)Installing the Rear I/O Cover (5)Adjusting the Monitor (6)Monitor Overview (7)Connecting the Monitor to PC (10)OSD Setup (11)Navi Key (11)Hot Key (11)OSD Menus (12)G.I. (13)Gaming (14)Professional (16)Image (16)Input Source (17)PIP/PBP (18)Navi Key (19)Setting (19)MSI OLED Care (22)Specifications (24)Preset Display Modes (26)Troubleshooting (29)Safety Instructions (30)TÜV Rheinland Certification (32)Regulatory Notices (33)RevisionV1.1, 2023/052ContentsGetting StartedThis chapter provides you with the information on hardware setup procedures. While connecting devices, be careful in holding the devices and use a grounded wrist strap to avoid static electricity.∙Contact your place of purchase or local distributor if any of the items is damaged or missing.∙Package contents may vary by country.∙The included power cord is exclusively for this monitor and should not be used with other products.3Getting StartedInstalling the Monitor Stand 1. Leave the monitor in its protective foam packaging. Align the stand to the monitor groove. Tighten the stand with screws.2. Connect the base to the stand and tighten the screw to secure the base.3. Align and push the stand cover towards the monitor groove until it locks in place.4. Make sure the stand assembly is properly installed before setting the monitor Important ∙Place the monitor on a soft, protected surface to avoid scratching the display panel. ∙Do not use any sharp objects on the panel. ∙The groove for installing the stand bracket can also be used for wall mount. Please contact your dealer for proper wall mount kit. ∙This product comes with NO protective film to be removed by the user! Any mechanical damages to the product including removal of the polarizing film may affect the warranty!Installing the Rear I/O CoverInstall the accompanied rear I/O cover as shown below.5Getting Started6Getting Started Adjusting the Monitor This monitor is designed to maximize your viewing comfort with its adjustment capabilities. ⚠Important ∙Avoid touching the display panel when adjusting the monitor. ∙Please slightly tilt the monitor backwards before pivoting it.Monitor Overview7Getting Started8Getting Started9 Getting StartedConnecting the Monitor to PC1. Turn off your computer.2. Connect the video cable from the monitor to your computer.3. Connect the power cord to the monitor power jack. (Figure A)4. Plug the power cord into the electrical outlet. (Figure B)5. Turn on the monitor. (Figure C)6. Power on the computer and the monitor will auto detect the signal source.10Getting StartedOSD SetupThis chapter provides you with essential information on OSD Setup.⚠ImportantAll information is subject to change without prior notice.Navi KeyThe monitor comes with a Navi Key, a multi-directional control that helps navigate theOn-Screen Display (OSD) menu.Up/Down/Left/Right:∙selecting function menus and items∙adjusting function values∙entering into/exiting from function menusPress (OK):∙launching the On-Screen Display (OSD)∙entering submenus∙confirming a selection or settingHot Key∙Users may enter into preset function menus by moving the Navi Key up, down, left or right when the OSD menu is inactive.∙Users may customize their own Hot Keys to enter into different function menus.11OSD Setup12OSD MenusOSD Menus⚠ImportantThe following settings will be grayed out when HDR signals are received: ∙Night Vision ∙Low Blue Light ∙Brightness ∙Contrast∙Color Temperature∙Optix Scope ∙Auto Brightness Control ∙Ambient RGB Light∙PIP/PBP13OSD Menus14OSD Menus15OSD Menus16OSD Menus17 OSD Menus18OSD Menus19 OSD Menus20OSD Menus21OSD Menus22OSD Menus23OSD Menus24Specifications* Based on CIE1976 test standards.25SpecificationsPreset Display ModesImportant26Preset Display Modes27Preset Display Modes28Preset Display ModesTroubleshootingThe power LED is off.• Press the monitor power button again.• Check if the monitor power cable is properly connected.No image.• Check if the computer graphics card is properly installed.• Check if the computer and monitor are connected to electrical outlets and are turned on.• Check if the monitor signal cable is properly connected.• The computer may be in Standby mode. Press any key to activate the monitor. The screen image is not properly sized or centered.• Refer to Preset Display Modes to set the computer to a setting suitable for the monitor to display.No Plug & Play.• Check if the monitor power cable is properly connected.• Check if the monitor signal cable is properly connected.• Check if the computer and graphics card are Plug & Play compatible.The icons, font or screen are fuzzy, blurry or have color problems.• Avoid using any video extension cables.• Adjust brightness and contrast.• Adjust RGB color or tune color temperature.• Check if the monitor signal cable is properly connected.• Check for bent pins on the signal cable connector.The monitor starts flickering or shows waves.• Change the refresh rate to match the capabilities of your monitor.• Update your graphics card drivers.• Keep the monitor away from electrical devices that may cause electromagnetic interference (EMI).29TroubleshootingSafety Instructions∙Read the safety instructions carefully and thoroughly.∙All cautions and warnings on the device or User Guide should be noted.∙Refer servicing to qualified personnel only.Power∙Make sure that the power voltage is within its safety range and has been adjustedproperly to the value of 100~240V before connecting the device to the power outlet. ∙If the power cord comes with a 3-pin plug, do not disable the protective earth pinfrom the plug. The device must be connected to an earthed mains socket-outlet.∙Please confirm the power distribution system in the installation site shall providethe circuit breaker rated 120/240V, 20A (maximum).∙Always disconnect the power cord or switch the wall socket off if the device wouldbe left unused for a certain time to achieve zero energy consumption.∙Place the power cord in a way that people are unlikely to step on it. Do not placeanything on the power cord.∙If this device comes with an adapter, use only the MSI provided AC adapter approved for use with this device.BatteryPlease take special precautions because this device comes with a battery.∙Danger of explosion if battery is incorrectly replaced. Replace only with the same or equivalent type recommended by the manufacturer.∙Avoid disposal of a battery into fire or a hot oven, or mechanically crushing orcutting of a battery, which can result in an explosion.∙Avoid leaving a battery in an extremely high temperature or extremely low airpressure environment that can result in an explosion or the leakage of flammableliquid or gas.∙Do not ingest battery. If the coin/button cell battery is swallowed, it can causesevere internal burns and can lead to death. Keep new and used batteries awayfrom children.European Union:Batteries, battery packs, and accumulators should not be disposed of asunsorted household waste. Please use the public collection system toreturn, recycle, or treat them in compliance with the local regulations. BSMI:廢電池請回收For better environmental protection, waste batteries should be collectedseparately for recycling or special disposal.30Safety InstructionsCalifornia, USA:The button cell battery may contain perchlorate material and requiresspecial handling when recycled or disposed of in California.For further information please visit: https:///perchlorate/ Environment∙To reduce the possibility of heat-related injuries or of overheating the device, do not place the device on a soft, unsteady surface or obstruct its air ventilators.∙Use this device only on a hard, flat and steady surface.∙To prevent the device from tipping over, secure the device to a desk, wall or fixed object with an anti-tip fastener that helps to properly support the device and keep it safe in place.∙To prevent fire or shock hazard, keep this device away from humidity and high temperature.∙Do not leave the device in an unconditioned environment with a storage temperature above 60℃ or below -20℃, which may damage the device.∙The maximum operating temperature is around 40℃.∙When cleaning the device, be sure to remove the power plug. Use a piece of soft cloth rather than industrial chemical to clean the device. Never pour any liquid into the opening; that could damage the device or cause electric shock.∙Always keep strong magnetic or electrical objects away from the device.∙If any of the following situations arises, get the device checked by service personnel:• The power cord or plug is damaged.• Liquid has penetrated into the device.• The device has been exposed to moisture.• The device does not work well or you can not get it working according to the User Guide.• The device has dropped and damaged.• The device has obvious sign of breakage.31Safety InstructionsTÜV Rheinland CertificationTÜV Rheinland Low Blue Light CertificationBlue light has been shown to cause eye fatigueand discomfort. MSI now offers monitors with TÜVRheinland Low Blue Light certification to ensureusers’ eye comfort and well-being. Please followthe instructions below to reduce the symptoms fromextended exposure to the screen and blue light.∙Place the screen 20 – 28 inches (50 – 70 cm) away from your eyes and a little below eye level.∙Consciously blinking the eyes every now and then will help to reduce eye strain after extended screen time.∙Take breaks for 20 minutes every 2 hours.∙Look away from the screen and gaze at a distant object for at least 20 secondsduring breaks.∙Make stretches to relieve body fatigue or pain during breaks.∙Turn on the optional Low Blue Light function.TÜV Rheinland Flicker Free Certification∙TÜV Rheinland has tested this product toascertain whether the display produces visibleand invisible flicker for the human eye andtherefore strains the eyes of users.∙TÜV Rheinland has defined a catalogue oftests, which sets out minimum standardsat various frequency ranges. The test catalogue is based on internationallyapplicable standards or standards common within the industry and exceeds theserequirements.∙The product has been tested in the laboratory according to these criteria.∙The keyword “Flicker Free” confirms that the device has no visible and invisibleflicker defined in this standard within the range of 0 - 3000 Hz under variousbrightness settings.∙The display will not support Flicker Free when Anti Motion Blur/MPRT is enabled.(The availability of Anti Motion Blur/MPRT varies by products.)32TÜV Rheinland CertificationRegulatory NoticesCE ConformityThis device complies with the requirements set out in the Council Directive on the Approximation of the Laws of the Member Statesrelating to Electromagnetic Compatibility (2014/30/EU), Low-voltage Directive (2014/35/EU), ErP Directive (2009/125/EC) and RoHS directive (2011/65/EU). This product has been tested and found to comply with the harmonized standards for Information Technology Equipment published under Directives of Official Journal of the European Union.FCC-B Radio Frequency Interference StatementThis equipment has been tested and found to comply with the limitsfor a Class B digital device, pursuant to Part 15 of the FCC Rules.These limits are designed to provide reasonable protection againstharmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, ifnot installed and used in accordance with the instruction manual, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determinedby turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the measures listed below:∙Reorient or relocate the receiving antenna.∙Increase the separation between the equipment and receiver.∙Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.∙Consult the dealer or an experienced radio/television technician for help. Notice 1The changes or modifications not expressly approved by the party responsible for compliance could void the user’s authority to operate the equipment.Notice 2Shielded interface cables and AC power cord, if any, must be used in order to comply with the emission limits.This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:1. This device may not cause harmful interference, and2. This device must accept any interference received, including interference that may cause undesired operation.MSI Computer Corp.901 Canada Court, City of Industry, CA 91748, USA(626) 913-082833Regulatory NoticesWEEE StatementUnder the European Union (“EU”) Directive on Waste Electrical and Electronic Equipment, Directive 2012/19/EU, products of “electrical and electronic equipment” cannot be discarded as municipal waste anymoreand manufacturers of covered electronic equipment will be obligated totake back such products at the end of their useful life. Chemical Substances InformationIn compliance with chemical substances regulations, such as the EU REACH Regulation (Regulation EC No. 1907/2006 of the European Parliament and the Council), MSI provides the information of chemical substances in products at: https:///global/indexRoHS StatementJapan JIS C 0950 Material DeclarationA Japanese regulatory requirement, defined by specification JIS C 0950, mandates that manufacturers provide material declarations for certain categories of electronic products offered for sale after July 1, 2006.https:///global/Japan-JIS-C-0950-Material-Declarations India RoHSThis product complies with the “India E-waste (Management and Handling) Rule 2016” and prohibits use of lead, mercury, hexavalent chromium, polybrominated biphenyls or polybrominated diphenyl ethers in concentrations exceeding 0.1 weight % and 0.01 weight % for cadmium, except for the exemptions set in Schedule 2 of the Rule. Turkey EEE RegulationConforms to the EEE Regulations of the Republic Of Turkey Ukraine Restriction of Hazardous SubstancesThe equipment complies with requirements of the Technical Regulation, approved by the Resolution of Cabinet of Ministry of Ukraine as of 10 March 2017, № 139, in terms of restrictions for the use of certain dangerous substances in electrical and electronic equipment.Vietnam RoHSAs from December 1, 2012, all products manufactured by MSI comply with Circular 30/2011/TT-BCT temporarily regulating the permitted limits for a number of hazardous substances in electronic and electric products.34Regulatory Notices35Regulatory Notices Green Product Features∙Reduced energy consumption during use and stand-by ∙Limited use of substances harmful to the environment and health∙Easily dismantled and recycled ∙Reduced use of natural resources by encouraging recycling ∙Extended product lifetime through easy upgrades ∙Reduced solid waste production through take-back policy Environmental Policy ∙The product has been designed to enable proper reuse of parts and recycling and should not be thrown away at its end of life. ∙Users should contact the local authorized point of collection for recycling and disposing of their end-of-life products. ∙Visit the MSI website and locate a nearby distributor for further recycling information. ∙*******************************************************************disposal, take-back, recycling, and disassembly of MSI products.Warning!Overuse of screens is likely to affect eyesight.Recommendations: 1. Take a 10-minute break for every 30 minutes of screen time. 2. Children under 2 years of age should have no screen time. For children aged 2 years and over, screen time should be limited to less than one hour per day.Copyright and Trademarks Notice Copyright © Micro-Star Int’l Co., Ltd. All rights reserved. The MSI logo used is a registered trademark of Micro-Star Int’l Co., Ltd. All other marks and names mentioned may be trademarks of their respective owners. No warranty as to accuracy or completeness is expressed or implied. MSI reserves the right to make changes to this document without prior notice.The terms HDMI™, HDMI™ High-Definition Multimedia Interface, HDMI™ Trade dress and the HDMI™ Logos are trademarks or registered trademarks of HDMI™ Licensing Administrator, Inc.Technical Support If a problem arises with your product and no solution can be obtained from the user’s manual, please contact your place of purchase or local distributor. Alternatively,please visit https:///support/ for further guidance.。

印度经八年研发首推5G NR基带芯片

印度经八年研发首推5G NR基带芯片
3月1日消息，总部位于班加罗尔的半导体公司Signalchip 经过八年的研究和开发终于推出了印度本土首个4G/LTE和5G NR基带芯片。

Signalchip 半导体公司发布了SCBM34XX 和SCRF34XX / 45XX 系列芯片组，代号为“Agumbe”。

SCMB3412 是一款4G/LTE 单芯片调制解调器，包含基带和收发器。

SCMB3404 是一款4X4 LTE 基带调制解调器，采用单芯片设计。

然后是2X2 LTE 收发器，称为SCRF3402，最后是SCRF4502，它是一个2X2 收发器，专为5G NR 标准而制造，射频段覆盖所有LTE/5G-NR频段至6GHz。

借助印度的NAVIC 卫星导航系统，所有这些芯片都将支持该国的卫星定位。

这些芯片组将有助于满足该国日益增长的数据需求，并将让印度在全球5G开发中承担一定的责任。

这款SoC可用作基站芯片组，适用于从低成本室内小型蜂窝到高性能基站的各种外形。

它们经过优化设计，可支持具有灵活接口配置的Open RAN / CRAN等不断发展的网络架构。

通过为该设备创建的IP，该公司现在有可能为多个相关领域设计产品，目前正在为5G NR的高级功能开发更多芯片组。

。

MCP3424的使用说明

MCP3424的使用说明
1.引脚连接
-VDD：连接到电源正极（2.7V至5.5V）。

-VSS：连接到电源负极和地线。

-A0、A1、A2：用于设置设备地址。

-SDA：用于串行数据传输。

-SCL：用于串行时钟传输。

2.电源供应
确保电源电压在2.7V至5.5V之间，将VDD引脚连接到正极，将VSS 引脚连接到负极和地线。

3.设备地址设置
4.通信接口
5.模式选择
6.增益设置
7.数据输出
8.校准和精度
9.转换速率
10.稳定性和滤波
总结：
MCP3424是一款高精度的模数转换器，通过I2C接口与主机控制器通信。

其主要特性包括多种转换模式选择、增益设置、高精度、校准方法、转换速率和稳定性等。

根据以上使用说明，可以根据具体需求来配置和使用MCP3424，以实现精确的模拟信号转换。

1、下载文档前请自行甄别文档内容的完整性，平台不提供额外的编辑、内容补充、找答案等附加服务。
2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
3、如文档侵犯您的权益，请联系客服反馈,我们会尽快为您处理(人工客服工作时间：9:00-18:30)。

TSM342430V N-Channel MOSFETSOT-23Features● Advance Trench Process Technology● High Density Cell Design for Ultra Low On-resistanceApplication● Load Switch ● PA SwitchOrdering InformationPart No.PackagePackingTSM3424CX6 RFSOT-263Kpcs / 7” ReelAbsolute Maximum Rating (Ta = 25o C unless otherwise noted)ParameterSymbolLimitUnitDrain-Source Voltage V DS 30 V Gate-Source Voltage V GS ±20 V Continuous Drain Current I D 6.7 A Pulsed Drain CurrentI DM 30 A Continuous Source Current (Diode Conduction)a,bI S 1.7 A Ta = 25oC 2.0 Maximum Power Dissipation Ta = 75o CP D1.3 WOperating Junction TemperatureT J +150 o C Operating Junction and Storage Temperature RangeT J , T STG-55 to +150oCThermal PerformanceParameterSymbolLimitUnitJunction to Case Thermal ResistanceR ӨJC 30 o C/W Junction to Ambient Thermal Resistance (PCB mounted) R ӨJA80oC/WNotes:a. Pulse width limited by the Maximum junction temperatureb. Surface Mounted on FR4 Board, t ≤ 10 sec.PRODUCT SUMMARY V DS (V) R DS(on)(m Ω)I D (A)30 @ V GS = 10V 6.7 3042 @ V GS = 4.5V5.7Block DiagramN-Channel MOSFETPin Definition: 1. Drain 6. Drain 2. Drain 5, Drain 3. Gate 4. SourceTSM342430V N-Channel MOSFETElectrical Specifications (Ta = 25o C unless otherwise noted)ParameterConditionsSymbolMinTypMaxUnitStaticDrain-Source Breakdown Voltage V GS = 0V, I D = 250µA BV DSS 30 -- -- V Gate Threshold Voltage V DS = V GS , I D = 250µA V GS(TH) 1 1.4 3 V Gate Body LeakageV GS = ±20V, V DS = 0V I GSS -- -- ±100 µA Zero Gate Voltage Drain Current V DS = 24V, V GS = 0V I DSS -- -- 1.0 µA On-State Drain CurrentV DS ≥ 5V, V GS = 10V I D(ON) 30 -- -- A V GS = 10V, I D = 6.7A -- 23 30 Drain-Source On-State Resistance V GS = 4.5V, I D = 5.7A R DS(ON) -- 32 42 m Ω Forward Transconductance V DS = 5V, I D = 5.0A g fs -- 14 -- S Diode Forward Voltage I S = 1.7A, V GS = 0VV SD -- 0.76 1 V Dynamic bTotal Gate Charge Q g -- 4.52-- Gate-Source Charge Q gs -- 1.24 -- Gate-Drain Charge V DS = 15V, I D = 6.7A, V GS = 10VQ gd -- 1.68 -- nC Input Capacitance C iss -- 400.96 -- Output CapacitanceC oss -- 100.47 -- Reverse Transfer Capacitance V DS = 15V, V GS = 0V, f = 1.0MHzC rss--71.82--pFSwitching cTurn-On Delay Time t d(on) -- 7.42 -- Turn-On Rise Time t r -- 3.41 -- Turn-Off Delay Timet d(off)-- 20.4 -- Turn-Off Fall Time V DD = 15V, R L = 2.2Ω, I D = 1A, V GEN = 10V, R G = 6Ωt f --3.01--nSNotes:a. pulse test: PW ≤300µS, duty cycle ≤2%b. For DESIGN AID ONLY, not subject to production testing.b. Switching time is essentially independent of operating temperature.TSM342430V N-Channel MOSFETElectrical Characteristics Curve (Ta = 25o C, unless otherwise noted)Output CharacteristicsTransfer CharacteristicsOn-Resistance vs. Drain CurrentGate ChargeOn-Resistance vs. Junction TemperatureSource-Drain Diode Forward VoltageTSM342430V N-Channel MOSFETElectrical Characteristics Curve (Ta = 25o C, unless otherwise noted)On-Resistance vs. Gate-Source VoltageThreshold VoltageSingle Pulse PowerNormalized Thermal Transient Impedance, Junction-to-AmbientTSM342430V N-Channel MOSFETSOT-26 Mechanical DrawingMarking Diagram24 = Device Code Y = Year Code M = Month Code(A =Jan, B =Feb, C =Mar, D =Apl, E =May, F =Jun, G =Jul, H =Aug, I =Sep, J =Oct, K =Nov, L =Dec) L = Lot CodeSOT-26 DIMENSIONMILLIMETERS INCHES DIM MIN TYP MAX MIN TYPMAXA 0.95 BSC 0.0374 BSCA1 1.9 BSC 0.0748 BSCB 2.60 2.80 3.00 0.1024 0.1102 0.1181C 1.40 1.50 1.70 0.0551 0.0591 0.0669D 2.80 2.90 3.10 0.1101 0.1142 0.1220E 1.00 1.10 1.20 0.0394 0.0433 0.0472F 0.00 -- 0.10 0.000.0039 G 0.35 0.40 0.50 0.0138 0.0157 0.0197 H 0.10 0.15 0.20 0.0039 0.0059 0.0079 I 0.30 -- 0.60 0.0118 -- 0.0236 J5º--10º5º--10ºTSM342430V N-Channel MOSFETNoticeSpecifications of the products displayed herein are subject to change without notice. TSC or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies.Information contained herein is intended to provide a product description only. No license, express or implied, to any intellectual property rights is granted by this document. Except as provided in TSC’s terms and conditions of sale for such products, TSC assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of TSC products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right.The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify TSC for any damages resulting from such improper use or sale.。