MAX4356ECD+中文资料

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MAX4350EUK+T中文资料

General DescriptionThe MAX4350 single and MAX4351 dual op amps are unity-gain-stable devices that combine high-speed per-formance with rail-to-rail outputs. Both devices operate from dual ±5V supplies. The common-mode input volt-age range extends to the negative power-supply rail. The MAX4350/MAX4351 require only 6.9mA of quies-cent supply current per op amp while achieving a 210MHz -3dB bandwidth and a 485V/µs slew rate. Both devices are excellent solutions in low-power systems that require wide bandwidth, such as video, communi-cations, and instrumentation.The MAX4350 is available in an ultra-small 5-pin SC70package and the MAX4351 is available in a space-saving 8-pin SOT23 package.ApplicationsSet-Top BoxesSurveillance Video Systems Video Line DriversAnalog-to-Digital Converter Interface CCD Imaging SystemsVideo Routing and Switching Systems Digital CamerasFeatures♦Ultra-Small 5-Pin SC70, 5-Pin SOT23, and 8-Pin SOT23 Packages ♦Low Cost♦High Speed210MHz -3dB Bandwidth 55MHz 0.1dB Gain Flatness 485V/µs Slew Rate ♦Rail-to-Rail Outputs♦Input Common-Mode Range Extends to V EE ♦Low Differential Gain/Phase: 0.02%/0.08°♦Low Distortion at 5MHz-65dBc SFDR-63dB Total Harmonic DistortionMAX4350/MAX4351Ultra-Small, Low-Cost, 210MHz, Dual-SupplyOp Amps with Rail-to-Rail Outputs________________________________________________________________Maxim Integrated Products 1Pin ConfigurationsTypical Operating Circuit19-1989; Rev 1; 10/05For pricing, delivery, and ordering information,please contact Maxim/Dallas Direct!at 1-888-629-4642, or visit Maxim’s website at .M A X 4350/M A X 4351Ultra-Small, Low-Cost, 210MHz, Dual-Supply Op Amps with Rail-to-Rail Outputs 2_______________________________________________________________________________________ABSOLUTE MAXIMUM RATINGSDC ELECTRICAL CHARACTERISTICS(V CC = +5V, V EE = -5V, R L = ∞to 0V, V OUT = 0, T A = T MIN to T MAX , unless otherwise noted. Typical values are at T A = +25°C.) (NoteSupply Voltage (V CC to V EE )................................................+12V IN_-, IN_+, OUT_..............................(V EE - 0.3V) to (V CC + 0.3V)Output Short-Circuit Current to V CC or V EE ......................150mA Continuous Power Dissipation (T A = +70°C)5-Pin SC70 (derate 2.5mW/°C above +70°C).............200mW 5-Pin SOT23 (derate 7.1mW/°C above +70°C)...........571mW8-Pin SOT23 (derate 5.26mW/°C above +70°C).........421mW 8-Pin SO (derate 5.9mW/°C above +70°C).................471mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range.............................-65°C to +150°C Lead Temperature (soldering, 10s).................................+300°CStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or at any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.MAX4350/MAX4351Ultra-Small, Low-Cost, 210MHz, Dual-SupplyOp Amps with Rail-to-Rail Outputs_______________________________________________________________________________________3AC ELECTRICAL CHARACTERISTICSM A X 4350/M A X 4351Ultra-Small, Low-Cost, 210MHz, Dual-Supply Op Amps with Rail-to-Rail Outputs 4_______________________________________________________________________________________Typical Operating Characteristics(V CC = +5V, V EE = -5V, V CM = 0V, A VCL = +1V/V, R F = 24Ω, R L = 100Ωto 0, T A = +25°C, unless otherwise noted.)4-6100k10M 100M1M1GSMALL-SIGNAL GAIN vs. FREQUENCYFREQUENCY (Hz)G A I N (d B )-5-4-3-2-101234-6100k 10M 100M 1M 1G LARGE-SIGNAL GAIN vs. FREQUENCYFREQUENCY (Hz)G A I N (d B )-5-4-3-2-101230.4-0.6100k 10M 100M 1M 1GGAIN FLATNESS vs. FREQUENCYFREQUENCY (Hz)G A I N (d B )-0.5-0.4-0.3-0.2-0.100.10.20.3100k10M 1M100M1GOUTPUT IMPEDANCE vs. FREQUENCYM A X 4350-05FREQUENCY (Hz)I M P E D A N C E (Ω)1000.010.1110-10-100100k100M10M1MDISTORTION vs. FREQUENCY-70-90-30-500-60-80-20-40FREQUENCY (Hz)D I S T O R T I O N (d B c )-10-100100k100M10M1MDISTORTION vs. FREQUENCY-70-90-30-500-60-80-20-40FREQUENCY (Hz)D I S T O R T I O N (d B c )-10-100100k100M10M1MDISTORTION vs. FREQUENCY-70-90-30-500-60-80-20-40FREQUENCY (Hz)D I S T O R T I O N (d B c )-100-70-80-90-60-50-40-30-20-100040020060080010001200DISTORTION vs. LOAD RESISTANCER LOAD (Ω)D I S T O R T I O N (d B c )0.4-0.6100k1M10M 100M1GGAIN FLATNESS vs. FREQUENCY-0.4FREQUENCY (Hz)G A I N (d B )-0.200.20.1-0.1-0.3-0.50.3MAX4350/MAX4351Ultra-Small, Low-Cost, 210MHz, Dual-SupplyOp Amps with Rail-to-Rail Outputs_______________________________________________________________________________________51000100DIFFERENTIAL GAIN AND PHASE-0.01000.0050.0150.025IRED I F F P H A SE (d e g r e e s )D I F F G A I N (%)M A X 4350-11IRE-0.0050.0200.010-0.040.020.040.080.1200.100.06-0.020-100100k 10M 100M 1M 1GCOMMON-MODE REJECTIONvs. FREQUENCYM A X 4350-12FREQUENCY (Hz)C M R (d B )-90-80-70-60-50-40-30-20-10P S R (d B )0-100100k10M 100M1M1GPOWER-SUPPLY REJECTIONvs. FREQUENCYM A X 4350-13FREQUENCY (Hz)-90-80-70-60-50-40-30-20-1000.40.21.00.80.61.41.21.60300400100200500600700800900OUTPUT VOLTAGE SWING vs. LOAD RESISTANCER LOAD (Ω)V S W I N G (V )INPUT 50mV/divOUTPUT 50mV/divSMALL-SIGNAL PULSE RESPONSE20ns/divR F = 24ΩA VCL = +1V/VINPUT 25mV/divOUTPUT 50mV/divSMALL-SIGNAL PULSE RESPONSE20ns/div R F = 500ΩA VCL = +2V/V INPUT 10mV/divOUTPUT 50mV/divSMALL-SIGNAL PULSE RESPONSE20ns/div R F = 500ΩA VCL = +5V/VINPUT 1V/divOUTPUT 1V/divLARGE-SIGNAL PULSE RESPONSE20ns/divR F = 24ΩA VCL = +1V/V-100-70-80-90-60-50-40-30-20-1000.51.01.52.0DISTORTION vs. VOLTAGE SWINGVOLTAGE SWING (Vp-p)D I S T O R T I O N (d B c )Typical Operating Characteristics (continued)(V CC = +5V, V EE = -5V, V CM = 0V, A VCL = +1V/V, R F = 24Ω, R L = 100Ωto 0, T A = +25°C, unless otherwise noted.)M A X 4350/M A X 4351Ultra-Small, Low-Cost, 210MHz, Dual-Supply Op Amps with Rail-to-Rail Outputs 6_______________________________________________________________________________________Typical Operating Characteristics (continued)(V CC = +5V, V EE = -5V, V CM = 0V, A VCL = +1V/V, R F = 24Ω, R L = 100Ωto 0, T A = +25°C, unless otherwise noted.)20ns/divINPUT 1V/divINPUT 1V/divLARGE-SIGNAL PULSE RESPONSER F = 500ΩA VCL = +2V/VV O L T A G E N O I S E (n V /H z )110k100101k100k1M10MVOLTAGE NOISE vs. FREQUENCYFREQUENCY (Hz)11010091110131********20010030040050250150350450500ISOLATION RESISTANCE vs. CAPACITIVE LOADC LOAD (pF)R I S O (Ω)0501001502002503000200100300400500600700800SMALL-SIGNAL BANDWIDTH vs. LOAD RESISTANCEM A X 4350-24R LOAD (Ω)B A N D W I D T H (M H z )8001001k 10kOPEN-LOOP GAIN vs. LOAD RESISTANCE2010M A X 4350-25R LOAD (Ω)O P E N -L O O P G A I N (d B c )4030506070C U R R E N T N O I S E (p A /H z)110k100101k100k1M10MCURRENT NOISE vs. FREQUENCYFREQUENCY (Hz)110100MAX4351CROSSTALK vs. FREQUENCYM A X 4350-26FREQUENCY (Hz)C R O S S T A L K (d B )-140-80-100-120-60-40-2002040600.1M1M10M 100M1GINPUT 500mV/divOUTPUT 1V/divLARGE-SIGNAL PULSE RESPONSE20ns/divR F = 500ΩA VCL = +2V/VDetailed DescriptionThe MAX4350/MAX4351 are single-supply, rail-to-rail,voltage-feedback amplifiers that employ current-feed-back techniques to achieve 485V/µs slew rates and 210MHz bandwidths. Excellent harmonic distortion and differential gain/phase performance make these ampli-fiers an ideal choice for a wide variety of video and RF signal-processing applications.The output voltage swings to within 125mV of each sup-ply rail. Local feedback around the output stage ensures low open-loop output impedance to reduce gain sensitivity to load variations. The input stage per-mits common-mode voltages beyond the negative sup-ply and to within 2.25V of the positive supply rail.Applications InformationChoosing Resistor ValuesUnity-Gain ConfigurationThe MAX4350/MAX4351 are internally compensated for unity gain. When configured for unity gain, a 24Ωresis-tor (R F ) in series with the feedback path optimizes AC performance. This resistor improves AC response by reducing the Q of the parallel LC circuit formed by the parasitic feedback capacitance and inductance.Inverting and Noninverting ConfigurationsSelect the gain-setting feedback (R F ) and input (R G )resistor values to fit your application (Figures 1a and 1b). Large resistor values increase voltage noise and interact with the amplifier’s input and PC board capaci-tance. This can generate undesirable poles and zeros and decrease bandwidth or cause oscillations. For example, a noninverting gain-of-two configuration (R F =R G ) using 1k Ω resistors, combined with 1pF of amplifier input capacitance and 1pF of PC board capacitance,causes a pole at 159MHz. Since this pole is within the amplifier bandwidth, it jeopardizes stability. Reducing the 1k Ωresistors to 100Ωextends the pole frequency to 1.59GHz, but could limit output swing by adding 200Ωin parallel with the amplifier’s load resistor.Layout and Power-Supply BypassingThese amplifiers operate from dual ±5V supplies. Bypass each supply with a 0.1µF capacitor to ground.Maxim recommends using microstrip and stripline tech-niques to obtain full bandwidth. To ensure that the PC board does not degrade the amplifier’s performance,design it for a frequency greater than 1GHz. Pay care-MAX4350/MAX4351Ultra-Small, Low-Cost, 210MHz, Dual-SupplyOp Amps with Rail-to-Rail Outputs_______________________________________________________________________________________7Figure 1a. Noninverting Gain ConfigurationFigure 1b. Inverting Gain Configurationful attention to inputs and outputs to avoid large para-sitic capacitance. Whether or not you use a constant-impedance board, observe the following design guide-lines:•Don’t use wire-wrap boards; they are too inductive.•Don’t use IC sockets; they increase parasitic capaci-tance and inductance.•Use surface-mount instead of through-hole compo-nents for better high-frequency performance.•Use a PC board with at least two layers; it should be as free from voids as possible.•Keep signal lines as short and as straight as possi-ble. Do not make 90°turns; round all corners.Rail-to-Rail Outputs, Ground-Sensing InputThe input common-mode range extends from V EE to (V CC - 2.25V) with excellent common-mode rejection. Beyond this range, the amplifier output is a nonlinear function of the input, but does not undergo phase reversal or latchup. The output swings to within 125mV of either power-supply rail with a 2k Ωload.Output Capacitive Load and StabilityThe MAX4350/MAX4351 are optimized for AC perfor-mance. They are not designed to drive highly reactive loads, which decrease phase margin and may produce excessive ringing and oscillation. Figure 2 shows a cir-cuit that eliminates this problem. Figure 3 is a graph of the I solation Resistance (R ISO ) vs. Capacitive Load.Figure 4 shows how a capacitive load causes exces-sive peaking of the amplifier’s frequency response if the capacitor is not isolated from the amplifier by a resistor. A small isolation resistor (usually 20Ωto 30Ω)placed before the reactive load prevents ringing and oscillation. At higher capacitive loads, AC performance is controlled by the interaction of the load capacitance and the isolation resistor. Figure 5 shows the effect of a 27Ωisolation resistor on closed-loop response.Coaxial cable and other transmission lines are easily driven when properly terminated at both ends with their characteristic impedance. Driving back-terminated transmission lines essentially eliminates the line’s capacitance.M A X 4350/M A X 4351Ultra-Small, Low-Cost, 210MHz, Dual-Supply Op Amps with Rail-to-Rail Outputs 8_______________________________________________________________________________________Figure 2. Driving a Capacitive Load Through an Isolation Resistor 302520510150CAPACITIVE LOAD (pF)50100200150250I S O L A T I O N R E S I S T A N C E (Ω)Figure 3. Isolation Resistance vs. Capacitive LoadMAX4350/MAX4351Ultra-Small, Low-Cost, 210MHz, Dual-SupplyOp Amps with Rail-to-Rail Outputs_______________________________________________________________________________________9Figure 4. Small-Signal Gain vs. Frequency with Load Capacitance and No Isolation ResistorFigure 5. Small-Signal Gain vs. Frequency with Load Capacitance and 27ΩIsolation ResistorPin Configurations (continued)Chip InformationMAX4350 TRANSISTOR COUNT: 86MAX4351 TRANSISTOR COUNT: 170M A X 4350/M A X 4351Ultra-Small, Low-Cost, 210MHz, Dual-Supply Op Amps with Rail-to-Rail OutputsPackage Information(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to /packages .)implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________11©2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.MAX4350/MAX4351Ultra-Small, Low-Cost, 200MHz, Dual-SupplyOp Amps with Rail-to-Rail OutputsPackage Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to /packages.)元器件交易网。

MAX4004中文资料

THYS
REF shorted to GND, junction temperature falling
5
°C
Input Current Limit MAX4004 Output Current Noise
MAX4006 Output Voltage Noise
Output Resistance Output Leakage
Level Translation
Selector Guide
PART
PIN-PACKAGE INTERNAL TYPICAL RESISTOR ACCURACY
MAX4004EUT-T 6 SOT23-6
None
5%
MAX4004ETA
8 Thin QFN
None
5%
MAX4006EUT-T 6 SOT23-6
o Current (MAX4004) or Voltage (MAX4006) Monitor Output
o Reference Current-Limit Protection (20mA, typ)
o Voltage Clamp Protects Subsequent Output Circuitry
The MAX4004/MAX4006 are available in tiny, spacesaving 6-pin SOT23 and 8-pin thin QFN packages, and operate over the extended temperature range of -40°C to +85°C.
-40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C

MAX465中文资料

Devices offered in this series are as follows:
PART
DESCRIPΒιβλιοθήκη IONMAX463 MAX464 MAX465 MAX466 MAX467 MAX468 MAX469 MAX470
Triple RGB Switch & Buffer Quad RGB Switch & Buffer Triple RGB Switch & Buffer Quad RGB Switch & Buffer Triple Video Buffer Quad Video Buffer Triple Video Buffer Quad Video Buffer
Continuous Power Dissipation (TA = +70°C) 16-Pin Plastic DIP (derate 22.22mW/°C above +70°C) ....1778mW 16-Pin Wide SO (derate 20.00mW/°C above +70°C) .......1600mW
The MAX463–MAX470 series of two-channel, triple/quad buffered video switches and video buffers combines high-accuracy, unity-gain-stable amplifiers with high-performance video switches. Fast switching time and low differential gain and phase error make this series of switches and buffers ideal for all video applications. The devices are all specified for ±5V supply operation with inputs and outputs as high as ±2.5V when driving 150Ω loads (75Ω back-terminated cable).

MAX4376FAUK中文资料

GAIN
SUFFIX
20
T
50
F
100
H
For example, MAX4376TAUK is a single high-side amplifier with a gain of 20.
High-side current monitoring is especially useful in battery-powered systems since it does not interfere with the ground path of the battery charger. The input common-mode range of 0 to +28V is independent of the supply voltage and ensures that the current-sense feedback remains viable even when connected to a battery pack in deep discharge.
-40°C to +125°C -40°C to +125°C -40°C to +125°C -40°C to +125°C -40°C to +125°C -40°C to +125°C
5 SOT23-5 5 SOT23-5 5 SOT23-5 8 SO 8 SO 8 SO
ADOG ADOH ADOI
Applications
Notebook Computers
Current-Limited Power Supplies
Fuel Gauges in PC
General-System/BoardLevel Current Monitoring

MAX4635EUB+中文资料

ELECTRICAL CHARACTERISTICS—Single +5V Supply
(V+ = +4.5V to +5.5V, VIH = +2.4V, VIL = +0.8V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 2, 9)
元器件交易网
Fast, Low-Voltage, Dual 4Ω SPDT CMOS Analog Switches MAX4635/MAX4636
ABSOLUTE MAXIMUM RATINGS
(Voltages Referenced to GND) V+, IN_ .....................................................................-0.3V to +6V COM_, NC_, NO_ (Note 1) .......................... -0.3V to (V+ + 0.3V) Continuous Current into Any Terminal .............................±30mA Peak Current into COM_, NC_, NO_ (pulsed at 1ms, 10% duty cycle).................................±100mA Continuous Power Dissipation (TA = +70°C) 10-Pin µMAX (derate 4.7mW/°C above +70°C) ............330mW 10-Pin Thin QFN (derate 24.4mW/°C above +70°C) ..1951mW Operating Temperature Range .......................... -40°C to +85°C Storage Temperature Range ........................... -65°C to +150°C Lead Temperature (soldering, 10s) ............................... +300°C

LT4356HMS-1#PBF中文资料

–40°C to 125°C
Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container. For more information on lead free part marking, go to: /leadfree/ For more information on tape and reel speciﬁcations, go to: /tapeandreel/
The LT®4356-1 surge stopper protects loads from high voltage transients. It regulates the output during an overvoltage event, such as load dump in automobiles, by controlling the gate of an external N-Channel MOSFET. The output is limited to a safe value thereby allowing the loads to continue functioning. The LT4356-1 also monitors the voltage drop between the VCC and SNS pins to protect against overcurrent faults. An internal ampliﬁer limits the current sense voltage to 50mV. In either fault condition, a timer is started inversely proportional to MOSFET stress. If the timer expires, the FLT pin pulls low to warn of an impending power down. If the condition persists, the MOSFET is turned off.

MAX2566EVKIT中文资料

General DescriptionThe MAX2560/MAX2566/MAX2572 evaluation kits (EV kits) simplify testing of the MAX2560/MAX2566/MAX2572. The EV kits provide 50ΩSMA connectors for all RF inputs, baseband inputs, and RF outputs. On-board VCOs are provided for the on-chip PLLs.The EV kits allow evaluation of the MAX2560/MAX2566/MAX2572s’ I/Q modulator, RF upconverter, IF and RF VGAs, IF and RF PLLs, 3-wire programmable interface,and power-management features.The MAX2560/MAX2566/MAX2572 support CDMA,TDMA, and EDGE modes for US PCS and cellular bands, as well as W-CDMA mode for UMTS band. The MAX2566/MAX2572 also support GSM-GPRS mode for all four bands.Features♦On-Board PCS and Cellular VCOs♦WCDMA, GSM900, DCS1800, GSM1900 Modes (MAX2566/MAX2572 EV Kits)♦50ΩSMA Connectors on All RF and Baseband Ports♦Low-Power Shutdown Mode♦EV-Kit Control Software Available at ♦SPI TM /QSPI TM /MICROWIRE TM CompatibleEvaluate: MAX2560/MAX2566/MAX2572MAX2560/MAX2566/MAX2572 Evaluation Kits________________________________________________________________Maxim Integrated Products 1MAX2560 Component ListOrdering Information19-3368; Rev 0; 7/04For pricing, delivery, and ordering information,please contact Maxim/Dallas Direct!at 1-888-629-4642, or visit Maxim’s website at .Component SuppliersSPI and QSPI are trademarks of Motorola, Inc.Microwire is a trademark of National Semiconductor Corp.E v a l u a t e : M A X 2560/M A X 2566/M A X 2572MAX2560/MAX2566/MAX2572 Evaluation Kits 2_______________________________________________________________________________________MAX2560 Component List (continued)Evaluate: MAX2560/MAX2566/MAX2572MAX2560/MAX2566/MAX2572 Evaluation Kits_______________________________________________________________________________________3MAX2560 Component List (continued)E v a l u a t e : M A X 2560/M A X 2566/M A X 2572MAX2560/MAX2566/MAX2572 Evaluation Kits 4_______________________________________________________________________________________Evaluate: MAX2560/MAX2566/MAX2572MAX2560/MAX2566/MAX2572 Evaluation Kits_______________________________________________________________________________________5MAX2566 Component List (continued)E v a l u a t e : M A X 2560/M A X 2566/M A X 2572MAX2560/MAX2566/MAX2572 Evaluation Kits 6_______________________________________________________________________________________MAX2566 Component List (continued)Evaluate: MAX2560/MAX2566/MAX2572MAX2560/MAX2566/MAX2572 Evaluation Kits_______________________________________________________________________________________7E v a l u a t e : M A X 2560/M A X 2566/M A X 2572MAX2560/MAX2566/MAX2572 Evaluation Kits 8_______________________________________________________________________________________Quick Start The MAX2560/MAX2566/MAX2572 EV kits are fully assembled and factory tested. Follow the instructions in the Connections and Setup section.Test Equipment Required This section lists the recommended test equipment to verify the operation of the MAX2560/MAX2566/ MAX2572. It is intended as a guide only, and substitu-tions may be possible.•One RF signal generator capable of delivering -5dBm of output power in the 1GHz to 3GHz frequency range (HP8648 or equivalent) for the external RF LO •An RF spectrum analyzer with optional digital modu-lation personality (Rohde & Schwarz FSEA30 or equivalent)• A power supply capable of providing 200mA at +5V • A power supply capable of providing 50mA at 6.8V • A power supply capable of providing -50mA at -3.2V •I/Q arbitrary waveform generator (Agilent E4433B or equivalent)•PC (486DX33 or better) with Windows TM95/98, 2000, NT 4.0 or later operating system and an available parallel port•INTF2300 interface board (supplied with EV kit)Connections and Setup This section provides step-by-step instructions for get-ting the EV kit up and running in CDMA, WCDMA, and GSM modes.1)Verify shunts JU6–JU22 and JU28–JU31 are in place.2)Connect the INTF2300 interface cable to the EV kit.Note:Pin 1 of the interface cable corresponds to the red wire. Pin 1 is designated in silkscreen on each of the PC boards.3)With the power supply turned off, connect a +5.0Vpower supply to the header labeled V5.0 (J31).Connect the power-supply ground to the header labeled GND (J5). (The MAX2560 requires two additional power supplies. Connect the +6.8V power supply to JU28, and connect the -3.2V to TP2. Connect the grounds to GND (J5) or GND (J20), or both.)4)Install and run the MAX2560/MAX2572 control soft-ware. The MAX2566 has its own control software.Software is available for download on the Maxim website at .5)With MAX2560/MAX2566/MAX2572 control softwareactive in the REG screen, set the SHDN box to 0 toplace the IC in shutdown mode.6)Turn on the power supplies.Cellular CDMA Mode Perform the following steps to evaluate the MAX2560 inthe cellular CDMA mode:1)Verify shunt JU24 is in the LOTDMA position.2)With MAX2560/MAX2566/MAX2572 control softwareactive in the REG screen, use Table 1 to set the oper-ating mode to cellular CDMA. Also, change the refer-ence frequency to 19.2MHz in the control software.3)Connect the I and Q outputs of the arbitrary wave-form generator to the I (J15) and Q (J16) ports. Setthe generator to reverse-channel CDMA settings.Set the output voltage level to 400mV PK.4)Connect RFL (J9) to the spectrum analyzer.Configure the spectrum analyzer to measure ACPRfor the reverse-channel CDMA. Set the center fre-quency to 836MHz with 50MHz span and a+10dBm reference level.5)Adjust the R6 (VGCIF) to obtain an output power of+8dBm after accounting for cable and connectorloss. The ACPR in 30kHz bandwidth at ±885kHzoffset should be -54dBc, and the ACPR in 30kHzbandwidth at ±1.98MHz offset should be -65dBc.PCS CDMA Mode Perform the following steps to evaluate the MAX2560 inthe PCS CDMA mode:1)Verify shunt JU24 is in the LOTDMA position.2)With MAX2560/MAX2566/MAX2572 control softwareactive in the REG screen, use Table 1 to set theoperating mode to PCS CDMA. Also, change the ref-erence frequency to 19.2MHz in the control software.3)Connect the I and Q outputs of the arbitrary wave-form generator to the I (J15) and Q (J16) ports. Setthe generator to reverse-channel CDMA settings.Set the output voltage level to 400mV PK.4)Connect RFH0 (J1) to the spectrum analyzer.Configure the spectrum analyzer to measure ACPRfor the reverse-channel CDMA. Set the center fre-quency to 1880MHz with 50MHz span and a+10dBm reference level.5)Adjust the R6 (VGCIF) to obtain an output power of+8dBm after accounting for cable and connectorloss. The ACPR in 30kHz bandwidth at ±1.25MHzoffset should be -54dBc, and the ACPR in 30kHzbandwidth at ±1.98MHz offset should be -65dBc. Evaluate: MAX2560/MAX2566/MAX2572MAX2560/MAX2566/MAX2572 Evaluation Kits _______________________________________________________________________________________9 Windows is a trademark of Microsoft.E v a l u a t e : M A X 2560/M A X 2566/M A X 2572WCDMA ModePerform the following steps to evaluate the MAX2566/MAX2572 in the WCDMA mode:1)Verify shunt JU24 is in the LOUMTS position.2)With MAX2560/MAX2566/MAX2572 control softwareactive in the REG screen, use Tables 2 and 3 to set the operating mode to WCDMA.3)Connect the I and Q outputs of the arbitrary wave-form generator to the I (J15) and Q (J16) ports. Set the generator to WCDMA settings. Verify 300mV peak baseband signal on Q+/Q- (JU2) and I+/I-(JU1), or 600mV peak-to-peak differential.4)The MAX2566 EV kit requires an external LO input.Apply an external LO 1565MHz at -10dBm to the LOH port.5)Connect RFH0 (J1) to the spectrum analyzer.Configure the spectrum analyzer to measure ACPR for the uplink WCDMA. Set the center frequency to 1950MHz with 50MHz span and a +10dBm refer-ence level.6)Adjust the R1 (VGCRF) and R6 (VGCIF) (only adjustVGCIF if VGS = 1) to obtain an output power of +8dBm after accounting for cable and connector loss.The ACPR in 3.84MHz bandwidth at ±5MHz offset should be -49dBc, and the ACPR in 3.84MHz band-width at ±10MHz offset should be -62dBc. Note that C112–C115 are disconnected for this measurement.GSM 900 ModePerform the following steps to evaluate the MAX2566/MAX2572 in the GSM 900 mode:1)Verify shunts JU23–JU26 and JU33 positions withTable 4.2)With MAX2560/MAX2566/MAX2572 control softwareactive in the REG screen, use Tables 2 and 3 to set the operating mode to GSM 900 mode.3)Connect the I and Q outputs of the arbitrary wave-form generator to the I (J15) and Q (J16) ports. Set the generator to GSM settings. Verify 300mV peak baseband signal on Q+/Q- (JU2) and I+/I- (JU1), or 600mV peak-to-peak differential.4)The MAX2566 EV kit requires an external LO input.Apply an external LO 1190MHz at -10dBm to the LOH port.5)Connect GSM (J3) to the spectrum analyzer.Configure the spectrum analyzer to measure spec-tral mask for the GSM signal. Set the center fre-quency to 900MHz with 50MHz span and a +10dBm reference level.MAX2560/MAX2566/MAX2572 Evaluation KitsDCS 1800 Mode Perform the following steps to evaluate the MAX2566/MAX2572 in the DCS 1800 mode:1)Verify shunts JU23–JU26 and JU33 positions withTable 4.2)With MAX2560/MAX2566/MAX2572 control softwareactive in the REG screen, use Tables 2 and 3 to set the operating mode to DCS 1800 mode.3)Connect the I and Q outputs of the arbitrary wave-form generator to the I (J15) and Q (J16) ports. Set the generator to GSM settings. Verify 300mV peak baseband signal on Q+/Q- (JU2) and I+/I- (JU1), or 600mV peak-to-peak differential.4)The MAX2566 EV kit requires an external LO input.Apply an external LO 1510MHz at -10dBm to the LOH port.5)Connect GSM (J33) to the spectrum analyzer.Configure the spectrum analyzer to measure spec-tral mask for the GSM signal. Set the center fre-quency to 1800MHz with 50MHz span and a +10dBm reference level.GSM 1900 Mode Perform the following steps to evaluate the MAX2566/MAX2572 in the GSM 1900 mode:1)Verify shunts JU23–JU26 and JU33 positions withTable 4.2)With MAX2560/MAX2566/MAX2572 control softwareactive in the REG screen, use Tables 2 and 3 to set the operating mode to GSM 1900 mode.3)Connect the I and Q outputs of the arbitrary wave-form generator to the I (J15) and Q (J16) ports. Setthe generator to GSM settings. Verify 300mV peakbaseband signal on Q+/Q- (JU2) and I+/I- (JU1), or600mV peak-to-peak differential.4)The MAX2566 EV kit requires an external LO input.Apply an external LO 1610MHz at -10dBm to theLOH port.5)Connect GSM (J33) to the spectrum analyzer.Configure the spectrum analyzer to measure spec-tral mask for the GSM signal. Set the center fre-quency to 1900MHz with a +10dBm reference level.Layout ConsiderationsThe MAX2560/MAX2566/MAX2572 EV kits can serve as guides for board layout. Keep PC board trace lengthsas short as possible to minimize parasitics. Also, keep decoupling capacitors as close to the IC as possiblewith a direct connection to the ground plane.INTF2300 SPI Interface BoardThe INTF2300 interface board is used to interface 3-wire SPI protocol from a PC’s parallel port to the EV kit.This board level translates 5V logic from the PC to VCCof the EV kit (typically, this is 2.85V logic). The INTF2300also provides buffering and EMI filtering. Its absolute maximum supply voltage is 4.6V, limited by the break-down of the buffer IC. The recommended operating supply voltage range is +2.7V to +3.6V.Evaluate: MAX2560/MAX2566/MAX2572MAX2560/MAX2566/MAX2572 Evaluation KitsE v a l u a t e : M A X 2560/M A X 2566/M A X 2572MAX2560/MAX2566/MAX2572 Evaluation KitsFigure 1. MAX2560 EV Kit Schematic (Sheet 1 of 3)MAX2560/MAX2566/MAX2572 Evaluation KitsEvaluate: MAX2560/MAX2566/MAX2572Figure 1. MAX2560 EV Kit Schematic (Sheet 2 of 3)E v a l u a t e : M A X 2560/M A X 2566/M A X 2572MAX2560/MAX2566/MAX2572 Evaluation KitsFigure 1. MAX2560 EV Kit Schematic (Sheet 3 of 3)MAX2560/MAX2566/MAX2572 Evaluation KitsEvaluate: MAX2560/MAX2566/MAX2572Figure 2. MAX2566 EV Kit Schematic (Sheet 1 of 3)E v a l u a t e : M A X 2560/M A X 2566/M A X 2572MAX2560/MAX2566/MAX2572 Evaluation KitsFigure 2. MAX2566 EV Kit Schematic (Sheet 2 of 3)MAX2560/MAX2566/MAX2572 Evaluation KitsEvaluate: MAX2560/MAX2566/MAX2572Figure 2. MAX2566 EV Kit Schematic (Sheet 3 of 3)E v a l u a t e : M A X 2560/M A X 2566/M A X 2572MAX2560/MAX2566/MAX2572 Evaluation KitsFigure 3. MAX2572 EV Kit Schematic (Sheet 1 of 3)MAX2560/MAX2566/MAX2572 Evaluation KitsEvaluate: MAX2560/MAX2566/MAX2572Figure 3. MAX2572 EV Kit Schematic (Sheet 2 of 3)E v a l u a t e : M A X 2560/M A X 2566/M A X 2572MAX2560/MAX2566/MAX2572 Evaluation KitsFigure 3. MAX2572 EV Kit Schematic (Sheet 3 of 3)Evaluate: MAX2560/MAX2566/MAX2572MAX2560/MAX2566/MAX2572 Evaluation Kits ______________________________________________________________________________________21Figure 5. MAX256_/MAX257_ EV Kit Component Placement Guide—Solder SideFigure 4. MAX256_/MAX257_ EV Kit Component PlacementGuide—Component SideFigure 7. MAX256_/MAX257_ EV Kit PC Board Layout—Ground PlaneFigure 6. MAX256_/MAX257_ EV Kit PC Board Layout—Component SideE v a l u a t e : M A X 2560/M A X 2566/M A X 2572MAX2560/MAX2566/MAX2572 Evaluation Kits Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.22____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600©2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.Figure 8. MAX256_/MAX257_ EV Kit PC Board Layout—Inner Layer Figure 9. MAX256_/MAX257_ EV Kit PC Board Layout—SolderSide。

MAX9406中文资料

General DescriptionThe MAX9406 high-speed, low-skew, quad differential input to current-mode logic (CML) translator features high-speed signal conversion of the DisplayPort (DP) to High-Definition Multimedia Interface (HDMI ™) technolo-gy. This device features ultra-low propagation delay of 350ps and channel-to-channel skew of less than 20ps.The MAX9406 supports typical data rates of 2Gbps.The MAX9406 provides the level shift for H DMI’s Display Data Channel (DDC) and hot-plug detection (H PD), which converts the 5V single-ended logic to 3.3V single-ended logic.The MAX9406 operates from a 3V to 3.6V core supply and is specified over the -40°C to +85°C extended tem-perature range. This device is available in 48-pin, 7mm x 7mm thin QFN and 32-pin, 5mm x 5mm thin QFN packages.ApplicationsLevel Conversion for DP to HDMI Data and Clock Driver and Buffer Backplane Data and Clock Distribution Base Stations ATEFeatures♦500mV Differential HDMI Output at 2Gbps Data Rate♦350ps Propagation Delay♦20ps Channel-to-Channel Skew at 2Gbps ♦Low Jitters: DJ = 11ps P-P and RJ = 0.5ps RMS ♦Bidirectional Level Shifter of 5V to 3.3V for DDC Pins ♦Level Shifter of 5V to 3.3V for I/Os♦Integrated 50ΩInput Terminations and Biasing ♦-40°C to +85°C Operating Temperature RangeMAX9406DisplayPort to DVI/HDMI Level Shifter________________________________________________________________Maxim Integrated Products 1Pin ConfigurationsOrdering Information19-1024; Rev 0; 10/07For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,or visit Maxim’s website at .*EP = Exposed paddle.HDMI is a trademark of HDMI Licensing, LCC.M A X 9406DisplayPort to DVI/HDMI Level Shifter 2_______________________________________________________________________________________ABSOLUTE MAXIMUM RATINGSDC ELECTRICAL CHARACTERISTICSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.V CC to GND..............................................................-0.3V to +4V All Pins to GND...........................................-0.3V to (V CC + 0.3V)Short-Circuit Duration (all outputs).............................Continuous Continuous Power Dissipation (T A = +70°C)32-Pin Thin QFN (derate 21.3mW/°C above +70°C).1702mW 48-Pin Thin QFN (derate 27.8mW/°C above +70°C).2222mW Junction-to-Case Thermal Resistance (θJC ) (Note 1)32-Pin Thin QFN........................................................+1.7°C/W 48-Pin Thin QFN........................................................+0.8°C/W Junction-to-Ambient Thermal Resistance (θJA ) (Note 1)32-Pin Thin QFN.........................................................+29°C/W 48-Pin Thin QFN.........................................................+25°C/WOperating Temperature Range..…………………-40°C to +85°C Junction Temperature………………………………………+150°C Storage Temperature Range ……………………-65°C to +150°C ESD ProtectionHuman Body Model (R D = 1.5k Ω, C S = 100pF)IN_D_ and OUT_D_ to GND..........................................±1.5kV Lead Temperature (soldering, 10s).………………………+300°CNote 1:Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a 4-layer board.For detailed information on package thermal considerations, refer to Application Note 4083at /thermal-tutorial.MAX9406DisplayPort to DVI/HDMI Level Shifter_______________________________________________________________________________________3DC ELECTRICAL CHARACTERISTICS (continued)AC ELECTRICAL CHARACTERISTICSTypical Operating Characteristics(V CC = 3.3V, outputs terminated with 50Ω, T A = +25°C, unless otherwise noted.)M A X 9406DisplayPort to DVI/HDMI Level Shifter 4_______________________________________________________________________________________798180838284853.03.23.43.6SUPPLY CURRENT vs. SUPPLY VOLTAGEV CC (V)I C C (m A )200ps/div50mV/divEYE DIAGRAM1.65Gbps PRBSDisplayPort to DVI/HDMI Level ShifterMAX9406 Array_______________________________________________________________________________________5M A X 9406DisplayPort to DVI/HDMI Level Shifter 6_______________________________________________________________________________________Detailed DescriptionThe MAX9406 high-speed, low-skew, quad differential input to CML translator is designed for high-speed sig-nal conversion of the DP to H DMI technology. This device features ultra-low propagation delay of 350ps and channel-to-channel skew of less than 20ps. The MAX9406 supports typical data rates of 2Gbps.The MAX9406 provides the level shift for HDMI’s DDC and HPD, which converts the 5V single-ended logic to 3.3V single-ended logic.High-Speed Signal EnablesOE controls the power through the entire length of the four high-speed signal paths. Setting OE low enables all of the high-speed signal paths. Setting OE high dis-ables all high-speed links and disconnects the internal biasing supply and brings the device to the low-power state. In the low-power state, however, the DDC and HPD ports are still functioning.Display Data Channel (DDC)The MAX9406 allows the translation between 5V and 3V of the lower speed DDC lines. Whenever one side is pulled to GND, the other side follows and vice versa.DDC_EN controls the gating to the DDC link. Setting DDC_EN high enables data to pass through the DDC,while setting DDC_EN low disables the DDC link.Hot-Plug Detection (HPD)The MAX9406 translates the HPD 5V logic into 3V logic.Applications InformationDVI/HDMI DriverThe MAX9406 can be used as the driver for the HDMI signal on the motherboard. The MAX9406 CML output provides a > 400mV differential HDMI output and sup-ports 3.3V pullup at the differential outputs. The level shifter boosts the differential signal from the graphics chip to the HDMI connector, located on the edge of the motherboard.High-Speed Signal Line Enable/DisableThe MAX9406 allows use of the DDC lines independent of the state of the high-speed signal lines and the OE pin. This allows communication through DDC without any high-speed signals.Output TerminationTerminate CML outputs through 50Ωto V CC or use an equivalent Thevinin termination. Terminate both outputs and use identical terminations on each for the lowest output-to-output skew.Power-Supply BypassingAdequate power-supply bypassing is necessary to maximize the performance and noise immunity. Bypass V CC to GND with high-frequency surface-mount 0.01µF ceramic capacitors as close to the device as e multiple bypass vias for connection to minimize inductance.Functional DiagramMAX9406DisplayPort to DVI/HDMI Level Shifter_______________________________________________________________________________________7Printed-Circuit Board (PCB) TracesInput and output trace characteristics affect the perfor-mance of the MAX9406. Connect each of the inputs and outputs to a 50Ωcharacteristic impedance trace.Avoid discontinuities in differential impedance and maximize common-mode noise immunity by maintain-ing the distance between differential traces, avoiding sharp corners. Minimize the number of vias to prevent impedance discontinuities. Reduce reflections by main-taining the 50Ωcharacteristic impedance through con-nectors and across cables. Minimize skew by matching the electrical length of the traces.Exposed PaddleThe thin QFN packages used for the MAX9406 have exposed paddles on the bottom. Connect the exposed paddle to ground using a landing pad large enough to accommodate the entire exposed paddle. Add vias from the exposed paddle's land area to a copper poly-gon on the other side of the PCB to provide lower ther-mal impedance from the MAX9406 to the ambient air.Chip InformationPROCESS: BiPolarM A X 9406DisplayPort to DVI/HDMI Level Shifter 8_______________________________________________________________________________________Package Information(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to /packages .)MAX9406DisplayPort to DVI/HDMI Level Shifter_______________________________________________________________________________________9Package Information (continued)(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to /packages .)Package Information (continued)(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to /packages .)M A X 9406DisplayPort to DVI/HDMI Level Shifter 10______________________________________________________________________________________MAX9406DisplayPort to DVI/HDMI Level ShifterMaxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________11©2007 Maxim Integrated Productsis a registered trademark of Maxim Integrated Products, Inc.Package Information (continued)(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to /packages.)元器件交易网。

MAX3491ECSD中文资料

元器件交易网
MAX3483E/MAX3485E/MAX3486E/MAX3488E/MAX3490E/MAX3491E
19-1474; Rev 0; 4/99
3.3V-Powered, ±15kV ESD-Protected, 12Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
PART
TEMP. RANGE PIN-PACKAGE
MAX3483ECSA
0°C to +70°C
8 SO
MAX3483ECPA
0°C to +70°C
8 Plastic DIP
MAX3483EESA -40°C to +85°C
8 SO
MAX3483EEPA -40°C to +85°C
8 Plastic DIP
o Industry-Standard 75176 Pinout (MAX3483E/MAX3485E/MAX3486E)
o Current-Limiting and Thermal Shutdown for Driver Overload Protection
Ordering Information
General Description
Devices in the MAX3483E family (MAX3483E/MAX3485E/ MAX3486E/MAX3488E/MAX3490E/MAX3491E) are ±15kV ESD-protected, +3.3V, low-power transceivers for RS-485 and RS-422 communications. Each device contains one driver and one receiver. The MAX3483E and MAX3488E feature slew-rate-limited drivers that minimize EMI and reduce reflections caused by improperly terminated cables, allowing error-free data transmission at data rates up to 250kbps. The partially slew-rate-limited MAX3486E transmits up to 2.5Mbps. The MAX3485E, MAX3490E, and MAX3491E transmit at up to 12Mbps.

MAX4164ESD+中文资料

ELECTRICAL CHARACTERISTICS: 3V Operation
(VDD = 3V, VSS = 0, VCM = VDD/2, VOUT = VDD/2, RL tied to VDD/2, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Operating Voltage Range Supply Current (Per Amplifier) Input Bias Current (Note 2)
Input Offset Voltage
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at .
________________________Applications
Battery-Powered Devices pH Probes Portable Equipment Low-Power, Low-Voltage Equipment
Medical Instruments Ionization Detectors Cellular Phones

MAX706中文简介

功能监控器MAX705/706/813中文资料。

概述MAX705/706/813L是一组CMOS监控电路，能够监控电源电压、电池故障和微处理器(MPU或mP)或微控制器(MCU或mC)的工作状态。

将常用的多项功能集成到一片8脚封装的小芯片内，与采用分立元件或单一功能芯片组合的电路相比，大大减小了系统电路的复杂性和元器件的数量，显著提高了系统可靠性和精确度。

该系列产品采用3种不同的8脚封装形式：DIP、SO和mMAX。

主要应用于：微处理器和微控制器系统；嵌入式控制器系统；电池供电系统；智能仪器仪表；通信系统；寻呼机；蜂窝移动电话机；手持设备；个人数字助理(PDA)；电脑电话机和无绳电话机等等。

功能说明RESET/RESET操作复位信号用于启动或者重新启动MPU/MCU，令其进入或者返回到预知的循环程序并顺序执行。

一旦MPU/MCU处于未知状态，比如程序“跑飞”或进入死循环，就需要将系统复位。

对于MAX705和MAX706而言，在上电期间只要Vcc大于，就能保证输出电压不高于的低电平。

在Vcc上升期间RESET维持低电平直到电源电压升至复位门限或以上。

在超过此门限后，内部定时器大约再维持200ms后释放RESET，使其返回高电平。

无论何时只要电源电压降低到复位门限以下(即电源跌落)，RESET引脚就会变低。

如果在已经开始的复位脉冲期间出现电源跌落，复位脉冲至少再维持140ms。

在掉电期间，一旦电源电压Vcc降到复位门限以下，只要Vcc不比还低，就能使RESET维持电压不高于的低电平。

MAX705和MAX706提供的复位信号为低电平RESET，而MAX813L提供的复位信号为高电平RESET，三者其它功能完全相同。

有些单片机，如INTEL的80C51系列，需要高电平有效的复位信号。

看门狗定时器MAX705/706/813L片内看门狗定时器用于监控MPU/MCU的活动。

如果在内WDI端没有收到来自MPU/MCU 的触发信号，并且WDI处于非高阻态，则WDO输出变低。

MAX9635中文资料

16-BIT ADC
Байду номын сангаас
6-BIT RANGE DIGITAL
CDR, TIM
SIGNAL
CONTROL PROCESSING
16-BIT ADC
方框图
VCC
SDA SCL I2C AO INT
N
GND
________________________________________________________________ Maxim Integrated Products 1 本文是英文数据资料的译文，文中可能存在翻译上的不准确或错误。如需进一步确认，请在您的设计中参考英文资料。
平板PC/笔记本电脑 TV/投影仪/显示器
数字照明管理便携设备
蜂窝电话/智能电话
安全系统
应用
业内功耗最低的环境光传感器，内置ADC
特性
♦♦0.045流明至188,000流明宽检测范围 ♦♦小尺寸、2mm x 2mm x 0.6mm UTDFN-Opto封装 ♦♦VCC = 1.7V至3.6V ♦♦工作电流ICC = 0.65µA ♦♦-40°C至+85°C工作温度范围
由于能够检测极其微弱的光线，非常适合光线较暗的工作环境。
片上光电二极管的光谱响应针对人眼对环境光的响应进行优化，集成红外及紫外线屏蔽功能。自适应增益电路可自动选
择正确的流明范围优化测试(计数值 / 流明)。
IC设计工作在1.7V至3.6V供电范围，满负荷工作时仅消耗0.65µA电流。器件采用小尺寸2mm x 2mm x 0.6mm UTDFN-Opto封装。
有关价格、供货及订购信息，请联络Maxim亚洲销售中心：10800 852 1249 (北中国区)，10800 152 1249 (南中国区)，或访问Maxim的中文网站：。

MAX4106中文资料

f = 10kHz f = 1MHz to 100MHz f = 10kHz f = 1MHz to 100MHz
VCM = ±2.5V
VS = ±4.5V to ±5.5V
VOUT = ±2.0V, VCM = 0V
RL = ∞ RL = 100Ω
VIN = 0V
RL = ∞
RL = 100Ω
RL = 30Ω, TA = 0°C to +85°C
SO (derate 5.88mW/°C above +70°C) ........................471mW
Operating Temperature Range MAX4106ESA/MAX4107ESA ..........................-40°C to +85°C
________________________________________________________________ Maxim Integrated Products 1
Call toll free 1-800-998-8800 for free samples or literature.
Short to ground
-2.5 70 75 80 80
±3.2 ±3.0 65
TYP
0.250 1.0 18 0.05
1
1
0.75 9.5 2.5 31
100 100 100 100 15 ±3.8 ±3.5 80 90
MAX UNITS
3
mV
µV/°C
26
µA
2
µA
MΩpFnV/√Hz NhomakorabeaµVRMS

AKD4356资料

n External analog circuitThe 2nd order LPF (fc=93.2kHz, Q=0.712) which adds differential outputs of AK4356 is implemented on the board.When the further attenuation of the out-band noise is needed, some additional LPF is required. Analog signal is output through BNC connectors on the board. And the output level of AK4356 is 5.5Vpp@5V.The AK4356 detects input signal “zero” conditions and assert high on DZFL/DZFR pins. As shown on Figure 2, analog output is muted externally with this signal.LOUT-(ROUT-)DZFL*(DZFR*)LOUT-(ROUT-)R1R2R3C1C24.7k4.7k 2003300p 470pTable 1. The value of R,C on this boardfin 20kHz 40kHz80kHz Frequency Response -0.004dB -0.123dB-1.823dBTable 2. Frequency Response of LPF <Calculation>f C =ω02π,ω0=12*C1*C2*R2*R3,Q=2*C1*ω0.+1R1+1R21R3n Operation sequence1) Set up the power supply lines.[AVDD](orange)= 4.5∼5.25V [DVDD](orange)= 4.5∼5.25V [VD](red)= 3.4∼5.0V [VP+](green)= +12V ∼+15V [VP-](blue)= -12V ∼-12V [AGND](black)= 0V [DGND](black)= 0VEach supply line should be distributed from the power supply unit.2) Set-up the evaluation modes, jumper pins and DIP switches (See the followings.)3) Power on.The AK4356 should be reset once bringing SW1(-PD) “L” upon power-up.n Evaluation modeApplicable evaluation modes1) DIR (Optical Link and RCA) (default)2) Using ROM data (AK43XX)3) Using AKM’s evaluation board for ADC 4) Feeding all signals from external1) DIR (Optical Link and RCA) <default>PORT4(TORX174) or J1(RCA) is used. All clock are supplied from CS8414(DIR). DIR generates MCLK,BICK, LRCK and SDATA from the received data through optical connector (TORX174) or RCA ed for the evaluation using CD test disk. Nothing should be connected to PORT2,3. In case of using optical connector (TORX174), select “OPT” on JP17(RCA/OPT). In case of using RCA connector, select “RCA”.JP15XTIJP14DIRJP4LRCKDIR ADC JP7BICKJP16XTEJP13SDATADIRADC D I RB N CX TLGNDVD 2) Ideal sine wave generated by ROM dataConnect the AKD43XX with PORT3(AD/ROM). AKD4356 sends MCLK to AKD43XX, and receives LRCK,BICK and SDATA. In case of using external master clock through a BNC connector, select “BNC” on JP15(XTI)and short JP16(XTE).JP15XTIJP14DIRJP4LRCKDIR ADC JP7BICKJP16XTEJP13SDATADIRADC D I RB N CX TLGNDVD3) Using AKM’s evaluation board for ADCTo evaluate AK4356 with analog input, the AKM’s evaluation board for ADC can be used. MCLK, BICK and LRCK are supplied from clock generator on the AKD4356, and analog signal is A/D converted and send to AKD4356 through PORT3(AD/ROM). In case of using external master clock through a BNC connector, select “BNC” on JP15(XTI) and short JP16(XTE).JP15XTIJP14DIRJP4LRCKDIR ADC JP7BICKJP16XTEJP13SDATADIRADC D I RB N CX TLGNDVD 4) Feeding all signals from externalUnder the following set-up, all external signals can be fed through POTR3.JP15XTIJP14DIRJP4LRCKDIR ADC JP7BICKJP16XTEJP13SDATADIRADC D I RB N CX TLGNDVD n BICK frequency[JP9]:When BICK is fed from 74HC4040 on board,it’s frequency is selected with JP9.128fs:BICK = 128fs64fs:BICK = 64fs (Figure 3)32fs:BICK = 32fsFigure 3. BICK frequencyJP9X_BICK128fs 64fs 32fsn DIP switch set upUpper side is “ON”(“H”), lower side is “OFF”(”L”).[SW3](MODE1): No.1 to 5 set the mode of AK4356 and No.6 to 8 set the mode of CS8412.No.Pin OFF ON1CAD1 2CAD0Chip address (2bit) <default=”00”>3DIF0 4DIF1 5DIF2Digital interface format of AK4356(See table 2.)6M2 7M1 8M0Digital interface format of CS8414(See table 2.)(Note)Table 3. SW3 set-up(Note:M2-0 should be selected at only evaluation mode 1.In other mode, these should be “OFF”.)345678JP6 Mode Format DIF0DIF1DIF2M2M1M0BICK2016bit, LSB justified000101THR120bit, LSB justified100----224bit, MSB justified010000INV3I2S110010THR default424bit, LSB justified001----Table 4. Digital interface format set-up (1=ON, 0=OFF)(CS8414 does not correspond to 20/24bit LSB justified format.)[SW4](MODE2): Set the mode of AK4356.No.Pin OFF <default>ON1DFS0Normal speed Double speed2DZFE Zero detect disable Zero detect enable3CKS2 4CKS1 5CKS0Clock select(See the datasheet of AK4356.JP5 and 8 should be selected as table 4.) Table 5. SW4 set-up[JP5, 8]: Set the dividing rate corresponding to CKS2-0. This set up is needed only for the evaluation mode 3.JP5JP8Mode FS2FS1128fs x1/2x1256fs x1x1512fs x1x2Table 6. JP5 and 8 set up(For 192fs/384fs/768fs mode, use the external divider.)PORT1CR-I/F12910-CS CCLK CDTIPORT2AC312910SDTI1SDTI2SDTI3MCLK BICK LRCKn Other jumpers set up[JP1](GND): Analog ground and digital groundOpen:Separated <default>Short:Common (The connector “DGND” can be open.)[JP2](DVDD): DVDD of AK4356DVDD:Independent of AVDD <default>AVDD:Same as AVDD (The connector “DVDD” can be open.)[JP3](REG): AVDD of AK4356Open:Supplied from “AVDD” connectorShort:Supplied from the regulator (The connector “AVDD” should be open.)[JP10-12](SDTI1-3): SDTI of AK4356DATA:Serial data <default>GND:“0” datan The function of the toggle SWUpper-side is “H” and lower-side is “L”.[SW1](-PD):Resets the AK4356. Keep “H” during normal operation.[SW2](SMUTE):Soft mute of AK4356. Bring “H” when using soft mute.n The indication content for LED[D2] (VERF):Monitors VERF pin of the CS8414. LED turns on when some error has occurred to CS8414.[D3] (PREM):Indicates whether the input data is pre-emphasized or not. LED turns on when the data is pre-emphasized.n Serial control modeThe AK4356 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT1(CR-I/F) with PC by 10-line flat cable packed with the AKD4356.Chip address can be selected by SW3(MODE1)-No.1(CAD1) and No.2(CAD0).Take care of the direction of connector. There is a mark at 1pin.The pin layout of PORT1 is as Figure 4.Figure 4. PORT1 pin layoutn Interface with AC3 decoderPORT2(AC3) is used for interface with AC3 decoder.MCLK, BICK, LRCK and 3-line serial data can be input from the decoder via PORT2.Pin layout of PORT2 is as Figure5.In this case, JP4(LRCK), JP7(BICK), JP15(XTI), JP16(XTE),JP14(DIR) and JP13(SDATA) should be set up as evaluation mode 4.Figure 5. PORT2 pin layoutMEASUREMENT RESULTS[Measurement condition]• Measurement unit: ROHDE & SCHWARZ, UPD04• MCLK: 256fs• BICK: 64fs• fs: 44.1kHz, 96kHz, 192kHz• BW: 20Hz∼20kHz (fs=44.1kHz), 20Hz∼40kHz (fs=96kHz), 20Hz∼80kHz (fs=192kHz)• Bit: 24bit• Power Supply: AVDD=DVDD=5V• Interface: DIR (fs=44.1kHz), Serial Multiplex (fs=96kHz, 192kHz)• Temperature: RoomParameter Input signal Measurement filter fs=44.1kHzS/(N+D)1kHz, 0dB20kLPF 97.5dBDR1kHz, -60dB20kLPF110.0dB20kLPF, A-weighted113.2dBS/N no signal20kLPF110.1dB20kLPF, A-weighted113.5dBParameter Input signal Measurement filter fs=96kHzS/(N+D)1kHz, 0dB40kLPF 94.4dBDR1kHz, -60dB40kLPF106.2dB20kLPF, A-weighted112.3dBS/N no signal40kLPF106.4dB20kLPF, A-weighted112.8dBParameter Input signal Measurement filter fs=192kHzS/(N+D)1kHz, 0dB80kLPF 90.0dBDR1kHz, -60dB80kLPF 92.6dB20kLPF, A-weighted112.8dBS/N no signal80kLPF 93.3dB20kLPF, A-weighted112.8dB[Measurement condition]• Measurement unit: Audio Precision, System two, Cascade• MCLK: 256fs• BICK: 64fs• fs: 44.1kHz• BW: 20Hz∼20kHz• Bit: 24bit• Power Supply: AVDD=DVDD=5V• Interface: DIR• Temperature: RoomParameter Input signal Measurement filter ResultsS/(N+D)1kHz, 0dB20kLPF 98.8dBDR1kHz, -60dB22kLPF, A-weighted112.2dBS/N no signal22kLPF, A-weighted112.6dBn Plots[Measurement condition]• Measurement unit: Audio Precision, System two, Cascade (fs=48kHz),ROHDE & SCHWARZ, UPD04 (fs=96kHz)• MCLK: 256fs• BICK: 64fs• fs: 44.1kHz, 96kHz, 192kHz• BW: 20Hz∼20kHz (fs=44.1kHz), 20Hz∼40kHz (fs=96kHz), 20Hz∼80kHz (fs=192kHz)• Bit: 24bit• Power Supply: VA=VD=5V• Interface: DIR (fs=48kHz, 96kHz), Serial Multiplex (fs=192kHz)• Temperature: Roomfs=44.1kHzFigure 6. THD+N vs Input Level (fin=1kHz)Figure 7. THD+N vs fin (0dBFS input)Figure 8. Linearity (fin=1kHz)Figure 9. Frequency Response (0dBFS input)Figure 10. Cross-talk (0dBFS input)Figure 11. FFT (1kHz, 0dBFS input)Figure 12. FFT (1kHz, -60dBFS input)Figure 13. FFT (noise floor)Figure 14. FFT (outband noise)fs=96kHzFigure 15. THD+N vs Input Level (fin=1kHz)Figure 16. THD+N vs fin (0dBFS input)Figure 17. Linearity (fin=1kHz)Figure 18. Frequency Response (0dBFS input)fs=192kHzFigure 19. THD+N vs Input Level (fin=1kHz)Figure 20. THD+N vs fin (0dBFS input)Figure 21. Linearity (fin=1kHz)Figure 22. Frequency Response (0dBFS input)AKMAK4356 THD+N vs Input Level (fs=44.1kHz, fin=1kHz)-120+0-110-100-90-80-70-60-50-40-30-20-10dBFSd B r AFigure 6. THD+N vs Input Level (fs=44.1kHz; fin=1kHz)AKMAK4356 THD+N vs fin (fs=44.1kHz, 0dBFS input)2020k501002005001k 2k 5k 10k Hzd B r AFigure 7. THD+N vs fin (fs=44.1kHz; 0dBFS input)AKMAK4356 Linearity (fs=44.1kHz, fin=1kHz)-140+0-130-120-110-100-90-80-70-60-50-40-30-20-10dBFSd B r AFigure 8. Linearity (fs=44.1kHz; fin=1kHz)AKMAK4356 Frequency Response (fs=44.1kHz, 0dBFS input)2k 20k4k 6k 8k 10k12k 14k 16k 18k Hzd B r AFigure 9. Frequency Response (fs=44.1kHz; 0dBFS input)* including output 2nd order LPF ResponseAKMAK4356 Cross-talk (fs=44.1kHz, 0dBFS input)2020k501002005001k 2k 5k 10k Hzd BFigure 10. Cross-talk (fs=44.1kHz; 0dBFS input)AKMAK4356 FFT (fs=44.1kHz; 1kHz, 0dBFS input)2020k501002005001k 2k 5k 10k Hzd B r AFigure 11. FFT (fs=44.1kHz; 1kHz, 0dBFS input)FFT point=16384, Avg=8AKMAK4356 FFT (fs=44.1kHz; 1kHz, -60dBFS input)2020k501002005001k 2k 5k 10k Hzd B r AFigure 12. FFT (fs=44.1kHz; 1kHz, -60dBFS input)FFT point=16384, Avg=8AKMAK4356 FFT (noise floor; fs=44.1kHz, no signal input)2020k501002005001k 2k 5k 10k Hzd B r AFigure 13. FFT (noise floor: fs=44.1kHz; no signal input)FFT point=16384, Avg=8AKMAK4356 FFT (outband noise: ~130kHz; fs=44.1kHz, no signal input)200100k5001k 2k 5k 10k 20k 50k Hzd B r AFigure 14. FFT (outband noise: fs=44.1kHz; no signal input)FFT point=16384, Avg=8AKMAK4356 THD+N vs Input Level (fs=96kHz, fin=1kHz)-120+0-110-100-90-80-70-60-50-40-30-20-10dBFSd B r AFigure 15. THD+N vs Input Level (fs=96kHz; fin=1kHz)AKMAK4356 THD+N vs fin (fs=96kHz, 0dBFS input)2040k501002005001k 2k 5k 10k 20k Hzd B r AFigure 16. THD+N vs fin (fs=96kHz; 0dBFS input)AKMAK4356 Linearity (fs=96kHz, fin=1kHz)-140+0-130-120-110-100-90-80-70-60-50-40-30-20-10dBFSd B r AFigure 17. Linearity (fs=96kHz; fin=1kHz)AKMAK4356 Frequency Response (fs=96kHz, 0dBFS input)2.5k 40k5k 7.5k 10k 12.5k 15k 17.5k 20k 22.5k 25k 27.5k 30k32.5k 35k 37.5k Hzd B r AFigure 18. Frequency Response (fs=96kHz; 0dBFS input)including external 2nd order LPF responseFigure 19. THD+N vs Input Level (fs=192kHz; fin=1kHz)Figure 20. THD+N vs fin (fs=192kHz; 0dBFS input)Figure 21. Linearity (fs=192kHz; fin=1kHz)Figure 22. Frequency Response (fs=192kHz; 0dBFS input) * including external 2nd order LPF responseAKD4356 Control Program ver 1.0 operation manual 1.Connect IBM-A T compatible PC with AKD4356 by 10-line type flat cable (packed with AKD4356).Take care of the direction of 10pin Header (Refer to manual of AKD4356).2.Start up “WINDOWS 95” or “WINDOWS 98”.3.Insert the floppy-disk labeled “AKD4356 Control Program ver 1.0” into the floppy-disk drive.4.Set up “MS-DOS” from start menu.5.Change directory to the floppy-disk drive(ex.a:) at MS-DOS prompt.6.Type “ak4356”.7.Then follow the displayed comment (See the following).==================== <<Operating flow>> =====================Input Chip Address (2bit)Write data/ Display register map/ Reset etc.à loop=========================================================At first the following message is displayed:****** AK4356 Control Program ver 1.0 , '99/3 ******copyright(c) 1999, Asahi Kasei Microsystems co.,ltd.All rights reserved.Input Chip Address(CAD1,CAD0) (2 figure, binary) =Input chip address in 2 figures of binary.Set CAD1 and CAD0 before the AKD4356 is powered up.When hanging CAD1 and CAD0, set SW1(-PD) “L”, then “H” after that.After chip address is defined, the following default register map is displayed (Loop starts from here): CAD1-0=00 ---------------------------------------------------------------- ADDR = 00 : 01 <Control 1> ( 0 SLOW DZFM DZFE DIF2 DIF1 DIF0 RSTN ) ADDR = 01 : 01 <Control 2> ( 0 0 0 CKS2 CKS1 CKS0 SMUTE RSTN ) ADDR = 02 : 0F <Speed & PD> ( 0 0 DFS1 DFS0 PW3 PW2 PW1 RSTN ) ADDR = 03 : 15 <DEM control>( 0 0 DEMC1 DEMC0 DEMB1 DEMB0 DEMA1 DEMA0) ADDR = 04 : FF <LOUT1 ATT> ( ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 ) ADDR = 05 : FF <ROUT1 ATT> ( ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 ) ADDR = 06 : FF <LOUT2 ATT> ( ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 ) ADDR = 07 : FF <ROUT2 ATT> ( ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 ) ADDR = 08 : FF <LOUT3 ATT> ( ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 ) ADDR = 09 : FF <ROUT3 ATT> ( ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 ) ADDR = 0A : 00 <Test> ( TEST7 TEST6 TEST5 TEST4 TEST3 TEST2 TEST1 TEST0) Input 1(Write), R(Reset), T(Table), I(Increment), D(Decrement) or S(Stop) :1) If you input “1”, you can write data to AK4356.You can write data to AK4356Input Register Address (2 figure, hex) (00-0A) =Input register address in 2 figures of hexadecimal.Then current data of this address is displayed:ADDR = 00 : 01 <Control 1> ( 0 SLOW DZFM DZFE DIF2 DIF1 DIF0 RSTN )0 0 0 0 0 0 0 1Input Register Data (2 figure, hex) (00-FF) =You can write control data to this address. Input control data in 2 figures of hexadecimal.Refer to datasheet of AK4356.Then the data written to this address is displayed:ADDR = 00 : 07 <Control 1> ( 0 SLOW DZFM DZFE DIF2 DIF1 DIF0 RSTN )0 0 0 0 0 1 1 12) If you input “R” or “r”, this program writes default data to all register addresses.3) If you input “T” or “t”, current register map is displayed.4) If you input “I” or “i”, this program increment data of current address by 1 (only for addr=04H to 09H). You can increment A TT value by 1step.5) If you input “D” or “d”, this program decrement data of current address by 1 (only for addr=04H to 09H). You can decrement A TT value by 1step.6) If you input “S” or “s”, this program is terminated.元器件交易网元器件交易网元器件交易网元器件交易网IMPORTANT NOTICE• These products and their specifications are subject to change without notice. Beforeconsidering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM)sales office or authorized distributor concerning their current status.• AKM assumes no liability for infringement of any patent, intellectual property, or other rightin the application or use of any information contained herein.• Any export of these products, or devices or systems containing them, may require an exportlicense or other official approval under the law and regulations of the country of exportpertaining to customs and tariffs, currency exchange, or strategic materials.• AKM products are neither intended nor authorized for use as critical components in anysafety, life support, or other hazard related device or system, and AKM assumes noresponsibility relating to any such use, except with the express written consent of theRepresentative Director of AKM. As used here:(a) A hazard related device or system is one designed or intended for life support ormaintenance of safety or for applications in medicine, aerospace, nuclear energy, orother fields, in which its failure to function or perform may reasonably be expected toresult in loss of life or in significant injury or damage to person or property.(b) A critical component is one whose failure to function or perform may reasonably beexpected to result, whether directly or indirectly, in the loss of the safety or effectivenessof the device or system containing it, and which must therefore meet very high standardsof performance and reliability.• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposesof, or otherwise places the product with a third party to notify that party in advance of theabove content and conditions, and the buyer or distributor agrees to assume any and allresponsibility and liability for and hold AKM harmless from any and all claims arising fromthe use of said product in the absence of such notification.。

MAX5436中文资料

TSSOP
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at .
MAX5436–MAX5439
Ordering Information
PART MAX5436EUB TEMP RANGE PINPACKAGE RESISTANCE (kΩ) 50 50 100 100
-40°C to +85°C 10 µMAX 40°C to +85°C 14 TSSOP -40°C to +85°C 10 µMAX -40°C to +85°C 14 TSSOP
元器件交易网
±15V, 128-Tap, Low-Drift Digital Potentiometers MAX5436–MAX5439
ABSOLUTE MAXIMUM RATINGS
VDD to GND, VSS = GND........................................-0.3V to +34V VSS to GND, VDD = GND........................................-34V to +0.3V VDD to VSS ..............................................................-0.3V to +34V VDD to VCC ........................................................-6.3V to +28.75V VCC to VSS ..............................................................-0.3V to +34V VCC to GND ..............................................................-0.3V to +6V DIN, SCLK, CS, SHDN ...............................-0.3V to (VCC + 0.3V) H, L, W, IN+, IN-, OUT .....................(VSS - 0.3V) to (VDD + 0.3V) Maximum Continuous Current into H, L, and W MAX5436–MAX5439.......................................................±1mA Continuous Power Dissipation (TA = +70°C) 10-Pin µMAX (derate 6.94mW/°C above +70°C) .........556mW 14-Pin TSSOP (derate 9.1mW/°C above +70°C) .........727mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C

CS4353资料

Preliminary Product InformationThis document contains information for a new product.Cirrus Logic reserves the right to modify this product without notice.3.3V Stereo Audio DAC with 2V RMS Line OutputFeaturesMulti-bit Delta-Sigma Modulator 106dB A-wt Dynamic Range -93dB THD+NSingle-ended Ground Centered AnalogArchitecture–No DC-blocking Capacitors Required–Integrated Step-up/Inverting Charge Pump –Filtered Line-level Outputs–Selectable 1 or 2V RMS Full-scale OutputLow Clock-jitter Sensitivity Low-latency Digital FilteringSupports Sample Rates up to 192kHz 24-bit Resolution+3.3V Charge Pump and Core Logic, +3.3VAnalog, and +0.9 to 3.3V Interface Power SuppliesLow Power Consumption24-pin QFN, Lead-free AssemblyDescriptionThe CS4353 is a complete stereo digital-to-analog sys-tem including digital interpolation, fifth-order multi-bit delta-sigma digital-to-analog conversion, digital de-em-phasis, analog filtering, and on-chip 2V RMS line-level driver from a 3.3V supply.The advantages of this architecture include ideal differ-ential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and temper-ature, high tolerance to clock jitter, and a minimal set of external components.The CS4353 is available in a 24-pin QFN package in both Automotive (-40°C to +105°C) and Commercial (-40°C to +85°C) grades. The CDB4353 Customer Demonstration Board is also available for device evalu-ation and implementation suggestions. Please see “Ordering Information” on page 26 for complete details.These features are ideal for cost-sensitive, 2-channel audio systems including video game consoles, DVD players and recorders, A/V receivers, set-top boxes,digital TVs, mini-component systems, and mixing consoles.CS4353TABLE OF CONTENTS1. PIN DESCRIPTIONS (4)2. CHARACTERISTICS AND SPECIFICATIONS (6)RECOMMENDED OPERATING CONDITIONS (6)ABSOLUTE MAXIMUM RATINGS (6)DAC ANALOG CHARACTERISTICS (COMMERCIAL - CNZ) (7)DAC ANALOG CHARACTERISTICS (AUTOMOTIVE - DNZ) (8)COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (9)SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE (10)DIGITAL INTERFACE CHARACTERISTICS (11)INTERNAL POWER-ON RESET THRESHOLD VOLTAGES (11)DC ELECTRICAL CHARACTERISTICS (12)3. TYPICAL CONNECTION DIAGRAM (13)4. APPLICATIONS (14)4.1.1 Ground-Centered Outputs (14)4.1.2 Full-Scale Output Amplitude Control (14)4.1.3 Pseudo-Differential Outputs (14)4.8.1 Power-Up Sequences (20)4.8.1.1 External RESET Power-Up Sequence (20)4.8.1.2 Internal Power-On Reset Power-Up Sequence (20)4.8.2 Power-Down Sequences (20)4.8.2.1 External RESET Power-Down Sequence (20)4.8.2.2 Internal Power-On Reset Power-Down Sequence (20)4.9.1 Capacitor Placement (21)5. DIGITAL FILTER RESPONSE PLOTS (22)6. PARAMETER DEFINITIONS (24)7. PACKAGE DIMENSIONS (25)8. ORDERING INFORMATION (26)9. REVISION HISTORY (27)LIST OF FIGURESFigure 1.Serial Input Timing (10)Figure 2.Power-On Reset Threshold Sequence (11)Figure 3.Typical Connection Diagram (13)Figure 4.Stereo Pseudo-Differential Output (14)Figure 5.I²S, up to 24-Bit Data (16)Figure 6.Left-Justified up to 24-Bit Data (16)Figure 7.De-Emphasis Curve, Fs = 44.1 kHz (17)Figure 8.Internal Power-On Reset Circuit (17)Figure 9.Initialization and Power-Down Sequence Diagram (19)Figure 10.Single-Speed Stopband Rejection (22)Figure 11.Single-Speed Transition Band (22)Figure 12.Single-Speed Transition Band (detail) (22)Figure 13.Single-Speed Passband Ripple (22)Figure 14.Double-Speed Stopband Rejection (22)Figure 15.Double-Speed Transition Band (22)Figure 16.Double-Speed Transition Band (detail) (23)Figure 17.Double-Speed Passband Ripple (23)Figure 18.Quad-Speed Stopband Rejection (23)Figure 19.Quad-Speed Transition Band (23)Figure 20.Quad-Speed Transition Band (detail) (23)Figure 21.Quad-Speed Passband Ripple (23)LIST OF TABLESTable 1. Power-On Reset Threshold Voltages (11)Table 2. Digital I/O Pin Characteristics (12)Table 3. CS4353 Operational Mode Auto-Detect (15)Table 4. Single-Speed Mode Standard Frequencies (15)Table 5. Double-Speed Mode Standard Frequencies (15)Table 6. Quad-Speed Mode Standard Frequencies (15)Table 7. Digital Interface Format (16)1. PIN DESCRIPTIONSPin Name Pin #Pin DescriptionSCLK 1Serial Clock (Input ) - Serial clock for the serial audio interface.MCLK 2Master Clock (Input ) - Clock source for the delta-sigma modulator and digital filters. VL 3Serial Audio Interface Power (Input ) - Positive power for the serial audio interface DGND 4Digital Ground (Input ) - Ground reference for the digital section.FLYP+FLYP-75Step-Up Charge Pump Cap Positive/Negative Nodes (Output) - Positive and Negative nodes for the step-up charge pump’s flying capacitor.VCP 6Charge Pump and Digital Core Logic Power (Input ) - Positive power supply for the step-up and invert-ing charge pumps as well as the digital core logic sections.VFILT+8Step-Up Charge Pump Filter Connection (Output) - Power supply from the step-up charge pump that provides the positive rail for the output amplifiersFLYN+FLYN-911Inverting Charge Pump Cap Positive/Negative Nodes (Output) - Positive and Negative nodes for the inverting charge pump’s flying capacitor.CPGND 10Charge Pump Ground (Input ) - Ground reference for the Charge Pump section.VFILT-12Inverting Charge Pump Filter Connection (Output) - Power supply from the inverting charge pump that provides the negative rail for the output amplifiers.AOUTB AOUTA 1315Analog Outputs (Output ) - The full-scale analog line output level is specified in the Analog Characteris-tics table.AOUT_REF 14Pseudo Diff. Analog Output Reference (Input ) - Ground reference for the analog output amplifiers. This pin must be at the same nominal DC voltage as the AGND pin.AGND16Analog Ground (Input ) - Ground reference for the low voltage analog section.S D I NL R C KI ²S /L JD E M1_2V R M SR E S E TF L Y P +V F I L T +F L Y N +C P G N DF L Y N -SCLK MCLKVL DGND FLYP-VBIAS VA AGND AOUT_REF AOUTBVCPV F I L T -AOUTAVA17Low Voltage Analog Power (Input) - Positive power supply for the analog section. VBIAS18Positive Voltage Reference (Output) - Positive reference voltage for the internal DAC.RESET19Reset (Input) - Optional connection for an external reset control. The device enters a powered-down state when this pin is set low (GND) OR when the VCP supply falls below the V off threshold (see Table1). This pin should be set high (VL) during normal operation.1_2VRMS201 or 2V RMS Select (Input) - Selects the analog output full-scale voltage. Setting this pin low (GND) selects 1V RMS, while setting it high (VL) selects 2V RMS.DEM21De-emphasis (Input) - Selects the standard 50µs/15µs digital de-emphasis filter response for 44.1 kHz sample rates when enabled.I²S/LJ22Digital Interface Format (Input) - Selects the serial audio interface format. Setting this pin low (GND) selects I²S, while setting it high (VL) selects Left-Justified.LRCK23Left / Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line.SDIN24Serial Audio Data Input (Input) - Input for two’s complement serial audio data.Thermal Pad-Thermal Relief Pad - This pad may be soldered to the board, however it MUST be electrically isolated from all board connections.2.CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONSAGND = DNGD = CPGND = 0V; all voltages with respect to ground.Notes:1.VCP and VA must be supplied with the same nominal voltage. Additional current draw will occur if the sup-ply voltages applied to VCP and VA differ by more than 0.5V.ABSOLUTE MAXIMUM RATINGSAGND = DNGD = CPGND = 0V; all voltages with respect to ground.WARNING:Operation at or beyond these limits may result in permanent damage to the device. Normal operationis not guaranteed at these extremes.ParametersSymbol Min TypMaxUnitsDC Power SupplyCharge Pump and Digital Core power (Note 1)Low Voltage Analog power (Note 1)Interface powerVCP VA VL 3.133.130.85 3.33.30.9 to 3.33.473.473.47V V V Ambient Operating Temperature (Power Applied)-CNZ-DNZT A T A-40-40--+85+105°C °CParametersSymbolMinMaxUnitsDC Power SupplyCharge Pump and Digital Core Logic PowerLow Voltage Analog Power Supply Voltage DifferenceInterface PowerVCP VA |VCP - VA|VL -0.3-0.3--0.3 3.633.630.53.63V V V V Input Current, Any Pin Except Supplies I in -±10mA Digital Input Voltage Digital Interface V IN-L -0.3V L + 0.4V Analog Input Voltage AOUT_REF V IN-A -0.30.5V Ambient Operating Temperature (Power Applied)T A -55+125°C Storage Temperature T stg-65+150°CTest conditions (unless otherwise specified): T A = 25°C; VCP =VA =3.3V; AOUT_REF =AGND = DGND =CPGND = 0V; VBIAS, +/-VFILT, and FLYP/N+/- capacitors as shown in Figure 3 on page 13; input test signal is a 997Hz sine wave at 0dBFS; measurement bandwidth 10Hz to 20kHz.Notes:2.Measured between the AOUTx and AOUT_REF pins.3.One-half LSB of triangular PDF dither is added to data.4.Measured with the specified minimum AC-Load Resistance present on the AOUTx pins. Additional im-pedance between the AOUTx pin and the load will lower the voltage delivered to the load.5.V PP is the controlling specification. V RMS specification valid for sine wave signals only.Note that for sine wave signals:6.Measured with AOUT_REF connected directly to ground. Additional impedance between AOUT_REFand ground will lower the AOUT_REF rejection.7.SDIN =0. AOUT_REF input test signal is a 60Hz, 50mVpp sine wave. Measured by applying the testsignal into the AOUT_REF pin and measuring the resulting output amplitude on the AOUTx pin. Spec-ification calculated by: 1_2VRMS =01_2VRMS =1ParameterSymbol MinTypMaxMinTypMaxUnitDynamic Performance, Fs = 48, 96, and 192kHz (Notes 2, 3)Dynamic Range24-bit A-Weightedunweighted 16-bit A-Weightedunweighted9491--100979289----10097--1061039895----dB dB dB dB Total Harmonic Distortion + Noise24-bit 0dB-20dB-60dB 16-bit 0dB-20dB-60dB THD+N--------93-77-37-93-75-29-87-71-31-----------93-83-43-93-75-35-87-77-37---dB dB dB dB dB dB Idle Channel Noise / Signal-to-Noise Ratio (A-wt)-100--106-dB Interchannel Isolation(1kHz)-115--115-dB Analog Output (Note 2)Full Scale AOUTx Output Voltage (Notes 4, 5)0.98 1.05 1.12 1.96 2.10 2.25V RMS 2.772.973.17 5.54 5.94 6.36V pp Max Current Draw from an AOUTx Pin I OUTmax-575--575-µA Interchannel Gain Mismatch -0.1--0.1-dB Output Offset -±5±8-±5±8mV Gain Drift-100--100-ppm/°C Output Impedance Z OUT -100--100-ΩAC-Load Resistance R L 5--5--k ΩLoad Capacitance C L --1000--1000pF AOUT_REF Rejection (Notes 6, 7)AOR-40--40-dB Analog Reference Input AOUT_REF Input Voltage(Note 8)--0.2--0.2VppV RMS V pp22---------=AOR dB 20log 10AOUT _REFAOUT _REF AOUTx–---------------------------------------------------------⎝⎠⎛⎞⋅=Test conditions (unless otherwise specified): TA = -40 to +85°C; VCP =VA =3.13V to 3.47V; AOUT_REF = AGND = DGND =CPGND = 0V; VBIAS, +/-VFILT, and FLYP/N+/- capacitors as shown in Figure 3 on page 13; input test signal is a 997Hz sine wave at 0dBFS; measurement bandwidth 10Hz to 20kHz.8.Applying a DC voltage on the AOUT_REF pin will cause a DC offset on the DAC output. See Section4.1.3 for more information.1_2VRMS =01_2VRMS =1ParameterSymbol MinTypMaxMinTypMaxUnitDynamic Performance, Fs = 48, 96, and 192kHz (Notes 2, 3)Dynamic Range24-bit A-Weightedunweighted 16-bit A-Weightedunweighted9491--100979289----10097--1061039895----dB dB dB dB Total Harmonic Distortion + Noise24-bit 0dB-20dB-60dB 16-bit 0dB-20dB-60dB THD+N--------93-77-37-93-75-29-87-71-31-----------93-83-43-93-75-35-87-77-37---dB dB dB dB dB dB Idle Channel Noise / Signal-to-Noise Ratio (A-wt)-100--106-dB Interchannel Isolation(1kHz)-115--115-dB Analog Output (Note 2)Full Scale AOUTx Output Voltage (Notes 4, 5)0.98 1.05 1.12 1.96 2.10 2.25V RMS 2.772.973.17 5.54 5.94 6.36V pp Max Current Draw from an AOUTx Pin I OUTmax-575--575-µA Interchannel Gain Mismatch -0.1--0.1-dB Output Offset -±5±8-±5±8mV Gain Drift-100--100-ppm/°C Output Impedance Z OUT -100--100-ΩAC-Load Resistance R L 5--5--k ΩLoad Capacitance C L --1000--1000pF AOUT_REF Rejection (Notes 6, 7)AOR-40--40-dB Analog Reference Input AOUT_REF Input Voltage(Note 8)--0.2--0.2VppCOMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSEThe filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sam-ple rate by multiplying the given characteristic by Fs. Notes:9.Response is clock-dependent and will scale with Fs.10.For Single- and Double-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs.For Quad-Speed Mode, the Measurement Bandwidth is from stopband to 1.34 Fs.11.De-emphasis is available only in Single-Speed Mode.12.Amplitude vs. Frequency plots of this data are available in “Digital Filter Response Plots” on page 22.ParameterMin TypMaxUnitSingle-Speed Mode - 48kHzPassband (Note 9)to -0.01dB corner to -3dB corner00--.454.499Fs Fs Frequency Response 10Hz to 20kHz -0.01-+0.01dB StopBand0.547--Fs StopBand Attenuation(Note 10)102--dB Total Group Delay (Fs = Sample Rate)-9.4/Fs -s Intra-channel Phase Deviation --±0.56/Fss Inter-channel Phase Deviation--0s De-emphasis Error (Note 11)(Relative to 1kHz)Fs = 44.1 kHz --±0.14dB Double-Speed Mode - 96kHzPassband (Note 9)to -0.01dB corner to -3dB corner00--.430.499Fs Fs Frequency Response 10Hz to 20kHz -0.01-0.01dB StopBand.583--Fs StopBand Attenuation(Note 10)80--dB Total Group Delay (Fs = Sample Rate)- 4.6/Fs -s Intra-channel Phase Deviation --±0.03/Fss Inter-channel Phase Deviation--0s Quad-Speed Mode - 192kHzPassband (Note 9)to -0.01 dB cornerto -3dB corner00--.105.490Fs Fs Frequency Response 10Hz to 20kHz -0.01-0.01dB StopBand.635--Fs StopBand Attenuation(Note 10)90--dB Total Group Delay (Fs = Sample Rate)- 4.7/Fs-sSWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACEParametersSymbol MinMaxUnitsMCLK Frequency 2.04851.2MHz MCLK Duty Cycle4555%Input Sample Rate (Auto selection)Single-Speed Mode Double-Speed Mode Quad-Speed ModeFs Fs Fs 88417054108216kHz kHz kHz LRCK Duty Cycle 4060%SCLK Pulse Width Low t sclkl 20-ns SCLK Pulse Width High t sclkh20-ns SCLK PeriodSingle-Speed Mode -s Double-Speed Mode -s Quad-Speed Mode-s SCLK rising to LRCK edge delay t slrd 20-ns SCLK rising to LRCK edge setup time t slrs 20-ns SDIN valid to SCLK rising setup time tsdlrs 20-ns SCLK rising to SDIN hold timet sdh20-nsFigure 1. Serial Input Timing1128()Fs ---------------------164()Fs ------------------164()Fs ------------------DIGITAL INTERFACE CHARACTERISTICSTest conditions (unless otherwise specified): AGND = DGND = CPGND = 0V; all voltages with respect to ground.INTERNAL POWER-ON RESET THRESHOLD VOLTAGESTest conditions (unless otherwise specified): AGND = DGND = CPGND = 0V; all voltages with respect to ground.Table 1. Power-On Reset Threshold VoltagesFigure 2. Power-On Reset Threshold SequenceParametersSymbolMin TypMaxUnitsHigh-Level Input Voltage 1.2V < VL ≤ 3.3V 0.9V ≤ VL ≤ 1.2V V IH V IH 0.7xVL 0.9xVL ----V V Low-Level Input Voltage 1.2V < VL ≤ 3.3V 0.9V ≤ VL ≤ 1.2VV IL V IL ----0.3xVL 0.1xVL V V Input Leakage Current I in--±10µA Input Capacitance-8-pFParametersSymbolMin Typ Max Units Internal Reset Asserted at Power-On V on1- 1.00-V Internal Reset Released at Power-On V on2- 2.14-V Internal Reset Asserted at Power-OffV off-2.00-VDC ELECTRICAL CHARACTERISTICSTest conditions (unless otherwise specified): VCP =VA =VL =3.3V; AGND = DGND = CPGND = 0V; SDIN =0; all voltages with respect to ground.Notes:13.Current consumption increases with increasing sample rate and increasing MCLK frequency. Typicalvalues are based on Fs =48kHz and MCLK =12.288MHz. Maximum values are based on highest sample rate and highest MCLK frequency; see Switching Specifications - Serial Audio Interface . Vari-ance between speed modes is small.14.Power-down is defined as RESET pin = Low with all clock and data lines held static low. All digital inputshave a weak pull-down (approximately 50k Ω) which is only present during reset. Opposing this pull-down will slightly increase the power-down current.15.Valid with the recommended capacitor value on VBIAS as shown in the typical connection diagram inSection 3.16.Typical voltage shown for “Initialization State”, see Section 4.7. Typical voltage may be up to 1.5V lowerduring normal operation.2.1Digital I/O Pin CharacteristicsInput and output levels and associated power supply voltage are shown in Table 2. Logic levels should not exceed the corresponding power supply voltage.Table 2. Digital I/O Pin CharacteristicsParametersSymbol Min Typ Max UnitsPower SuppliesPower Supply Current (Note 13)Normal OperationPower-Down, All Supplies (Note 14)I VCPI VA I VL I PD----362.40.1654330.2-mA mA mA µA Power Dissipation (All Supplies)Normal Operation, 1_2VRMS =0(Note 13)Power-Down (Note 14)--1271152-mW mW Power Supply Rejection Ratio (Note 15) (1 kHz)(60 Hz)PSRR --6060--dB dB DC Output VoltagesPin VoltageFLYP+ to FLYP-VFILT+ to GND (Note 16)FLYN+ to FLYN-GND to VFILT- (Note 16)VA to VBIAS-----3.36.66.66.62.1-----V V V V VPin Name Power SupplyI/O Driver ReceiverRESET VLInput -0.9V - 3.3V, with HysteresisMCLK Input -0.9V - 3.3V LRCK Input -0.9V - 3.3V SCLK Input -0.9V - 3.3V SDIN Input -0.9V - 3.3V DEM Input -0.9V - 3.3V I²S/LJ Input -0.9V - 3.3V 1_2VRMSInput-0.9V - 3.3V3.TYPICAL CONNECTION DIAGRAMFigure 3. Typical Connection Diagram4.APPLICATIONS4.1Line Outputs4.1.1Ground-Centered OutputsAn on-chip charge pump creates both positive and negative high-voltage supplies, which allows the full-scale output swing to be centered around ground. This eliminates the need for large DC-blocking capac-itors which create audible pops at power-on, allows the CS4353 to deliver a larger full-scale output at low-er supply voltages, and provides improved bandwidth frequency response.4.1.2Full-Scale Output Amplitude ControlThe full-scale output voltage amplitude is selected via the 1_2VRMS pin. When the pin is connected to VL, the full-scale output voltage at the AOUTx pins is approximately 2V RMS. When the pin is connected to GND, the full-scale output voltage at the AOUTx pins is approximately 1V RMS. Additional impedance between the AOUTx pin and the load will lower the voltage delivered to the load. See the DAC Analog Characteristics (Commercial - CNZ) or DAC Analog Characteristics (Automotive - DNZ) table for the com-plete specifications of the full-scale output voltage.4.1.3Pseudo-Differential OutputsThe CS4353 implements a pseudo-differential output stage. The AOUT_REF input is intended to be used as a pseudo-differential reference signal. This feature provides common mode noise rejection with single-ended signals. Figure4 shows a basic diagram outlining the internal implementation of the pseudo-differ-ential output stage, including a recommended stereo pseudo-differential output topology. If pseudo-differ-ential output functionality is not required, simply connect the AOUT_REF pin to ground next to the CS4353. If a split-ground design is used, the AOUT_REF pin should be connected to AGND. See the Ab-solute Maximum Ratings table for the maximum allowable voltage on the AOUT_REF pin. Applying a DC voltage on the AOUT_REF pin will cause a DC offset on the DAC output.Figure 4. Stereo Pseudo-Differential Output4.2Sample Rate Range/Operational Mode DetectThe CS4353 operates in one of three operational modes. The device will auto-detect the correct mode when the input sample rate (Fs), defined by the LRCK frequency, falls within one of the ranges illustrated in Table 3. Sample rates outside the specified range for each mode are not supported. In addition to a valid LRCK frequency, a valid serial clock (SCLK) and master clock (MCLK) must also be applied to the device for speed mode auto-detection; see Figure 9.Table 3. CS4353 Operational Mode Auto-Detect4.3System ClockingThe device requires external generation of the master (MCLK), left/right (LRCK) and serial (SCLK) clocks.The left/right clock, defined also as the input sample rate (Fs), must be synchronously derived from the MCLK signal according to specified ratios. The specified ratios of MCLK to LRCK, along with several stan-dard audio sample rates and the required MCLK frequency, are illustrated in Tables 4-6.Refer to Section 4.4 for the required SCLK timing associated with the selected Digital Interface Format and to “Switching Specifications - Serial Audio Interface” on page 10 for the maximum allowed clock frequen-cies.Table 4. Single-Speed Mode Standard FrequenciesTable 5. Double-Speed Mode Standard FrequenciesTable 6. Quad-Speed Mode Standard FrequenciesInput Sample Rate (Fs)Mode8 kHz - 54 kHz Single-Speed Mode 84 kHz - 108 kHz Double-Speed Mode 170 kHz - 216 kHzQuad-Speed ModeSample Rate(kHz)MCLK (MHz)256x384x512x768x1024x328.192012.288016.384024.576032.768044.111.289616.934422.579233.868845.15844812.288018.432024.576036.864049.1520Sample Rate(kHz)MCLK (MHz)128x192x256x384x512x88.211.289616.934422.579233.868845.15849612.288018.432024.576036.864049.1520Sample Rate(kHz)MCLK (MHz)128x192x256x176.422.579233.868845.158419224.576036.864049.15204.4Digital Interface FormatThe device will accept audio samples in either I²S or Left-Justified digital interface formats, as illustrated in Table 7.The desired format is selected via the I²S/LJ pin. For an illustration of the required relationship between the LRCK, SCLK and SDIN, see Figures 5-6. For all formats, SDIN is valid on the rising edge of SCLK. Also,SCLK must have at least 32 cycles per LRCK period in the Left-Justified format.For more information about serial audio formats, refer to Cirrus Logic Application Note AN282: The 2-Chan-nel Serial Audio Interface: A Tutorial , available at .Table 7. Digital Interface FormatFigure 5. I²S, up to 24-Bit DataFigure 6. Left-Justified up to 24-Bit DataI²S/LJDescriptionFigure0I²S, up to 24-bit Data51Left-Justified, up to 24-bit Data64.5De-Emphasis ControlThe device includes on-chip digital de-emphasis. Figure 7 shows the de-emphasis curve for Fs equal to 44.1kHz. The frequency response of the de-emphasis curve scales with changes in the sample rate, Fs.The de-emphasis error will increase for sample rates other than 44.1kHz.When the DEM pin is connected to VL, the 44.1kHz de-emphasis filter is activated. When the DEM pin is connected to GND, the de-emphasis filter is turned off.Note: De-emphasis is only available in Single-Speed Mode.4.6Internal Power-On ResetThe CS4353 features an internal power-on reset (POR) circuit. The POR circuit allows the RESET pin to be connected to VL during power-up and power-down sequences if the external reset function is not needed.This circuit monitors the VCP supply and automatically asserts or releases an internal reset of the DAC’s digital circuitry when the supply reaches defined thresholds (see “Internal Power-On Reset Threshold Volt-ages” on page 11). No external clocks are required for the POR circuit to function.Figure 8. Internal Power-On Reset CircuitWhen power is first applied, the POR circuit monitors the VCP supply voltage to determine when it reaches a defined threshold, V on1. At this time, the POR circuit asserts the internal reset low, resetting all of the digital circuitry. Once the VCP supply reaches the secondary threshold, V on2, the POR circuit releases the internal reset.Figure 7. De-Emphasis Curve, Fs = 44.1 kHzNote:For correct operation of the internal POR circuit, the voltage on VL must rise before or simulta-neously with VCP.When power is removed and the VCP voltage reaches a defined threshold, V off, the POR circuit asserts the internal reset low, resetting all of the digital circuitry.4.7InitializationWhen power is first applied, the DAC enters a reset (low power) state at the beginning of the initialization sequence. In this state, the AOUTx pins are weakly pulled to ground and VBIAS is connected to VA.The device will remain in the reset state until the RESET pin is brought high. Once the RESET pin is high, the internal digital circuitry is reset and the DAC enters a power-down state until MCLK is applied. Alterna-tively, if no external reset control is required, the internal power-on reset can be used by tying the RESET pin to VL (see Section 4.6).Once MCLK is valid, the device enters an initialization state in which the charge pump powers up and charg-es the capacitors for both the positive and negative high-voltage supplies.Once LRCK and SCLK are valid, the number of MCLK cycles is counted relative to the LRCK period to de-termine the MCLK/LRCK frequency ratio. Next, the device enters the power-up state in which the interpo-lation and decimation filters and delta-sigma modulators are turned on, the internal voltage reference, VBIAS, powers up to normal operation, the analog output pull-down resistors are removed, and power is applied to the output amplifiers.After this power-up state sequence is complete, normal operation begins and analog output is generated.If valid MCLK, LRCK, and SCLK are applied to the DAC before RESET is set high, the total time from RE-SET being set high to the analog audio output from AOUTx is less than 50ms.See Figure9 for a diagram of the device’s states and transition conditions.Figure 9. Initialization and Power-Down Sequence Diagram4.8Recommended Power-Up and Power-Down Sequences4.8.1Power-Up Sequences4.8.1.1External RESET Power-Up SequenceFollow the power-up sequence below if the external RESET pin is used:1.Hold RESET low while the power supplies are turned on.2.Set the I²S/LJ, 1_2VRMS, and DEM configuration pins to the desired state.3.Provide the correct MCLK, LRCK, and SCLK signals locked to the appropriate frequencies asdiscussed in Section 4.3.4.After the power supplies, configuration pins, and clock signals are stable, bring RESET high. Thedevice will initiate the power-up sequence seen in Figure9. The sequence will complete and audiowill be output from AOUTx within 50ms after RESET is set high.4.8.1.2Internal Power-On Reset Power-Up SequenceFollow the power-up sequence below if the internal power-on reset is used:1.Hold RESET high (connected to VL) while the power supplies are turned on. The power-on resetcircuitry will function as described in Section 4.6.2.Set the I²S/LJ, 1_2VRMS, and DEM configuration pins to the desired state.3.After the power supplies and configuration pins are stable, provide the correct MCLK, LRCK, andSCLK signals to progress from the ‘Power-Down State’ in the power-up sequence seen in Figure9.The sequence will complete and audio will be output from the AOUTx pins within 50ms after validclocks are applied.4.8.2Power-Down Sequences4.8.2.1External RESET Power-Down SequenceFollow the power-down sequence below if the external RESET pin is used:1.For minimal pops, set the input digital data to zero for at least 8192 consecutive samples.2.Bring RESET low.3.Remove the power supply voltages.4.8.2.2Internal Power-On Reset Power-Down SequenceFollow the power-down sequence below if the internal power-on reset is used:1.For minimal pops, set the input digital data to zero for at least 8192 consecutive samples.2.Remove the MCLK signal without applying any glitched pulses to the MCLK pin.3.Remove the power supply voltages.Note: A glitched pulse is any pulse that is shorter than the period defined by the minimum/maximum MCLK signal duty cycle specification and the nominal frequency of the input MCLK signal. A transient may occur on the analog outputs if the MCLK signal duty cycle specification is violated when the MCLK signal is removed during normal operation; see “Switching Specifications - Serial Audio Interface” on page10.。

MAX6323-MAX6324中文资料

Input Current, VCC, WDI, MR ..............................................20mA Output Current, RESET, WDPO ..........................................20mA Rate of Rise, VCC ............................................................100V/µs
SUFFIX
FAST
MAX
UNITS
SLOW
MIN
UNITS
A
1.5
ms
10
B
15
ms
100
ms
C
15
ms
300
D
15
ms
10
s
E
15
ms
60
F
23
ms
47
ms
G
39
ms
82
H
719
ms
1.3
s
*See Figure 1 for operation.
________________________________________________________________ Maxim Integrated Products 1
Medical
Embedded Control Systems
Features
♦ Min/Max (Windowed) Watchdog, 8 Factory-Trimmed Timing Options
♦ Pulsed Open-Drain, Active-Low Watchdog Output ♦ Power-On Reset ♦ Precision Monitoring of +2.5V, +3.0V, +3.3V,

MAX1642EUA中文资料

_________________Pin Configurations
TOP VIEW
BATT 1 8 OUT LX GND FB
__________Typical Operating Circuit
PFI 2 PFO 3 SHDN 4
MAX1642
7 6 5
INPUT 0.88V TO 1.65V 22µF
Note 1: The reverse battery current is measured from the Typical Operating Circuit’s input terminal to GND when the battery is connected backward. A reverse current of 220mA will not exceed package dissipation limits but, if left for an extended time (more than 10 minutes), may degrade performance.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

max3485中文资料

max3485eesa + T概述Max3485eesa + T是3.3V电源±15kV ESD保护，真正的RS485 / RS422收发器，采用8引脚nsoic封装。

该低功耗收发器包含一个驱动器和一个接收器。

max3485e传输速率高达15Mbps。

它具有增强的静电保护。

所有发送器输出和接收器输入均具有±15kV保护，并通过IEC 1000-4-2气隙放电；±8Kv保护是通过IEC 1000-4-2接触放电，±15kV保护是通过人体模型。

驱动器受到短路电流的限制，并通过将驱动器输出置于高阻抗状态的热关断电路来防止过多的功耗。

接收器输入具有故障安全功能，如果两个输入均打开，则提供逻辑高电平输出。

Max3485e适用于EMI敏感应用，集成服务，数字网络和数据包交换电源电压范围：3V至3.6V工作温度范围-40°C至85°C半双工通讯该操作由单个+ 3.3V电源供电，无电荷泵兼容+ 5V逻辑2Na小电流关闭模式共模输入电压范围：-7V至+ 12V工业标准75176引脚输出驱动器/接收器启用功能工业控制LAN，ISDN，低功耗RS-485 / RS-422收发器;分组交换;电信;用于EMI敏感应用的收发器Max3483，max3485，max3486，max3488，max3490和max3491是用于RS-485和RS-422通信的3.3V低功耗收发器，每个收发器都有一个驱动器和一个接收器。

Max3483和max3488具有有限速率驱动器，可以降低EMI并减少由于端子匹配电缆不合适而引起的反射，从而实现高达250kbps的无错误数据传输。

由于其有限的摆幅速率，Max3486可以实现最大2.5mbps 的传输速率。

Max3485，max3490和max3491可以实现高达10Mbps的传输速率。

驱动器具有短路电流限制，并且可以通过热关断电路将驱动器的输出设置为高阻状态，以防止过多的功率损耗。

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General DescriptionThe MAX4356 is a 16 ✕16 highly integrated video crosspoint switch matrix with input and output buffers and On-Screen Display (OSD) Insertion. This device operates from dual ±3V to ±5V supplies or from a sin-gle +5V supply. Digital logic is supplied from an inde-pendent single +2.7V to +5.5V supply. Individual outputs can be switched between an input video signal source and OSD information through an internal, dedi-cated fast 2:1 mux (40ns switching times) located before the output buffer. All inputs and outputs are buffered, with all outputs able to drive standard 75Ωreverse-terminated video loads.The switch matrix configuration and output buffer gain are programmed via an SPI/QSPI ™-compatible, three-wire serial interface and initialized with a single update signal. The unique serial interface operates in two modes facilitating both fast updates and initialization.On power-up, all outputs are initialized in the disabled state to avoid output conflicts in large-array configura-tions.Superior flexibility, high integration, and space-saving packaging make this nonblocking switch matrix ideal for routing video signals in security and video-on-demand systems.The MAX4356 is available in a 128-pin TQFP package and specified over an extended -40°C to 85°C temper-ature range.ApplicationsSecurity SystemsVideo RoutingVideo-on-Demand SystemsFeatureso 16 ✕16 Nonblocking Matrix with Buffered Inputs and Outputs o Operates from ±3V, ±5V, or +5V Supplies o Individually Programmable Output Buffer Gain (A V = +1V/V or +2V/V)o High-Impedance Output Disable for Wired-OR Connections o Fast-Switching (40ns) 2:1 OSD Insertion Mux o 0.1dB Gain Flatness to 14MHzo -62dB Crosstalk, -110dB Isolation at 6MHz o 0.02%/0.12°Differential Gain/Differential Phase Error o Low 195mW Power Consumption (0.76mW per Point)MAX435616x 16 Nonblocking Video Crosspoint Switch with On-Screen Display Insertion and I/O Buffers________________________________________________________________Maxim Integrated Products1Ordering InformationTypical Operating CircuitFunctional Diagram19-2113; Rev 0; 8/01For pricing, delivery, and ordering information,please contact Maxim/Dallas Direct!at 1-888-629-4642, or visit Maxim’s website at .SPI and QSPI are trademarks of Motorola, Inc.Pin Configuration appears at end of data sheet.M A X 435616x 16 Nonblocking Video Crosspoint Switch with On-Screen Display Insertion and I/O Buffers 2_______________________________________________________________________________________ABSOLUTE MAXIMUM RATINGSDC ELECTRICAL CHARACTERISTICS —DUAL SUPPLIES ±5V(V CC = +5V, V EE = -5V, V DD = +5V, AGND = DGND = 0, V IN _= 0, V OSDFILL _ = 0, R L = 150Ωto AGND, and T A = T MIN to T MAX ,unless otherwise noted. Typical values are at T A = +25°C.)Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Analog Supply Voltage (V CC - V EE ).....................................+11V Digital Supply Voltage (V DD - DGND) ...................................+6V Analog Supplies to Analog Ground(V CC - AGND) and (AGND - V EE )......................................+6V Analog Ground to Digital Ground .........................-0.3V to +0.3V IN_, OSDFILL_ Voltage Range........(V CC + 0.3V) to (V EE - 0.3V)OUT_ Short-Circuit Duration to AGND, V CC , or V EE ......Indefinite SCLK, CE , UPDATE , MODE, A_, DIN, DOUT,RESET , AOUT , OSDKEY_.......(V DD + 0.3V) to (DGND - 0.3V)Current into Any Analog Input Pin (IN_, OSDFILL_).........±50mA Current into Any Analog Output Pin (OUT_).....................±75mA Continuous Power Dissipation (T A = +70°C)128-Pin TQFP (derate 25mW/°C above +70°C).................2W Operating Temperature Range ...........................-40°C to +85°C Junction Temperature......................................................+150°C Storage Temperature Range.............................-65°C to +150°C Lead Temperature (soldering, 10s)................................+300°CMAX435616x 16 Nonblocking Video Crosspoint Switch with On-Screen Display Insertion and I/O Buffers_______________________________________________________________________________________3DC ELECTRICAL CHARACTERISTICS —DUAL SUPPLIES ±5V (continued)(V= +5V, V = -5V, V = +5V, AGND = DGND = 0, V _= 0, V _ = 0, R = 150Ωto AGND, and T = T to T ,M A X 435616x 16 Nonblocking Video Crosspoint Switch with On-Screen Display Insertion and I/O Buffers 4_______________________________________________________________________________________DC ELECTRICAL CHARACTERISTICS —DUAL SUPPLIES ±3V(V CC = +3V, V EE = -3V, V DD = +3V, AGND = DGND = 0, V IN _ = 0, V OSDFILL _ = 0, R L = 150Ωto AGND, and T A = T MIN to T MAX ,unless otherwise noted. Typical values are at T A = +25°C.)MAX435616x 16 Nonblocking Video Crosspoint Switch with On-Screen Display Insertion and I/O Buffers_______________________________________________________________________________________5DC ELECTRICAL CHARACTERISTICS —DUAL SUPPLIES ±3V (continued)(V CC = +3V, V EE = -3V, V DD = +3V, AGND = DGND = 0, V IN _ = 0, V OSDFILL _ = 0, R L = 150Ωto AGND, and T A = T MIN to T MAX ,DC ELECTRICAL CHARACTERISTICS —SINGLE SUPPLY +5V(V CC = +5V, V EE = 0, V DD = +5V, AGND = DGND = 0, V IN _ = V OSDFILL _ = +1.75V, A V = +1V/V, R L = 150Ωto AGND, and T A = T MINto T MAX , unless otherwise noted. Typical values are at T A = +25°C.)M A X 435616x 16 Nonblocking Video Crosspoint Switch with On-Screen Display Insertion and I/O Buffers 6_______________________________________________________________________________________DC ELECTRICAL CHARACTERISTICS —SINGLE SUPPLY +5V (continued)(V CC = +5V, V EE = 0, V DD = +5V, AGND = DGND = 0, V IN _ = V OSDFILL _ = +1.75V, A V = +1V/V, R L = 150Ωto AGND, and T A = T MINMAX435616x 16 Nonblocking Video Crosspoint Switch with On-Screen Display Insertion and I/O Buffers_______________________________________________________________________________________7LOGIC-LEVEL CHARACTERISTICS(V CC - V EE)= +4.5V to +10.5V, V DD = +2.7V to +5.5V, AGND = DGND = 0, V IN _ = V OSDFILL _ = 0, R L = 150Ωto AGND, andAC ELECTRICAL CHARACTERISTICS —DUAL SUPPLIES ±5V(V CC = +5V, V EE = -5V, V DD = +5V, AGND = DGND = 0, V IN _ = V OSDFILL _ = 0, R L = 150Ωto AGND, and T A = +25°C, unless other-wise noted.)M A X 435616x 16 Nonblocking Video Crosspoint Switch with On-Screen Display Insertion and I/O BuffersAC ELECTRICAL CHARACTERISTICS —DUAL SUPPLIES ±5V (continued)(V = +5V, V = -5V, V = +5V, AGND = DGND = 0, V _ = V _ = 0, R = 150Ωto AGND, A = +1V/V, and T = +25°C,AC ELECTRICAL CHARACTERISTICS —DUAL SUPPLIES ±3V(V CC = +3V, V EE = -3V, V DD = +3V, AGND = DGND = 0, V IN _= V OSDFILL _ = 0, R L = 150Ωto AGND, A V = +1V/V, and T A = +25°C,MAX435616x 16 Nonblocking Video Crosspoint Switch with On-Screen Display Insertion and I/O Buffers_______________________________________________________________________________________9AC ELECTRICAL CHARACTERISTICS —DUAL SUPPLIES ±3V (continued)(V CC = +3V, V EE = -3V, V DD = +3V, AGND = DGND = 0, V IN _= V OSDFILL _ = 0, R L = 150Ωto AGND, A V = +1V/V, and T A = +25°C,unless otherwise noted.)M A X 435616x 16 Nonblocking Video Crosspoint Switch with On-Screen Display Insertion and I/O Buffers 10______________________________________________________________________________________AC ELECTRICAL CHARACTERISTICS —SINGLE SUPPLY +5VMAX4356with On-Screen Display Insertion and I/O BuffersSWITCHING CHARACTERISTICS((V CC - V EE ) = +4.5V to +10.5V, V DD = +2.7V to +5.5V, DGND = AGND = 0, V IN _ = V OSDFILL _ = 0 for dual supplies, V IN _ =V OSDFILL _ = +1.75V for single supply, R L = 150Ωto AGND, C L = 100pF, A V = +1V/V, and T A = T MIN to T MAX , unless otherwise noted. Typical values are at T A = +25°C. )offset voltage. Gain is specified for IN_ and OSDFILL_ signal paths.Note 2:Logic-level characteristics apply to the following pins: DIN, DOUT, SCLK, CE , UPDATE , RESET , A3–A0, MODE, AOUT , andOSDKEY_.Note 3:Switching transient settling time is guaranteed by the settling time (t S ) specification. Switching transient is a result of updat-ing the switch matrix.Note 4:Input test signal: 3.58MHz sine wave of amplitude 40IRE superimposed on a linear ramp (0 to 100IRE). IRE is a unit ofvideo-signal amplitude developed by the International Radio Engineers: 140IRE = 1.0V.Note 5:All devices are 100% production tested at T A = +25°C. Specifications over temperature limits are guaranteed by design.M A X 4356with On-Screen Display Insertion and I/O BuffersMAX4356with On-Screen Display Insertion and I/O BuffersFigure 1. Timing DiagramM A X 4356with On-Screen Display Insertion and I/O Buffers Typical Operating Characteristics—Dual Supplies ±5V(V CC = +5V and V EE = -5V, V DD = +5V, AGND = DGND = 0, V IN_= 0, R L = 150Ωto AGND, and T A = +25°C, unless otherwise noted.)3-70.11101001000LARGE-SIGNAL FREQUENCY RESPONSE-5FREQUENCY (MHz)N O R M A L I Z E D G A I N (d B )-3-110-2-4-623-70.11101001000MEDIUM-SIGNAL FREQUENCY RESPONSE-5FREQUENCY (MHz)N O R M A L I Z E D G A I N (d B )-3-110-2-4-623-70.11101001000SMALL-SIGNAL FREQUENCY RESPONSE-5FREQUENCY (MHz)N O R M A L I Z E D G A I N (d B )-3-110-2-4-623-70.11101001000LARGE-SIGNAL FREQUENCY RESPONSE-5FREQUENCY (MHz)N O R M A L I Z E D G A I N (d B )-3-110-2-4-623-70.11101001000MEDIUM-SIGNAL FREQUENCY RESPONSE-5FREQUENCY (MHz)N O R M A L I Z E D G A I N (d B )-3-110-2-4-623-70.11101001000SMALL-SIGNAL FREQUENCY RESPONSE-5FREQUENCY (MHz)N O R M A L I Z E D G A I N (d B )-3-110-2-4-620.3-0.70.11101001000LARGE-SIGNAL GAIN FLATNESSvs. FREQUENCY-0.5FREQUENCY (MHz)N O R M A L I Z E D G A I N (d B )-0.3-0.10.10-0.2-0.4-0.60.20.3-0.70.11101001000LARGE-SIGNAL GAIN FLATNESSvs. FREQUENCY-0.5FREQUENCY (MHz)N O R M A L I Z E D G A I N (d B )-0.3-0.10.10-0.2-0.4-0.60.23-70.11101001000LARGE-SIGNAL FREQUENCY RESPONSE(A V = +1V/V)-5FREQUENCY (MHz)N O R M A L I Z E D G A I N (d B )-3-110-2-4-62MAX4356with On-Screen Display Insertion and I/O BuffersTypical Operating Characteristics—Dual Supplies ±5V (continued)(V CC = +5V and V EE = -5V, V DD = +5V, AGND = DGND = 0, V IN_= 0, R L = 150Ωto AGND, and T A = +25°C, unless otherwise noted.)3-70.11101001000LARGE-SIGNAL FREQUENCY RESPONSE(A V = +2V/V)-5FREQUENCY (MHz)N O R M A L I Z E D G A I N (d B )-3-110-2-4-620.11011001000MEDIUM-SIGNAL FREQUENCY RESPONSE(A V = +1V/V)FREQUENCY (MHz)N O R M A L I Z E D G A I N (d B )-10-551015730.11101001000MEDIUM-SIGNAL FREQUENCY RESPONSE(A V = +2V/V)1FREQUENCY (MHz)N O R M A L I Z E D G A I N (d B )13542026-40-1000.11010011000FREQUENCY (MHz)C R OS S T A L K (d B )-90-80-70-60-50CROSSTALK vs. FREQUENCY-40-1000.11010011000FREQUENCY (MHz)C R O S S T A L K (d B )-90-80-70-60-50CROSSTALK vs. FREQUENCY-10-1000.1100101DISTORTION vs. FREQUENCY-70-90-30-500-60-80-20-40FREQUENCY (MHz)D I S T O R T I ON (d B c )-10-1000.1100101DISTORTION vs. FREQUENCY-70-90-30-500-60-80-20-40FREQUENCY (MHz)D I S T O R T I O N (d B c )0.11011001000ENABLED-OUTPUT IMPEDANCEvs. FREQUENCYM A X 4356 t o c 17FREQUENCY (MHz)O U T P U T I M P E D A N C E (Ω)1000-0.11101001M 1100k 10M 100M 1M 1GM A X 4356 t o c 18FREQUENCY (Hz)O U T P U T I M P E D A N C E (Ω)101001k 10k 100k DISABLED-OUTPUT IMPEDANCEvs. FREQUENCYM A X 4356with On-Screen Display Insertion and I/O Buffers Typical Operating Characteristics—Dual Supplies ±5V (continued)(V CC = +5V and V EE = -5V, V DD = +5V, AGND = DGND = 0, V IN_= 0, R L = 150Ωto AGND, and T A = +25°C, unless otherwise noted.)-40-50-60-70-80-90-100-110-120100k10M 100M1M1GM A X 4356 t o c 19FREQUENCY (Hz)O F F I S O L A T I O N (d B )OFF ISOLATION vs. FREQUENCY10k1M 100k10M100MPOWER-SUPPLY REJECTION RATIOvs. FREQUENCYFREQUENCY (Hz)P S R R (d B )-75-70-60-65-55-50100011010k100k1M1001k10MINPUT VOLTAGE NOISE vs. FREQUENCY100M A X 4356 t oc 21FREQUENCY (Hz)V O L T A G EN O I S E (n V /√H z )25ns/divLARGE-SIGNAL PULSE RESPONSE(A V = +1V/V)INPUT 1V/divOUTPUT0.5V/divMAX4356 toc2225ns/div LARGE-SIGNAL PULSE RESPONSE(A V = +2V/V)INPUT 0.5V/div OUTPUT 0.5V/div MAX4356 toc2325ns/divMEDIUM-SIGNAL PULSE RESPONSE(A V = +1V/V)INPUT 100mV/divOUTPUT 50mV/divMAX4356 toc2425ns/div MEDIUM-SIGNAL PULSE RESPONSE(A V = +2V/V)INPUT 50mV/div OUTPUT 50mV/div MAX4356 toc2520ns/div SWITCHING TIME (A V = +1V/V)V UPDATE 5V/div V OUT 00mV/div MAX4356 toc2620ns/divSWITCHING TIME (A V = +2V/V)V UPDATE 5V/divV OUT 1V/divMAX4356 toc27MAX4356with On-Screen Display Insertion and I/O BuffersTypical Operating Characteristics—Dual Supplies ±5V (continued)(V CC = +5V and V EE = -5V, V DD = +5V, AGND = DGND = 0, V IN_= 0, R L = 150Ωto AGND, and T A = +25°C, unless otherwise noted.)20ns/div SWITCHING TRANSIENT (GLITCH)(A V = +1V/V)V 5V/div V OUT 25mV/divMAX4356 toc2820ns/div SWITCHING TRANSIENT (GLITCH)(A V = +2V/V)V UPDATE 5V/divV OUT 25mV/divMAX4356 toc2910050200150250300-15-11-9-7-13-5-3-1135OFFSET VOLTAGE DISTRIBUTIONOFFSET VOLTAGE (mV)-0.0501020304050607080901000102030405060708090100DIFFERENTIAL GAIN AND PHASE(R L = 150Ω)0.000.00-0.020.050.020.040.100060.080.15IRED I F F P H A SE (°)D I F F G A I N (%)M A X 4356 t o c 310.010.0001020304050607080901000102030405060708090100DIFFERENTIAL GAIN AND PHASE(R L= 1k Ω)-0.0040.02-0.0020.0000.0020.0040.03IRED I FF P H A S E (°)D I F FG A I N (%)M A X 4356 t o c 32-0.0125ns/divLARGE-SIGNAL PULSE RESPONSE WITH CAPACITIVE LOAD (C L = 30pF, A V = +1V/V)INPUT 1V/divOUTPUT 0.5/VdivMAX4356 toc3325ns/div LARGE-SIGNAL PULSE RESPONSE WITH CAPACITIVE LOAD (C L = 30pF, A V = +2V/V)INPUT 0.5V/div OUTPUT 0.5/Vdiv MAX4356 toc3425ns/div MEDIUM-SIGNAL PULSE RESPONSE WITH CAPACITIVE LOAD (C L = 30pF, A V = +1V/V)INPUT 100mV/div OUTPUT 50mV/div MAX4356 toc3525ns/divMEDIUM-SIGNAL PULSE RESPONSE WITH CAPACITIVE LOAD (C L = 30pF, A V = +2V/V)INPUT 50mV/divOUTPUT 50mV/divMAX4356 toc36M A X 4356with On-Screen Display Insertion and I/O Buffers Typical Operating Characteristics—Dual Supplies ±5V (continued)(V CC = +5V and V EE = -5V, V DD = +5V, AGND = DGND = 0, V IN_= 0, R L = 150Ωto AGND, and T A = +25°C, unless otherwise noted.)-0.20-0.15-0.10-0.0500.050.100.150.20-50-25255075100GAIN vs. TEMPERATURETEMPERATURE (°C)N O R M A L I Z E D G A I N (d B )1p 10n 1µ100p 10p 1n 100n 10µ100µ10n10µ1µ100n 100µ1m 10m 100m 101RESET DELAY vs. C R E S E T D E L A Y (s )C RESET (F)OSD SWITCHING TRANSIENT (100IRE LEVEL SWITCH) (A V = +2V/V)MAX4356 toc3950ns/divV OSDKEY05V/divV OUT0500mV/div100IRE0IREOSD SWITCHING 3.58MHz SIGNAL(A V = +2V/V)MAX4356 toc4050ns/divV OSDKEY05V/divV OUT0500mV/div020104030605070-50025-255075100SUPPLY CURRENT vs. TEMPERATURETEMPERATURE (°C)S U P P L Y C U R R E N T (m A )MAX4356with On-Screen Display Insertion and I/O BuffersTypical Operating Characteristics—Dual Supplies ±3V(V CC = +3V and V EE = -3V, V DD = +3V, AGND = DGND = 0, V IN_= 0, R L = 150Ωto AGND, and T A = +25°C, unless otherwise noted.)3-70.11101001000LARGE-SIGNAL FREQUENCYRESPONSE-5FREQUENCY (MHz)N O R M A L I Z E D G A I N (d B )-3-110-2-4-623-70.11101001000MEDIUM-SIGNAL FREQUENCYRESPONSE-5FREQUENCY (MHz)N O R M A L I Z E D G A I N (d B )-3-110-2-4-623-70.11101001000SMALL-SIGNAL FREQUENCYRESPONSE-5FREQUENCY (MHz)N O R M A L I Z E D G A I N (d B )-3-110-2-4-623-70.11101001000LARGE-SIGNAL FREQUENCYRESPONSE-5FREQUENCY (MHz)N O R M A L I Z E D G A I N (d B )-3-110-2-4-623-70.11101001000MEDIUM-SIGNAL FREQUENCYRESPONSE-5FREQUENCY (MHz)N O R M A L I Z E D G A I N (d B )-3-110-2-4-623-70.11101001000SMALL-SIGNAL FREQUENCYRESPONSE-5FREQUENCY (MHz)N O R M A L I Z E D G A I N (d B )-3-110-2-4-620.3-0.70.11101001000LARGE-SIGNAL GAIN FLATNESS-0.5FREQUENCY (MHz)N O R M A L I Z E D G A I N (d B )-0.3-0.10.10-0.2-0.4-0.60.20.3-0.70.11101001000LARGE-SIGNAL GAIN FLATNESS-0.5FREQUENCY (MHz)N O R M A L I Z E D G A I N (d B )-0.3-0.10.10-0.2-0.4-0.60.23-70.11101001000LARGE-SIGNAL FREQUENCY RESPONSE(A V = +1V/V)-5FREQUENCY (MHz)N O R M A L I Z E D G A I N (d B )-3-110-2-4-62M A X 4356with On-Screen Display Insertion and I/O Buffers Typical Operating Characteristics—Dual Supplies ±3V (continued)(V CC = +3V and V EE = -3V, V DD = +3V, AGND = DGND = 0, V IN_= 0, R L = 150Ωto AGND, and T A = +25°C, unless otherwise noted.)3-70.11101001000LARGE-SIGNAL FREQUENCY RESPONSE(A V = +2V/V)-5FREQUENCY (MHz)N O R M A L I Z E D G A I N (d B )-3-110-2-4-628-80.11101001000MEDIUM-SIGNAL FREQUENCY RESPONSE(A V = +1V/V)FREQUENCY (MHz)N O R M A L I Z E D G A I N (d B )-2240-4-666-40.11101001000MEDIUM-SIGNAL FREQUENCY RESPONSE(AV = +2V/V)-2FREQUENCY (MHz)N O R M A L I Z E D G A I N (d B )02431-1-35-40-901k1M 10M 100M 1G CROSSTALK VS. FREQUENCY-80FREQUENCY (Hz)C R O S S T A L K (d B )-70-60-50-55-65-75-85-45-30-800.11101001000CROSSTALK VS. FREQUENCY-70FREQUENCY (MHz)C R O S S T A L K (d B )-60-50-40-45-55-65-75-35-10-1000.1100101DISTORTION VS. FREQUENCY-70-90-30-500-60-80-20-40FREQUENCY (MHz)D I S T O R T I O N (d B c )-10-1000.1100M10M 1M DISTORTION VS. FREQUENCY-70-90-30-500-60-80-20-40FREQUENCY (Hz)C R O S S T A L K (d B c )0.11011001000ENABLED OUTPUT IMPEDANCEVS. FREQUENCYM A X 4356 t o c 58FREQUENCY (MHz)O U T P U T I M P E D A N C E (Ω)10000.11101001M 10.11010011000DISABLED OUTPUT IMPEDANCEVS. FREQUENCYM A X 4356 t o c 59FREQUENCY (MHz)O U T P U T I M P E D A N C E (Ω)101001k 10k 100kMAX4356with On-Screen Display Insertion and I/O BuffersTypical Operating Characteristics—Dual Supplies ±3V (continued)(V CC = +3V and V EE = -3V, V DD = +3V, AGND = DGND = 0, V IN_= 0, R L = 150Ωto AGND, and T A = +25°C, unless otherwise noted.)-40-50-60-70-80-90-100-110-120100k10M 100M1M1GOFF ISOLATION VS. FREQUENCYA X 4356 t o c 60FREQUENCY (Hz)O F F I S O L A T I O N (d B )-50-7510k100k10M100MPOWER-SUPPLY REJECTION RATIOVS. FREQUENCY-70-65-55M A X 4356 t o c 61FREQUENCY (Hz)P S R R (d B )1M 1000101010k100k1M1001k10MINPUT VOLTAGE NOISE vs. FREQUENCY100M A X 4356 t o c 62FREQUENCY (Hz)V O L T A G E N O IS E (n V /H z)LARGE-SIGNAL PULSE RESPONSE(A V = +1V/V)MAX4356 toc63OUTPUT 0.5V/div INPUT 1V/div 25ns/divLARGE-SIGNAL PULSE RESPONSE(AV = +2V/V)MAX4356 toc64OUTPUT 0.5V/div INPUT 0.5V/div 25ns/div MEDIUM-SIGNAL PULSE RESPONSE(A V = +1V/V)MAX4356 toc65OUTPUT 50mV/divINPUT 100mV/div25ns/div MEDIUM-SIGNAL PULSE RESPONSE(A V = +2V/V)MAX4356 toc66OUTPUT 50mV/div INPUT 50mV/div 25ns/div SWITCHING TIME (A V = +1V/V)MAX4356 toc67V OUT 500mV/div V UPDATE 3V/div 20ns/div SWITCHING TIME (A V = +2V/V)MAX4356 toc68V OUT 1V/divV UPDATE 3V/div20ns/divM A X 4356with On-Screen Display Insertion and I/O Buffers Typical Operating Characteristics—Dual Supplies ±3V (continued)(V CC = +3V and V EE = -3V, V DD = +3V, AGND = DGND = 0, V IN_= 0, R L = 150Ωto AGND, and T A = +25°C, unless otherwise noted.)SWITCHING TRANSIENT (GLITCH)MAX4356 toc69(A V = +1V/V)V OUT 25mV/div V UPDATE3V/div 20ns/divSWITCHING TRANSIENT (GLITCH)MAX4356 toc70(A V = +2V/V)V OUT 25mV/divV 3V/div20ns/div500150100250200300-15-11-9-7-13-5-3-1135OFFSET VOLTAGE DISTRIBUTIONOFFSET VOLTAGE (mV)0.050-0.050.150.100.200.050-0.050.150.100.200.25103040502060708090100DIFFERENTIAL GAIN AND PHASE(R L = 150Ω)M A X 4356 t o c 72IRED I F FE R E N T I A L G A I N (%)D I F FE R E N T I A L P H A S E (°)0.020-0.020.060.040.08103040502060708090100DIFFERENTIAL GAIN AND PHASE(R L = 1k Ω)M A X 4356t o c 73IRED I F FE R E N TI A L G A I N (%)D I F F ER E N T I A L P H A S E (°)0.0150.02000.0100.0050.010LARGE-SIGNAL PULSE RESPONSEWITH CAPACITIVE LOAD(C L = 30pF, A V = +1V/V)MAX4356 toc74OUTPUT 500mV/divINPUT 1V/div25ns/divLARGE-SIGNAL PULSE RESPONSEWITH CAPACITIVE LOAD (C L = 30pF, A V = + 2V/V)MAX4356 toc75OUTPUT 0.5V/div INPUT 0.5V/div25ns/divMEDIUM-SIGNAL PULSE RESPONSEWITH CAPACITIVE LOAD (C L = 30pF, A V = + 1V/V)MAX4356 toc76OUTPUT 50mV/div 100mV/div25ns/div MEDIUM-SIGNAL PULSE RESPONSEWITH CAPACITIVE LOAD (C L = 30pF, A V = + 2V/V)MAX4356 toc77OUTPUT 50mV/divINPUT 50mV/div25ns/divMAX4356with On-Screen Display Insertion and I/O BuffersTypical Operating Characteristics—Dual Supplies ±3V (continued)(V CC = +3V and V EE = -3V, V DD = +3V, AGND = DGND = 0, V IN_= 0, R L = 150Ωto AGND, and T A = +25°C, unless otherwise noted.)-50-25255075100GAIN VS. TEMPERATURETEMPERATURE (°C)N O R M A L I Z E D G A I N (d B )-0.20-0.15-0.05-0.100.100.150.050.2001p 10n 1µ100p 10p 1n 100n 10µ100µ10n10µ1µ100n 100µ1m 10m 100m 101RESET DELAY vs. C R E S E T D E L A Y (s )C (F)OSD SWITCHING TRANSIENT (100IRE LEVEL SWITCH)V OUT0500mV/divV OSDKEY03V/div50ns/div100IRE0IREOSD SWITCHING 3.58MHz SIGNALMAX4356 toc81V OUT0500mV/divV OSDKEY03V/div50ns/divA V = + 2V/V3-7100k 1M 10M 100M 1G LARGE-SIGNAL FREQUENCY RESPONSE-5FREQUENCY (Hz)N O R M A L I Z E D G A I N (d B )-3-110-2-4-62M A X 4356with On-Screen Display Insertion and I/O Buffers Typical Operating Characteristics—Single Supply +5V(V CC = +5V and V EE = 0, V DD = +5V, AGND = DGND = 0, V IN_= 0, R L = 150Ωto AGND, A V = +1V/V, and T A = +25°C, unless oth-erwise noted.)3-70.11101001000LARGE-SIGNAL FREQUENCY RESPONSE-5FREQUENCY (MHz)N O R M A L I Z E D G A I N (d B )-3-110-2-4-623-70.11101001000MEDIUM-SIGNAL FREQUENCY RESPONSE-5FREQUENCY (MHz)N O R M A L I Z E D G A I N (d B )-3-110-2-4-623-70.11101001000SMALL-SIGNAL FREQUENCY RESPONSE-5FREQUENCY (MHz)N O R M A L I Z E D G A I N (d B )-3-110-2-4-623-7100k 1M 10M 100M 1GMEDIUM-SIGNAL FREQUENCY RESPONSE-5FREQUENCY (Hz)N O R M A L I Z E D G A I N (d B )-3-110-2-4-623-7100k 1M 10M 100M 1GSMALL-SIGNAL FREQUENCY RESPONSE-5FREQUENCY (Hz)N O R M A L I Z E D G A I N (d B )-3-110-2-4-620.3-0.70.11101001000LARGE-SIGNAL GAIN FLATNESS-0.5FREQUENCY (MHz)N O R M A L I Z E D G A I N (d B )-0.3-0.10.10-0.2-0.4-0.60.20.3-0.70.11101001000LARGE-SIGNAL GAIN FLATNESS-0.5FREQUENCY (MHz)N O R M A L I Z E D G A I N (d B )-0.3-0.10.10-0.2-0.4-0.60.23-70.11101001000LARGE-SIGNAL FREQUENCY RESPONSE-5FREQUENCY (MHz)N O R M A L I Z E D G A I N (d B )-3-110-2-4-62MAX4356with On-Screen Display Insertion and I/O BuffersTypical Operating Characteristics—Single Supply +5V (continued)(V CC = +5V and V EE = 0, V DD = +5V, AGND = DGND = 0, V IN_= 0, R L = 150Ωto AGND, A V = +1V/V, and T A = +25°C, unless oth-erwise noted.)7-7100k1M10M 100M1GMEDIUM-SIGNAL FREQUENCY RESPONSEFREQUENCY (Hz)N O R M A L I Z E D G A I N (d B )-113-3-55-50-100100k1M10M100M1GCROSSTALK vs. FREQUENCY-90M A X 4356 t o c 92FREQUENCY (MHz)C R O S S T A L K (d B)-80-70-60-65-75-85-95-550-1000.1110100DISTORTION vs. FREQUENCY-80FREQUENCY (MHz)D I S T O R T I O N (Ω)-60-40-20-30-50-70-90-100.11011001000ENABLED-OUTPUT IMPEDANCEvs. FREQUENCYM A X 4356 t o c 94FREQUENCY (MHz)O U T P U T I M P E D A N C E (Ω)1k 0.11101001M 1100k10M 100M1M1GM A X 4356 t o c 95FREQUENCY (Hz)O U T P U T I M P E D A N C E (Ω)101001k 10k 100k DISABLED-OUTPUT IMPEDANCEvs. FREQUENCY-40-50-60-70-80-90-100-110-120100k10M 100M1M1GM A X 4356 t o c 96FREQUENCY (Hz)O F F I S O L A T I O N(d B )OFF ISOLATION vs. FREQUENCY10k1M 100k10M100MPOWER-SUPPLY REJECTION RATIOvs. FREQUENCYFREQUENCY (Hz)P S R R (d B )-75-70-60-65-55-50100011010k100k1M1001k10MINPUT VOLTAGE NOISE vs. FREQUENCY100M A X 4356 t o c 98FREQUENCY (Hz)V O L T A G E N O I S E (n V / H z )LARGE-SIGNAL PULSE RESPONSEMAX4356 toc9925ns/divINPUT 1V/divOUTPUT 0.5V/divM A X 4356with On-Screen Display Insertion and I/O Buffers Typical Operating Characteristics—Single Supply +5V (continued)(V CC = +5V and V EE = 0, V DD = +5V, AGND = DGND = 0, V IN_= 0, R L = 150Ωto AGND, A V = +1V/V, and T A = +25°C, unless oth-erwise noted.)MEDIUM-SIGNAL PULSE RESPONSEMAX4356 toc10025ns/div INPUT 100mV/divOUTPUT 50mV/divSWITCHING TIMEMAX4356 toc10120ns/divV UPDATE 5V/divV OUT 500mV/divSWITCHING TRANSIENT (GLITCH)MAX4356 toc10220ns/div V UPDATE 5V/divV OUT 25mV/div50150100200250-20-16-14-12-18-10-8-6-4-20OFFSET VOLTAGE HISTOGRAMOFFSET VOLTAGE (mV)-0.101020304050607080901000102030405060708090100DIFFERENTIAL GAIN AND PHASE(R L = 150Ω)0.00.200.100.00-0.100.10.20.300.3IRED I F F P H A SE (°)D I F F G A I N (%)M A X 4356 t o c 104-0.0201020304050607080901000102030405060708090100DIFFERENTIAL GAIN AND PHASE(R L = 1k Ω)0.000.100.000.10-0.200.020.040.200.06IRED I F F P H A SE (°)D I F F G A I N (%)M A X 4356 t o c 105。