DSPIC30F2013AT-20ES-ES中文资料
基于DSPIC的双向DC-DC变换器
基于DSPIC的双向DC-DC变换器
钟卓杰;徐溢豪;王玲娣;金海;沈军民
【期刊名称】《工业控制计算机》
【年(卷),期】2016(0)9
【摘要】设计了一款基于DSPIC的双向DC-DC变换器;该系统处理器选用的是Microchip公司的DSPIC30F4011处理器,采用康铜丝和INA282搭配的方法来实时检测主电路的电流,主控处理器根据反馈输出对应PWM波,通过驱动芯片来控制主电路中的两个MOSFET开关管,实现直流电正向降压和反向升压的目的.实验结果表明,该系统工作稳定,可以达到预期的电流精度控制效果,具有良好的实用性和推广前景.
【总页数】3页(P146-147,150)
【作者】钟卓杰;徐溢豪;王玲娣;金海;沈军民
【作者单位】浙江理工大学信息学院,浙江杭州310018;浙江理工大学信息学院,浙江杭州310018;浙江理工大学信息学院,浙江杭州310018;浙江理工大学信息学院,浙江杭州310018;浙江理工大学信息学院,浙江杭州310018
【正文语种】中文
【相关文献】
1.基于DSPIC30F2020的双向DC/DC变换器的设计 [J], 汪丽燕;阮志煌;谢子鸣;
2.基于DSPIC30F2020的双向DC/DC变换器的设计 [J], 汪丽燕;阮志煌;谢子鸣
3.基于MOSFET的小功率双向变换DC-DC变换器设计 [J], 谢驰;孙幸临;刘影
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刘春松
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dsPIC30F 在无传感器 BLDC 控制中的应用
• 不需要详细了解电机特性。 • 对电机制造容许公差要求不太严格。 • 它对电压控制或电流控制都有效。
过零检测技术适用于速度接近零时不需要闭环操作的多 种应用，它尤其适合在风扇和泵中的应用。
假设速度大于零，则每个电周期中某相的 BEMF 为零的 位置只有两个，可以通过图 2 中所示通过过零点时 BEMF 的斜率来区分这些位置。
以最简单的形式，BEMF 过零检测方法可以这样实现：
• 通过分压器和 A/D 转换器来监测所有三相的端电压 和 VDC。
• 在相应的时间段内检测相 BEMF 何时经过 ½VDC。 对于某个特定的时间段，只需监测一相的电压。
• 使用一个可用的定时器测量 60° （即两次过零点 之间）的时间。将这个值除以 2，然后加载到另一 个定时器中，这样就可以取消正确换相所需的隐含 30°补偿。
所选无传感器技术的实现
具体的实现方法基于检测不通电相的 BEMF 为零时的情 况。除了可选的母线电流检测信号放大以及功率开关门 驱动电路外，采用 dsPIC30F 单芯片实现提供所有的控 制功能。
AN901
选择所谓的 BEMF “过零检测”技术是因为：
• 它适用于多种电机。 • 理论上，Y 型连接和 ∆ 型连接的三相电机都可以使
2004 Microchip Technology Inc.
DS00901A_CN 第 1 页
AN901
BLDC 电机换相的无传感器技术
本文讨论的方法仅适用于标准结构的三相电机（不含搜 索线圈或不对称设计） 。 另外，本文还假定采用常规 120°通电方式，这样在一些时间段会出现某相上电流 为零、不通电的现象。 为使电机运行，必须按照周期性 间隔切换通电的相 （即换相）。
MICROCHIP dsPIC30F 系列概述 dsPIC 高性能 16 位 数字信号控制器 说明书
• 12 位 200 Ksps A/D 转换器模块： - 最多 16 路带有自动扫描功能的输入通道 - 16 字深度的结果缓冲区 - 可手动启动转换或与 3 个触发源中的一个同 步 - 休眠模式下仍可进行转换 - 积分非线性误差最大为 ±1 LSB - 微分非线性误差最大为 ±1 LSB
CMOS 闪存技术：
• 10 位 1 Msps A/D 转换器模块： - 2 或 4 路同步采样 - 最多 16 路带有自动扫描功能的输入通道 - 16 字深度的结果缓冲器 - 可手动启动转换或与 4 个触发源中的一个同 步 - 休眠模式下仍可进行转换 - 积分非线性误差最大为 ±1 LSB - 微分非线性误差最大为 ±1 LSB
125°C）温度范围
dsPIC30F SMPS 闪存编程规范
地址从 0x800000 至 0x8005BE 的存储单元保留用作执 行程序代码存储区。该区域用于存储编程执行程序或调 试执行程序。 编程执行程序用于器件编程，而调试执行 程序用于在线调试。该存储器区域不能用于存储用户代 码。
地址从 0xF80000 至 0xF8000E 的存储单元保留用作配 置寄存器区。 可以设置这些寄存器中的位，以选择各种 器件配置，这将在第 5.7 节 “配置位编程”中进行说 明。 即使应用了代码保护也可正常读出配置位。
图 5-1 高度概括了编程的过程。编程过程从进入增强型 ICSP 模式开始。然后对芯片执行批量擦除操作，将所 有存储区置为 1，以允许对器件进行编程。 在开始编程 前对芯片擦除进行校验， 接下来对代码存储区、数据闪
存和配置位进行编程。在对这些存储区进行编程后要逐
一校验以确保编程成功。 如果未检测到任何错误，将完
7FFFFE 800000
8005BE 8005C0 8005FE 800600
保留
配置存储 空间
配置寄存器 （8 x 16 位）
保留
器件 ID （2 x 16 位）
保留
注： 用户闪存代码存储区的地址边界因器件而异。
F7FFFE F80000 F8000E F80010
FEFFFE FF0000 FF0002 FF0004 FFFFFE
2.2 编程时使用的引脚
表 2-2 中列出了编程时需要用到的引脚。请参见相应器 件的数据手册，以了解完整的引脚说明。
2.3 程序存储器映射
程序存储空间从 0x000000 延伸到 0xFFFFFE。代码存 储在该存储器映射的最低地址部分，支持最多 12 KB （4K 指令字）。表 2-1 给出了每个器件型号程序存储空 间的位置和容量。
dsPIC30F器件实现BLDC电机控制入门
GS001引言由于直流无刷（BLDC）电机可降低能耗及维护成本，因此在对效率和可靠性要求较高的应用场合BLDC电机正重新受到关注。
在大量应用中，dsPIC30F电机控制芯片是多种类型BLDC电机的理想驱动和控制器件。
Microchip已经开发了许多基于dsPIC30F和BLDC电机的解决方案。
本文档将帮助用户为BLDC电机应用选择最佳的解决方案。
BLDC电机基本知识直流有刷电机中的永磁体安装在定子上而电机绕组则安装在转子上。
在旋转过程中，绕组中的电流通过机械碳刷和转子上的换向器进行换向。
BLDC电机的永磁体安装在转子上而电绕组则安装在定子上。
BLDC电机的突出优点在于消除了机械换向器和碳刷，这将极大增强机械可靠性。
直流电机中的换向器和碳刷会导致火花，因此这些部件的消除意味着BLDC电机可以工作在恶劣的环境中。
由于BLDC电机绕组铜耗 I2R 发生在定子中，因此可方便通过电机机壳进行散热。
BLDC电机的效率从而得到极大的提升。
然而，与普通直流电机相比BLDC电机控制较为复杂。
首先，需在电机绕组中建立一个旋转的电枢磁场。
该电枢磁场方向必须根据转子永磁磁场位置进行调整。
BLDC电机的效率很大程度上取决于两个磁场的相对位置关系。
通常使用霍尔位置传感器来检测转子磁场位置。
根据来自霍尔传感器的信号正确对绕组进行激励。
不过当转子速度升高时，由于绕组电感的作用，电压激励与其在绕组中产生的电流效应之间存在一定程度的延迟。
为克服该延迟，通常将电压激励提前一些。
这种现象称为相位超前，主要在高转速时通过软件实现。
采用相位超前技术可改善BLDC电机运行的效率。
有位置传感器的BLDC电机控制当对BLDC电机进行驱动时，必须知道相对于定子的转子磁场位置。
最常见的方法是通过霍尔效应传感器来产生转子位置反馈信号。
此类型控制称为有传感器BLDC 电机控制。
大多数BLDC电机具有三相绕组。
根据转子磁场的位置，每一个时刻只对其中两相绕组进行供电。
基于dsPIC30F3010的无刷直流电动机控制系统设计
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dsPIC30F系列
dsPIC30F系列数字信号控制器（DSC）dsPIC30F系列DSC采用程序存储器和数据存储器完全分离的哈佛体系结构：1、CPU结构概述：dsPIC30F的CPU拥有24位指令字。
程序计数器PC为24位宽，最低有效位总是0，除一些特殊指令外，在程序的正常执行中总是忽略其最高有效位，因此程序计数器PC可以寻址4M×24位的用户程序存储器空间。
工作寄存器阵列由16个16位的寄存器构成。
每个工作寄存器都可以充当数据、地址或地址偏移寄存器。
第16个工作寄存器（W15）作为软件堆栈的指针工作，用于中断服务程序和子程序的调用。
dsPIC30F指令集有两类指令：MCU类指令和DSP类指令。
这两类指令无缝地集成到架构中并从同一个执行单元执行。
指令集包括很多寻址模式。
CPU支持固有（无操作数）寻址、相对寻址、立即数寻址、存储器直接寻址、寄存器直接寻址和寄存器间接寻址模式。
每条指令最多支持6种寻址模式。
CPU中包含一个DSP引擎，如图2-2所示，它具备一个高速17位×17位乘法器、一个40位ALU、两个40位饱和累加器和一个40位双向桶形移位寄存器。
该桶形移位寄存器在单个周期内至多可将一个40位的值右移15位或左移16位。
DSP指令可以无缝地与所有其他指令一起操作，其设计可实现最佳的实时性能。
MAC指令和其他相关指令可以同时从存储器中取出两个数据操作数并将两个W寄存器相乘。
这要求数据空间对于这些指令拆分为两块，但对所有其他指令保持线性。
这是通过为每个地址空间指定某些工作寄存器，以透明和灵活的方式实现的。
CPU不支持多级指令流水线，而是利用单级指令预取机制，它在指令执行的前一个周期存取并解码部分指令，以便使可利用的执行时间达到最长。
单周期指令预取机制用来帮助维持吞吐量并提供可预测的执行。
除了改变程序流的指令、双字移动（MOV.D）指令和表指令以外，所有指令都在单个周期内执行。
使用DO和REPEAT 指令支持无开销的程序循环结构，这两个指令在任何时候都可被中断。
基于dsPIC30F3013的永磁同步电动机正弦驱动
效应传感器来获得转子位置信息。这三个位置传感 器沿定 子 圆周 分布 ， 每 个 电周 期 内产 生 六个 不 同 在 的逻辑状态。电周期和机械转速之间的比率关系取 决于 电机极对数， 本文中的电机 ５ 对极 ， 因此电机每
转一周 需经 历 ５个 电周期 。对 于常规 的 电压激励 方
脉宽调制模块 ， Ｄ Ｐ 由 Ｓ 提供所需的快速数学运算。
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用dsPIC30F3010实现无刷直流电动机正弦波驱动
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中 图分 类 号
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Ｍ匣 ＮＧ Ｓ ｈ ａ ｎ ＬＡＮＧ Ｂａ ｏ ｈ ｕ ａ
（ Ｓ ｃ ｈ ｏ ｏ ｌ ｏ ｆ Ｅｌ ｅ ｃ ｔ ｒ ｏ ｎ ｉ ｃ Ｉ ｎ ｆ ｏ ｒ ｍａ ｔ ｉ ｏ ｎ Ｅｎｇ ｉ ｎ ｅ ｅ ｒ ｉ ｎ ｇ，Ｘｉ ’ ａ ｎ Ｔｅ ｃ ｈ ｎ ｏ ｌ ｏ ｇ ｉ ｃ ａ ｌ Ｕｎ ｉ ｖ ｅ ｒ ｓ ｉ ｔ ｙ，Ｘｉ ’ ａ ｎ ７ １ ０ ０ ２１ ）
好 的调 速 功 能 ， 又具 备 换 向 的特 点 。 无 刷 直 流 电 机 按 照 驱
实际磁通去逼近基准磁 通 ， 由此决 定逆变 器 中电子器件 的 开关状态 ， 进而产生 Ｐ ＷＭ 波 。同 Ｓ Ｐ ＷＭ 比较 Ｓ ＶＰ ＷＭ 具 有使 电机 转 矩 脉 动 小 、 噪声低、 直 流 电 压 利 用 率 高 的优 势＿ 】 。而且 Ｓ ＶＰ ＷＭ 更适合于数字化控制系统 ， 所 以本文 采用 Ｓ ＶＰ ＷＭ 实现无刷直 流电机 的正 弦波驱动 。 本文使用空间矢量 脉宽调 制［ ７ Ｊ （ Ｓ ｐ ａ ｃ ｅ Ｖｅ ｃ ｔ ｏ ｒ Ｍｏ ｄ ｕ ｌ ａ — ｔ ｉ ｏ ｎ ， Ｓ ＶＭ） 方法来驱动 Ｂ Ｌ Ｄ Ｃ， 此调制方法的实现要 由以下 几个模块 组成 ： 基于 ｄ ｓ Ｐ Ｉ Ｃ ３ ０ Ｆ ３ ０ １ ０外 围硬件 电路 的设计 ， 驱动 电路 及 逆 变 电路 的设 计 ， 依 照 软件 框 图 在 ＭＰ Ｌ ＡＢ Ｉ Ｄ Ｅ ｖ ８ ． ９开发环境下 ， 采 用 Ｃ语 言 与汇编语 言编写 系统 的 主程序与 中断子程序＿ １ ］ 。
使用dsPIC30F DSC 实现PMSM 电机的正弦驱动
图 3：
0 A相 60
梯形波反电动势
120 180 240 300 0 60
B相
C相
根据需要，可使能或禁止其他设置或在应用中对其进行 修改。
背景知识
由于具有体积小、控制方便和高效率的特点，许多消费 者和工业应用都所采用 BLDC 电机。BLDC 电机愈来愈 多地出现在汽车应用中以取代传动带和液压系统，这样 可进一步增强功能和降低油耗。在高性能应用中，如机 床设备和低噪声风机应用中，平稳的转矩输出是至关重 要的。 由于采用非正弦分布的定子绕组，使得 BLDC 电机难以 应用在需要低转矩脉动和低噪声运行的场合。 如图 3 所 示，具有非正弦绕组分布的 BLDC 电机将产生梯形波的 反电动势。具有梯形波反电动势的 BLDC 电机专门设计 为采用与电机转子角位置同步的方波电压进行驱动。这 种控制方式通常称为六拍换相。 这里假定读者已充分了解六拍换相技术方面的知识，本 应用笔记将不再对该控制方式作进一步介绍。然而，有 关如何通过六拍换相控制 BLDC 电机的详细信息，可参 阅 Microchip 的其他应用笔记： • AN857 “Brushless DC Motor Control Made （DS00857） Easy ” • AN957 《使用 dsPIC30F2010 控制带传感器的 BLDC 电机》 （DS00957A_CN）
应用特性
• 使用空间矢量调制 （Space Vector Modulation， SVM）方法产生用于驱动 PMSM 电机各相的正弦 电流 • 正弦电压与 PMSM 电机转子位置同步 • 四象限运行，可实现正向、反向和制动运行 • 基于数字比例－积分－微分 （Proportional Integral Derivative， PID）控制的闭环转速控制 • 相位超前技术可实现更宽的调速范围 • 由 dsPIC® DSC 的 DSP 引擎实现小数数学运算
dsPIC30F 器件配置(第二部分 70271a_cn
U — bit 16
中间字节：
U
U
U
U
U
U
U
U
—
—
—
—
—
—
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bit 15
bit 8
低字节：
R/P
R/P
R/P
U-0
FCKSM<1:0>
FRANGE
—
bit 7
U-0
R/P
R/P
R/P
— OSCIOFNC POSCMD<1:0>
bit 0
bit 23-8 bit 7-6
bit 5
未实现：读为 0
FCKSM<1:0>：时钟切换和监视器选择配置位 1x = 禁止时钟切换；禁止故障保护时钟监视器 01 = 使能时钟切换；禁止故障保护时钟监视器 00 = 使能时钟切换；使能故障保护时钟监视器
dsPIC30F 系列参考手册
寄存器 33-6： 高字节：
U — bit 23
FPOR：上电复位配置寄存器
U
U
U
—
—
—
U
U
U
—
—
—
U — bit 16
中间字节：
U
U
U
U
U
U
U
U
—
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—
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bit 15
bit 8
低字节：
U
U
U
U
U
R/P
R/P
R/P
—
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FPWRT<2:0>
bit 7
bit 0
Microchip dsPIC30F 系列参考手册说明书
6Section 6. InterruptsHIGHLIGHTSThis section of the manual contains the following topics:6.1Introduction....................................................................................................................6-26.2Non-Maskable Traps......................................................................................................6-66.3Interrupt Processing Timing.........................................................................................6-116.4Interrupt Control and Status Registers.........................................................................6-146.5Interrupt Setup Procedures..........................................................................................6-426.6Register Map................................................................................................................6-436.7Design Tips..................................................................................................................6-446.8Related Application Notes............................................................................................6-456.9Revision History...........................................................................................................6-46dsPIC30F Family Reference Manual6.1IntroductionThe dsPIC30F interrupt controller module reduces the numerous peripheral interrupt requestsignals to a single interrupt request signal to the dsPIC30F CPU and has the following features:•Up to 8 processor exceptions and software traps•7 user selectable priority levels•Interrupt Vector Table (IVT) with up to 62 vectors• A unique vector for each interrupt or exception source•Fixed priority within a specified user priority level•Alternate Interrupt Vector Table (AIVT) for debug support•Fixed interrupt entry and return latencies6.1.1Interrupt Vector TableThe Interrupt Vector Table (IVT) is shown in Figure6-1. The IVT resides in program memory,starting at location 0x000004. The IVT contains 62 vectors consisting of 8 non-maskable trapvectors plus up to 54 sources of interrupt. In general, each interrupt source has its own vector.Each interrupt vector contains a 24-bit wide address. The value programmed into each interruptvector location is the starting address of the associated Interrupt Service Routine (ISR).6.1.2Alternate Vector TableThe Alternate Interrupt Vector Table (AIVT) is located after the IVT as shown in Figure6-1.Access to the AIVT is provided by the ALTIVT control bit (INTCON2<15>). If the ALTIVT bit isset, all interrupt and exception processes will use the alternate vectors instead of the defaultvectors. The alternate vectors are organized in the same manner as the default vectors.The AIVT supports emulation and debugging efforts by providing a means to switch betweenan application and a support environment without requiring the interrupt vectors to bereprogrammed. This feature also enables switching between applications for evaluation ofdifferent software algorithms at run-time. If the AIVT is not needed, the AIVT should beprogrammed with the same addresses used in the IVT.6.1.3Reset SequenceA device Reset is not a true exception because the interrupt controller is not involved in the Resetprocess. The dsPIC30F device clears its registers in response to a Reset which forces the PC tozero. The processor then begins program execution at location 0x000000. The user programsa GOTO instruction at the Reset address which redirects program execution to the appropriatestart-up routine.Note:Any unimplemented or unused vector locations in the IVT and AIVT should beprogrammed with the address of a default interrupt handler routine that contains aRESET instruction.Section 6. Interrupts 6Figure 6-1:Interrupt Vector TableTable 6-1:Trap Vector Details D e c r e a s i n g N a t u r a l O r d e r P r i o r i t y 0x0000000x000014Reserved Address Error Trap Vector Stack Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0Interrupt Vector 1———Interrupt Vector 52Interrupt Vector 53Arithmetic Error Trap Vector Oscillator Fail Trap Vector ReservedInterrupt Vector 0Interrupt Vector 1———Interrupt Vector 52Interrupt Vector 53IVTAIVT 0x0000800x00007E 0x0000FEReserved Reserved Address Error Trap Vector Stack Error Trap Vector ReservedReservedArithmetic Error Trap Vector Oscillator Fail Trap Vector 0x000094Reset – GOTO Instruction Reset – GOTO Address 0x000002Reserved 0x0000820x0000840x000004See Table 6-2Vector details.for Interrupt VectorNumberIVT Address AIVT Address Trap Source0x0000040x000084Reserved 10x0000060x000086Oscillator Failure 20x0000080x000088Address Error 30x00000A 0x00008A Stack Error 40x00000C 0x00008C Arithmetic Error 50x00000E 0x00008E Reserved 60x0000100x000090Reserved 70x0000120x000092ReserveddsPIC30F Family Reference ManualTable 6-2:Interrupt Vector DetailsVectorIVT Address AIVT Address Interrupt SourceNumber80x0000140x000094INT0 – External Interrupt 090x0000160x000096IC1 – Input Compare 1100x0000180x000098OC1 – Output Compare 1110x00001A0x00009A T1 – Timer 1120x00001C0x00009C IC2 – Input Capture 2130x00001E0x00009E OC2 – Output Compare 2140x0000200x0000A0T2 – Timer 2150x0000220x0000A2T3 – Timer 3160x0000240x0000A4SPI1170x0000260x0000A6U1RX – UART1 Receiver180x0000280x0000A8U1TX – UART1 Transmitter190x00002A0x0000AA ADC – ADC Convert Done200x00002C0x0000AC NVM – NVM Write Complete210x00002E0x0000AE I2C™ Slave Operation – MessageDetect220x0000300x0000B0I2C Master Operation – MessageEvent Complete230x0000320x0000B2Change Notice Interrupt240x0000340x0000B4INT1 – External Interrupt 1250x0000360x0000B6IC7 – Input Capture 7260x0000380x0000B8IC8 – Input Capture 8270x00003A0x0000BA OC3 – Output Compare 3280x00003C0x0000BC OC4 – Output Compare 4290x00003E0x0000BE T4 – Timer 4300x0000400x0000C0T5 – Timer 5310x0000420x0000C2INT2 – External Interrupt 2320x0000440x0000C4U2RX – UART2 Receiver330x0000460x0000C6U2TX – UART2 Transmitter340x0000480x0000C8SPI2350x00004A0x0000CA CAN1360x00004C0x0000CC IC3 – Input Capture 3370x00004E0x0000CE IC4 – Input Capture 4380x0000500x0000D0IC5 – Input Capture 5390x0000520x0000D2IC6 – Input Capture 6400x0000540x0000D4OC5 – Output Compare 5410x0000560x0000D6OC6 – Output Compare 6420x0000580x0000D8OC7 – Output Compare 7430x00005A0x0000DA OC8 – Output Compare 8440x00005C0x0000DC INT3 – External Interrupt 3450x00005E0x0000DE INT4 – External Interrupt 4460x0000600x0000E0CAN2470x0000620x0000E2PWM – PWM Period Match480x0000640x0000E4QEI – Position Counter Compare490x0000660x0000E6DCI – Codec Transfer Done500x0000680x0000E8LVD – Low Voltage Detect510x00006A0x0000EA FLTA – MCPWM Fault A520x00006C0x0000EC FLTB – MCPWM Fault B53-610x00006E-0x00007E0x00006E-0x00007E ReservedSection 6. Interrupts6 6.1.4CPU Priority StatusThe CPU can operate at one the of sixteen priority levels, 0-15. An interrupt or trap source musthave a priority level greater than the current CPU priority in order to initiate an exception process.Peripheral and external interrupt sources can be programmed for level 0-7, while CPU prioritylevels 8-15 are reserved for trap sources. A trap is a non-maskable interrupt source intended todetect hardware and software problems (see Section 6.2 “Non-Maskable Traps”). The prioritylevel for each trap source is fixed and only one trap is assigned to a priority level. Note that aninterrupt source programmed to priority level 0 is effectively disabled, since it can never begreater than the CPU priority.The current CPU priority level is indicated by the following four status bits:•IPL<2:0> status bits located in SR<7:5>•IPL3 status bit located in CORCON<3>The IPL<2:0> status bits are readable and writable, so the user may modify these bits to disableall sources of interrupts below a given priority level. If IPL<2:0> = 3, for example, the CPU willnot be interrupted by any source with a programmed priority level of 0, 1, 2 or 3.Trap events have higher priority than any user interrupt source. When the IPL3 bit is set, a trapevent is in progress. The IPL3 bit can be cleared, but not set by the user. In some applications,it may be desirable to clear the IPL3 bit when a trap has occurred and branch to an instructionother than the instruction after the one that originally caused the trap to occur.All user interrupt sources can be disabled by setting IPL<2:0> = 111.Note:The IPL<2:0> bits become read only bits when interrupt nesting is disabled. SeeSection 6.2.4.2 “Interrupt Nesting” for more information.6.1.5Interrupt PriorityEach peripheral interrupt source can be assigned to one of the seven priority levels. The userassignable interrupt priority control bits for each individual interrupt are located in the LeastSignificant 3 bits of each nibble within the IPCx register(s). Bit 3 of each nibble is not used andis read as a ‘0’. These bits define the priority level assigned to a particular interrupt. The usablepriority levels start at ‘1’ as the lowest priority and level 7 as the highest priority. If the IPC bitsassociated with an interrupt source are all cleared, then the interrupt source is effectivelydisabled.Note:If the application program reconfigures the interrupt priority levels on the fly, it mustdisable the interrupts while doing so. Failure to disable interrupts can produceunexpected results.Since more than one interrupt request source may be assigned to a specific priority level, anoption is provided to resolve priority conflicts within a given user-assigned level. Each source ofinterrupt has a natural order priority based on its location in the IVT. Table6-2 shows the locationof each interrupt source in the IVT. The lower numbered interrupt vectors have higher naturalpriority, while the higher numbered vectors have lower natural priority. The overall priority levelfor any pending source of interrupt is determined first by the user-assigned priority of that sourcein the IPCx register, then by the natural order priority within the IVT.Natural order priority is used only to resolve conflicts between simultaneous pending interruptswith the same user-assigned priority level. Once the priority conflict is resolved and the exceptionprocess begins, the CPU can only be interrupted by a source with a higher user-assigned priority.Interrupts with the same user-assigned priority but a higher natural order priority, that becomepending after the exception process begins, will remain pending until the current exceptionprocess completes.The ability for the user to assign each interrupt source to one of seven priority levels means thatthe user can give an interrupt with a low natural order priority a very high overall priority level. Forexample: the PLVD (Programmable Low Voltage Detect) can be given a priority of 7 and the INT0(External Interrupt 0) may be assigned to priority level 1, thus giving it a very low effective priority.Note:The peripherals and sources of interrupt available in the IVT will vary depending onthe specific dsPIC30F device. The sources of interrupt shown in this documentrepresent a comprehensive listing of all interrupt sources found on dsPIC30Fdevices. Refer to the specific device data sheet for further details.dsPIC30F Family Reference Manual6.2Non-Maskable TrapsTraps can be considered as non-maskable, nestable interrupts which adhere to a fixed prioritystructure. Traps are intended to provide the user a means to correct erroneous operation duringdebug and when operating within the application. If the user does not intend to take correctiveaction in the event of a trap error condition, these vectors must be loaded with the address of asoftware routine that will reset the device. Otherwise, the trap vector is programmed with theaddress of a service routine that will correct the trap condition.The dsPIC30F has the four implemented sources of non-maskable traps listed below:•Oscillator Failure Trap•Stack Error Trap•Address Error Trap•Arithmetic Error TrapNote that many of these trap conditions can only be detected when they happen. Consequently,the instruction that caused the trap is allowed to complete before exception processing begins.Therefore, the user may have to correct the action of the instruction that caused the trap.Each trap source has a fixed priority as defined by its position in the IVT. An oscillator failure traphas the highest priority, while an arithmetic error trap has the lowest priority (see Figure6-1). Inaddition, trap sources are classified into two distinct categories: ‘Hard’ traps and ‘Soft’ traps. 6.2.1Soft TrapsThe arithmetic error trap (priority level 11) and stack error trap (priority level 12) are categorizedas ‘soft’ trap sources. Soft traps can be treated like non-maskable sources of interrupt thatadhere to the priority assigned by their position in the IVT. Soft traps are processed like interruptsand require 2 cycles to be sampled and Acknowledged prior to exception processing. Therefore,additional instructions may be executed before a soft trap is Acknowledged.6.2.1.1Stack Error Trap (Soft Trap, Level 12)The stack is initialized to 0x0800 during Reset. A stack error trap will be generated should thestack pointer address ever be less than 0x0800.There is a Stack Limit register (SPLIM) associated with the stack pointer that is uninitialized atReset. The stack overflow check is not enabled until a word write to SPLIM occurs.All Effective Addresses (EA) generated using W15 as a source or destination pointer arecompared against the value in SPLIM. Should the EA be greater than the contents of the SPLIMregister, then a stack error trap is generated. In addition, a stack error trap will be generatedshould the EA calculation wrap over the end of data space (0xFFFF).A stack error can be detected in software by polling the STKERR status bit (INTCON1<2>). Toavoid re-entering the Trap Service Routine, the STKERR status flag must be cleared in softwareprior to returning from the trap with a RETFIE instruction.Section 6. Interrupts6 6.2.1.2Arithmetic Error Trap (Soft Trap, Level 11)Any of the following events will cause an arithmetic error trap to be generated:•Accumulator A Overflow•Accumulator B Overflow•Catastrophic Accumulator Overflow•Divide by Zero•Shift Accumulator (SFTAC) operation exceeding +/-16 bitsThere are three enable bits in the INTCON1 register that enable the three types of accumulatoroverflow traps. The OVATE control bit (INTCON1<10>) is used to enable traps for anAccumulator A overflow event. The OVBTE control bit (INTCON1<9>) is used to enable traps foran Accumulator B overflow event. The COVTE control bit (INTCON1<8>) is used to enable trapsfor a catastrophic overflow of either accumulator.An Accumulator A or Accumulator B overflow event is defined as a carry-out from bit 31. Notethat no accumulator overflow can occur if the 31-bit Saturation mode is enabled for theaccumulator. A catastrophic accumulator overflow is defined as a carry-out from bit 39 of eitheraccumulator. No catastrophic overflow can occur if accumulator saturation (31-bit or 39-bit) isenabled.Divide-by-zero traps cannot be disabled. The divide-by-zero check is performed during the firstiteration of the REPEAT loop that executes the divide instruction.Accumulator shift traps cannot be disabled. The SFTAC instruction can be used to shift theaccumulator by a literal value or a value in one of the W registers. If the shift value exceeds+/-16bits, an arithmetic trap will be generated. The SFTAC instruction will execute, but the resultsof the shift will not be written to the target accumulator.An arithmetic error trap can be detected in software by polling the MATHERR status bit(INTCON1<4>). To avoid re-entering the Trap Service Routine, the MATHERR status flag mustbe cleared in software prior to returning from the trap with a RETFIE instruction. Before theMATHERR status bit can be cleared, all conditions that caused the trap to occur must also becleared. If the trap was due to an accumulator overflow, the OA and OB status bits (SR<15:14>)must be cleared. The OA and OB status bits are read only, so the user software must perform adummy operation on the overflowed accumulator (such as adding ‘0’) that will cause thehardware to clear the OA or OB status bit.6.2.2Hard TrapsHard traps include exceptions of priority level 13 through level 15, inclusive. The address error(level13) and oscillator error (level 14) traps fall into this category.Like soft traps, hard traps can also be viewed as non-maskable sources of interrupt. Thedifference between hard traps and soft traps is that hard traps force the CPU to stop codeexecution after the instruction causing the trap has completed. Normal program execution flowwill not resume until after the trap has been Acknowledged and processed.6.2.2.1Trap Priority and Hard Trap ConflictsIf a higher priority trap occurs while any lower priority trap is in progress, processing of the lowerpriority trap will be suspended and the higher priority trap will be Acknowledged and processed.The lower priority trap will remain pending until processing of the higher priority trap completes.Each hard trap that occurs must be Acknowledged before code execution of any type maycontinue. If a lower priority hard trap occurs while a higher priority trap is pending, Acknowledged,or is being processed, a hard trap conflict will occur. The conflict occurs because the lowerpriority trap cannot be Acknowledged until processing for the higher priority trap completes.The device is automatically reset in a hard trap conflict condition. The TRAPR status bit(RCON<15>) is set when the Reset occurs, so that the condition may be detected in software.dsPIC30F Family Reference Manual6.2.2.2Oscillator Failure Trap (Hard Trap, Level 14)An oscillator failure trap event will be generated for any of the following reasons:•The Fail-Safe Clock Monitor (FSCM) is enabled and has detected a loss of the systemclock source.• A loss of PLL lock has been detected during normal operation using the PLL.•The FSCM is enabled and the PLL fails to achieve lock at a Power-On Reset (POR).An oscillator failure trap event can be detected in software by polling the OSCFAIL status bit(INTCON1<1>), or the CF status bit (OSCCON<3>). To avoid re-entering the Trap ServiceRoutine, the OSCFAIL status flag must be cleared in software prior to returning from the trap witha RETFIE instruction.For more information about the FSCM, refer to Section 7.“Oscillator” and Section24.“Device Configuration”.6.2.2.3Address Error Trap (Hard Trap, Level 13)The following paragraphs describe operating scenarios that would cause an address error trapto be generated:1. A misaligned data word fetch is attempted. This condition occurs when an instructionperforms a word access with the LSb of the effective address set to ‘1’. The dsPIC30FCPU requires all word accesses to be aligned to an even address boundary.2. A bit manipulation instruction using the Indirect Addressing mode with the LSb of theeffective address set to ‘1’.3. A data fetch from unimplemented data address space is attempted.4.Execution of a “BRA #litera l” instruction or a “GOTO #literal” instruction, whereliteral is an unimplemented program memory address.5.Executing instructions after modifying the PC to point to unimplemented program memoryaddresses. The PC may be modified by loading a value into the stack and executing aRETURN instruction.Data space writes will be inhibited whenever an address error trap occurs, so that data is notdestroyed.An address error can be detected in software by polling the ADDRERR status bit (INTCON1<3>).To avoid re-entering the Trap Service Routine, the ADDRERR status flag must be cleared insoftware prior to returning from the trap with a RETFIE instruction.Note:In the MAC class of instructions, the data space is split into X and Y spaces. In theseinstructions, unimplemented X space includes all of Y space, and unimplemented Yspace includes all of X space.6.2.3Disable Interrupts InstructionThe DISI (disable interrupts) instruction has the ability to disable interrupts for up to 16384instruction cycles. This instruction is useful when time critical code segments must be executed.The DISI instruction only disables interrupts with priority levels 1-6. Priority level 7 interrupts andall trap events still have the ability to interrupt the CPU when the DISI instruction is active.The DISI instruction works in conjunction with the DISICNT register. When the DISICNT registeris non-zero, priority level 1-6 interrupts are disabled. The DISICNT register is decremented oneach subsequent instruction cycle. When the DISICNT register counts down to ‘0’, prioritylevel1-6 interrupts will be re-enabled. The value specified in the DISI instruction includes allcycles due to PSV accesses, instruction stalls, etc.The DISICNT register is readable and writable. The user can terminate the effect of a previousDISI instruction early by clearing the DISICNT register. The amount of time that interrupts aredisabled can also be increased by writing to or adding to DISICNT.Section 6. Interrupts 6Note that if the DISICNT register is zero, interrupts cannot be disabled by writing a non-zero value to the register. Interrupts must first be disabled by using the DISI instruction. Once the DISI instruction has executed and DISICNT holds a non-zero value, the interrupt disable time can be extended by modifying the contents of DISICNT.The DISI status bit (INTCON2<14>) is set whenever interrupts are disabled as a result of the DISI instruction.6.2.4Interrupt OperationAll interrupt event flags are sampled during each instruction cycle. A pending Interrupt Request (IRQ) is indicated by the flag bit being equal to a ‘1’ in an IFSx register. The IRQ will cause an interrupt to occur if the corresponding bit in the Interrupt Enable (IECx) registers is set. For the rest of the instruction cycle in which the IRQ is sampled, the priorities of all pending interrupt requests are evaluated.No instruction will be aborted when the CPU responds to the IRQ. The instruction that was in progress when the IRQ is sampled will be completed before the ISR is executed.If there is a pending IRQ with a user-assigned priority level greater than the current processor priority level, indicated by the IPL<2:0> status bits (SR<7:5>), an interrupt will be presented to the processor. The processor then saves the following information on the software stack:•the current PC value•the low byte of the Processor Status register (SRL)•the IPL3 status bit (CORCON<3>)These three values that are saved on the stack allow the return PC address value, MCU status bits, and the current processor priority level to be automatically saved.After the above information is saved on the stack, the CPU writes the priority level of the pending interrupt into the IPL<2:0> bit locations. This action will disable all interrupts of less than, or equal priority, until the Interrupt Service Routine (ISR) is terminated using the RETFIE instruction. Figure 6-2:Stack Operation for Interrupt Event 6.2.4.1Return from InterruptThe RETFIE (Return from Interrupt) instruction will unstack the PC return address, IPL3 status bit and SRL register to return the processor to the state and priority level prior to the interrupt sequence.Note:Software modification of the DISICNT register is not recommended.Note:The DISI instruction can be used to quickly disable all user interrupt sources if nosource is assigned to CPU priority level 7.<Free Word>PC<15:0>PC<22:16>015W15 (before IRQ)W15 (after IRQ)S t a c k G r o w s T o w a r d s H i g h e r A d d r e s s SR<7:0>This stack location used to store the IPL3 status bit (CORCON<3>).dsPIC30F Family Reference Manual6.2.4.2Interrupt NestingInterrupts, by default, are nestable. Any ISR that is in progress may be interrupted by anothersource of interrupt with a higher user-assigned priority level. Interrupt nesting may be optionallydisabled by setting the NSTDIS control bit (INTCON1<15>). When the NSTDIS control bit is set,all interrupts in progress will force the CPU priority to level 7 by setting IPL<2:0> = 111. Thisaction will effectively mask all other sources of interrupt until a RETFIE instruction is executed.When interrupt nesting is disabled, the user-assigned interrupt priority levels will have no effect,except to resolve conflicts between simultaneous pending interrupts.The IPL<2:0> bits become read only when interrupt nesting is disabled. This prevents the usersoftware from setting IPL<2:0> to a lower value, which would effectively re-enable interruptnesting.6.2.5Wake-up from Sleep and IdleAny source of interrupt that is individually enabled, using its corresponding control bit in the IECxregisters, can wake-up the processor from Sleep or Idle mode. When the interrupt status flag fora source is set and the interrupt source is enabled via the corresponding bit in the IEC Controlregisters, a wake-up signal is sent to the dsPIC30F CPU. When the device wakes from Sleep orIdle mode, one of the following actions may occur:1.If the interrupt priority level for that source is greater than the current CPU priority level,then the processor will process the interrupt and branch to the ISR for the interrupt source.2.If the user-assigned interrupt priority level for the source is less than or equal the currentCPU priority level, then the processor will simply continue execution, starting with theinstruction immediately following the PWRSAV instruction that previously put the CPU inSleep or Idle mode.Note:User interrupt sources that are assigned to CPU priority level 0 cannot wake theCPU from Sleep or Idle mode, because the interrupt source is effectively disabled.To use an interrupt as a wake-up source, the CPU priority level for the interrupt mustbe assigned to CPU priority level 1 or greater.6.2.6A/D Converter External Conversion RequestThe INT0 external interrupt request pin is shared with the A/D converter as an externalconversion request signal. The INT0 interrupt source has programmable edge polarity, which isalso available to the A/D converter external conversion request feature.6.2.7External Interrupt SupportThe dsPIC30F supports up to 5 external interrupt pin sources (INT0-INT4). Each externalinterrupt pin has edge detection circuitry to detect the interrupt event. The INTCON2 register hasfive control bits (INT0EP-INT4EP) that select the polarity of the edge detection circuitry. Eachexternal interrupt pin may be programmed to interrupt the CPU on a rising edge or falling edgeevent. See Register6-4 for further details.。
微芯片 dsPIC30F 音频回声消除库文档说明书
DS70148B-14dsPIC30FAcoustic Echo Cancellation LibraryDevices SupporteddsPIC30F6014dsPIC30F6014A dsPIC30F6012dsPIC30F6012AdsPIC30F5013 (for a max. of 32 ms echo delay)dsPIC30F5011 (for a max. of 32 ms echo delay)SummaryThe dsPIC30F Acoustic Echo Cancellation (AEC) Library provides a function to eliminate echo generated in the acoustic path between a speaker and a microphone. This function is useful for speech and telephony applications in which a speaker and a microphone are located in close proximity to each other and are susceptible to signals propagating from the speaker to the microphone resulting in a perceptible and distracting echo effect at the far-end. It is especially suitable for these applications:• Hands-free cell phone kits • Speakerphones • Intercoms• Teleconferencing systemsFor hands-free phones intended to be used in compact environments, such as a car cabin, this library is fully compliant with the G.167 standard for acoustic echo cancellation.The AEC Library is written entirely in assembly language and is highly optimized to make extensive use of the dsPIC30F DSP instruction set and advanced addressing modes. The algorithm avoids data overflow. The AEC Library provides an “AcousticEchoCancellerInit ” function for initializing the various data structures required by the algorithm and an “AcousticEchoCanceller ” function to remove the echo component from a 10 ms block of sampled 16-bit speech data. The user can easily call both functions through a well-documented Application Programmer’s Interface (API).The “AcousticEchoCanceller ” function is primarily a Time Domain algorithm. The received far-end speech samples (typically received across a communication channel such as a telephone line) are filtered using an adaptive Finite Impulse Response (FIR) filter. The coefficients of this filter are adapted using the Normalized Least Mean Square (NLMS) algorithm, such that the filter closely models the acoustic path between the near-end speaker and the near-end microphone (i.e., the path traversed by the echo). Voice Activity Detection (VAD) and Double Talk Detection (DTD) algorithms are used to avoid updating the filter coefficients when there is no far-end speech and also when there is simultaneous speech from both ends of the communication link (double talk). As a consequence, the algorithm functions correctly even in the presence of full-duplex communication. A Non-Linear Processor (NLP) algorithm is used to eliminate residual echo.The dsPIC30F Acoustic Echo Cancellation Library uses an 8 kHz sampling rate. However, the library includes a sample rate conversion function that ensures interoperability with libraries designed for higher sampling rates (9.6 kHz, 11.025 kHz or 12 kHz). The conversion function allows incoming signals at higher sampling rates to be converted to a representative 8 kHz sample. Similarly, the conversion function allows the output signal to be converted upward from 8 kHz to match the user application.FeaturesKey features of the Acoustic Echo Cancellation Librar include:• All functions can be called from either a C or assembly applicationprogram• Five user functions:– AcousticEchoCancellerInit – AcousticEchoCanceller – InitRateConverter – SRC_upConvert – SRC_downConvert• Full compliance with the Microchip MPLAB® C30 C Compiler,assembler and linker• Simple user interface – one library file and one header file• Highly optimized assembly code, utilizing DSP instructions andadvanced addressing modes• Echo cancellation for 16, 32 or 64 ms echo delays or ‘tail lengths’(configurable)• Fully tested for compliance with G.167 specifications for in-carapplications• Audio bandwidth: 0-4 kHz at 8 kHz sampling rate• Convergence rate: Up to 43 dB/sec., typically > 30 dB/sec.• Echo cancellation: Up to 50 dB, typically > 40 dB• Can be used together with the Noise Suppression (NS) Library, sincethe same processing block size (10 ms) is used• dsPIC30F Acoustic Echo Cancellation Library User’s Guide is included • Demo application source code is provided with the library• Accessory Kit available for purchase includes an audio cable,headset, oscillators, microphone, speaker, DB9 M/F RS-232 cable, DB9M-DB9M null modem adapter and can be used for library evaluation64 16.5 6 5.7 32 10.5 6 3.4 16 7.5 6 2.6Sample Rate ConversionComputational requirements: 1 MIPS Program Flash memory: 2.6 KB RAM: 0.5 KBNote: The user application might require an additional 2 to 2.5 KB of RAM for data buffering (application-dependent)。
dsPIC30F闪存编程规范
dsPIC30F1.0概述与适用范围本文档定义了dsPIC30F系列数字信号控制器（Digital Signal Controller，DSC）的编程规范。
本编程规范仅供使用第三方工具对dsPIC30F器件进行编程的开发人员使用。
使用dsPIC30F器件的客户应该采用支持器件编程的开发工具。
本文档包括下列器件的编程规范：• dsPIC30F2010、 2011和 2012• dsPIC30F3010、 3011、 3012、 3013和3014• dsPIC30F4011、 4012和 4013• dsPIC30F5011、5013、 5015和 5016• dsPIC30F6010、 6011、 6012、 6013、 6014和6015• dsPIC30F6010A、6011A、 6012A、 6013A和6014A2.0dsPIC30F的编程概述dsPIC30F系列DSC包含一块用于简化器件编程的片上存储区域。
这部分存储区用于存储编程执行程序，编程执行程序使得能够以比传统方法更快的速度对dsPIC30F 器件编程。
一旦外部编程器（如Microchip的MPLAB®ICD 2、 MPLAB® PM3 或 PRO MATE® II）将编程执行程序存储到该存储区，编程执行程序就能与外部编程器配合工作来对器件高效编程。
编程器和编程执行程序存在一种主从关系，其中编程器是主编程设备，而编程执行程序则处于从动地位，如图2-1所示。
可使用两种方法对用户系统中的芯片编程。
一种方法是使用增强型在线串行编程（In-Circuit Serial Programming TM，ICSP TM）协议，并使用编程执行程序。
另一种方法是仅使用在线串行编程（ICSP™）协议，不使用编程执行程序。
增强型ICSP协议采用速度更快的高电压编程法，这个编程方法利用了编程执行程序。
编程执行程序通过一个小的命令集提供擦除、编程和校验芯片所必需的所有功能。
MICROCHIP AN984 使用 dsPIC30F MCU 控制交流感应电机 说明书
罩极电机具有由层叠铁片构成的磁极结构。在该结构中 放置了一个线圈。通过在两个关键位置将短路环环绕在 磁极叠片上可以产生 “旋转”磁场。短路环使磁通分布 不均，从而产生旋转磁场。
您可能已注意到我说的是“交流电流”而不是“交流电 压”。我们将使用在 dsPIC® MCU 上电机控制 PWM 来 控制逆变器电路中的功率晶体管。如果将示波器探头放 在三相连接中的某相连接上，将会看到幅值大约与直流 母线电压相等的 PWM 信号。由于电机绕组是感性的， 输入电压将被积分产生与 PWM 占空比成比例的电机电 流。调制 PWM 占空比，即可产生任意波形的交流电流。
第二种分相电机有两个绕组、一个离心式开关和一个与 起动绕组串联的电容。这个电容提供相移从而增大了起 动转矩并减小了起动电流。当电机接近全速后，离心式 开关断开起动绕组 （和电容） 。这类电机通常被称为 “电容起动”电机。
第三类分相电机省去了离心式开关，但是仍有一个电容 与副绕组串联。由于没有离心式开关，因此副绕组从不 会断开。这类分相电机通常被称为 “电容运转”电机， 在所有类型的分相电机中性能最佳。电容运转电机在运 行 速 度 范 围 之 内 有 最 佳 的 转 矩。在 所 有 类 型 的 单 相 ACIM 中，电容运转电机是进行变速控制的最佳选择。
您可能想知道调制频率的分辨率。要确定此分辨率，需 要知道调节正弦表指针的频率。现在，假定每个 PWM 周期调节一次。假定 PWM 频率为 16 kHz，调制频率分 辨率将是：
公式 2： 调制频率分辨率
= fPWM/216 = 0.244 Hz/ 位
L2-CPU结构
dsPIC30F---结构
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dsPIC30F结构
dsPIC30F 器件的每个都可划分为以下三个部分： – 1. CPU 内核 – 2. 系统集成 – 3. 外设 CPU 内核 • CPU 内核是器件运行所必需的基本部分。包括： 1. CPU
2. 数据存储器
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指令集
– 指令集有两类指令ቤተ መጻሕፍቲ ባይዱMCU 类指令和DSP 类指令。 – 这两类指令无缝地集成到架构中并从同一个执行单元执行。
– 指令集包括很多寻址模式，指令的设置可使C 编译器的效率达到
最优。
单级指令预取机制
内核不支持多级指令流水线。
使用了单级指令预取机制，在指令执行的前一个周期取指令并部 分译码指令。 除了一些特例外，大部分指令都在单个周期内执行。
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根据所使用的指令模式，ALU 可以执行8 位或16 位操作。根据指令的寻址模式，ALU
操作的数据可以来自W 寄存器阵列或数据存储器，输出数据可以被写入W 寄存器阵列 或数据存储单元。
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dsPIC30F 有两条指令有助于混合8 位和16 位ALU 操作。
– 符号扩展（SE）指令获取W 寄存器或数据存储器的一个字节值并创建存储在W 寄
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7、DSP 引擎
DSP 引擎由一个高速17 位x 17 位乘法器、一个桶形移位寄存器和一个40 位加法器/ 减 法器（两个目标累加器、舍入逻辑和饱和逻辑）组成。
dsPIC30F 器件采用单周期指令流，可以执行DSP 指令或MCU 指令。许多硬件资源可以被 DSP 和MCU 指令共用。
基于dsPIC30F的交错并联Buck变换器研究
基于dsPIC30F的交错并联Buck变换器研究周香;刘闯;左月飞【摘要】针对高速永磁发电系统对功率变换器宽输入范围、高功率密度、高效率等要求,设计并研制了与之匹配的交错并联Buck变换器.分析了交错并联Buck变换器的工作原理,提出了采用专用电源和电机数字控制芯片dsPIC30F2023实现逐周期限流控制的方案,解决了并联变换器的均流问题.实验结果表明,变换器具有较好的输入、输出性能,系统的安全性、可靠性以及集成性等得到提升,满足设计要求.【期刊名称】《电源技术》【年(卷),期】2016(040)001【总页数】3页(P192-194)【关键词】高速永磁发电系统;交错并联;dsPIC30F;均流;逐周期限流控制【作者】周香;刘闯;左月飞【作者单位】南京航空航天大学自动化学院,江苏南京210016;南京航空航天大学自动化学院,江苏南京210016;南京航空航天大学自动化学院,江苏南京210016【正文语种】中文【中图分类】TM313高速永磁发电机因其功率密度高、噪音小、动态响应较快等优点而被广泛应用，但永磁同步发电机从外部调节磁场变化极为困难，导致不能直接调节电压。
为使高速永磁发电系统输出28.5 V恒定直流电压，需要设计与之匹配的功率变换器，满足宽输入电压范围、高功率密度、高效率、高可靠性等要求[1]。
近年来随着变换器功率等级增大及复杂程度提高，交错并联技术得到了快速的发展。
在相同输出条件下，交错并联技术在各支路中进行合理的热损耗分配，提高系统可靠性，提高变换器的功率等级，降低变换器中开关管的应力，提高效率，减小输出纹波[2]。
针对高速永磁发电系统对功率变换器的性能要求及技术指标要求，本文选用交错并联Buck变换器。
目前，交错并联式变换器控制多采用模拟芯片 (如UC3842、UCC28070)实现，电路设计复杂、通用性不好、功能不易扩展。
本文采用数字控制芯片dsPIC30F2023实现交错并联Buck变换器的数字控制，硬件电路的设计，提高了抗干扰能力，可实现开关电源智能化。
dsPIC30F语音编码 解码库简介说明书
dsPIC30FEncoding/Decoding Library SummaryThe dsPIC30F Speech Encoding/Decoding Library performstoll-quality voice compression and voice decompression. Thelibrary is a modified version of the Speex speech coder madespecifically for the dsPIC30F family of Digital Signal Controllers(DSCs) and features a 16:1 compression ratio. Encoding usesCode Excited Linear Prediction (CELP), which is a popular codingtechnique. CELP provides a reasonable trade-off betweenperformance and computational complexity.The library is appropriate for half-duplex systems and with itssmall footprint, it is also ideal for playback-only applicationsincluding:•Answering machines•Building and home safety systems•Intercoms•Smart appliances•Voice recorders•Walkie-talkies•Any application using message playbackPredominantly written in assembly language, the Speech Encoding/Decoding Library optimizes computational performance and minimizes RAM usage. A well-defined API makes it easy to integrate with the application.A flexible analog interface gives your design several options to consider. The speech encoder samples speech at 8 kHz using either an external codec or the on-chip 12-bit analog-to-digital converter. The speech decoder plays decoded speech through an external codec or the on-chip Pulse Width Modulator (PWM). Storing compressed speech for playback requires approximately1 Kbyte of memory for each second of speech.A PC-based Speech Encoder Utility program (pictured above) creates encoded speech files for playback. Encoded speech files are made from either a PC microphone or existing WAV file. Once the encoded speech files are created, they are added to an MPLAB® C30 project, just like a regular source file, and built into the application.The Speech Encoder Utility allows four target memory areasto store a speech file: program memory, data EEPROM, RAM and external flash memory. External flash memory stored many minutes of speech (1 minute of speech requires 60 KB) and it is supported through a dsPIC30F general purpose I/O port. FeaturesKey features of the Speech Encoding/Decoding Library include:•Fixed 8 kHz sample rate•Fixed 8 kbps output rate•PESQ-based Mean Opinion Score: 3.7 – 4.2 (out of 5.0)•Code Excited Linear Prediction (CELP)-based coding •Two analog input interfaces – codec or on-chip 12-bit ADC •Two analog output interfaces – codec or on-chip PWM •Optional voice activity detection•Playback-only applications benefit from the Speech Encoder utility; encoded speech files can be created from the desktop using a PC microphone or WAV file•Storing compressed speech requires 1 KB of memory per second of speech•Off-chip support for playback of long speech samples •Royalty free (only one-time license fee)•Full compliance with Microchip MPLAB® C30 Language Tools•dsPIC30F Speech Encoding/Decoding Library User’s Guide assists in using the library (DS70154)•Designed to run on dsPICDEM™ 1.1 General PurposeDevelopment Board (DM300014)Resource RequirementsEncoder:Sampling Interface: Si-3000 Audio Codec or 12-bit ADC Computational Power: 19 MIPS (worst case)Program Flash Memory: 33 KBRAM*: 5.4 KB (1.2 KB is scratch)* Full-duplex support is now possible and requires 6.8 KB of RAM Decoder•Playback Interface: Si-3000audio codec or PWM•Computational Power: 3 MIPS•Program Flash Memory: 15 KB•RAM*: 3.2 KBDS70148B-17。
微芯,DSPIC30F系列,规格书,Datasheet 资料
© 2010 Microchip Technology Inc.DS70102K-page1dsPIC30F1.0OVERVIEW AND SCOPEThis document defines the programming specification for the dsPIC30F family of Digital Signal Controllers (DSCs). The programming specification is required only for the developers of third-party tools that are used to program dsPIC30F devices. Customers using dsPIC30F devices should use development tools that already provide support for device programming.This document includes programming specifications for the following devices:•dsPIC30F2010/2011/2012•dsPIC30F3010/3011/3012/3013/ 3014•dsPIC30F4011/4012/4013•dsPIC30F5011/5013/5015/5016•dsPIC30F6010/6011/6012/6013/6014/6015•dsPIC30F6010A/6011A/6012A/6013A/6014A2.0PROGRAMMING OVERVIEW OF THE dsPIC30FThe dsPIC30F family of DSCs contains a region of on-chip memory used to simplify device programming. This region of memory can store a programming executive, which allows the dsPIC30F to be programmed faster than the traditional means. Once the programming executive is stored to memory by an external programmer (such as Microchip’s MPLAB ®ICD 2, MPLAB PM3, PRO MATE ® II, or MPLAB REAL ICE™), it can then interact with the external programmer to efficiently program devices.The programmer and programming executive have a master-slave relationship, where the programmer is the master programming device and the programming executive is the slave, as illustrated in Figure 2-1.FIGURE 2-1:OVERVIEW OF dsPIC30F PROGRAMMINGTwo different methods are used to program the chip in the user’s system. One method uses the Enhanced In-Circuit Serial Programming™ (Enhanced ICSP™) protocol and works with the programming executive. The other method uses In-Circuit Serial Programming (ICSP) protocol and does not use the programming executive.The Enhanced ICSP protocol uses the faster, high-voltage method that takes advantage of the programming executive. The programming executive provides all the necessary functionality to erase, program and verify the chip through a small command set. The command set allows the programmer to program the dsPIC30F without having to deal with the low-level programming protocols of the chip.The ICSP programming method does not use the programming executive. It provides native, low-level programming capability to erase, program and verify the chip. This method is significantly slower because it uses control codes to serially execute instructions on the dsPIC30F device.This specification describes the ICSP and Enhanced ICSP programming methods. Section 3.0 “Programming Executive Application” describes the programming executive application and Section 5.0 “Device Programming” describes its application programmer’s interface for the hostprogrammer.Section 11.0 “ICSP™ Mode”describes the ICSP programming method.2.1 Hardware RequirementsIn ICSP or Enhanced ICSP mode, the dsPIC30F requires two programmable power supplies: one for V DD and one for MCLR. For Bulk Erase programming, which is required for erasing code protection bits, V DD must be greater than 4.5 volts. Refer to Section 13.0 “AC/DC Characteristics and Timing Requirements”for additional hardware parameters.Programmer dsPIC30F DeviceProgramming Executive On-chip Memory 2dsPIC30F Flash Programming SpecificationdsPIC30F Flash Programming SpecificationDS70102K-page 2© 2010 Microchip Technology Inc.2.2Pins Used During ProgrammingThe pins identified in Table 2-1 are used for device programming. Refer to the appropriate device data sheet for complete pin descriptions.TABLE 2-1:dsPIC30F PIN DESCRIPTIONS DURING PROGRAMMINGPin Name Pin TypePin Description MCLR/V PP P Programming Enable V DD P Power Supply V SS P Ground PGC I Serial Clock PGDI/OSerial Data2.3Program Memory MapThe program memory space extends from 0x0 to 0xFFFFFE. Code storage is located at the base of the memory map and supports up to 144 Kbytes (48K instruction words). Code is stored in three, 48 Kbyte memory panels that reside on-chip. Table 2-2 shows the location and program memory size of each device.Locations 0x800000 through 0x8005BE are reserved for executive code memory. This region stores either the programming executive or debugging executive. The programming executive is used for device programming, while the debug executive is used for in-circuit debugging. This region of memory cannot be used to store user code.Locations 0xF80000 through 0xF8000E are reserved for the Configuration registers. The bits in these registers may be set to select various device options, and are described in Section 5.7 “Configuration Bits Programming”.Locations 0xFF0000 and 0xFF0002 are reserved for the Device ID registers. These bits can be used by the programmer to identify what device type is being programmed and are described in Section 10.0 “Device ID”. The device ID reads out normally, even after code protection is applied.Figure 2-2 illustrates the memory map for the dsPIC30F devices.2.4Data EEPROM MemoryThe Data EEPROM array supports up to 4 Kbytes of data and is located in one memory panel. It is mapped in program memory space, residing at the end of User Memory Space (see Figure 2-2). Table 2-2 shows the location and size of data EEPROM in each device.TABLE 2-2:CODE MEMORY AND DATA EEPROM MAP AND SIZE DeviceCode Memory map (Size in Instruction Words)Data EEPROM Memory Map(Size in Bytes)dsPIC30F20100x000000-0x001FFE (4K)0x7FFC00-0x7FFFFE (1K)dsPIC30F20110x000000-0x001FFE (4K)None (0K)dsPIC30F20120x000000-0x001FFE (4K)None (0K)dsPIC30F30100x000000-0x003FFE (8K)0x7FFC00-0x7FFFFE (1K)dsPIC30F30110x000000-0x003FFE (8K)0x7FFC00-0x7FFFFE (1K)dsPIC30F30120x000000-0x003FFE (8K)0x7FFC00-0x7FFFFE (1K)dsPIC30F30130x000000-0x003FFE (8K)0x7FFC00-0x7FFFFE (1K)dsPIC30F30140x000000-0x003FFE (8K)0x7FFC00-0x7FFFFE (1K)dsPIC30F40110x000000-0x007FFE (16K)0x7FFC00-0x7FFFFE (1K)dsPIC30F40120x000000-0x007FFE (16K)0x7FFC00-0x7FFFFE (1K)dsPIC30F40130x000000-0x007FFE (16K)0x7FFC00-0x7FFFFE (1K)dsPIC30F50110x000000-0x00AFFE (22K)0x7FFC00-0x7FFFFE (1K)dsPIC30F50130x000000-0x00AFFE (22K)0x7FFC00-0x7FFFFE (1K)dsPIC30F50150x000000-0x00AFFE (22K)0x7FFC00-0x7FFFFE (1K)dsPIC30F50160x000000-0x00AFFE (22K)0x7FFC00-0x7FFFFE (1K)dsPIC30F60100x000000-0x017FFE (48K)0x7FF000-0x7FFFFE (4K)dsPIC30F6010A 0x000000-0x017FFE (48K)0x7FF000-0x7FFFFF (4K)dsPIC30F60110x000000-0x015FFE (44K)0x7FF800-0x7FFFFE (2K)dsPIC30F6011A 0x000000-0x015FFE (44K)0x7FF800-0x7FFFFE (2K)dsPIC30F60120x000000-0x017FFE (48K)0x7FF000-0x7FFFFE (4K)dsPIC30F6012A 0x000000-0x017FFE (48K)0x7FF000-0x7FFFFE (4K)dsPIC30F60130x000000-0x015FFE (44K)0x7FF800-0x7FFFFE (2K)dsPIC30F6013A 0x000000-0x015FFE (44K)0x7FF800-0x7FFFFE (2K)dsPIC30F60140x000000-0x017FFE (48K)0x7FF000-0x7FFFFE (4K)dsPIC30F6014A 0x000000-0x017FFE (48K)0x7FF000-0x7FFFFE (4K)dsPIC30F60150x000000-0x017FFE (48K)0x7FF000-0x7FFFFE (4K)Legend:I = Input, O = Output, P = Power© 2010 Microchip Technology Inc.DS70102K-page 3dsPIC30F Flash Programming SpecificationFIGURE 2-2:PROGRAM MEMORY MAPU s e r M e m o r y S p a c e000000Configuration RegistersUser Flash Code Memory 018000017FFE C o n f i g u r a t i o n M e m o r y S p a c eData EEPROM (48K x 24-bit)(2K x 16-bit)800000F80000(8 x 16-bit)F8000E F80010Device ID FEFFFE FF0000FFFFFEReservedF7FFFE Reserved7FF0007FEFFE 8005BE 8005C0Executive Code Memory7FFFFE ReservedFF0002FF0004Reserved(2 x 16-bit)(Reserved)Note:The address boundaries for user Flash code memory and data EEPROM are device-dependent.Unit ID (32 x 24-bit)8005FE 800600dsPIC30F Flash Programming SpecificationDS70102K-page 4© 2010 Microchip Technology Inc.3.0PROGRAMMING EXECUTIVE APPLICATION3.1Programming Executive OverviewThe programming executive resides in executive memory and is executed when Enhanced ICSP Programming mode is entered. The programming exec-utive provides the mechanism for the programmer (host device) to program and verify the dsPIC30F, using a simple command set and communication protocol.The following capabilities are provided by the programming executive:•Read memory-Code memory and data EEPROM -Configuration registers -Device ID •Erase memory-Bulk Erase by segment -Code memory (by row)-Data EEPROM (by row)•Program memory -Code memory-Data EEPROM-Configuration registers •Query-Blank Device-Programming executive software versionThe programming executive performs the low-level tasks required for erasing and programming. This allows the programmer to program the device by issuing the appropriate commands and data.The programming procedure is outlined in Section 5.0 “Device Programming”.3.2Programming Executive Code MemoryThe programming executive is stored in executive code memory and executes from this reserved region of memory. It requires no resources from user code memory or data EEPROM.3.3Programming Executive Data RAMThe programming executive uses the device’s data RAM for variable storage and program execution. Once the programming executive has run, no assumptions should be made about the contents of data RAM.4.0CONFIRMING THE CONTENTS OF EXECUTIVE MEMORYBefore programming can begin, the programmer must confirm that the programming executive is stored in exec-utive memory. The procedure for this task is illustrated in Figure 4-1.First, ICSP mode is entered. The unique application ID word stored in executive memory is then read. If the programming executive is resident, the application ID word is 0xBB, which means programming can resume as normal. However, if the application ID word is not 0xBB, the programming executive must be programmed to Executive Code memory using the method described in Section 12.0 “Programming the Programming Executive to Memory”.Section 11.0 “ICSP™ Mode” describes the process for the ICSP programming method. Section 11.13 “Reading the Application ID Word” describes the procedure for reading the application ID word in ICSP mode.FIGURE 4-1:CONFIRMING PRESENCE OF THE PROGRAMMING EXECUTIVEIsStartEnter ICSP™ ModeApplication ID0xBB?Resident in MemoryYesNoProg. Executive is Application ID Read the be ProgrammedProg. Executive must from Address 0x8005BEFinishdsPIC30F Flash Programming Specification5.0DEVICE PROGRAMMING5.1Overview of the ProgrammingProcessOnce the programming executive has been verified in memory (or loaded if not present), the dsPIC30F can be programmed using the command set shown in Table 5-1. A detailed description for each command is provided in Section 8.0 “Programming Executive Commands”.TABLE 5-1:COMMAND SET SUMMARY Command DescriptionSCHECK Sanity checkREADD Read data EEPROM, Configurationregisters and device IDREADP Read code memoryPROGD Program one row of data EEPROMand verifyPROGP Program one row of code memory andverifyPROGC Program Configuration bits and verify ERASEB Bulk Erase, or erase by segment ERASED Erase data EEPROMERASEP Erase code memoryQBLANK Query if the code memory and dataEEPROM are blankQVER Query the software versionA high-level overview of the programming process is illustrated in Figure 5-1. The process begins by enter-ing Enhanced ICSP mode. The chip is then bulk erased, which clears all memory to ‘1’ and allows the device to be programmed. The Chip Erase is verified before programming begins. Next, the code memory, data Flash and Configuration bits are programmed. As these memories are programmed, they are each verified to ensure that programming was successful. If no errors are detected, the programming is complete and Enhanced ICSP mode is exited. If any of the verifications fail, the procedure should be repeated, starting from the Chip Erase.If Advanced Security features are enabled, then individual Segment Erase operations need to be performed, based on user selections (i.e., based on the specific needs of the user application). The specific operations that are used typically depend on the order in which various segments need to be programmed for a given application or system.Section 5.2 “Entering Enhanced ICSP Mode”through Section 5.8 “Exiting Enhanced ICSP Mode”describe the programming process in detail.FIGURE 5-1:PROGRAMMING FLOWStartProgram andProgram andProgram and verifyConfiguration bitsFinishverify codeverify dataEnter EnhancedExit Enhanced ICSPModePerform ChipEraseProgramConfigurationregisters toICSP™ modedefault value© 2010 Microchip Technology Inc.DS70102K-page 5dsPIC30F Flash Programming SpecificationDS70102K-page 6© 2010 Microchip Technology Inc.5.2Entering Enhanced ICSP ModeThe Enhanced ICSP mode is entered by holding PGC and PGD high, and then raising MCLR/V PP to V IHH (high voltage), as illustrated in Figure 5-2. In this mode, the code memory, data EEPROM and Configuration bits can be efficiently programmed using the program-ming executive commands that are serially transferred using PGC and PGD.FIGURE 5-2:ENTERING ENHANCED5.3Chip EraseBefore a chip can be programmed, it must be erased. The Bulk Erase command (ERASEB ) is used to perform this task. Executing this command with the MS command field set to 0x3 erases all code memory, data EEPROM and code-protect Configuration bits. The Chip Erase process sets all bits in these three memory regions to ‘1’.Since non-code-protect Configuration bits cannot be erased, they must be manually set to ‘1’ using multiple PROGC commands. One PROGC command must be sent for each Configuration register (see Section 5.7 “Configuration Bits Programming”).If Advanced Security features are enabled, then indi-vidual Segment Erase operations would need to be performed, depending on which segment needs to be programmed at a given stage of system programming. The user should have the flexibility to select specific segments for programming.Note:The Device ID registers cannot be erased. These registers remain intact after a Chip Erase is performed.5.4Blank CheckThe term “Blank Check” means to verify that the device has been successfully erased and has no programmed memory cells. A blank or erased memory cell reads as ‘1’. The following memories must be blank checked: •All implemented code memory •All implemented data EEPROM•All Configuration bits (for their default value)The Device ID registers (0xFF0000:0xFF0002) can be ignored by the Blank Check since this region stores device information that cannot be erased. Additionally, all unimplemented memory space should be ignored from the Blank Check.The QBLANK command is used for the Blank Check. It determines if the code memory and data EEPROM are erased by testing these memory regions. A ‘BLANK’ or ‘NOT BLANK’ response is returned. The READD command is used to read the Configuration registers. If it is determined that the device is not blank, it must be erased (see Section 5.3 “Chip Erase”) before attempting to program the chip.Note 1:The sequence that places the device intoEnhanced ICSP mode places all unused I/Os in the high-impedance state.2:Before entering Enhanced ICSP mode,clock switching must be disabled using ICSP , by programming the FCKSM<1:0> bits in the FOSC Configuration register to ‘11’ or ‘10’.3:When in Enhanced ICSP mode, the SPIoutput pin (SDO1) will toggle while the device is being programmed.dsPIC30F Flash Programming Specification5.5Code Memory Programming5.5.1OVERVIEWThe Flash code memory array consists of 512 rows ofthirty-two, 24-bit instructions. Each panel stores 16Kinstruction words, and each dsPIC30F device haseither 1, 2 or 3 memory panels (see Table 5-2).TABLE 5-2:DEVICE CODE MEMORY SIZEDevice Code Size(24-bitWords)NumberofRowsNumberofPanelsdsPIC30F20104K1281 dsPIC30F20114K1281 dsPIC30F20124K1281 dsPIC30F30108K2561 dsPIC30F30118K2561 dsPIC30F30128K2561 dsPIC30F30138K2561 dsPIC30F30148K2561 dsPIC30F401116K5121 dsPIC30F401216K5121 dsPIC30F401316K5121 dsPIC30F501122K7042 dsPIC30F501322K7042 dsPIC30F501522K7042 dsPIC30F501622K7042 dsPIC30F601048K15363 dsPIC30F6010A48K15363 dsPIC30F601144K14083 dsPIC30F6011A44K14083 dsPIC30F601248K15363 dsPIC30F6012A48K15363 dsPIC30F601344K14083 dsPIC30F6013A44K14083 dsPIC30F601448K15363 dsPIC30F6014A48K15363 dsPIC30F601548K153635.5.2PROGRAMMING METHODOLOGY Code memory is programmed with the PROGP command. PROGP programs one row of code memory to the memory address specified in the command. The number of PROGP commands required to program a device depends on the number of rows that must be programmed in the device.A flowchart for programming of code memory is illus-trated in Figure 5-3. In this example, all 48K instruction words of a dsPIC30F6014A device are programmed. First, the number of commands to send (called ‘RemainingCmds’ in the flowchart) is set to 1536 and the destination address (called ‘BaseAddress’) is set to ‘0’. Next, one row in the device is programmed with a PROGP command. Each PROGP command contains data for one row of code memory of the dsPIC30F6014A. After the first command is processed successfully, ‘RemainingCmds’ is decremented by 1 and compared to 0. Since there are more PROGP commands to send, ‘BaseAddress’ is incremented by 0x40 to point to the next row of memory.On the second PROGP command, the second row of each memory panel is programmed. This process is repeated until the entire device is programmed. No special handling must be performed when a panel boundary is crossed.FIGURE 5-3:FLOWCHART FORPROGRAMMINGdsPIC30F6014A CODEMEMORYIsPROGP responsePASS?IsRemainingCmds0?BaseAddress = 0x0RemainingCmds = 1536RemainingCmds =RemainingCmds – 1FinishBaseAddress =BaseAddressNoNoYesYes+ 0x40StartFailureReport ErrorSend PROGPCommand to ProgramBaseAddress© 2010 Microchip Technology Inc.DS70102K-page 7dsPIC30F Flash Programming SpecificationDS70102K-page 8© 2010 Microchip Technology Inc.5.5.3PROGRAMMING VERIFICATIONOnce code memory is programmed, the contents of memory can be verified to ensure that programming was successful. Verification requires code memory to be read back and compared against the copy held in the programmer’s buffer.The READP command can be used to read back all the programmed code memory.Alternatively, you can have the programmer perform the verification once the entire device is programmed using a checksum computation, as described in Section 6.8 “Checksum Computation”.5.6Data EEPROM Programming5.6.1OVERVIEWThe panel architecture for the data EEPROM memory array consists of 128 rows of sixteen 16-bit data words. Each panel stores 2K words. All devices have either one or no memory panels. Devices with data EEPROM provide either 512 words, 1024 words or 2048 words of memory on the one panel (see Table 5-3).TABLE 5-3:DATA EEPROM SIZEDevice Data EEPROM Size (Words)Number of RowsdsPIC30F201051232dsPIC30F201100dsPIC30F201200dsPIC30F301051232dsPIC30F301151232dsPIC30F301251232dsPIC30F301351232dsPIC30F301451232dsPIC30F401151232dsPIC30F401251232dsPIC30F401351232dsPIC30F501151232dsPIC30F501351232dsPIC30F501551232dsPIC30F501651232dsPIC30F60102048128dsPIC30F6010A 2048128dsPIC30F6011102464dsPIC30F6011A 102464dsPIC30F60122048128dsPIC30F6012A 2048128dsPIC30F6013102464dsPIC30F6013A 102464dsPIC30F60142048128dsPIC30F6014A 2048128dsPIC30F601520481285.6.2PROGRAMMING METHODOLOGYThe programming executive uses the PROGD command to program the data EEPROM. Figure 5-4 illustrates the flowchart of the process. Firstly, the number of rows to program (RemainingRows) is based on the device size, and the destination address (DestAddress) is set to ‘0’. In this example, 128 rows (2048 words) of data EEPROM will be programmed.The first PROGD command programs the first row of data EEPROM. Once the command completes successfully, ‘RemainingRows’ is decremented by 1 and compared with 0. Since there are 127 more rows to program, ‘BaseAddress’ is incremented by 0x20 to point to the next row of data EEPROM. This process is then repeated until all 128 rows of data EEPROM are programmed.FIGURE 5-4:FLOWCHART FOR PROGRAMMINGdsPIC30F6014A DATA EEPROMIsPROGD responsePASS?IsRemainingRows0?Remaining Rows = 128BaseAddress = 0RemainingRows =RemainingRows – 1FinishBaseAddress =BaseAddress NoNoYes Yes+ 0x20StartSend PROGD Command with BaseAddressFailure Report ErrordsPIC30F Flash Programming Specification5.6.3PROGRAMMING VERIFICATIONOnce the data EEPROM is programmed, the contents of memory can be verified to ensure that the programming was successful. Verification requires the data EEPROM to be read back and compared against the copy held in the programmer’s buffer. The READD command reads back the programmed data EEPROM. Alternatively, the programmer can perform the verification once the entire device is programmed using a checksum computation, as described in Section 6.8 “Checksum Computation”.Note:TBLRDL instructions executed within a REPEAT loop must not be used to readfrom Data EEPROM. Instead, it isrecommended to use PSV access.5.7Configuration Bits Programming5.7.1OVERVIEWThe dsPIC30F has Configuration bits stored in seven 16-bit registers. These bits can be set or cleared to select various device configurations. There are two types of Configuration bits: system-operation bits and code-protect bits. The system-operation bits determine the power-on settings for system-level components such as the oscillator and Watchdog Timer. The code- protect bits prevent program memory from being read and written. The FOSC Configuration register has three different register descriptions, based on the device. The FOSC Configuration register description for the dsPIC30F2010 and dsPIC30F6010/6011/6012/6013/ 6014 devices are shown in Table 5-4.Note:If user software performs an erase opera-tion on the configuration fuse, it must befollowed by a write operation to this fusewith the desired value, even if the desiredvalue is the same as the state of theerased fuse.The FOSC Configuration register description for the dsPIC30F4011/4012 and dsPIC30F5011/5013 devicesis shown in Table 5-5.The FOSC Configuration register description forall remaining devices (dsPIC30F2011/2012, dsPIC30F3010/3011/3012/3013, dsPIC30F3014/ 4013, dsPIC30F5015 and dsPIC30F6011A/6012A/ 6013A/ 6014A) is shown in Table 5-6. Always use the correct register descriptions for your target processor.The FWDT, FBORPOR, FBS, FSS, FGS and FICD Configuration registers are not device-dependent. The register descriptions for these Configuration registersare shown in Table 5-7.The Device Configuration register maps are shown in Table 5-8 through Table 5-11.TABLE 5-4:FOSC CONFIGURATION BITS DESCRIPTION FOR dsPIC30F2010 ANDdsPIC30F6010/6011/6012/6013/6014Bit Field Register DescriptionFCKSM<1:0>FOSC Clock Switching Mode1x =Clock switching is disabled, Fail-Safe Clock Monitor is disabled01 =Clock switching is enabled, Fail-Safe Clock Monitor is disabled00 =Clock switching is enabled, Fail-Safe Clock Monitor is enabledFOS<1:0>FOSC Oscillator Source Selection on POR11 =Primary Oscillator10 =Internal Low-Power RC Oscillator01 =Internal Fast RC Oscillator00 =Low-Power 32 kHz Oscillator (Timer1 Oscillator)FPR<3:0>FOSC Primary Oscillator Mode1111 = ECIO w/PLL 16X – External Clock mode with 16X PLL. OSC2 pin is I/O1110 = ECIO w/PLL 8X – External Clock mode with 8X PLL. OSC2 pin is I/O1101 = ECIO w/PLL 4X – External Clock mode with 4X PLL. OSC2 pin is I/O1100 = ECIO – External Clock mode. OSC2 pin is I/O1011 = EC – External Clock mode. OSC2 pin is system clock output (F OSC/4)1010 = Reserved (do not use)1001 = ERC – External RC Oscillator mode. OSC2 pin is system clock output(F OSC/4)1000 = ERCIO – External RC Oscillator mode. OSC2 pin is I/O0111 = XT w/PLL 16X – XT Crystal Oscillator mode with 16X PLL0110 = XT w/PLL 8X – XT Crystal Oscillator mode with 8X PLL0101 = XT w/PLL 4X – XT Crystal Oscillator mode with 4X PLL0100 = XT – XT Crystal Oscillator mode (4 MHz-10 MHz crystal)001x = HS – HS Crystal Oscillator mode (10 MHz-25 MHz crystal)000x = XTL – XTL Crystal Oscillator mode (200 kHz-4 MHz crystal)© 2010 Microchip Technology Inc.DS70102K-page 9dsPIC30F Flash Programming SpecificationTABLE 5-5:FOSC CONFIGURATION BITS DESCRIPTION FOR dsPIC30F4011/4012 AND dsPIC30F5011/5013Bit Field Register DescriptionFCKSM<1:0>FOSC Clock Switching Mode1x =Clock switching is disabled, Fail-Safe Clock Monitor is disabled01 =Clock switching is enabled, Fail-Safe Clock Monitor is disabled00 =Clock switching is enabled, Fail-Safe Clock Monitor is enabledFOS<1:0>FOSC Oscillator Source Selection on POR11 =Primary Oscillator10 =Internal Low-Power RC Oscillator01 =Internal Fast RC Oscillator00 =Low-Power 32 kHz Oscillator (Timer1 Oscillator)FPR<3:0>FOSC Primary Oscillator Mode1111 =ECIO w/PLL 16X – External Clock mode with 16X PLL. OSC2 pin is I/O1110 =ECIO w/PLL 8X – External Clock mode with 8X PLL. OSC2 pin is I/O1101 =ECIO w/PLL 4X – External Clock mode with 4X PLL. OSC2 pin is I/O1100 =ECIO – External Clock mode. OSC2 pin is I/O1011 =EC – External Clock mode. OSC2 pin is system clock output (F OSC/4)1010 =FRC w/PLL 8x – Internal fast RC oscillator with 8x PLL. OSC2 pin is I/O1001 =ERC – External RC Oscillator mode. OSC2 pin is system clock output(F OSC/4)1000 =ERCIO – External RC Oscillator mode. OSC2 pin is I/O0111 =XT w/PLL 16X – XT Crystal Oscillator mode with 16X PLL0110 =XT w/PLL 8X – XT Crystal Oscillator mode with 8X PLL0101 =XT w/PLL 4X – XT Crystal Oscillator mode with 4X PLL0100=XT – XT Crystal Oscillator mode (4 MHz-10 MHz crystal)0011 =FRC w/PLL 16x – Internal fast RC oscillator with 16x PLL. OSC2 pin is I/O0010=HS – HS Crystal Oscillator mode (10 MHz-25 MHz crystal)0001 =FRC w/PLL 4x – Internal fast RC oscillator with 4x PLL. OSC2 pin is I/O0000=XTL – XTL Crystal Oscillator mode (200 kHz-4 MHz crystal)DS70102K-page 10© 2010 Microchip Technology Inc.dsPIC30F Flash Programming Specification TABLE 5-6:FOSC CONFIGURATION BITS DESCRIPTION FOR dsPIC30F2011/2012,dsPIC30F3010/3011/3012/3013/3014, dsPIC30F4013, dsPIC30F5015/5016,dsPIC30F6010A/6011A/6012A/6013A/6014A AND dsPIC30F6015 Bit Field Register DescriptionFCKSM<1:0>FOSC Clock Switching Mode1x =Clock switching is disabled, Fail-Safe Clock Monitor is disabled01 =Clock switching is enabled, Fail-Safe Clock Monitor is disabled00 =Clock switching is enabled, Fail-Safe Clock Monitor is enabledFOS<2:0>FOSC Oscillator Source Selection on POR111 = Primary Oscillator110 = Reserved101 = Reserved100 = Reserved011 = Reserved010 = Internal Low-Power RC Oscillator001 = Internal Fast RC Oscillator (no PLL)000 = Low-Power 32 kHz Oscillator (Timer1 Oscillator)FPR<4:0>FOSC Primary Oscillator Mode (when FOS<2:0> = 111b)11xxx = Reserved (do not use)10111 = HS/3 w/PLL 16X – HS/3 crystal oscillator with 16X PLL(10 MHz-25 MHz crystal)10110 = HS/3 w/PLL 8X – HS/3 crystal oscillator with 8X PLL(10 MHz-25 MHz crystal)10101 = HS/3 w/PLL 4X – HS/3 crystal oscillator with 4X PLL(10 MHz-25 MHz crystal)10100 = Reserved (do not use)10011 = HS/2 w/PLL 16X – HS/2 crystal oscillator with 16X PLL(10 MHz-25 MHz crystal)10010 = HS/2 w/PLL 8X – HS/2 crystal oscillator with 8X PLL(10 MHz-25 MHz crystal10001 = HS/2 w/PLL 4X – HS/2 crystal oscillator with 4X PLL(10 MHz-25 MHz crystal)10000 = Reserved (do not use)01111 = ECIO w/PLL 16x – External clock with 16x PLL. OSC2 pin is I/O01110 = ECIO w/PLL 8x – External clock with 8x PLL. OSC2 pin is I/O01101 = ECIO w/PLL 4x – External clock with 4x PLL. OSC2 pin is I/O01100 = Reserved (do not use)01011 = Reserved (do not use)01010 = FRC w/PLL 8x – Internal fast RC oscillator with 8x PLL. OSC2 pin is I/O01001 = Reserved (do not use)01000 = Reserved (do not use)00111 = XT w/PLL 16X – XT crystal oscillator with 16X PLL00110 = XT w/PLL 8X – XT crystal oscillator with 8X PLL00101 = XT w/PLL 4X – XT crystal oscillator with 4X PLL00100 = Reserved (do not use)00011 = FRC w/PLL 16x – Internal fast RC oscillator with 8x PLL. OSC2 pin is I/O00010 = Reserved (do not use)00001 = FRC w/PLL 4x – Internal fast RC oscillator with 4x PLL. OSC2 pin is I/O00000 = Reserved (do not use)© 2010 Microchip Technology Inc.DS70102K-page 11。
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dsPIC30F3014, dsPIC30F4013Data SheetHigh-PerformanceDigital Signal Controllers 2004 Microchip Technology Inc.Advance Information DS70138CDS70138C-page iiAdvance Information2004 Microchip Technology Inc.Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications.M ICROCHIP M AKES NO REPRESENTATIONS OR WAR-RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,WRITTEN OR ORAL, STATUTORY OR OTHERWISE,RELATED TO THE INFORM ATION, INCLUDING BUT NOT LIM ITED TO ITS CONDITION, QUALITY , PERFORM ANCE,M ERCHANTABILITY OR FITNESS FOR PURPOSE .Microchip disclaims all liability arising from this information and its use. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by M icrochip. No licenses are conveyed,implicitly or otherwise, under any Microchip intellectual property rights.TrademarksThe Microchip name and logo, the Microchip logo, Accuron, dsPIC, K EE L OQ , micro ID , MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt areregistered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.Analog-for-the-Digital Age, Application Maestro, dsPICDEM, , dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit SerialProgramming, ICSP , ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, , PICLAB, PICtail, PowerCal, PowerInfo, PowerMate,PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.All other trademarks mentioned herein are property of their respective companies.© 2004, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.Printed on recycled paper.Note the following details of the code protection feature on Microchip devices:•Microchip products meet the specification contained in their particular Microchip Data Sheet.•Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.•There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to ourknowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.•Microchip is willing to work with the customer who is concerned about the integrity of their code.•Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes andprocedures are for its PICmicro ® 8-bit MCUs, K EE L OQ ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.2004 Microchip Technology Inc.Advance InformationDS70138C-page 1dsPIC30F3014/4013High-Performance Modified RISC CPU:•Modified Harvard architecture• C compiler optimized instruction set architecture •Flexible addressing modes •84 base instructions•24-bit wide instructions, 16-bit wide data path •Up to 48 Kbytes on-chip Flash program space • 2 Kbytes of on-chip data RAM• 1 Kbyte of non-volatile data EEPROM •16 x 16-bit working register array •Up to 30 MIPs operation:-DC to 40MHz external clock input -4MHz-10MHz oscillator input with PLL active (4x, 8x, 16x)•Up to 33 interrupt sources:-8 user selectable priority levels - 3 external interrupt sources - 4 processor trapsDSP Features:•Dual data fetch•Modulo and Bit-reversed modes•Two 40-bit wide accumulators with optional saturation logic•17-bit x 17-bit single cycle hardware fractional/integer multiplier•All DSP instructins are single cycle-Multiply-Accumulate (MAC) operation •Single cycle ±16 shiftPeripheral Features:•High current sink/source I/O pins: 25mA/25mA •Up to five 16-bit timers/counters; optionally pair up 16-bit timers into 32-bit timer modules •Up to four 16-bit Capture input functions•Up to four 16-bit Compare/PWM output functions •Data Converter Interface (DCI) supports common audio Codec protocols, including I 2S and AC’97•3-wire SPI™ module (supports 4 Frame modes)•I 2C™ module supports Multi-Master/Slave mode and 7-bit/10-bit addressing•Up to two addressable UART modules with FIFO buffers•CAN bus module compliant with CAN 2.0B standardAnalog Features:•12-bit Analog-to-Digital Converter (A/D) with:-100 Ksps conversion rate -Up to 13 input channels-Conversion available during Sleep and Idle •Programmable Low Voltage Detection (PLVD)•Programmable Brown-out Detection and Reset generationSpecial Microcontroller Features:•Enhanced Flash program memory:-10,000 erase/write cycle (min.) forindustrial temperature range, 100K (typical)•Data EEPROM memory:-100,000 erase/write cycle (min.) forindustrial temperature range, 1M (typical)•Self-reprogrammable under software control•Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)•Flexible Watchdog Timer (WDT) with on-chip low power RC oscillator for reliable operation •Fail-Safe Clock Monitor operation:-Detects clock failure and switches to on-chip low power RC oscillatorNote: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU,peripherals, register descriptions and general device functionality, refer to the dsPIC30F Family Reference Manual (DS70046). For more information on the device instruction set and programming, refer to the dsPIC30F Programmer’s Reference Manual (DS70030).dsPIC30F3014/4013 High-PerformanceDigital Signal ControllersdsPIC30F3014/4013DS70138C-page 2Advance Information2004 Microchip Technology Inc.Special Microcontroller Features (Cont.):•Programmable code protection•In-Circuit Serial Programming™ (ICSP™)•Selectable Power Management modes: -Sleep, Idle and Alternate Clock modesCMOS Technology:•Low power, high speed Flash technology •Wide operating voltage range (2.5V to 5.5V)•Industrial and Extended temperature ranges •Low power consumptiondsPIC30F3014/4013 Controller FamilyPin DiagramsDevicePins Program MemorySRAM Bytes EEPROM Bytes Timer 16-bit Input Cap OutputComp/StdPWMCodec Interface A/D 12-bit100 Ksps U A R TS P I ™I 2C ™C A N Bytes Instructions dsPIC30F301440/4424K 8K 20481024322-13 ch 2110dsPIC30F401340/4448K16K20481024544AC’97, I 2S13 ch2111PGD/EMUD/AN7/RB7PGC/EMUC/AN6/OCFA/RB6RF0RF1RD2IC1/INT1/RD8AN8/RB812345678910111213141516171819204039383736353433323130292827262524232221dsPIC30F3014MCLRV DD VssIC2/INT2/RD9EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13OSC2/CLKO/RC15OSC1/CLKIN AN9/RB9AN10/RB10AN11/RB11AN12/RB12EMUD2/OC2/RD1AV DD AVss RD3Vss V DD EMUC3/SCK1/RF6U1RX/SDI1/SDA/RF2EMUD3/U1TX/SDO1/SCL/RF3EMUC2/OC1/RD0V DDU2RX/CN17/RF4U2TX/CN18/RF5AN4/CN6/RB4AN2/SS1/LVDIN/CN4/RB2AN1/V REF -/CN3/RB1AN0/V REF +/CN2/RB0AN5/CN7/RB5INT0/RA11VssAN3/CN5/RB340-Pin PDIP2004 Microchip Technology Inc.Advance InformationDS70138C-page 3dsPIC30F3014/4013Pin Diagrams (Continued)Note:For descriptions of individual pins, see Section 1.0.1011234561181920212212131415388744434241403916172930313233232425262728363435937E M U D 3/U 1T X /S D O 1/S C L /R F 3E M U C 3/S C K 1/R F 6I C 1/N T 1/R D 8R D 2V D D E M U C 1/S O S C O /T 1C K /U 1A R X /C N 0/R C 14N C V S S R D 3I C 2/I N T 2/R D 9I N T 0/R A 11A N 3/C N 5/R B 3A N 2/S S 1/L V D I N /C N 4/R B 2A N 1/V R E F -/C N 3/R B 1A N 0/V R E F +/C N 2/R B 0M C L R N C A V D DA V S S A N 9/RB 9A N 10/R B 10AN12/RB12EMUC2/OC1/RD0EMUD2/OC2/RD1V DDV SS RF0RF1U2RX/CN17/RF4U2TX/CN18/RF5U1RX/SDI1/SDA/RF2AN4/CN6/RB4AN5/CN7/RB5PGC/EMUC/AN6/OCFA/RB6PGD/EMUD/AN7/RB7AN8/RB8NCV DDV SS OSC1/CLKIN OSC2/CLKO/RC15EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13dsPIC30F301444-Pin TQFPAN11/RB11N CdsPIC30F3014/4013DS70138C-page 4Advance Information2004 Microchip Technology Inc.Pin Diagrams (Continued)Note:For descriptions of individual pins, see Section 1.0.44-Pin QFNdsPIC30F3014E M U D 3/U 1T X /S D O 1/S C L /RF 3E M U C 3/S C K 1/R F 6I C 1/I N T 1/R D 8R D 2V D DE M U C 1/S O S C O /T 1C K /U 1A R X /C N 0/R C 14E M U D 1/S O S C I /T 2C K /U 1A T X /C N 1/R C 13V S SR D 3I C 2/I N T 2/R D 9I N T 0/R A 11AN4/CN6/RB4AN5/CN7/RB5PGC/EMUC/AN6/OCFA/RB6PGD/EMUD/AN7/RB7AN8/RB8OSC2/CLKO/RC15V DDV DD V SS V SS OSC1/CLKIN EMUC2/OC1/RD0EMUD2/OC2/RD1V DDV DD V SS RF0RF1U2RX/CN17/RF4U2TX/CN18/RF5U1RX/SDI1/SDA/RF2AN12/RB12A N 3/C N 5/RB 3A N 2/S S 1/L V D I N /C N 4/RB 2A N 1/V R E F -/C N 3/R B 1A N 0/V R E F +/C N 2/R B 0M C L R A N 11/R B 11A VD DA V S SA N 9/RB 9A N 10/R B 10NC 44434241403938373635121314151617181920213302928272625242345789101112323162233342004 Microchip Technology Inc.Advance InformationDS70138C-page 5dsPIC30F3014/4013Pin Diagrams (Continued)Note:For descriptions of individual pins, see Section 1.0.PGD/EMUD/AN7/RB7PGC/EMUC/AN6/OCFA/RB6C1RX/RF0C1TX/RF1OC3/RD2IC1/INT1/RD8AN8/RB812345678910111213141516171819204039383736353433323130292827262524232221dsPIC30F4013MCLRV DD V SSIC2/INT2/RD9EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13OSC2/CLKO/RC15OSC1/CLKIN AN9/CSCK/RB9AN10/CSDI/RB10AN11/CSDO/RB11AN12/COFS/RB12EMUD2/OC2/RD1AV DD AV SSOC4/RD3V SSV DD EMUC3/SCK1/RF6U1RX/SDI1/SDA/RF2EMUD3/U1TX/SDO1/SCL/RF3EMUC2/OC1/RD0V DDU2RX/CN17/RF4U2TX/CN18/RF5AN4/IC7/CN6/RB4AN2/SS1/LVDIN/CN4/RB2AN1/V REF -/CN3/RB1AN0/V REF +/CN2/RB0AN5/IC8/CN7/RB5INT0/RA11V SSAN3/CN5/RB340-Pin PDIP1011234561181920212212131415388744434241403916172930313233232425262728363435937E M U D 3/U 1T X /S D O 1/S C L /R F 3E M U C 3/S C K 1/R F 6I C 1/I N T 1/R D 8O C 3/R D 2V D D E M U C 1/S O S C O /T 1C K /U 1A R X /C N 0/R C 14N C V S S O C 4/R D 3I C 2/I N T 2/R D 9I N T 0/R A 11A N 3/C N 5/R B 3A N 2/S S 1/L V D I N /C N 4/R B 2A N 1/V R E F -/C N 3/R B 1A N 0/V R E F +/C N 2/R B 0M C L R N C A V D DA V S S A N 9/C S C K /RB 9A N 10/C SD I /R B 10AN12/COFS/RB12EMUC2/OC1/RD0EMUD2/OC2/RD1V DDV SS CRX1/RF0CTX1/RF1U2RX/CN17/RF4U2TX/CN18/RF5U1RX/SDI1/SDA/RF2AN4/IC7/CN6/RB4AN5/IC8/CN7/RB5PGC/EMUC/AN6/OCFA/RB6PGD/EMUD/AN7/RB7AN8/RB8NCV DDV SS OSC1/CLKIN OSC2/CLKO/RC15EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13dsPIC30F401344-Pin TQFPAN11/CSDO/RB11N CdsPIC30F3014/4013DS70138C-page 6Advance Information2004 Microchip Technology Inc.Pin Diagrams (Continued)For descriptions of individual pins, see Section 1.0.44-Pin QFN444342414039383736351213141516171819202133029282726252423457891011123231dsPIC30F40136223334E M U D 3/U 1T X /S D O 1/S C L /RF 3E M U C 3/S C K 1/R F 6I C 1/N T 1/R D 8O C 3/R D 2V D DE M U C 1/S O S C O /T 1C K /U 1A R X /C N 0/R C 14E M U D 1/S O S C I /T 2C K /U 1A T X /C N 1/R C 13V S SO C 4/R D 3I C 2/I N T 2/R D 9I N T 0/R A 11AN4/IC7/CN6/RB4AN5/IC8/CN7/RB5PGC/EMUC/AN6/OCFA/RB6PGD/EMUD/AN7/RB7AN8/RB8OSC2/CLKO/RC15V DDV DD V SS V SS OSC1/CLKIN EMUC2/OC1/RD0EMUD2/OC2/RD1V DDV DD V SS CRX1/RF0CTX1/RF1U2RX/CN17/RF4U2TX/CN18/RF5U1RX/SDI1/SDA/RF2AN12/COFS/RB12A N 3/C N 5/RB 3A N 2/S S 1/L V D I N /C N 4/R B 2A N 1/V R E F -/C N 3/R B 1A N 0/V R E F +/C N 2/R B 0M C L R A N 11/C SD O /R B 11A V D DA V S SA N 9/C S C K /RB 9A N 10/C SD I /R B 10N CdsPIC30F3014/4013Table of Contents1.0Device Overview (9)2.0CPU Architecture Overview (13)3.0Memory Organization (23)4.0Address Generator Units (35)5.0Flash Program Memory (41)6.0Data EEPROM Memory (47)7.0I/O Ports (51)8.0Interrupts (55)9.0Timer1 Module (63)10.0Timer2/3 Module (67)11.0Timer4/5 Module (73)12.0Input Capture Module (77)13.0Output Compare Module (81)14.0SPI Module (85)15.0I2C Module (89)16.0Universal Asynchronous Receiver Transmitter (UART) Module (97)17.0CAN Module (105)18.0Data Converter Interface (DCI) Module (115)19.012-bit Analog-to-Digital Converter (A/D) Module (125)20.0System Integration (131)21.0Instruction Set Summary (149)22.0Development Support (157)23.0Electrical Characteristics (163)24.0Packaging Information (205)Index (209)On-Line Support (215)Systems Information and Upgrade Hot Line (215)Reader Response (216)Product Identification System (217)TO OUR VALUED CUSTOMERSIt is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@ or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback.Most Current Data SheetTo obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).ErrataAn errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.To determine if an errata sheet exists for a particular device, please check with one of the following:•Microchip’s Worldwide Web site; •Your local Microchip sales office (see last page)When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using.Customer Notification SystemRegister on our web site at to receive the most current information on all of our products.2004 Microchip Technology Inc.Advance Information DS70138C-page 7dsPIC30F3014/4013NOTES:DS70138C-page 8Advance Information 2004 Microchip Technology Inc.1.0DEVICE OVERVIEWThis document contains specific information for the dsPIC30F3014/4013 Digital Signal Controller (DSC)devices. The dsPIC30F3014/4013 devices contain extensive Digital Signal Processor (DSP) functionality within a high-performance 16-bit microcontroller (MCU)architecture. Figure 1-1 and Figure 1-2 show device block diagrams for dsPIC30F3014 and dsPIC30F4013respectively.FIGURE 1-1:dsPIC30F3014 BLOCK DIAGRAMNote: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU,peripherals, register descriptions and general device functionality, refer to the dsPIC30F Family Reference Manual (DS70046). For more information on the device instruction set and programming, refer to the dsPIC30F Programmer’s Reference Manual (DS70030).AN8/RB8AN9/RB9AN10/RB10AN11/RB11Power-up Timer Oscillator Start-up Timer POR/BOR ResetWatchdog Timer Instruction Decode and ControlOSC1/CLKIMCLR V DD , V SS AN4/CN6/RB4AN12/RB12Low Voltage DetectUART1,Timing GenerationAN5/CN7/RB516PCH PCL Program CounterALU<16>1624242424X Data BusIRI 2C™DCI PGC/EMUC/AN6/OCFA/RB6PGD/EMUD/AN7/RB7PCU 12-bit ADCTimers U2TX/CN18/RF5EMUC3/SCK1/RF6Input Capture Module Output Compare ModuleEMUD1/SOSCI/T2CK/U1ATX/PORTBRF0RF1U1RX/SDI1/SDA/RF2EMUD3/U1TX/SDO1/SCL/RF3PORTD1616 16 16 x 16W Reg Array Divide UnitEngineDSP DecodeROM Latch16Y Data BusEffective AddressX RAGUX WAGUY AGUAN0/CN2/RB0AN1/CN3/RB1AN2/SS1/LVDIN/CN4/RB2AN3/CN5/RB3OSC2/CLKO/RC15U2RX/CN17/RF4A V DD , A V SSUART21616161616PORTCPORTF1616 16168Interrupt ControllerPSV & Table Data Access Control BlockStackControlLogic Loop Control LogicData Latch Data Latch Y Data (1 Kbyte)RAM X Data (1 Kbyte)RAM Address LatchAddress LatchControl Signalsto Various Blocks EMUC2/OC1/RD0EMUD2/OC2/RD1RD2RD3IC1/INT1/RD8IC2/INT2/RD916SPI1Address Latch Program Memory (24 Kbytes)Data LatchData EEPROM (1 Kbyte) 16CN1/RC13EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14PORTAINT0/RA11FIGURE 1-2:dsPIC30F4013 BLOCK DIAGRAMAN8/RB8AN9/CSCK/RB9AN10/CSDI/RB10AN11/CSDO/RB11Power-up Timer Oscillator Start-up Timer POR/BOR ResetWatchdog Timer InstructionDecode &ControlOSC1/CLKIMCLR V DD , V SS AN4/IC7/CN6/RB4AN12/COFS/RB12Low Voltage DetectTiming GenerationAN5/IC8/CN7/RB516PCH PCL Program CounterALU<16>1624242424X Data BusIRPGC/EMUC/AN6/OCFA/RB6PGD/EMUD/AN7/RB7PCU U2TX/CN18/RF5EMUC3/SCK1/RF6EMUD1/SOSCI/T2CK/U1ATX/PORTBC1RX/RF0C1TX/RF1U1RX/SDI1/SDA/RF2EMUD3/U1TX/SDO1/SCL/RF3PORTD1616 16 16 x 16W Reg Array Divide UnitEngineDSP DecodeROM Latch16Y Data BusEffective AddressX RAGU X WAGUY AGUAN0/CN2/RB0AN1/CN3/RB1AN2/SS1/LVDIN/CN4/RB2AN3/CN5/RB3OSC2/CLKO/RC15U2RX/CN17/RF4A V DD , A V SS1616161616PORTCPORTF1616 16168Interrupt ControllerPSV & Table Data Access Control BlockStackControlLogic Loop Control LogicData Latch Data Latch Y Data (1 Kbyte)RAM X Data (1 Kbyte)RAM Address LatchAddress LatchControl Signalsto Various Blocks EMUC2/OC1/RD0EMUD2/OC2/RD1OC3/RD2OC4/RD3IC1/INT1/RD8IC2/INT2/RD916Address Latch Program Memory (48 Kbytes)Data LatchData EEPROM (1 Kbyte) 16CN1/RC13EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14PORTAINT0/RA11UART1,I 2C™DCI 12-bit ADC Timers Input Capture ModuleOutput Compare ModuleUART2SPI1CAN1Table1-1 provides a brief description of device I/O pinouts and the functions that may be multiplexed to a port pin. Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin.TABLE 1-1:PINOUT I/O DESCRIPTIONSPin Name PinType BufferType DescriptionAN0-AN12I Analog Analog input channels.AN6 and AN7 are also used for device programming data andclock inputs, respectively.AV DD P P Positive supply for analog module.AV SS P P Ground reference for analog module.CLKI CLKO IOST/CMOS—External clock source input. Always associated with OSC1 pinfunction.Oscillator crystal output. Connects to crystal or resonator inCrystal Oscillator mode. Optionally functions as CLKO in RCand EC modes. Always associated with OSC2 pin function.CN0-CN7, CN17-CN18I ST Input change notification inputs.Can be software programmed for internal weak pull-ups on allinputs.COFS CSCK CSDI CSDO I/OI/OIOSTSTST—Data Converter Interface Frame Synchronization pin.Data Converter Interface Serial Clock input/output pin.Data Converter Interface Serial data input pin.Data Converter Interface Serial data output pin.C1RX C1TX IOST—CAN1 Bus Receive pin.CAN1 Bus Transmit pin.EMUD EMUC EMUD1 EMUC1 EMUD2 EMUC2 EMUD3 EMUC3I/OI/OI/OI/OI/OI/OI/OI/OSTSTSTSTSTSTSTSTICD Primary Communication Channel data input/output pin.ICD Primary Communication Channel clock input/output pin.ICD Secondary Communication Channel data input/output pin.ICD Secondary Communication Channel clock input/output pin.ICD Tertiary Communication Channel data input/output pin.ICD Tertiary Communication Channel clock input/output pin.ICD Quaternary Communication Channel data input/output pin.ICD Quaternary Communication Channel clock input/output pin.IC1, IC2, IC7, IC8I ST Capture inputs 1,2, 7 and 8.INT0 INT1 INT2IIISTSTSTExternal interrupt 0.External interrupt 1.External interrupt 2.LVDIN I Analog Low Voltage Detect Reference Voltage input pin.MCLR I/P ST Master Clear (Reset) input or programming voltage input. Thispin is an active low Reset to the device.OCFA OC1-OC4IOST—Compare Fault A input (for Compare channels 1, 2, 3 and 4).Compare outputs 1 through 4.OSC1 OSC2II/OST/CMOS—Oscillator crystal input. ST buffer when configured in RC mode;CMOS otherwise.Oscillator crystal output. Connects to crystal or resonator inCrystal Oscillator mode. Optionally functions as CLKO in RCand EC modes.PGD PGC I/OISTSTIn-Circuit Serial Programming data input/output pin.In-Circuit Serial Programming clock input pin.Legend:CMOS=CMOS compatible input or output Analog=Analog input ST=Schmitt Trigger input with CMOS levels O=OutputI=Input P=PowerRA11I/O ST PORTA is a bidirectional I/O port.RB0-RB12I/O ST PORTB is a bidirectional I/O port.RC13-RC15I/O ST PORTC is a bidirectional I/O port.RD0-RD3, RD8, RD9I/O ST PORTD is a bidirectional I/O port.RF0-RF5I/O ST PORTF is a bidirectional I/O port.SCK1SDI1SDO1SS1I/O I O I ST ST —ST Synchronous serial clock input/output for SPI1.SPI1 Data In.SPI1 Data Out.SPI1 Slave Synchronization.SCL SDA I/O I/O ST ST Synchronous serial clock input/output for I 2C.Synchronous serial data input/output for I 2C.SOSCO SOSCI O I —ST/CMOS32 kHz low power oscillator crystal output.32 kHz low power oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise.T1CK T2CK I I ST ST Timer1 external clock input.Timer2 external clock input.U1RX U1TX U1ARX U1ATX I O I O ST —ST —UART1 Receive.UART1 Transmit.UART1 Alternate Receive.UART1 Alternate Transmit.V DD P —Positive supply for logic and I/O pins.V SS P —Ground reference for logic and I/O pins.V REF +I Analog Analog Voltage Reference (High) input.V REF -IAnalogAnalog Voltage Reference (Low) input.TABLE 1-1:PINOUT I/O DESCRIPTIONS (CONTINUED)Pin NamePin Type Buffer Type DescriptionLegend:CMOS =CMOS compatible input or output Analog =Analog inputST =Schmitt Trigger input with CMOS levels O =Output I =Input P =Power2.0CPU ARCHITECTUREOVERVIEW2.1Core OverviewThis section contains a brief overview of the CPU architecture of the dsPIC30F.The core has a 24-bit instruction word. The Program Counter (PC) is 23-bits wide with the Least Significant (LS) bit always clear (refer to Section3.1), and the Most Significant (MS) bit is ignored during normal pro-gram execution, except for certain specialized instruc-tions. Thus, the PC can address up to 4M instruction words of user program space. An instruction pre-fetch mechanism is used to help maintain throughput. Pro-gram loop constructs, free from loop count manage-ment overhead, are supported using the DO and REPEAT instructions, both of which are interruptible at any point.The working register array consists of 16 x 16-bit regis-ters, each of which can act as data, address or offset registers. One working register (W15) operates as a software stack pointer for interrupts and calls.The data space is 64 Kbytes (32K words) and is split into two blocks, referred to as X and Y data memory. Each block has its own independent Address Genera-tion Unit (AG U). Most instructions operate solely through the X memory, AG U, which provides the appearance of a single unified data space. The Multiply-Accumulate (MAC) class of dual source DSP instructions operate through both the X and Y AGUs, splitting the data address space into two parts (see Section3.2). The X and Y data space boundary is device specific and cannot be altered by the user. Each data word consists of 2 bytes, and most instructions can address data either as words or bytes.There are two methods of accessing data stored in program memory:•The upper 32 Kbytes of data space memory canbe mapped into the lower half (user space) of pro-gram space at any 16K program word boundary, defined by the 8-bit Program Space Visibility Page (PSVPAG) register. This lets any instruction access program space as if it were data space, with a limitation that the access requires an addi-tional cycle. Moreover, only the lower 16 bits of each instruction word can be accessed using this method.•Linear indirect access of 32K word pages within program space is also possible using any working register, via table read and write instructions. Table read and write instructions can be used to access all 24 bits of an instruction word.Overhead-free circular buffers (modulo addressing) are supported in both X and Y address spaces. This is primarily intended to remove the loop overhead for DSP algorithms.The X AGU also supports bit-reversed addressing on destination effective addresses to greatly simplify input or output data reordering for radix-2 FFT algorithms. Refer to Section4.0 for details on modulo and bit-reversed addressing.The core supports Inherent (no operand), Relative, Literal, Memory Direct, Register Direct, Register Indirect, Register Offset and Literal Offset Addressing modes. Instructions are associated with predefined Addressing modes, depending upon their functional requirements.For most instructions, the core is capable of executing a data (or program data) memory read, a working reg-ister (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, 3-operand instructions are supported, allowing C=A+B operations to be executed in a single cycle.A DSP engine has been included to significantly enhance the core arithmetic capability and throughput. It features a high speed 17-bit by 17-bit multiplier, a 40-bit ALU, two 40-bit saturating accumulators and a 40-bit bidirectional barrel shifter. Data in the accumula-tor or any working register can be shifted up to 15 bits right, or 16 bits left in a single cycle. The DSP instruc-tions operate seamlessly with all other instructions and have been designed for optimal real-time performance. The MAC class of instructions can concurrently fetch two data operands from memory while multiplying two W registers. To enable this concurrent fetching of data operands, the data space has been split for these instructions and linear for all others. This has been achieved in a transparent and flexible manner, by dedicating certain working registers to each address space for the MAC class of instructions.Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the dsPIC30F Family Reference Manual (DS70046). For more information on the device instruction set and programming, refer to the dsPIC30F Programmer’s Reference Manual (DS70030).。