BL-RXX3G中文资料
XSZ-H中文正文资料
目录1、简介 (1)2、规格··········································································································（1－2）3、安装··········································································································（3－5）4、使用··········································································································（6－7）5、常见故障及排除方法 (8)6、维护与保养 (9)7、可提供的选购件 (9)8、相衬装置使用说明 (10)9、摄影装置使用说明 (11)10、暗场装置使用说明 (11)11、偏光装置使用说明 (11)12、描绘装置使用说明 (12)13、电视、录像装置使用说明 (12)14、色衬装置使用说明 (13)15、落射荧光装置使用说明.............................................................................（14－15）标准配套表 . (17)选购件表 (18)1简介XSZ－H系列生物显微镜现代的多功能系列化设计与精良的制造技术，使之成为同类产品的佼佼者。
ARM汇编手册
ARM 汇编手册
版权声明
本手册为北京顶嵌开源科技有限公司内部培训资料，仅 供本公司内部学习使用，在未经本公司授权的情况下，请勿 用作任何商业用途。
400-661-5264
专注嵌入式 Linux 技术
北京顶嵌开源科技有限公司
目录
寄存器装载和存储.............................................................................................................................5 传送单一数据.............................................................................................................................5 传送多个数据.............................................................................................................................7 SWP : 单一数据交换................................................................................................................ 9
乘法指令........................................................................................................................................... 19 MLA : 带累加的乘法..............................................................................................................19 MUL : 乘法..............................................................................................................................19
MBRS360BT3G;MBRS360T3G;中文规格书,Datasheet资料
MBRS360T3G,MBRS360BT3G,NRVBS360T3G,NRVBS360BT3GSurface MountSchottky Power RectifierThis device employs the Schottky Barrier principle in a large area metal−to−silicon power diode. State−of−the−art geometry features epitaxial construction with oxide passivation and metal overlay contact. Ideally suited for low voltage, high frequency rectification, oras free wheeling and polarity protection diodes, in surface mount applications where compact size and weight are critical to the system. Features•Small Compact Surface Mountable Package with J−Bend Leads •Rectangular Package for Automated Handling•Highly Stable Oxide Passivated Junction•Excellent Ability to Withstand Reverse Avalanche Energy Transients •Guard−Ring for Stress Protection•NRVBS Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable•These are Pb−Free DevicesMechanical Characteristics•Case: Epoxy, Molded, Epoxy Meets UL 94 V−0•Weight:217 mg (Approximately), SMC95 mg (Approximately), SMB•Finish: All External Surfaces Corrosion Resistant and Terminal Leads are Readily Solderable•Lead and Mounting Surface Temperature for Soldering Purposes: 260°C Max. for 10 Seconds•Polarity: Notch in Plastic Body Indicates Cathode Lead •Device Meets MSL 1 Requirements•ESD Ratings:♦Machine Model, C♦Human Body Model, 3BDevice Package Shipping†ORDERING INFORMATIONSMCCASE 403SCHOTTKY BARRIERRECTIFIERS3.0 AMPERES, 60 VOLTS†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.MBRS360T3G SMC(Pb−Free)2,500 /Tape & Reel B36= Specific Device CodeA= Assembly LocationY= YearWW= Work WeekG= Pb−Free Package(Note: Microdot may be in either location)MARKING DIAGRAMSAYWWB36GGSMBCASE 403AAYWWB36GGMBRS360BT3G SMB(Pb−Free)2,500 /Tape & Reel NRVBS360T3G SMC(Pb−Free)2,500 /Tape & Reel2,500 /Tape & Reel NRVBS360BT3G SMB(Pb−Free)MAXIMUM RATINGSRatingSymbol Value Unit Peak Repetitive Reverse Voltage Working Peak Reverse Voltage DC Blocking VoltageV RRM V RWM V R 60VAverage Rectified Forward CurrentI F(AV) 3.0 @ T L = 137°C 4.0 @ T L = 127°CA Nonrepetitive Peak Surge Current(Surge applied at rated load conditions halfwave, single phase, 60 Hz)I FSM 125A Storage Temperature RangeT stg −65 to +175°C Operating Junction Temperature (Note 1)T J−65 to +175°CStresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.1.The heat generated must be less than the thermal conductivity from Junction −to −Ambient: dP D /dT J < 1/R q JA .THERMAL CHARACTERISTICSCharacteristicSymbol Value Unit Thermal Resistance, Junction −to −Lead (Note 2)SMC Package SMB PackageR q JL1115°C/WThermal Resistance, Junction −to −Ambient (Note 2)SMC Package SMB PackageR q JA136145°C/WThermal Resistance, Junction −to −Ambient (Note 3)SMC PackageSMB Package (Note 4)R q JA7173°C/WELECTRICAL CHARACTERISTICSMaximum Instantaneous Forward Voltage (Note 5)(i F = 3.0 A, T J = 25°C)V F 0.740V Maximum Instantaneous Reverse Current (Note 5)(Rated dc Voltage, T J = 25°C)(Rated dc Voltage, T J = 100°C)i R0.1510mA2.Mounted with minimum recommended pad size, PC Board FR4.3. 1 inch square pad size (1 x 0.5 inch for each lead) on FR4 board.4.Typical Value; 1 inch square pad size (1 x 0.5 inch for each lead) on FR4 board.5.Pulse Test: Pulse Width = 300 m s, Duty Cycle ≤2.0%.V F , INSTANTANEOUS FORWARD VOLTAGE (V)Figure 1. Typical Forward Voltage Figure 2. Maximum Forward VoltageI F , I N S T A N T A N E O U S F OR W A R D C U R R E N T (A )V F , INSTANTANEOUS FORWARD VOLTAGE (V)0.010.11100.010.1110I F , I N S T A N T A N E O U S F O R W A R D C U R R E N T (A )V R , INSTANTANEOUS REVERSE VOLTAGE (V)Figure 3. Typical Reverse CurrentFigure 4. Maximum Reverse CurrentI R , I N S T A N T A N E O U S R E V E R S E C U R R E N T (A )V R , INSTANTANEOUS REVERSE VOLTAGE (V)I R , I N S T A N T A N E OU S R E V E R S E C U R R E N T (A )1.0E −1.0E −1.0E −1.0E −1.0E −1.0E −1.0E −1.0E+001.0E −1.0E −1.0E −1.0E −1.0E −1.0E −1.0E+00T L , LEAD TEMPERATURE (°C)Figure 5. Current DeratingFigure 6. Forward Power DissipationI F (A V ), A V E R A G E F O R W A R D C U R R E N T (A )I O , AVERAGE FORWARD CURRENT (A)P F O , A V E R A G E P O W E R D I S S I P A T I O N (W )Figure 7. Typical CapacitanceV R , REVERSE VOLTAGE (V)C , C A P A C I T A N C E (p F )t, TIME (s)Figure 8. Thermal Response, Junction −to −Ambient, SMC Packager (t ), T R A N S I E N T T H E R M A L R E S P O N S E 0.000010.00010.0010.01110010000.110Figure 9. Typical Thermal Response, Junction −to −Ambient, SMB PackagePULSE TIME (s)0.010.1110100R (t ) (°C /W )SMC PLASTIC PACKAGE CASE 403−03ISSUE EDIMAMINNOM MAX MINMILLIMETERS1.902.13 2.410.075INCHESA10.050.100.150.002b 2.92 3.00 3.070.115c0.150.230.300.006D 5.59 5.84 6.100.220E 6.60 6.867.110.260L0.76 1.02 1.270.0300.0840.0950.0040.0060.1180.1210.0090.0120.2300.2400.2700.2800.0400.050NOM MAX7.757.948.130.3050.3130.320H EǒmmǓ*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.SOLDERING FOOTPRINT*cNOTES:1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.2.CONTROLLING DIMENSION: INCH.3. D DIMENSION SHALL BE MEASURED WITHIN DIMENSION P.4.403-01 THRU -02 OBSOLETE, NEW STANDARD 403-03.0.020 REF0.51 REFL1SMBCASE 403A −03ISSUE HcNOTES:1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.2.CONTROLLING DIMENSION: INCH.3. D DIMENSION SHALL BE MEASURED WITHIN DIMENSION P.ǒmm inchesǓSCALE 8:1*For additional information on our Pb −Free strategy and solderingdetails, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.SOLDERING FOOTPRINT*DIM A MIN NOM MAX MIN MILLIMETERS1.902.20 2.280.075INCHES A10.050.100.190.002b 1.96 2.03 2.200.077c 0.150.230.310.0063.30 3.56 3.950.130E4.06 4.32 4.600.160L 0.761.02 1.600.0300.0870.0900.0040.0070.0800.0870.0090.0120.1400.1560.1700.1810.0400.063NOM MAX 5.21 5.44 5.600.2050.2140.220H E 0.51 REF0.020 REFD L1ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries,affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.PUBLICATION ORDERING INFORMATION分销商库存信息:ONSEMIMBRS360BT3G MBRS360T3G。
BL8506中文资料
TO-92
SOT-23-3
3
1
1
3
2
2
－
－
－
－
SOT-23-5 1 2 3 4
5
PIN Name
VOUT VDD VSS NC NC
Function
Voltage detection output Pin Voltage input Pin GND Pin No connection No connection
Selection Guide： BL8506-XX X XX
Pin Assignment：
Package Type： RM： SOT-23-3 RN： SOT-23-5 SM： SOT-89-3 T： TO-92 （Default、Pb Free）
Output Type： N：Nch Open-drain C：CMOS
Two type of output, CMOS and N-channel open-drain are available.
BL8506 is available in SOT-89-3,SOT-23-3 TO92, SOT23-5 packages which is Pb free.
BL8506
BL8506
N channel open-drain
CMOS output
Absolute Maximum Ratings：
Input Voltage range -------------------------------------------------------------------------------------0.3V~12V Output Voltage range-----------------------------------------------------------------------------------0.3V~12V Maximum Output current -----------------------------------------------------------------------------70mA Maximum power dissipation -------------------------------------------------------------------------150mW Ambient temperature ---------------------------------------------------------------------------------- -40~+70°C Storage temperature----------------------------------------------------------------------------------- -40~125°C Lead temperature and time --------------------------------------------------------------------------260°C,10S
BL8506-30NRM中文资料
TPLH
Parameter Detector Threshold Detector Threshold
Hysteresis Current consumption Maximum operating
voltage Minimum Operating
voltage
Output current
Output Delay Time
Selection Guide： BL8506-XX X XX
Pin Assignment：
Package Type： RM： SOT-23-3 RN： SOT-23-5 SM： SOT-89-3 T： TO-92 （Default、Pb Free）
Output Type： N：Nch Open-drain C：CMOS
voltage Minimum Operating
voltage
Output current
Output Delay Time
Conditions
VDD=4.7V
Nch VDS=0.05V， VDD=0.70V Pch VDS=-2.1V， VDD=4.50V
Reference data
Min.
Typ.
BL8506 is composed of high precision voltage reference, comparator, output driver and resistor array. Internally preset detect voltage has a low temperature drift and requires no external trimming.
Two type of output, CMOS and N-channel open-drain are available.
MMBZ5250BLT3G中文资料
MMBZ5221BLT1 SeriesPreferred DeviceZener Voltage Regulators 225 mW SOT−23 Surface MountThis series of Zener diodes is offered in the convenient, surface mount plastic SOT−23 package. These devices are designed to provide voltage regulation with minimum space requirement. They are well suited for applications such as cellular phones, hand held portables, and high density PC boards.Features•Pb−Free Packages are Available•225 mW Rating on FR−4 or FR−5 Board•Zener V oltage Range − 2.4 V to 91 V•Package Designed for Optimal Automated Board Assembly •Small Package Size for High Density Applications•ESD Rating of Class 3 (>16 KV) per Human Body Model Mechanical CharacteristicsCASE:V oid-free, transfer-molded, thermosetting plastic case FINISH:Corrosion resistant finish, easily solderableMAXIMUM CASE TEMPERATURE FOR SOLDERING PURPOSES: 260°C for 10 SecondsPOLARITY:Cathode indicated by polarity bandFLAMMABILITY RATING:UL 94 V−0MAXIMUM RATINGSMaximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.1.FR−5 = 1.0 X 0.75 X 0.62 in.2.Alumina = 0.4 X 0.3 X 0.024 in, 99.5% alumina.Devices listed in bold, italic are ON Semiconductor Preferred devices. Preferred devices are recommended choices for future use and best overall value.ELECTRICAL CHARACTERISTICS(Pinout: 1-Anode, 2-No Connection, 3-Cathode) (T A = 25°C unless otherwise noted, V= 0.95 V Max. @ I = 10 mA)ZNOTE:MMBZ5233BLT1, MMBZ5246BLT1, MMBZ5251BLT1, and MMBZ5252BLT1 Not Available in 10,000/Tape & Reel.V Z , T E M P E R A T U R E C O E F F I C I E N T (m V /C )°θV Z , NOMINAL ZENER VOLTAGE (V)− 3− 2−1012345678Figure 1. Temperature Coefficients (Temperature Range −55°C to +150°C)V Z , T E M P E R A T U R E C O E F F I C I E N T (m V /C)°θ100101V Z , NOMINAL ZENER VOLTAGE (V)Figure 2. Temperature Coefficients (Temperature Range −55°C to +150°C)V Z , NOMINAL ZENER VOLTAGEFigure 3. Effect of Zener Voltage onZener ImpedanceZ Z T , D Y N A M I C I M P E D A N C E ()Ω1000100101V F , FORWARD VOLTAGE (V)Figure 4. Typical Forward VoltageI F , F O R W A R D C U R R E N T (m A )1000100101C , C A P A C I T A N C E (p F )V Z , NOMINAL ZENER VOLTAGE (V)Figure 5. Typical Capacitance 1000100101V Z , ZENER VOLTAGE (V)1001010.10.01I Z , Z E NE R C U R R E N T (m A )V Z , ZENER VOLTAGE (V)1001010.10.01I R , L E A K A G E C U R R E N T (A )µV Z , NOMINAL ZENER VOLTAGE (V)Figure 6. Typical Leakage Current10001001010.10.010.0010.00010.00001I Z , Z E N E R C U R R E N T (m A )Figure 7. Zener Voltage versus Zener Current(V Z Up to 12 V)Figure 8. Zener Voltage versus Zener Current(12 V to 91 V)PACKAGE DIMENSIONSSOT−23 (TO−236)CASE 318−08ISSUE AJ*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.SOLDERING FOOTPRINT*ǒmm inchesǓSCALE 10:1STYLE 8:PIN 1.ANODE2.NO CONNECTION3.CATHODEON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.PUBLICATION ORDERING INFORMATION。
用户操作手册
基于Web Service的3G手机应用《小小翻译》用户操作手册拟制人：***审核人：***批准人：***2010年09月02日济南职业学院小小鸟团队用户操作手册目录重要声明............................................................................................................................................. 客户忠告............................................................................................................................................. 小小鸟队联系方式.............................................................................................................................1. 概述...............................................................................................................................................1.1 编写目的.............................................................................................................................1.2 背景.....................................................................................................................................1.3 定义.....................................................................................................................................1.4 软件开发参考书籍.............................................................................................................2.软件概述.........................................................................................................................................2.1代码结构..............................................................................................................................2.2运行说明..............................................................................................................................3.运行环境.........................................................................................................................................3.1硬设备..................................................................................................................................4.安装信息.........................................................................................................................................4.1 用户安装说明..................................................................................................................... 5．其他信息.......................................................................................................................................5.1 加载程序.............................................................................................................................5.2 异常情况处理.....................................................................................................................重要声明感谢你使用由济南职业学院小小鸟团队开发的基于Web Service的3G手机应用《小小翻译》软件。
About Flash................................................................................
Production of multimedia content using FlashDepartment of Electronics and Computer Science, University of Southampton1. AbstractMacromedia Flash is one of the most powerful web authoring tools available to web designers today and is used to produce animated and still graphics. However, because of the poor use of Flash animations on the Internet, Flash has acquired a reputation for poor usability. Macromedia itself Macromedia itself and other individuals have produced tools and documentation to help designers make the most out of Flash have now published many usability tips. If these are followed, good multimedia content can be produced which is usable to others.ContentsKeywords ............................................................................................. 1 Introduction .......................................................................................... 1 Background .......................................................................................... 2 Research.............................................................................................. 2 About Flash ..................................................................................... 3 Flash Usability ................................................................................. 3 Alternatives to Flash........................................................................ 4 My Film ............................................................................................ 4 Conclusions.......................................................................................... 9 References......................................................................................... 102. KeywordsMacromedia Flash, Multimedia Content Creation, Animation Graphics, Sound, Video,3. IntroductionThe aim of this paper is to look at multimedia content produced by Macromedia Flash. Flash has become very popular over the past few years; 474 million Internet users use it today. In this paper I research into how Flash is used by developers today and why to give a background into the use of Flash. The advantages and disadvantages of Flash as a multimedia content creation tool are discussed to help developers to decide if Flash is a suitable tool for their project. A number of usability tips for Flash have been put together by a number of individuals, which it is recommended to follow if a usable Flash application is to1be made. I will research into these and outline them. I will also research briefly into alternatives to Flash. To fully understand how to create multimedia applications with Flash, I made a small movie of my own in Flash. I will describe the nature of my film and how it was created. Finally, I will evaluate my film and report my findings and give a summary of my experiences using Macromedia Flash.4. BackgroundFlash was first introduced in 1996 and was known as FutureSplash Animator and run by a company called FutureWave. It was used to play back animation on web browsers through Java. The company decided to sell off their technology due to financial difficulties, they tried Adobe who turned them down, but were soon bought by Macromedia. FutureSplash Animator became Macromedia Flash 1.0. There are 2 main components to the Flash software, which are: • Flash Editor – which is used to create the graphics and animation that make up the end movie • Plug-in or Flash Player – which is used by web-browsers to display the Flash movie Flash can be used to create movies, which incorporate graphics, sound and animation. These movies are generally placed on web sites on the Internet. The main reason web designers use Flash is because it provides a good online user interface, allowing visitors to interact with a web site. Also, animation is known to have a tremendous effect on human peripheral vision and therefore is a good way to relay information to people. Unfortunately, bad use of Flash on web sites has left Flash with a tarnished reputation. Most people either love it or hate it. Even though Flash is very popular on the Internet, many people find the Flash content unusable and annoying. The main arguments for Flash content being unusable are as follows: • The majority of Flash content is unnecessary and gratuitous • Content is usually built once and then not updated regularly • Content usually follows the established standards for Web content5. ResearchFirstly, it is important to look at reasons why and why not to use Flash as a way of conveying information on the Internet. These reasons are outlined below. Advantages of using Flash: • Flash films are browser independent; therefore they can be viewed with any browser, so is not limited. • Designers are able to control colours, fonts and resolution quality, and so can make their films to their needs. • As vector graphics are used, films can be scaled without it affecting the image resolution and objects will be smaller than their bitmap equivalents.2• •Animated and interactive films can be produced with sound, which will be more appealing to visitors, and get information across more easily. Flash software is very powerful, well supported and updated frequently.Disadvantages of using Flash: • Flash is quite a hard piece of software to learn, it may take developers a significant amount of time to learn to use the flash development environment • A plug-in is required to view Flash films, so not all machines will be able to view Flash films. • Flash does not have a user-friendly interface and it not intuitive for designers, and therefore might take designers longer to produce multimedia content. • Printing Flash movies results in poor text quality. • Search engines are unable to read Flash movies, so they do not show up. • It takes longer to create a Flash website than the usual HTML ones.About Flash Flash files have the .SWF extension. These files combine code, media and data into a format that is compact. These are loaded using a steaming model, where the first few frames become available to view once. The files are also cached, so that they can be retrieved again locally, saving time. Video and audio are streamed, which means that MP3 content can be dynamically loaded and player, and that full-motion films can be added. The Sorenson Spark Codec is used for high quality playback with low bandwidth. Flash uses a compressing/decompressing model to help lower network costs. Developers can compress their code when publishing the movie, and when a user wants to run this, it is decompressed on the user’s machine at runtime. Flash Usability One of the main problems with Flash is that it is known to have poor usability. Some usability tips have been produced by individuals. Macromedia’s Flash Usability tips: [/software/flash/productinfo/usability/tips/] • Remember user goals • Remember site goals • Avoid unnecessary intros • Provide logical navigation and interactivity • Design for consistency • Don’t overuse animation • Use sound sparingly • Target low-bandwidth users • Design for accessibility • Test for usability3Alternatives to Flash Flash is not the only development tool available to create multimedia content. A brief discussion of alternatives is presented below. Synchronized Multimedia Integration Language (SMIL) – this is a mark-up language (XML) which is used to write interactive multimedia content. Developers can define the temporal behaviour of their content and the layout of this on screen. Video and audio can be streamed with together with other media types. Scalable Vector Graphics (SVG) – this is a language used to describe two dimensional vector based graphics. It allows for images, text and vector and vector graphic shapes. The Document Object Model (DOM) includes full XML DOM, which allows for effective vector animation via scripting. My Film I used Macromedia Flash to create a small animated film which is to be placed on my university website. I had only ever encountered these types of films on the Internet, but never made one of my own. I also had never used Flash before, so it was a new experience. My film is titled “How to Turn a Geek into a Super Stud”, and shows through animated and still graphics how you can make a geek into a super stud! It can be viewed at /~mkg100 There are some important concepts that need to be understood before starting with Flash, these are described below. • SYMBOLS – these are graphics that have been created by using the drawing tools, and can be used over and over again within the film. • LAYERS – these can be thought of as transparent sheets that are placed on top of each other. Objects can be drawn on one layer without affecting objects in other layers. • FRAMES – displays the contents of I second of the film; a film is made of a series of frames. • KEYFRAMES – these are frames where changes in animation occur. The first frame in a frame is automatically a keyframe. • TIMELINE – shows the frames in all the layers of the film, and what events are occurring in the frames. The film starts of with the opening screen which shows the title, with a moving flashy yellow border, and a button, which when pressed will start the main part of the film. These three objects are placed in their own layers (I made a new layer for each). To place the title on screen, I created a layer called text (Insert ! Layer) and had to use the Text tool from the drawing tools, which works pretty much the same way as the ones found in other programs. You just have to enter the required text into the4box, and change the font size, type and alignment, as you so please. I also inserted a keyframe at frame 25 (Insert ! Keyframe), as this is the last frame that the text appears in. To insert the keyframe, you have to have that particular frame selected from the timeline. I created a new layer for the yellow flashy border, which was created by using keyframes and motion tweening. Motion tweening is used to change the size of objects or rotate them in an animated manner. I placed a keyframe every 5 frames, up to frame 25, and changed the size of the border in each one by transforming the shape (Window ! Inspectors ! Transform), or you could use the re-size option in the drawing tools to change the size. I then inserted the motion tween in each keyframe (Insert ! Create Motion Tween), which makes the border move from one size to the other. These 25 frames run continuously until the arrow button is pressed. This was achieved by selecting frame 25 in this layer and modifying the frame properties (Modify ! Frame ! Actions tab). I added a ‘Go to’ action and specified the frame to ‘go to and play’ scene 1, frame 1; the beginning of the film. The red arrow was also created in another layer, using the drawing tools, and was then turned into a button (Insert ! Convert to Symbol ! Button). When the cursor is placed over the button, the arrow increases in size. To do this you have to select the arrow button and then edit the object (Edit ! Edit Selected). This brings up a new scene with just the button in it. The timeline at the top of the screen has frames for ‘up’, ‘down’, ‘over’ and ‘hit’. You need to edit the button design in each frame depending on what you want the button to do when the corresponding actions occur. In this case, in the ‘over’ frame I drew an enlarged arrow by using the re-size tool. When the arrow button is pressed, the film jumps to the next screen, which starts in frame 30. The button performs this action by editing the buttons properties (Modify ! Instance ! Actions tab). I added a ‘Go to’ action and specified the frame ‘go to and play’ at as frame 30. Again I added a keyframe at frame 25, as this is the last frame for the arrow. There is another layer in this screen, which displays the background. In this instance the layer is empty as the background is white. The next scene shows the geek and ‘Mandy’s Geek Transformer’ machine, which starts from frame 30. The background is now a sea blue colour, which I created by drawing a large box with the drawing tools to fill the screen. The background layer must be the layer at the bottom so that all the other objects can be place on top of it. I created a new layer for the geek and placed a keyframe at frame 30. In this frame I used the drawing tools to create the geek. I then used drawing tools to create the speech bubble and then added a text box inside this to add the words. I also wanted some to be played at this frame; the geek saying “hello, my names Colin”. I had recorded some voices earlier with my microphone onto my5computer. I then imported this sound into Flash (File ! Import ! select sound file). I wanted the sound to be played at frame 30, so created a new layer for this sound. I then edited the frame properties to play the required sound file (Modify ! Frame ! Sound tab ! select file from drop down box) at this frame. Then I added another keyframe at frame 45, as this is the frame in which the transformer machine enters the film. I wanted the film to stop here until the button on the machine is pressed. Therefore, I set an action to frame 45 in the geek layer called ‘Stop’. This causes the film to stop at that frame until another event is triggered; in this case, the red button on the machine is selected. The machine is also drawn in a new layer and is created with the drawing tools. The title is drawn using the text facility. The red circle on the machine is a button whose action is to ‘go to and play’ at frame 50. At frame 50, I placed keyframes in the geek layer and the machine layer, as I wanted the objects in this layer to be displayed on screen but I deleted the geek’s speech bubble, as it was no longer required. I then created another layer, which starts at frame 50. This layer contains the rays that shoot out of the machine when the button is pressed and the ‘zap’ graphic. I drew the rays and zap with the drawing tools and then inserted another keyframe in this layer 3 frames down, frame 53, and used the re-size tool to reduce the size of the rays. I then used motion tweening to make the ray’s change in size on an animated way. I repeated this until frame 71, increasing and decreasing the size of the rays each time, with motion tweening between each. This was to give a shooting rays effect. I moved the ‘zap’ graphic in each of these keyframes as well with the aid of the arrow tool from the drawing tools. During the zapping, the geek shouts “Nooo!” which occurs from frame 50 to frame 82. Again I used the drawing tools to create this.After the zapping has finished the film has reached frame 83. The layer that contains the machine is no longer needed, so there are no frames for this layer anymore. In the geek layer, the geek has a speech bubble beside him, which was made by the drawing tools. The only layers active at this point are the one with the geek in it and the background.6Now the geek transformation begins!In this scene, which starts at frame 98, I entered a keyframe and deleted the glasses from the geek and added a text box, both changes were made to the geek layer. I also drew some new eyes with the drawing tools and placed them over the old eye. I left this scene and all the others after this on for 15 frames in order to give people time read the text and note the difference in the geek.This scene starts at frame 113, where I placed a keyframe. I deleted the spots from the geeks face and entered new text into the text box.Another keyframe was placed at frame 128 in the geek layer. I drew another mouth using the drawing tools and placed it over the old one. I also edited the text in the text box.I placed another keyframe at frame 143 in the geek layer. I deleted the excess hair from the nose and ears with the aid of the eraser tool from the drawing tools. I then re-drew the hair using the paintbrush tool. Again, I edited the text.7This keyframe was added at frame 158 in the geek layer. I used the drawing tools to change the shape of the face and changed the text.A keyframe was inserted at frame at 173, and again drawing tools were used to change the shape of the body.This keyframe is at frame 188 and I used the fill tool to change the colours of the clothes.This is the last scene and the keyframe was inserted at frame 203 and I used the text tool to edit the text. I also created a button using the drawing tool to draw it. I then added an action to the button, which is ‘go to and play’ frame 1, which is the beginning of the film. I also added some sound to this frame, which says “hey baby!”, by changing the frame properties.8This concludes my film. The final step is to convert the Flash file into a movie so that is can be viewed in Flash players (File ! Export Movie ! specify file name and Save).6. ConclusionsI found Macromedia Flash a very powerful tool. It allowed me to draw pictures and make simple animations quite easily. I found Flash relatively easy to use when drawing basic pictures and animations, but it started to get very complicated when I attempted to produce more advanced animations. In my film, where the rays bombard the geek, I tried to animate the geek so that it looked like he was getting electrocuted. Unfortunately I was unable to do this. When I animated the geek Flash automatically turned the geek into a symbol, which meant that I was unable to change the appearance of the geek after this. This meant that I could not finish my film as the last part of the film is concerned with editing the appearance of the geek. I therefore decided that it would be more beneficial to not have the animated geek, but to have the appearance of the geek change. Flash has a large variety of tools, but there are far too many to learn. It would take a tremendous amount of time to fully learn all the tools and functions available. Also, as there are lots of things that Flash can do, it is hard to know exactly what can be done, as lots of time would be required to learn everything. It can also get very confusing knowing what does what. There are a number of tutorials that are available in the Flash software, which cover: • Basic drawing • Concepts • Buttons • Simple animation • Streaming audio These tutorials are extremely useful as you can learn enough to make a simple film and are very easy to follow. There are step-by-step instructions on how to make objects and lots of screen dumps so you can check if you are doing the right thing. Flash also has a good Help, where you can search on keywords. The concept of layers in Flash is extremely useful as it helps to organise objects. You can also colour code the layers, which helps to show which objects belong to which layer, especially when there are a lot of objects. It is also possible to lock layers, which is useful when you do not want to accidentally change objects, Making simple animations is quite straight forward, especially since there is a whole tutorial on it. But it is a lot harder to make complex animations, as there is no extra help. I found Flash quite easy to use, but to fully master it would take a lot of time and energy. It is very good for making multimedia content, as it allows you to incorporate graphics with animation and sound without any programming knowledge. It can annoying sometimes as it can quite awkward to draw objects as you want and it could benefit from more advanced drawing tools. Also, more help is needed on how to produce animations.97. References1. /alertbox/9512.html (last accessed 13/12/02) 2. http://www/iboost/com/build/design/articles/pageview/603.htm (last accessed 13/12/02) 3. /acrlnec/sigs/itig/tc_july_aug2000.htm (last accessed 13/12/02) 4. /software/flash/productinfo/usability/tips/ (last accessed 13/12/02) 5. /macromedia/events/john_gay/page04.html# (last accessed 13/12/02) 6. /approach/ (last accessed 13/12/02) 7. Allaire.J, Macromedia Flash MX – A next - generation rich client 8. /archives/2000/10/desirevu2/ (last accessed 13/12/02) 9. /TR/smil20/ (last accessed 13/12/02) 10. /Graphics/SVG/Overview.htm8 (last accessed 13/12/02)10。
XXXXXX项目BT
XXXXXX项目（BT）投资建设合同书地产相关合同 2009-03-20 17:06:53 阅读627 评论0 字号：大中小订阅本合同由XXXXXXXXXX （下称甲方）与XXXXXXXXXX集团有限公司（下称乙方）签署。
本合同甲方是XXXXXXXXXX人民政府委托授权指定对XXXXXXXXXX 体育馆工程项目的投资建设方按照BT方式进行公开招标的招标人及合同签订人。
授权委托书详见附件（4）。
本工程项目是甲方通过公开招标方式确定乙方为XXXXXXXXXX体育馆项目的投资建设方，按照“企业投资建设，政府回购”的BT方式的运作模式进行实施。
甲方于发出的《项目招商中标通知书》详见附件（3）。
有鉴于此，甲乙双方根据双方就本工程项目投资建设所签订框架协议及依照《中华人民共和国合同法》、《中华人民共和国建筑法》及其他有关法律、行政法规、遵循平等、自愿、公平和诚实信用的原则，就本项目投资建设事宜协商一致，订立本合同。
第1条项目名称、位置1.1名称：XXXXXXXXXX项目。
1.2位置：XXXXXXXXXX 。
第2条项目规模及内容2.1规模： XXXXXXXXXXXXXXX。
2.2内容：地基与基础工程、主体工程（含钢结构）、屋面工程、装饰装修工程、给水排水工程、电气工程、通风与空调工程、门窗工程、电梯工程、智能化工程以及室外附属工程（例如市政道路、园林景观工程、太阳能工程、燃气工程、高低压配电及发电设备安装工程、白蚁防治工程、停车场管理系统工程（含地下室车道划线）、扶手、栏杆制作安装工程）等甲方提供的工程施工图纸所包含的全部范围及内容，但不包括室内器材、家具和可移动设备等。
最终的工程内容以甲方提供的设计文件（施工图等）、施工过程中发生的设计变更文件、监理机构的签证文件为准。
2.3 签证：因设计更改及其他原因引致的工程量变更签证由监理公司报乙方后7个日历天内，乙方予以答复，不做回复的视为对该签证的认可，乙方将此签证再报甲方后7个日历天内予以核定，不做回复或核定的，视为同意该签证。
辽宁联通3g产品手册xxxx25 (2)
辽宁联通3G产品手册2013年11月目录iPhone合约（iPhone4、iPhone4S、iPhone5、iPhone5C、iPhone5S） (5)NoteⅢ（GT- N9002 16G） (20)NoteⅢ（GT- N9002 32G） (21)Note II（GT-N7102 32G） (22)三星GT-I9200 (23)三星G3502 (24)三星GT-I9300 (25)诺基亚920 (26)三星I9082i、三星Baffin（I9082） (27)魅族MX2 (29)魅族MX3 16GB (30)魅族MX3 32GB (31)魅族MX3 64GB (32)小米1S (33)小米2 (34)小米1S青春版 (35)小米2S (36)小米2A (37)小米-红米 (38)HTC Butterfly s（9060） (38)HTC A620e（8S） (40)HTC x920e（Butterfly） (41)HTC606w (42)三星S4 GT-I9500(16G单卡) (44)三星S4 GT-I9502(16G双卡) (45)三星S4 GT-I9502(32G双卡) (47)三星SM-C101 (48)HTC One max(8060豪华版) (49)HTC One max(8060标准版) (50)HTC7060 (51)HTC6160 (52)HTC One(802w) (53)HTC One(801e) (54)HTC301e (55)华硕Padfone infinity(A80) (56)华硕FonePad（ME371MG） (57)OPPO Find5(X909) (58)华为Mate (60)华为P6 (61)诺基亚720 (62)诺基亚625 (63)诺基亚925 (65)诺基亚1020 (66)OPPO Ulike2(U705W) (67)OPPO R815W (68)OPPO R820 (69)金立E3 (69)金立E6 (70)金立风华2快乐版（GN705W） (72)索尼M35h (72)索尼S39h (73)联想P780 (74)酷派9150w (75)中兴N988 (76)中兴V5S (78)TCL Y910 (79)TCL S950 (80)天语Kis 2W (80)联想A269 (81)海信U929、酷派7231、联想A369 (81)中兴V790、海信U820、天语W621、联想A66 (81)联想A60+、天语W619、酷派7019A、中兴V788D、海信U850、万利达I5、华为Y210、酷派7020、酷派7011、天语655、海尔W617、万利达I50、海信U912、万利达I60、TCL J310、天语W68、TCL J320、华为Y320、酷派7230s、天语W70、三星S6812C、海信U936 (82)酷派7230、联想A690、天语W719、海信U930、中兴V889S、酷派7235、天语W656、华为Y300、联想A390、三星GT-S6812i、飞利浦W635、中兴V818、海信U939、酷派7269、华为Y511、酷派7270、海信U966 (83)摩托罗拉XT390、三星S6102E (83)华为G330D、联想A789、酷派7266、天语W760、海信U909、TCL S500、中兴V955、联想A800、天语U6、金立GN135、华为G510、中兴V956、海信U958、天语U86、联想A630、酷派7295A、天语W95、三星S7562i、华为G520、联想A766、TCL S700、联想A820、联想A760、酷派7295C、海信U978、天语W98 (84)三星S6352 (84)酷派7290、海信U950、万利达I8、天语S5、酷派7268、万利达I90、HTC T327W、海尔W856、酷派7295、中兴V967S、联想A830、海信U970、华为G610S (85)酷派7296、联想A850、天语kis3W (86)诺基亚520 (86)金立GN700W（风华1） (87)中兴V889M (87)HTC T329W (88)天语W806 (89)金立GN708W（风华2） (89)华为G600 (89)中兴V987 (91)HTC T328W (91)LG P705 (93)HTC T528W (93)华为G700 (94)iPhone合约（iPhone4、iPhone4S、iPhone5、iPhone5C、iPhone5S）iPhone4 8GBiPhone4S 8GBiPhone4S 16GB机型：iPhone4S 32GB机型：iPhone4S 64GBiPhone5 16GBiPhone5 32GBiPhone5 64GBiPhone5C 16GBiPhone5C 32GBiPhone5S 16GBiPhone5S 32GBiPhone5S 64GBNoteⅢ（GT- N9002 16G）NoteⅢ（GT- N9002 32G）Note II（GT-N7102 32G）三星GT-I9200三星G3502三星GT-I9300 （1）二年期（2）三年期诺基亚920 （1）二年期（2）三年期三星I9082i、三星Baffin（I9082）（1）二年期（2）三年期魅族MX2魅族MX3 16GB小米1S （1）二年期（2）三年期小米2 （1）二年期（2）三年期小米1S青春版（1）二年期（2）三年期小米2S （1）二年期（2）三年期小米2A （1）二年期（2）三年期小米-红米HTC Butterfly s（9060）HTC A620e（8S）（1）二年期（2）三年期HTC x920e（Butterfly）（1）二年期（2）三年期HTC 606w （1）二年期（2）三年期三星S4 GT-I9500(16G单卡) （1）二年期（2）三年期三星S4 GT-I9502(16G双卡) （1）二年期（2）30个月（3）三年期三星S4 GT-I9502(32G双卡) （1）二年期（2）30个月三星SM-C101 （1）二年期（2）三年期HTC One max(8060豪华版)HTC One max(8060标准版)。
M295V040-120XN3R中文资料
AI0137219A0-A18W DQ0-DQ7V CCM29F040GE V SS8Figure 1. Logic DiagramM29F0404 Mbit (512Kb x8, Uniform Block) Single Supply Flash MemoryNOT FOR NEW DESIGNM29F040 is replaced by the M29F040B5V ± 10% SUPPLY VOLTAGE for PROGRAM,ERASE and READ OPERATIONS FAST ACCESS TIME: 70nsBYTE PROGRAMMING TIME: 10µs typical ERASE TIME–Block: 1.0 sec typical –Chip: 2.5 sec typicalPROGRAM/ERASE CONTROLLER (P/E.C.)–Program Byte-by-Byte–Data Polling and Toggle bits Protocol for P/E.C. StatusMEMORY ERASE in BLOCKS–8 Uniform Blocks of 64 KBytes each –Block Protection –Multiblock EraseERASE SUSPEND and RESUME MODES LOW POWER CONSUMPTION–Read mode: 8mA typical (at 12MHz)–Stand-by mode: 25µA typical –Automatic Stand-by mode100,000 PROGRAM/ERASE CYCLES per BLOCK20 YEARS DATA RETENTION –Defectivity below 1ppm/year ELECTRONIC SIGNATURE –Manufacturer Code: 20h –Device Code: E2h A0-A18Address Inputs DQ0-DQ7Data Input / Outputs E Chip Enable G Output Enable W Write Enable V CC Supply Voltage V SSGroundTable 1. Signal NamesPLCC32 (K)TSOP32 (N)8 x 20 mmNovember 19991/31This is information on a product still in production but not recommended for new designs.A1A0DQ0A7A4A3A2A6A5A13A10A8A9DQ7A14A11G E DQ5DQ1DQ2DQ3DQ4DQ6A17W A16A12A18V CC A15AI01379M29F040(Normal)8191617242532V SS Figure 2B. TSOP Pin ConnectionsAI01378A 17A13A10D Q 517A1A0DQ0D Q 1D Q 2D Q 3D Q 4A7A4A3A2A6A59W A81A 16A9DQ7A 12A1432A 18V C C M29F040A 15A11D Q 6G E 25V S S Figure 2A. LCC Pin ConnectionsA1A0DQ0A7A4A3A2A6A5A13A10A8A9DQ7A14A11G E DQ5DQ1DQ2DQ3DQ4DQ6A17W A16A12A18V CC A15AI01174BM29F040(Reverse)8191617242532V SS Figure 2C. TSOP Reverse Pin ConnectionsDESCRIPTIONThe M29F040 is a non-volatile memory that may be erased electrically at the block level, and pro-grammed Byte-by-Byte.The interface is directly compatible with most mi-croprocessors. PLCC32 and TSOP32 (8 x 20mm)packages are available. Both normal and reverse pin outs are available for the TSOP32 anisationThe Flash Memory organisation is 512K x8 bits with Address lines A0-A18 and Data Inputs/Outputs DQ0-DQ7. Memory control is provided by Chip Enable, Output Enable and Write Enable Inputs.Erase and Program are performed through the internal Program/Erase Controller (P/E.C.).Data Outputs bits DQ7 and DQ6 provide polling or toggle signals during Automatic Program or Erase to indicate the Ready/Busy state of the internal Program/Erase Controller.Memory BlocksErasure of the memory is in blocks. There are 8uniform blocks of 64 Kbytes each in the memory address space. Each block can be programmed and erased over 100,000 cycles. Each uniform block may separately be protected and unpro-2/31M29F040Symbol Parameter Value Unit T A Ambient Operating Temperature (3)–40 to 125 °CT BIAS Temperature Under Bias–50 to 125 °CT STG Storage Temperature–65 to 150 °CV IO (2)Input or Output Voltages–0.6 to 7 VV CC Supply Voltage–0.6 to 7 VV A9 (2)A9 Voltage–0.6 to 13.5 V Notes:1.Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any otherconditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute MaximumRating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.2.Minimum Voltage may undershoot to –2V during transition and for less than 20ns.3.Depends on range.Table 2. Absolute Maximum Ratings (1)tected against program and erase. Block erasure may be suspended, while data is read from other blocks of the memory, and then resumed.Bus OperationsSeven operations can be performed by the appro-priate bus cycles, Read Array, Read Electronic Signature, Output Disable, Standby, Protect Block, Unprotect Block, and Write the Command of an Instruction.Command InterfaceCommand Bytes can be written to a Command Interface (C.I.) latch to perform Reading (from the Array or Electronic Signature), Erasure or Pro-gramming. For added data protection, command execution starts after 4 or 6 command cycles. The first, second, fourth and fifth cycles are used to input a code sequence to the Command Interface (C.I.). This sequence is equal for all P/E.C. instruc-tions. Command itself and its confirmation - if it applies - are given on the third and fourth or sixth cycles.InstructionsSeven instructions are defined to perform Reset, Read Electronic Signature, Auto Program, Block Auto Erase, Chip Auto Erase, Block Erase Suspend and Block Erase Resume. The internal Pro-gram/Erase Controller (P/E.C.) handles all timing and verification of the Program and Erase instruc-tions and provides Data Polling, T oggle, and Status data to indicate completion of Program and Erase Operations.Instructions are composed of up to six cycles. The first two cycles input a code sequence to the Com-mand Interface which is common to all P/E.C. instructions (see Table 7 for Command Descrip-tions). The third cycle inputs the instruction set up command instruction to the Command Interface. Subsequent cycles output Signature, Block Protec-tion or the addressed data for Read operations. For added data protection, the instructions for pro-gram, and block or chip erase require further com-mand inputs. For a Program instruction, the fourth command cycle inputs the address and data to be programmed. For an Erase instruction (block or chip), the fourth and fifth cycles input a further code sequence before the Erase confirm command on the sixth cycle. Byte programming takes typically 10µs while erase is performed in typically 1.0 sec-ond.Erasure of a memory block may be suspended, in order to read data from another block, and then resumed. Data Polling, Toggle and Error data may be read at any time, including during the program-ming or erase cycles, to monitor the progress of the operation. When power is first applied or if V CC falls below V LKO, the command interface is reset to Read Array.3/31M29F040Operation E G W DQ0 - DQ7 Read V IL V IL V IH Data Output Write V IL V IH V IL Data Input Output Disable V IL V IH V IH Hi-Z Standby V IH X X Hi-ZNote:X = V IL or V IHTable 3. OperationsCode E G W A0A1A6A9OtherAddressesDQ0 - DQ7 Manufact. Code V IL V IL V IH V IL V IL V IL V ID Don’t Care20h Device Code V IL V IL V IH V IH V IL V IL V ID Don’t Care E2h Table 4. Electronic SignatureCode E G W A0A1A6A16A17A18OtherAddressesDQ0 - DQ7 Protected Block V IL V IL V IH V IL V IH V IL SA SA SA Don’t Care01h Unprotected Block V IL V IL V IH V IL V IH V IL SA SA SA Don’t Care00h Note:SA = Address of block being checkedTable 5. Block Protection StatusDEVICE OPERATIONSignal DescriptionsAddress Inputs (A0-A18). The address inputs for the memory array are latched during a write opera-tion. The A9 address input is used also for the Electronic Signature read and Block Protect veri-fication. When A9 is raised to V ID, either a Read Manufacturer Code, Read Device Code or Verify Block Protection is enabled depending on the com-bination of levels on A0, A1 and A6. When A0, A1 and A6 are Low, the Electronic Signature Manufac-turer code is read, when A0 is High and A1 and A6 are Low, the Device code is read, and when A1 is High and A0 and A6 are low, the Block Protection Status is read for the block addressed by A16, A17, A18.Data Input/Outputs (DQ0-DQ7). The data input is a byte to be programmed or a command written to the C.I. Both are latched when Chip Enable E and Write Enable W are active. The data output is from the memory Array, the Electronic Signature, the Data Polling bit (DQ7), the Toggle Bit (DQ6), the Error bit (DQ5) or the Erase Timer bit (DQ3). Ou-puts are valid when Chip Enable E and Output Enable G are active. The output is high impedance when the chip is deselected or the outputs are disabled.Chip Enable (E). The Chip Enable activates the memory control logic, input buffers, decoders and sense amplifiers. E High deselects the memory and reduces the power consumption to the standby level. E can also be used to control writing to the command register and to the memory array, while W remains at a low level. Addresses are then latched on the falling edge of E while data is latched on the rising edge of E. The Chip Enable must be forced to V ID during Block Unprotect operations. Output Enable (G). The Output Enable gates the outputs through the data buffers during a read operation. G must be forced to V ID level during Block Protect and Block Unprotect operations. Write Enable (W). This input controls writing to the Command Register and Address and Data latches. Addresses are latched on the falling edge of W, and Data Inputs are latched on the rising edge of W. V CC Supply Voltage. The power supply for all operations (Read, Program and Erase).V SS Ground. V SS is the reference for all voltage measurements.4/31M29F040Mne.Instr.Cyc.1st Cyc.2nd Cyc.3rd Cyc.4th Cyc.5th Cyc.6th Cyc.7th Cyc.RST (4,10)Read Array/Reset 1+Addr.(3,7)XRead Memory Array until a new write cycle is initiated.Data F0h3+Addr.(3,7)5555h2AAAh5555h Read Memory Array until a new writecycle is initiated.Data AAh55h F0hRSIG (4)ReadElectronicSignature3+Addr.(3,7)5555h2AAAh5555h Read Electronic Signature until a newwrite cycle is initiated. See Note 5.Data AAh55h90hRBP (4)Read BlockProtection3+Addr.(3,7)5555h2AAAh5555h Read Block Protection until a new writecycle is initiated. See Note 6.Data AAh55h90hPG Program4Addr.(3,7)5555h2AAAh5555h ProgramAddress Read Data Polling or Toggle Bituntil Program completes.Data AAh55h A0h ProgramDataBE Block Erase6Addr.(3,7)5555h2AAAh5555h5555h2AAAh BlockAddressAdditionalBlock (8) Data AAh55h80h AAh55h30h30hCE Chip Erase6Addr.(3,7)5555h2AAAh5555h5555h2AAAh5555hNote 9 Data AAh55h80h AAh55h10hES EraseSuspend1Addr.(3,7)X Read until Toggle stops, then read all the data needed from anyuniform block(s) not being erased then Resume Erase.Data B0hER EraseResume1Addr.(3,7)X Read Data Polling or Toggle Bit until Erase completes or Eraseis suspended another timeData30hNotes:mand not interpreted in this table will default to read array mode.2.While writing any command or during RSG and RSP execution, the P/E.C. can be reset by writing the command 00h to the C.I.3.X = Don’t Care.4.The first cycle of the RST, RBP or RSIG instruction is followed by read operations to read memory array, Status Register orElectronic Signature codes. Any number of read cycles can occur after one command cycle.5.Signature Address bits A0, A1, A6 at V IL will output Manufacturer code (20h). Address bits A0 at V IH and A1, A6 at V IL will outputDevice code.6.Protection Address: A0, A6 at V IL, A1 at V IH and A16, A17, A18 within the uniform block to be checked, will output the Block Protectionstatus.7.Address bits A15-A18 are don’t care for coded address inputs.8.Optional, additional blocks addresses must be entered within a 80µs delay after last write entry, timeout status can be verifiedthrough DQ3 value. When full command is entered, read Data Polling or T oggle bit until Erase is completed or suspended.9.Read Data Polling or T oggle bit until Erase completes.10.A wait time of 5µs is necessary after a Reset command, if the memory is in a Block Erase status, before startingany operation.Table 6. Instructions (1,2)5/31M29F040Memory BlocksThe memory blocks of the M29F040 are shown in Figure 3. The memory array is divided in 8 uniform blocks of 64 Kbytes. Each block can be erased separately or any combination of blocks can be erased simultaneously. The Block Erase operation is managed automatically by the P/E.C. The opera-tion can be suspended in order to read from any other block, and then resumed.Block Protection provides additional data security. Each uniform block can be separately protected or unprotected against Program or Erase. Bringing A9 and G to V ID initiates protection, while bringing A9, G and E to V ID cancels the protection. The block affected during protection is addressed by the in-puts on A16, A17, and A18. Unprotect operation affects all blocks.OperationsOperations are defined as specific bus cycles and signals which allow Memory Read, Command Write, Output Disable, Standby, Read Status Bits, Block Protect/Unprotect, Block Protection Check and Electronic Signature Read. They are shown in Tables 3, 4, 5.Read. Read operations are used to output the contents of the Memory Array, the Status Register or the Electronic Signature. Both Chip Enable E and Output Enable G must be low in order to read the output of the memory. The Chip Enable input also provides power control and should be used for device selection. Output Enable should be used to gate data onto the output independent of the device selection. The data read depends on the previous command written to the memory (see instructions RST and RSIG, and Status Bits).Write. Write operations are used to give Instruction Commands to the memory or to latch input data to be programmed. A write operation is initiated when Chip Enable E is Low and Write Enable W is Low with Output Enable G High. Addresses are latched on the falling edge of W or E whichever occurs last. Commands and Input Data are latched on the rising edge of W or E whichever occurs first.Output Disable. The data outputs are high imped-ance when the Output Enable G is High with Write Enable W High.Standby. The memory is in standby when Chip Enable E is High and Program/Erase Controller P/E.C. is Idle. The power consumption is reduced to the standby level and the outputs are high im-pedance, independent of the Output Enable G or Write Enable W inputs.Automatic Standby. After 150ns of inactivity and when CMOS levels are driving the addresses, the chip automatically enters a pseudo standby mode where consumption is reduced to the CMOS standby value, while outputs are still driving the bus.Electronic Signature. Two codes identifying the manufacturer and the device can be read from the memory, the manufacturer’s code for STMicroelec-tronics is 20h, and the device code is E2h for the M29F040. These codes allow programming equip-ment or applications to automatically match their interface to the characteristics of the particular manufacturer’s product. The Electronic Signature is output by a Read operation when the voltage applied to A9 is at V ID and address inputs A1 and A6 are at Low. The manufacturer code is output when the Address input A0 is Low and the device code when this input is High. Other Address inputs are ignored. The codes are output on DQ0-DQ7. This is shown in Table 4.The Electronic Signature can also be read, without raising A9 to V ID by giving the memory the instruc-tion RSIG (see below).Block Protection. Each uniform block can be separately protected against Program or Erase. Block Protection provides additional data security, as it disables all program or erase operations. This mode is activated when both A9 and G are set to V ID and the block address is applied on A16-A18. Block Protection is programmed using a Presto F program like algorithm. Protection is initiated on the edge of W falling to V IL. Then after a delay of 100µs, the edge of W rising to V IH ends the protection operation. Protection verify is achieved by bringing G, E and A6 to V IL while W is at V IH and A9 at V ID. Under these conditions, reading the data output will yield 01h if the block defined by the inputs on A16-A18 is protected. Any attempt to program or erase a protected block will be ignored by the device.Any protected block can be unprotected to allow updating of bit contents. All blocks must be pro-tected before an unprotect operation. Block Un-protect is activated when A9, G and E are at V ID. The addresses inputs A6, A12, A16 must be main-tained at V IH. Block Unprotect is performed through a Presto F Erase like algorithm. Unprotect is initi-ated by the edge of W falling to V IL. After a delay of 10ms, the edge of W rising to V IH will end the unprotection operation. Unprotect verify is achieved by bringing G and E to V IL while A6 and W are at V IH and A9 at V ID. In these conditions, reading the output data will yield 00h if the block defined by the inputs on A16-A18 has been suc-cessfully unprotected. All combinations of A16-A18 must be addressed in order to ensure that all of the 8 uniform blocks have been unprotected. Block Protection Status is shown in Table 5.6/31M29F04064K Bytes Block AI01362B7FFFFh 6FFFFh 5FFFFh 4FFFFh 3FFFFh 2FFFFh 1FFFFh 0FFFFhTOP ADDRESS 70000h 60000h 50000h 40000h 30000h 20000h 10000h 00000hBOTTOM ADDRESS A181164K Bytes Block 64K Bytes Block64K Bytes Block 64K Bytes Block A1711A16101100100011100010Figure 3. Memory Map and Block Address TableHex Code Command00h Read10h Chip Erase Confirm30h Block Erase Resume/Confirm 80h Set-up Erase90h Read Electronic Signature/Block Protection Status A0h Program B0h Erase Suspend F0hRead Array/ResetTable 7. CommandsInstructions and CommandsThe Command Interface (C.I.) latches commands written to the memory. Instructions are made up from one or more commands to perform Read Array/Reset, Read Electronic Signature, Block Erase, Chip Erase, Program, Block Erase Suspend and Erase Resume. Commands are made of ad-dress and data sequences. Addresses are latched on the falling edge of W or E and data is latched on the rising of W or E. The instructions require from 1 to 6 cycles, the first or first three of which are always write operations used to initiate the com-mand. They are followed by either further write cycles to confirm the first command or execute the command immediately. Command sequencing must be followed exactly. Any invalid combination of commands will reset the device to Read Array.The increased number of cycles has been chosen to assure maximum data security. Commands are initialised by two preceding coded cycles which unlock the Command Interface. In addition, for Erase, command confirmation is again preceeded by the two coded cycles.P/E.C. status is indicated during command execu-tion by Data Polling on DQ7, detection of Toggle onDQ6, or Error on DQ5 and Erase Timer DQ3 bits.Any read attempt during Program or Erase com-mand execution will automatically output those four bits. The P/E.C. automatically sets bits DQ3, DQ5,DQ6 and DQ7. Other bits (DQ0, DQ1, DQ2 and DQ4) are reserved for future use and should be masked.7/31M29F040DQ Name Logic Level Definition Note7DataPolling’1’Erase CompleteIndicates the P/E.C. status, check duringProgram or Erase, and on completionbefore checking bits DQ5 for Program orErase Success.’0’Erase on GoingDQ Program CompleteDQ Program on Going6Toggle Bit ’-1-0-1-0-1-0-1-’Erase or Program on Going Successive read output complementarydata on DQ6 while Programming or Eraseoperations are going on. DQ6 remain atconstant level when P/E.C. operations arecompleted or Erase Suspend isacknowledged.’-0-0-0-0-0-0-0-’Program (’0’ on DQ6)Complete’-1-1-1-1-1-1-1-’Erase or Program(’1’ on DQ6) Complete5Error Bit ’1’Program or Erase Error This bit is set to ’1’ if P/E.C. has excededthe specified time limits.’0’Program or Erase on Going4’1’’0’3EraseTime Bit ’1’Erase Timeout Period Expired P/E.C. Erase operation has started. Onlypossible command entry is Erase Suspend(ES). An additional block to be erased inparallel can be entered to the P/E.C.’0’Erase Timeout Period onGoing2Reserved1Reserved0ReservedNote:Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations. Table 8. Status RegisterData Polling bit (DQ7). When Programming op-erations are in progress, this bit outputs the com-plement of the bit being programmed on DQ7. During Erase operation, it outputs a ’0’. After com-pletion of the operation, DQ7 will output the bit last programmed or a ’1’ after erasing. Data Polling is valid only effective during P/E.C. operation, that is after the fourth W pulse for programming or after the sixth W pulse for Erase. It must be performed at the address being programmed or at an address within the block being erased. If the byte to be programmed belongs to a protected block the com-mand is ignored. If all the blocks selected for era-sure are protected, DQ7 will set to ’0’ for about 100µs, and then return to previous addressed memory data. See Figure 9 for the Data Polling flowchart and Figure 10 for the Data Polling wave-forms.Toggle bit (DQ6). When Programming operations are in progress, successive attempts to read DQ6 will output complementary data. DQ6 will toggle following toggling of either G or E when G is low.The operation is completed when two successive reads yield the same output data. The next read will output the bit last programmed or a ’1’ after erasing. The toggle bit is valid only effective during P/E.C. operations, that is after the fourth W pulse for programming or after the sixth W pulse for Erase. If the byte to be programmed belongs to a protected block the command will be ignored. If the blocks selected for erasure are protected, DQ6 will toggle for about 100µs and then return back to Read. See Figure 11 for Toggle Bit flowchart and Figure 12 for Toggle Bit waveforms.Error bit (DQ5). This bit is set to ’1’ by the P/E.C when there is a failure of byte programming, block erase, or chip erase that results in invalid data being programmed in the memory block. In case of error in block erase or byte program, the block in which the error occured or to which the pro-grammed byte belongs, must be discarded. Other blocks may still be used. Error bit resets after Reset (RST) instruction. In case of success, the error bit will set to ’0’ during Program or Erase and to valid data after write operation is completed.8/31M29F040AI01275B3VHigh Speed0V1.5V2.4VStandard 0.45V2.0V 0.8VFigure 4. AC Testing Input Output Waveform AI01276B1.3VOUTC LC L = 30pF for High Speed C L = 100pF for Standard C L includes JIG capacitance3.3k Ω1N914DEVICE UNDER TESTFigure 5. AC Testing Load CircuitSymbol ParameterTest ConditionMinMax Unit C IN Input Capacitance V IN = 0V 6pF C OUTOutput CapacitanceV OUT = 0V12pFNote: 1.Sampled only, not 100% tested.Table 10. Capacitance (1) (T A = 25 °C, f = 1 MHz )Erase Timer bit (DQ3). This bit is set to ’0’ by the P/E.C. when the last Block Erase command has been entered to the Command Interface and it is awaiting the Erase start. When the wait period is finished, after 80 to 120µs, DQ3 returns back to ’1’.Coded Cycles. The two coded cycles unlock the Command Interface. They are followed by a com-mand input or a comand confirmation. The coded cycles consist of writing the data AAh at address 5555h during the first cycle and data 55h at address 2AAAh during the second cycle. Addresses are latched on the falling edge of W or E while data is latched on the rising edge of W or E. The coded cycles happen on first and second cycles of the command write or on the fourth and fifth cycles.Read Array/Reset (RST) instruction. The Reset instruction consists of one write operation giving the command F0h. It can be optionally preceded by the two coded cycles. A wait state of 5µs before read operations is necessary if the Reset command is applied during an Erase operation.Read Electronic Signature (RSIG) instruction.This instruction uses the two coded cycles followed by one write cycle giving the command 90h to address 5555h for command setup. A subsequent read will output the manufacturer code, the device code or the Block Protection status depending on the levels of A0, A1, A6, A16, A17 and A18. The manufacturer code, 20h, is output when the ad-dresses lines A0, A1 and A6 are Low, the device code, E2h is output when A0 is High with A1 and A6 Low.High SpeedStandard Input Rise and Fall Times ≤ 10ns ≤ 10ns Input Pulse Voltages0 to 3V 0.45V to 2.4V Input and Output Timing Ref. Voltages1.5V0.8V and 2VTable 9. AC Measurement Conditions9/31M29F040Symbol ParameterTest Condition MinMax Unit I LI Input Leakage Current 0V ≤ V IN ≤ V CC ±1µA I LO Output Leakage Current 0V ≤ V OUT ≤ V CC ±1µA I CC1Supply Current (Read) E = V IL , G = V IH , f = 6MHz15mA I CC2Supply Current (Standby) TTL E = V IH 1mA I CC3Supply Current (Standby) CMOS E = V CC ± 0.2V 50µA I CC4Supply Current (Program or Erase)Byte Program, Block Erase 20mA I CC5Supply Current Chip Erase in progress40mA V IL Input Low Voltage –0.50.8V V IH Input High Voltage 2V CC + 0.5V V OL Output Low Voltage I OL = 10mA 0.45V V OHOutput High Voltage TTLI OH = –2.5mA 2.4V Output High Voltage CMOSI OH = –100µA V CC –0.4V I OH = –2.5mA0.85 V CC V V ID A9 Voltage (Electronic Signature)11.512.5V I ID A9 Current (Electronic Signature)A9 = V ID50µA V LKOSupply Voltage (Erase and Program lock-out)3.24.2VTable 11. DC Characteristics(T A = 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C; V CC = 5V ± 10%)Read Block Protection (RBP) instruction. The use of Read Electronic Signature (RSIG) command also allows access to the Block Protection status verify. After giving the RSIG command, A0 and A6are set to V IL with A1 at V IH , while A16, A17 and A18 define the block of the block to be verified. A read in these conditions will output a 01h if block is protected and a 00h if block is not protected.This Read Block Protection is the only valid way to check the protection status of a block. Neverthe-less, it must not be used during the Block Protection phase as a method to verify the block protection.Please refer to Block Protection paragraph.Chip Erase (CE) instruction. This instruction uses six write cycles. The Erase Set-up command 80h is written to address 5555h on third cycle after the two coded cycles. The Chip Erase Confirm com-mand 10h is written at address 5555h on sixth cycle after another two coded cycles. If the second com-mand given is not an erase confirm or if the coded cycles are wrong, the instruction aborts and the device is reset to Read Array. It is not necessary to program the array with 00h first as the P/E.C. will automatically do this before erasing to FFh. Read operations after the sixth rising edge of W or E output the status register bits. During the execu-tion of the erase by the P/E.C. the memory accepts only the Reset (RST) command. Read of Data Polling bit DQ7 returns ’0’, then ’1’ on completion.The T oggle Bit DQ6 toggles during erase operation and stops when erase is completed. After comple-tion the Status Register bit DQ5 returns ’1’ if there has been an Erase Failure because the erasure has not been verified even after the maximum number of erase cycles have been executed.10/31M29F040SymbolAltParameterTest ConditionM29F040Unit-70-90V CC = 5V ± 5%V CC = 5V ± 10%Standard Interface Standard Interface MinMaxMin Maxt AVAV t RC Address Valid to Next Address Valid E = V IL , G = V IL 7090ns t AVQV t ACC Address Valid to Output Valid E = V IL , G = V IL7090ns t ELQX (1)t LZ Chip Enable Low to Output Transition G = V IL 0ns t ELQV (2)t CE Chip Enable Low to Output Valid G = V IL 7090ns t GLQX (1)t OLZ Output Enable Low to Output TransitionE = V IL 0ns t GLQV (2)t OE Output Enable Low to Output Valid E = V IL 3035ns t EHQX t OH Chip Enable High to Output TransitionG = V IL 0ns t EHQZ (1)t HZ Chip Enable High to Output Hi-Z G = V IL 2020ns t GHQX t OH Output Enable High to Output TransitionE = V IL 0ns t GHQZ (1)t DF Output Enable High to Output Hi-Z E = V IL 2020ns t AXQXt OHAddress Transition to Output TransitionE = V IL , G = V IL2020ns Notes:1.Sampled only, not 100% tested.2.G may be delayed by up to t ELQV - t GLQV after the falling edge of E without increasing t ELQV .3.The temperature range –40 to 125°C is guaranteed at 70ns with High Speed Interface test condition and V CC = 5V ± 5%.Table 12A. Read AC Characteristics(T A = 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C)(3)Block Erase (BE) instruction . This instruction uses a minimum of six write cycles. The Erase Set-up command 80h is written to address 5555h on third cycle after the two coded cycles. The Block Erase Confirm command 30h is written on sixth cycle after another two coded cycles. During the input of the second command an address within the block to be erased is given and latched into the memory. Additional Block Erase confirm com-mands and block addresses can be written sub-sequently to erase other blocks in parallel, without further coded cycles. The erase will start after an Erase timeout period of about 100µs. Thus, addi-tional Block Erase commands must be given within this delay. The input of a new Block Erase com-mand will restart the timeout period. The status of the internal timer can be monitored through the level of DQ3, if DQ3 is ’0’ the Block Erase Com-mand has been given and the timeout is running, if DQ3 is ’1’, the timeout has expired and the P/E.Cis erasing the block(s). Before and during Erase timeout, any command different from 30h will abort the instruction and reset the device to read array mode. It is not necessary to program the block with 00h as the P/E.C. will do this automatically before erasing to FFh. Read operations after the sixth rising edge of W or E output the status register bits.During the execution of the erase by the P/E.C., the memory accepts only the ES (Erase Suspend) and RST (Reset) instructions. Data Polling bit DQ7returns ’0’ while the erasure is in progress and ’1’when it has completed. The Toggle Bit DQ6 toggles during the erase operation. It stops when erase is completed. After completion the Status Register bit DQ5 returns ’1’ if there has been an Erase Failure because erasure has not completed even after the maximum number of erase cycles have been executed. In this case, it will be necessary to input a Reset (RST) to the command interface in order to reset the P/E.C.11/31。
NCV8843MNR2G资料
NCV88431.5 A, 340 kHz, Buck Regulator with Synchronization Capability The NCV8843 is a 1.5 A buck regulator IC operating at a fixed−frequency of 340 kHz. The device uses the V2t control architecture to provide unmatched transient response, the best overall regulation and the simplest loop compensation for today’s high−speed logic. The NCV8843 accommodates input voltages from 4.5 V to 40 V and contains synchronization circuitry.The on−chip NPN transistor is capable of providing a minimum of 1.5 A of output current, and is biased by an external “boost” capacitor to ensure saturation, thus minimizing on−chip power dissipation. Protection circuitry includes thermal shutdown, cycle−by−cycle current limiting and frequency foldback.Features•V2 Architecture Provides Ultra−Fast Transient Response, Improved Regulation and Simplified Design•2.0% Error Amp Reference V oltage Tolerance•Switch Frequency Decrease of 4:1 in Short Circuit Conditions Reduces Short Circuit Power Dissipation•BOOST Lead Allows “Bootstrapped” Operation to Maximize Efficiency•Sync Function for Parallel Supply Operation or Noise Minimization •Shutdown Lead Provides Power−Down Option•1.0 m A Quiescent Current During Power−Down•Thermal Shutdown•Soft−Start•Internally Fused Leads in SO−16L Package•NCV Prefix for Automotive and Other Applications Requiring Site and Control Changes•Pb−Free Packages are AvailableSee detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet.ORDERING INFORMATIONFigure 1. Application Diagram, 4.5 V − 16 V to 3.3 V @ 1.0 A ConverterVout (3.3 V)Vin (7 V to 16 V)R6SYNCm FMAXIMUM RATINGS*RatingValue Unit Peak Transient Voltage (31 V Load Dump @ V IN = 14 V)45V Operating Junction Temperature Range, T J −40 to 150°C Lead Temperature Soldering: Reflow: (Note 1)240 peak (Note 2)°C Storage Temperature Range, T S −65 to +150°C ESD(Human Body Model)(Machine Model)(Charge Device Model)2.0200>1.0kV V kV Package Thermal ResistanceSO−16 Junction−to−Case, R q JC SO−16 Junction−to−Ambient, R q JA18−Lead DFN Junction−to−Ambient, R q JA165735°C/W °C/W °C/WStresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.*The maximum package power dissipation must be observed.1.60 second maximum above 183°C.2.−5°C/0°C allowable conditions.MAXIMUM RATINGS (Voltages are with respect to GND)Pin Name V Max V MIN I SOURCE I SINK V IN (DC)*40 V −0.3 V N/A 4.0 A BOOST 40 V −0.3 VN/A 100 mA V SW 40 V −0.6 V/−1.0 V, t < 50 ns4.0 A 10 mA V C 7.0 V −0.3 V 1.0 mA 1.0 mA SHDNB 7.0 V −0.3 V 1.0 mA 1.0 mA SYNC 7.0 V −0.3 V 1.0 mA 1.0 mA V FB7.0 V−0.3 V1.0 mA1.0 mA*See table above for load dump.PACKAGE PIN DESCRIPTIONSO−8SO−16PIN SYMBOL FUNCTION115BOOST The BOOST pin provides additional drive voltage to the on−chip NPN power transistor. The resulting decrease in switch on voltage increases efficiency.216V IN This pin is the main power input to the IC.31V SWThis is the connection to the emitter of the on−chip NPN power transistor and serves as the switch output to the inductor. This pin may be subjected to nega-tive voltages during switch off−time. A catch diode is required to clamp the pin voltage in normal operation. This node can stand −1.0 V for less than 50 ns during switch node flyback.42SHDNBThe shutdown pin is active low and TTL compatible. The IC goes into sleep mode, drawing less than 1.0 m A when the pin voltage is pulled below 1.0 V. This pin should be left floating in normal position.57SYNC This pin provides the synchronization input.68GND Power return connection for the IC.79V FBThe FB pin provides input to the inverting input of the error amplifier. If V FB is lower than 0.29 V, the oscillator frequency is divided by four, and current limit folds back to about 1 A. These features protect the IC under severe overcurrent or short circuit conditions.810V CThe V C pin provides a connection point to the output of the error amplifier and input to the PWM comparator. Driving of this pin should be avoided because on−chip test circuitry becomes active whenever current exceeding 0.5 mA is forced into the IC.− 3 − 6, 11 − 14NCNo ConnectionPIN CONNECTIONS116V FBGNDV C SYNC NC NC NC NC NC NC NC NC BOOST SHDNBV INV SW 123456789181716151413121110BOOSTV IN V IN V IN Vsw V SW V SW SHDNBNC NC V C V FB NC NC GND NC NC SYNCSO−1618−Lead DFNELECTRICAL CHARACTERISTICS (−40°C < T J< 125°C, 4.5 V< V IN < 40V; unless otherwise specified.)Characteristic Test Conditions Min Typ Max Unit OscillatorOperating Frequency−306340374kHz Frequency Line Regulation−−0.050.15%/V Maximum Duty Cycle−859095% V FB Frequency Foldback Threshold−0.290.320.36V PWM ComparatorSlope Compensation Voltage Fix V FB,D V C/D T ON 5.09.017mV/m s Minimum Output Pulse Width V FB to V SW−100200ns Power SwitchCurrent Limit V FB > 0.36 V 1.6 2.3 3.0A Foldback Current V FB < 0.29 V0.9 1.5 2.1A Saturation Voltage I OUT = 1.5 A, V BOOST = V IN + 2.5 V0.40.7 1.0V Current Limit Delay(Note 3)−120160ns Error AmplifierInternal Reference Voltage− 1.244 1.270 1.296V Reference PSRR(Note 3)−40−dB FB Input Bias Current−−0.020.1m A Output Source Current V C = 1.270 V, V FB = 1.0 V152535m A Output Sink Current V C = 1.270 V, V FB = 2.0 V152535m A Output High Voltage V FB = 1.0 V 1.39 1.46 1.53V Output Low Voltage V FB = 2.0 V 5.02060mV Unity Gain Bandwidth(Note 3)−500−kHz Open Loop Amplifier Gain(Note 3)−70−dB Amplifier Transconductance(Note 3)− 6.4−mA/V SyncSync Frequency Range−377−710kHz Sync Pin Bias Current V SYNC = 5.0 V−360485m A Sync Threshold Voltage−0.9 1.5 1.9V ShutdownShutdown Threshold Voltage− 1.0 1.3 1.6V Shutdown Pin Bias Current V SHDNB = 0 V0.14 5.0035m A Thermal ShutdownOvertemperature Trip Point(Note 3)175185195°C Thermal Shutdown Hysteresis(Note 3)−42−°C 3.Guaranteed by design, not 100% tested in production.ELECTRICAL CHARACTERISTICS (continued) (−40°C < T J< 125°C, 4.5 V< V IN < 40V; unless otherwise specified.)Test ConditionsTypMinCharacteristic UnitMaxGeneralQuiescent Current I SW = 0 A− 4.07.5mA Shutdown Quiescent Current V SHDNB = 0 V− 1.0 5.0m A Boost Operating Current V BOOST − V SW = 2.5 V 6.01540mA/A Minimum Boost Voltage(Note 4)−− 2.5V Startup Voltage− 2.2 3.3 4.4V Minimum Output Current−−7.012mA 4.Guaranteed by design, not 100% tested in production.V INBOOSTSWVV CFigure 2. Block DiagramAPPLICATIONS INFORMATIONTHEORY OF OPERATIONV 2 ControlThe NCV8843 buck regulator provides a high level of integration and high operating frequencies allowing the layout of a switch−mode power supply in a very small board area. This device is based on the proprietary V 2 control architecture. V 2 control uses the output voltage and its ripple as the ramp signal, providing an ease of use not generally associated with voltage or current mode control. Improved line regulation, load regulation and very fast transient response are also major advantages.Figure 3. Buck Converter with V 2 Control.V OAs shown in Figure 3, there are two voltage feedback paths in V 2 control, namely FFB(Fast Feedback) and SFB(Slow Feedback). In FFB path, the feedback voltage connects directly to the PWM comparator. This feedback path carries the ramp signal as well as the output DC voltage.Artificial ramp derived from the oscillator is added to the feedback signal to improve stability. The other feedback path, SFB, connects the feedback voltage to the error amplifier whose output V C feeds to the other input of the PWM comparator. In a constant frequency mode, the oscillator signal sets the output latch and turns on the switch S1. This starts a new switch cycle. The ramp signal,composed of both artificial ramp and output ripple,eventually comes across the V C voltage, and consequently resets the latch to turn off the switch. The switch S1 will turn on again at the beginning of the next switch cycle. In a buck converter, the output ripple is determined by the ripple current of the inductor L1 and the ESR (equivalent series resistor) of the output capacitor C1.The slope compensation signal is a fixed voltage ramp provided by the oscillator. Adding this signal eliminates subharmonic oscillation associated with the operation at duty cycle greater than 50%. The artificial ramp also ensures the proper PWM function when the output ripple voltage is inadequate. The slope compensation signal is properly sized to serve it purposes without sacrificing the transient response speed.Under load and line transient, not only the ramp signal changes, but more significantly the DC component of the feedback voltage varies proportionally to the output voltage.FFB path connects both signals directly to the PWM comparator. This allows instant modulation of the duty cycle to counteract any output voltage deviations. The transient response time is independent of the error amplifier bandwidth. This eliminates the delay associated with error amplifier and greatly improves the transient response time.The error amplifier is used here to ensure excellent DC accuracy.Error AmplifierThe NCV8843 has a transconductance error amplifier,whose non−inverting input is connected to an Internal Reference V oltage generated from the on−chip regulator.The inverting input connects to the V FB pin. The output of the error amplifier is made available at the V C pin. A typical frequency compensation requires only a 0.1 m F capacitor connected between the V C pin and ground, as shown in Figure 1. This capacitor and error amplifier’s output resistance (approximately 8.0 M W ) create a low frequency pole to limit the bandwidth. Since V 2 control does not require a high bandwidth error amplifier, the frequency compensation is greatly simplified.The V C pin is clamped below Output High V oltage. This allows the regulator to recover quickly from over current or short circuit conditions.Oscillator and Sync FeatureThe on−chip oscillator is trimmed at the factory and requires no external components for frequency control. The high switching frequency allows smaller external components to be used, resulting in a board area and cost savings. The tight frequency tolerance simplifies magnetic components selection. The switching frequency is reduced to 25% of the nominal value when the V FB pin voltage is below Frequency Foldback Threshold. In short circuit or over−load conditions, this reduces the power dissipation of the IC and external components.An external clock signal can sync the NCV8843 to a higher frequency. The rising edge of the sync pulse turns on the power switch to start a new switching cycle, as shown in Figure 4. There is approximately 0.5 m s delay between the rising edge of the sync pulse and rising edge of the V SW pin voltage. The sync threshold is TTL logic compatible, andduty cycle of the sync pulses can vary from 10% to 90%. The frequency foldback feature is disabled during the syncmode.Figure 4. A NCV8843 Buck Regulator isSynchronized to an External 443 kHz Pulse Signal Power Switch and Current LimitThe collector of the built−in NPN power switch is connected to the V IN pin, and the emitter to the V SW pin.When the switch turns on, the V SW voltage is equal to the V IN minus switch Saturation V oltage. In the buck regulator,the V SW voltage swings to one diode drop below ground when the power switch turns off, and the inductor current is commutated to the catch diode. Due to the presence of high pulsed current, the traces connecting the V SW pin, inductor and diode should be kept as short as possible to minimize the noise and radiation. For the same reason, the input capacitor should be placed close to the V IN pin and the anode of the diode.The saturation voltage of the power switch is dependent on the switching current, as shown in Figure 5.Figure 5. The Saturation Voltage of the Power SwitchIncreases with the Conducting Current0.5 1.0 1.5SWITCHING CURRENT (A)V I N − V S W (V )The NCV8843 contains pulse−by−pulse current limiting to protect the power switch and external components. When the peak of the switching current reaches the Current Limit,the power switch turns off after the Current Limit Delay. The switch will not turn on until the next switching cycle. The current limit threshold is independent of switching duty cycle. The maximum load current, given by the following formula under continuous conduction mode, is less than the Current Limit due to the ripple current.I O(MAX)+I LIM *V O (V IN*V O )2(L)(V IN )(f s )where:f S = switching frequency,I LIM = current limit threshold,V O = output voltage,V IN = input voltage,L = inductor value.When the regulator runs under current limit, the subharmonic oscillation may cause low frequency oscillation, as shown in Figure 6. Similar to current mode control, this oscillation occurs at the duty cycle greater than 50% and can be alleviated by using a larger inductor value.The current limit threshold is reduced to Foldback Current when the FB pin falls below Foldback Threshold. This feature protects the IC and external components under the power up or over−load conditions.Figure 6. The Regulator in Current LimitWhen the power switch is turned on, the voltage on the BOOST pin is equal toV BOOST +V IN )V O *V Fwhere:V F = diode forward voltage.The anode of the diode can be connected to any DC voltage as well as the regulated output voltage (Figure 1).However, the maximum voltage on the BOOST pin shall not exceed 40 V .As shown in Figure 7, the BOOST pin current includes a constant 7.0 mA pre−driver current and base current proportional to switch conducting current. A detailed discussion of this current is conducted in Thermal Consideration section. A 0.1 m F capacitor is usually adequate for maintaining the Boost pin voltage during the on time.Figure 7. The Boost Pin Current Includes 7.0 mA Pre−Driver Current and Base Current when the Switch is Turned On. The Beta Decline of the Power Switch Further Increases the BaseCurrent at High Switching Current SWITCHING CURRENT (A)B O O S T P I NC U R R E N T (m A )ShutdownThe internal power switch will not turn on until the V IN pin rises above the Startup V oltage. This ensures no switching will occur until adequate supply voltage is provided to the IC.The IC enters a sleep mode when the SHDNB pin is pulled below the Shutdown Threshold V oltage. In sleep mode, the power switch is kept open and the supply current reduces to Shutdown Quiescent Current (1 m A typically). This pin hasan internal pull−down current. When not in use, pull this pin up to V CC with a resistor (See Figure 1).StartupDuring power up, the regulator tends to quickly charge up the output capacitors to reach voltage regulation. This gives rise to an excessive in−rush current which can be detrimental to the inductor, IC and catch diode. In V 2 control , the compensation capacitor provides Soft−Start with no need for extra pin or circuitry. During the power up, the Output Source Current of the error amplifier charges the compensation capacitor which forces V C pin and thus output voltage ramp up gradually. The Soft−Start duration can be calculated byT SS +V CC COMPI SOURCEwhere:V C = V C pin steady−state voltage, which is approximatelyequal to error amplifier’s reference voltage.C COMP = Compensation capacitor connected to the V C pin I SOURCE = Output Source Current of the error ing a 0.1 m F C COMP , the calculation shows a T SS over 5.0 ms which is adequate to avoid any current stresses.Figure 8 shows the gradual rise of the V C , V O and envelope of the V SW during power up. There is no voltage over−shoot after the output voltage reaches the regulation. If the supply voltage rises slower than the V C pin, output voltage may over−shoot.Figure 8. The Power Up Transition of NCV8843RegulatorShort CircuitWhen the V FB pin voltage drops below Foldback Threshold, the regulator reduces the peak current limit by 40% and switching frequency to 1/4 of the nominal frequency. These features are designed to protect the IC and external components during over load or short circuit conditions. In those conditions, peak switching current is clamped to the current limit threshold. The reduced switching frequency significantly increases the ripple current, and thus lowers the DC current. The short circuit can cause the minimum duty cycle to be limited by Minimum Output Pulse Width. The foldback frequency reduces the minimum duty cycle by extending the switching cycle. This protects the IC from overheating, and also limits the power that can be transferred to the output. The current limit foldback effectively reduces the current stress on the inductor and diode. When the output is shorted, the DC current of the inductor and diode can approach the current limit threshold. Therefore, reducing the current limit by 40% can result in an equal percentage drop of the inductor and diode current. The short circuit waveforms are captured in Figure 9, and the benefit of the foldback frequency and current limit is self−evident.Figure 9. In Short Circuit, the Foldback Current and Foldback Frequency Limit the Switching Current toProtect the IC, Inductor and Catch Diode Thermal ConsiderationsA calculation of the power dissipation of the IC is always necessary prior to the adoption of the regulator. The current drawn by the IC includes quiescent current, pre−driver current, and power switch base current. The quiescent current drives the low power circuits in the IC, which include comparators, error amplifier and other logic blocks. Therefore, this current is independent of the switching current and generates power equal toW Q+V IN I Qwhere:I Q = quiescent current.The pre−driver current is used to turn on/off the power switch and is approximately equal to 12 mA in worst case. During steady state operation, the IC draws this current from the Boost pin when the power switch is on and then receives it from the V IN pin when the switch is off. The pre−driver current always returns to the V SW pin. Since the pre−driver current goes out to the regulator’s output even when the power switch is turned off, a minimum load is required to prevent overvoltage in light load conditions. If the Boost pin voltage is equal to V IN + V O when the switch is on, the power dissipation due to pre−driver current can be calculated by W DRV+12mA(V IN*V O)V O2IN)The base current of a bipolar transistor is equal to collector current divided by beta of the device. Beta of 60 is used here to estimate the base current. The Boost pin provides the base current when the transistor needs to be on. The power dissipated by the IC due to this current isW BASE+V O2V INI S60where:I S = DC switching current.When the power switch turns on, the saturation voltage and conduction current contribute to the power loss of a non−ideal switch. The power loss can be quantified asW SAT+V OV INI S V SATwhere:V SAT = saturation voltage of the power switch which is shown in Figure 5.The switching loss occurs when the switch experiences both high current and voltage during each switch transition. This regulator has a 30 ns turn−off time and associated power loss is equal toW S+I S V IN230ns f SThe turn−on time is much shorter and thus turn−on loss is not considered here.The total power dissipated by the IC is sum of all the above W IC+W Q)W DRV)W BASE)W SAT)W S The IC junction temperature can be calculated from the ambient temperature, IC power dissipation and thermal resistance of the package. The equation is shown as follows,T J+W IC R q JA)T AMinimum Load RequirementAs pointed out in the previous section, a minimum load is required for this regulator due to the pre−driver current feeding the output. Placing a resistor equal to V O divided by 12 mA should prevent any voltage overshoot at light load conditions. Alternatively, the feedback resistors can be valued properly to consume 12 mA current.COMPONENT SELECTIONInput CapacitorIn a buck converter, the input capacitor witnesses pulsed current with an amplitude equal to the load current. This pulsed current and the ESR of the input capacitors determine the V IN ripple voltage, which is shown in Figure 10. For V IN ripple, low ESR is a critical requirement for the input capacitor selection. The pulsed input current possesses a significant AC component, which is absorbed by the input capacitors. The RMS current of the input capacitor can be calculated using:I RMS +I O D(1*D)Ǹwhere:D = switching duty cycle which is equal to V O /V IN .I O = load current.Figure 10. Input Voltage Ripple in a Buck ConverterDUTY CYCLEI R M S (X I O )Selecting the capacitor type is determined by each design’s constraint and emphasis. The aluminum electrolytic capacitors are widely available at lowest cost.Their ESR and ESL (equivalent series inductor) are relatively high. Multiple capacitors are usually paralleled to achieve lower ESR. In addition, electrolytic capacitors usually need to be paralleled with a ceramic capacitor for filtering high frequency noises. The OS−CON are solid aluminum electrolytic capacitors, and therefore has a much lower ESR. Recently, the price of the OS−CON capacitors has dropped significantly so that it is now feasible to use them for some low cost designs. Electrolytic capacitors are physically large, and not used in applications where the size,and especially height is the major concern.Ceramic capacitors are now available in values over 10 m F.Since the ceramic capacitor has low ESR and ESL, a single ceramic capacitor can be adequate for both low frequency and high frequency noises. The disadvantage of ceramic capacitors are their high cost. Solid tantalum capacitors can have low ESR and small size. However, the reliability of the tantalum capacitor is always a concern in the application where the capacitor may experience surge current.Output CapacitorIn a buck converter, the requirements on the output capacitor are not as critical as those on the input capacitor.The current to the output capacitor comes from the inductor and thus is triangular. In most applications, this makes the RMS ripple current not an issue in selecting output capacitors.The output ripple voltage is the sum of a triangular wave caused by ripple current flowing through ESR, and a square wave due to ESL. Capacitive reactance is assumed to be small compared to ESR and ESL. The peak to peak ripple current of the inductor is:I P *P +V O (V IN*V O )(V IN )(L)(f S )V RIPPLE(ESR), the output ripple due to the ESR, is equal to the product of I P−P and ESR. The voltage developed across the ESL is proportional to the di/dt of the output capacitor. It is realized that the di/dt of the output capacitor is the same as the di/dt of the inductor current. Therefore,when the switch turns on, the di/dt is equal to (V IN − V O )/L,and it becomes V O /L when the switch turns off. The total ripple voltage induced by ESL can then be derived fromV RIPPLE(ESL)+ESL(VO L ))ESL(V IN *V O L)+ESL(VIN L )The total output ripple is the sum of the V RIPPLE(ESR) andV RIPPLE(ESL).Figure 12. The Output Voltage Ripple Using Two 10 m FCeramic Capacitors in Parallel Figure 13. The Output Voltage Ripple Using One 100 m F POSCAP CapacitorFigure 14. The Output Voltage Ripple UsingOne 100 m F OS−CON Figure 15. The Output Voltage Ripple Using One 100 m F Tantalum CapacitorFigure 12 to Figure 15 show the output ripple of a 5.0 V to 3.3 V/500 mA regulator using 22 m H inductor and various capacitor types. At the switching frequency, the low ESR and ESL make the ceramic capacitors behave capacitively as shown in Figure 12. Additional paralleled ceramic capacitors will further reduce the ripple voltage, but inevitably increase the cost. “POSCAP”, manufactured by SANYO, is a solid electrolytic capacitor. The anode is sintered tantalum and the cathode is a highly conductive polymerized organic semiconductor. TPC series, featuring low ESR and low profile, is used in the measurement of Figure 13. It is shown that POSCAP presents a good balance of capacitance and ESR, compared with a ceramic capacitor. In this application, the low ESR generates less than 5.0 mV of ripple and the ESL is almost unnoticeable. The ESL of the through−hole OS−CON capacitor give rise to the inductive impedance. It is evident from Figure 14 which shows the step rise of the output ripple on the switch turn−on and large spike on the switch turn−off. The ESL prevents the output capacitor from quickly charging up the parasitic capacitor of the inductor when the switch node is pulled below ground through the catch diode conduction. This results in the spike associated with the falling edge of the switch node. The D package tantalum capacitor used in Figure 15 has the same footprint as the POSCAP, but doubles the height. The ESR of the tantalum capacitor is apparently higher than the POSCAP. The electrolytic and tantalum capacitors provide a low−cost solution with compromised performance. The reliability of the tantalum capacitor is not a serious concern for output filtering because the output capacitor is usually free of surge current and voltage.Diode SelectionThe diode in the buck converter provides the inductor current path when the power switch turns off. The peak reverse voltage is equal to the maximum input voltage. The peak conducting current is clamped by the current limit of the IC. The average current can be calculated from:I D(AVG)+I O(V IN*V O)V INThe worse case of the diode average current occurs during maximum load current and maximum input voltage. For the diode to survive the short circuit condition, the current rating of the diode should be equal to the Foldback Current Limit. See Table 1 for Schottky diodes from ON Semiconductor which are suggested for use with the NCV8843 regulator. Inductor SelectionWhen choosing inductors, one might have to consider maximum load current, core and copper losses, component height, output ripple, EMI, saturation and cost. Lower inductor values are chosen to reduce the physical size of the inductor. Higher value cuts down the ripple current, core losses and allows more output current. For most applications, the inductor value falls in the range between 2.2 m H and 22 m H. The saturation current ratings of the inductor shall not exceed the I L(PK), calculated according toI L(PK)+I O)V O(V IN*V O)2(f S)(L)(V IN)The DC current through the inductor is equal to the loadcurrent. The worse case occurs during maximum loadcurrent. Check the vendor’s spec to adjust the inductor valueunder current loading. Inductors can lose over 50% ofinductance when it nears saturation.The core materials have a significant effect on inductorperformance. The ferrite core has benefits of small physicalsize, and very low power dissipation. But be careful not tooperate these inductors too far beyond their maximumratings for peak current, as this will saturate the core.Powered Iron cores are low cost and have a more gradualsaturation curve. The cores with an open magnetic path, suchas rod or barrel, tend to generate high magnetic fieldradiation. However, they are usually cheap and small. Thecores providing a close magnetic loop, such as pot−core andtoroid, generate low electro−magnetic interference (EMI).There are many magnetic component vendors providingstandard product lines suitable for the NCV8843. Table 2lists three vendors, their products and contact information.Table 1.Part Number V BREAKDOWN (V)I AVERAGE (A)V(F) (V) @ I AVERAGE Package 1N581720 1.00.45Axial Lead 1N581830 1.00.55Axial Lead 1N581940 1.00.6Axial Lead MBR0520200.50.385SOD−123 MBR0530300.50.43SOD−123 MBR0540400.50.53SOD−123 MBRS12020 1.00.55SMBMBRS13030 1.00.395SMBMBRS14040 1.00.6SMBTable 2.Vendor Product Family Web Site Telephone Coiltronics UNI−Pac1/2: SMT, barrelTHIN−PAC: SMT, toroid, low profileCTX: Leaded, toroid(516) 241−7876Coilcraft DO1608: SMT, barrelDS/DT 1608: SMT, barrel, magnetically shieldedDO3316: SMT, barrelDS/DT 3316: SMT, barrel, magnetically shieldedDO3308: SMT, barrel, low profile(800) 322−2645 Pulse−(619) 674−8100。
STPD0175BTC3资料
®STPC CLIENT PC Compatible Embedded MicroprocessorFebruary8,2000Figure1.Logic Diagram•POWERFUL X86PROCESSOR •64-BIT66MHz BUS INTERFACE •64-BIT DRAM CONTROLLER •SVGA GRAPHICS CONTROLLER •UMA ARCHITECTURE •VIDEO SCALER•VIDEO OUTPUT PORT •VIDEO INPUT PORT•CRT CONTROLLER•135MHz RAMDAC•2OR3LINE FLICKER FILTER•SCAN CONVERTER•PCI MASTER/SLAVE/ARBITER•ISA MASTER/SLAVE•IDE CONTROLLER•DMA CONTROLLER•INTERRUPT CONTROLLER•TIMER/COUNTERS•POWER MANAGEMENTSTPC CLIENT OVERVIEWThe STPC Client integrates a standard5th generation x86core,a DRAM controller,a graphics subsystem,a video pipeline,and support logic including PCI,ISA,and IDE controllers to provide a single Consumer orientated PC compatible subsystem on a single device.The device is based on a tightly coupled Unified Memory Architecture(UMA),sharing the same memory array between the CPU main memory and the graphics and video frame buffers.Extra facilities are implemented to handle video streams.Features include smooth scaling and colour space conversion of the video input stream and mixing of the video stream with non-video data from the frame buffer.The chip also includes anti-flicker filters to provide a stable,high-quality Digital TV output.The STPC Client is packaged in a388Plastic Ball Grid Array(PBGA).PBGA388x86CoreHost I/FDRAMVIPPCI PCI BUSISAEIDPCIISA BUSCRT HWMonitorTV OutputSYNC OutputCol-Col-ourVid-CCIR InputEIDE2DAnti-IPCIssue1.71/48STPC CLIENT2/48Issue 1.7-February 8,2000•X86Processor core•Fully static 32-bit 5-stage pipeline,x86proc-essor with DOS,Windows and UNIX compat-ibility.•Can access up to 4GB of external memory.•KBytes unified instruction and data cache with write back and write through capability .•Parallel processing integral floating point unit,with automatic power down.•Clock core speeds up to of 75MHz.•Fully static design for dynamic clock control.•Low power and system management modes.•Optimized design for 3.3V operation.•DRAM Controller•Integrated system memory and graphic frame memory.•Supports up to 128MBytes system memory in 4banks and as little as MBytes.•Supports 4MBytes,8MBites,16MBites,32MBites single-sided and double-sided DRAM SIMMs.•Four quad-word write buffers for CPU to DRAM and PCI to DRAM cycles.•Four 4-word read buffers for PCI masters.•Supports Fast Page Mode &EDO DRAMs.•Programmable timing for DRAM parameters including CAS pulse width,CAS pre-charge time,and RAS to CAS delay .•60,70,80&100ns DRAM speeds.•Memory hole size of 1MByte to 8MBytes supported for PCI/ISA buses.•Hidden refresh.To check if your memory device is supported by the STPC,please refer to Table 7-69in the Programming Manual.•Graphics Controller•64-bit windows accelerator .•Backward compatibility to SVGA standards.•Hardware acceleration for text,bitblts,trans-parent blts and fills.•Up to 64x 64bit graphics hardware cursor.•Up to 4MB long linear frame buffer.•8-,16-,and 24-bit pixels.•CRT Controller•Integrated 135MHz triple RAMDAC allowing up to 1024x 768x 75Hz display .•8-,16-,24-bit per pixels.•Interlaced or non-interlaced output.•Video Pipeline•Two-tap interpolative horizontal filter.•Two-tap interpolative vertical filter.•Colour space conversion (RGB to YUV and YUV to RGB).•Programmab le window size.•Chroma and colour keying allowing video overlay .•Programmab le two tap filter with gamma cor-rection or three tap flicker filter.•Progressive to interlaced scan converter.•Video Input port•Decodes video inputs in ITU-R 601/656com-patible formats.•Optional 2:1decimator•Stores captured video in off setting area of the onboard frame buffer.•Video pass through to the onboard PAL/NTSC encoder for full screen video images.•HSYNC and B/T generation or lock onto external video timing source.•PCI Controller•Integrated PCI arbitration interface able to directly manage up to 3PCI masters at a time.•Translation of PCI cycles to ISA bus.•Translation of ISA master initiated cycle to PCI.•Support for burst read/write from PCI master.•The PCI clock runs at a third or half CPU clock speed.STPC CLIENTIssue 1.7-February 8,20003/48•ISA master/slave•The ISA clock generated from either 14.318MHz oscillator clock or PCI clock •Supports programmable extra wait state for ISA cycles•Supports I/O recovery time for back to back I/O cycles.•Fast Gate A20and Fast reset.•Supports the single ROM that C,D,or E.blocks shares with F block BIOS ROM.•Supports flash ROM.•Buffered DMA &ISA master cycles to reduce bandwidth utilization of the PCI and Host bus.•IDE Interface •Supports PIO•Supports up to Mode 5Timings •Supports up to 4IDE devices•Individual drive timing for all four IDE devices •Concurrent channel operation (PIO modes)-4x 32-Bit Buffer FIFO per channel •Support for PIO mode 3&4•Support for 11.1/16.6MB/s,I/O Channel Ready PIO data transfers.•Supports both legacy &native IDE modes •Supports hard drives larger than 528MB •Support for CD-ROM and tape peripherals •Backward compatibility with IDE (A TA-1).•Integrated peripheral controller•2X8237/A T compatible 7-channel DMA con-troller.•2X8259/A T compatible interrupt Controller.16interrupt inputs -ISA and PCI.•Three 8254compatible Timer/Counters.•Power Management•Four power saving modes:On,Doze,Stand-by,Suspend.•Programmab le system activity detector •Supports SMM.•Supports STOPCLK.•Supports IO trap &restart.•Independent peripheral time-out timer to monitor hard disk,serial ¶llel ports.•Supports RTC,interrupts and DMAs wake-upSTPC CLIENT4/48Issue1.7-February8,2000UPDATE HISTORY FOR OVERVIEWIssue 1.7-February 8,20005/48UPDATE HISTORY FOR OVERVIEWThe following changes have been made to the Board Layout Chapter on 02/02/2000.The following changes have been made to the Board Layout Chapter from Revision 1.0to Release 1.2.SectionChange TextAddedTo check if your memory device is supported by the STPC,please refer to Table 7-69Host Address to MA Bus Mappingin the Programming Manual.Section Change TextN/A Replaced “fully PC compatible”With “with DOS,Windows and UNIX compatibility”N/A Replaced “133MHz ”With 75MHz”N/A Removed “Drivers for Windows and other operating systems.”N/A Removed “Requires external frequency synthesizer and reference sources.”N/A Replaced “Chroma and colour keying for integrated video overlay .”With “Chroma and colour keying allowing video overlay .N/AReplaced“Accepts video inputs in CCIR 601/656or ITU-R 601/656,and decodes the stream .”With “Decodes video inputs in ITU-R 601/656compatible formats .N/A Replaced“Fully compliant with PCI 2.1specification.Integrated PCI arbitration interface.Up to 3masters can connect directly.External P AL allows for greater than 3masters.”With“Integrated PCI arbitration interface able to directly manage up to 3PCI masters at a time.”N/A Replaced “0.33X and 0.5X CPU clock PCI clock.”With “The PCI clock runs at a third or half CPU clock speed.”N/A Removed “Supports flash ROM.”N/A Replaced “Supports ISA hidden refresh.”With “Supports flash ROM.”N/A Replaced “Buffered DMA &ISA master cycles to reduce bandwidth utilization of the PCI and Host bus.NSP compliant.”With “Buffered DMA &ISA master cycles to reduce bandwidth utilization of the PCI and Host bus.“N/A Replaced “Supports PIO and Bus Master IDE”With “Supports PIO”N/A Removed “Transfer Rates to 22MBytes/sec”N/AAdded“Individual drive timing for all four IDE devices “N/A Replaced“Concurrent channel operation (PIO &DMA modes)-4x 32-Bit Buffer FIFO per channel”With“Concurrent channel operation (PIO modes)-4x 32-Bit Buffer FIFO per channel”N/A Removed“Support for DMA mode 1&2.”“Support for 11.1/16.6MB/s,I/O Channel Ready PIO data transfers.”“Supports 13.3/16.6MB/s DMA data transfers”“Bus Master with scatter/gather capability ““Multi-word DMA support for fast IDE drives ““Individual drive timing for all four IDE devices ““Supports both legacy &native IDE modes”“Supports hard drives larger than 528MB”“Support for CD-ROM and tape peripherals”“Backward compatibility with IDE (ATA-1).”“Drivers for Windows and other OSes”UPDATE HISTORY FOR OVERVIEW6/48Issue 1.7-February 8,2000N/A Added“Support for 11.1/16.6MB/s,I/O Channel Ready PIO data transfers.”“Supports both legacy &native IDE modes”“Supports hard drives larger than 528MB”“Support for CD-ROM and tape peripherals”“Backward compatibility with IDE (ATA-1).”N/A Removed “Co-processor error support logic.”N/A Replaced “Supports SMM and APM”With “Supports SMM”N/ARemoved“Slow system clock down to 8MHz”“Slow Host clock down to 8Hz”“Slow graphic clock down to 8Hz”SectionChangeTextGENERAL DESCRIPTIONIssue 1.7-February 8,20007/481.GENERAL DESCRIPTIONAt the heart of the STPC Client is an advanced processor block,dubbed the ST X86.The ST X86includes a powerful x86processor core along with a 64-bit DRAM controller,advanced 64bit acceler-ated graphics and video controller,a high speed PCI local-bus controller and Industry standard PC chip set functions (Interrupt controller,DMA Con-troller,Interval timer and ISA bus)and EIDE con-troller.The STPC Client has in addition to the 5ST86a Video subsystem and high quality digital Televi-sion output.The STMicroelectronics x86processor core is em-bedded with standard and application specific pe-ripheral modules on the same silicon die.The core has all the functionality of the ST Microelectronics standard x86processor products,including the low power System Management Mode (SMM).System Management Mode (SMM)provides an additional interrupt and address space that can be used for system power management or software transparent emulation of peripherals.While run-ning in isolated SMM address space,the SMM in-terrupt routine can execute without interfering with the operating system or application programs.Further power management facilities include a suspend mode that can be initiated from either hardware or software.Because of the static nature of the core,no internal data is lost.The STPC Client makes use of a tightly coupled Unified Memory Architecture (UMA),where the same memory array is used for CPU main memo-ry and graphics frame-buffer.This significantly re-duces total system memory with system perform-ances equal to that of a comparable solution with separate frame buffer and system memory.In ad-dition,memory bandwidth is improved by attach-ing the graphics engine directly to the 64-bit proc-essor host interface running at the speed of the processor bus rather than the traditional PCI bus.The 64-bit wide memory array provides the sys-tem with 320MB/s peak bandwidth,double that of an equivalent system using 32bits.This allows for higher screen resolutions and greater colour depth.The processor bus runs at the speed of the processor (DX devices)or half the speed (DX2de-vices).The ‘standard’PC chipset functions (DMA,inter-rupt controller,timers,power management logic)are integrated with the x86processor core.The PCI bus is the main data communication link to the STPC Client chip.The STPC Client trans-lates appropriate host bus I/O and Memory cycles onto the PCI bus.It also supports the generation of Configuration cycles on the PCI bus.The STPC Client,as a PCI bus agent (host bridge class),fully complies with PCI specification 2.1.The chip-set also implements the PCI mandatory header regis-ters in Type 0PCI configuration space for easy porting of PCI aware system BIOS.The device contains a PCI arbitration function for three exter-nal PCI devices.The STPC Client integrates an ISA bus controller.Peripheral modules such as parallel and serial communications ports,keyboard controllers and additional ISA devices can be accessed by the STPC Client chip set through this bus.An industry standard EIDE (ATA 2)controller is built into the STPC Client and connected internally via the PCI bus.Graphics functions are controlled by the on-chip SVGA controller and the monitor display is man-aged by the 2D graphics display engine.This Graphics Engine is tuned to work with the host CPU to provide a balanced graphics system with a low silicon area cost.It performs limited graphics drawing operations,which include hard-ware acceleration of text,bitblts,transparent blts and fills.These operations can operate on off-screen or on-screen areas.The frame buffer size is up to 4MBytes anywhere in the physical main memory.The graphics resolution supported is a maximum of 1280x1024in 65536colours at 75Hz refresh rate and is VGA and SVGA compatible.Horizontal timing fields are VGA compatible while the vertical fields are extended by one bit to accommodate above display resolution.STPC Client provides several additional functions to handle MPEG or similar video streams.The Video Input Port accepts an encoded digital video stream in one of a number of industry standard formats,decodes it,optionally decimates it by a factor of 2:1,and deposits it into an off screen area of the frame buffer.An interrupt request can be generated when an entire field or frame has been captured.The video output pipeline incorporates a video-scaler and colour space converter function and provisions in the CRT controller to display a video window.While repainting the screen the CRT con-troller fetches both the video as well as the normal non-video frame buffer in two separate internal FIFOs (256-Bytes each).The video stream can be colour-space converted (optionally)and smoothGENERAL DESCRIPTION8/48Issue 1.7-February 8,2000scaled.Smooth interpolative scaling in both hori-zontal and vertical direction are implemented.Col-our and Chroma key functions are also imple-mented to allow mixing video stream with non-vid-eo frame buffer.The video output passes directly to the RAMDAC for monitor output or through another optional col-our space converter (RGB to 4:2:2YCrCb)to the programmable anti-flicker filter.The flicker filter is configured as either a two line filter with gamma correction (primarily designed for DOS type text)or a 3line flicker filter (primarily designed for Win-dows type displays).The flicker filter is optional and can be software disabled for use with large screen area’s of video.The Video output pipeline of the STPC Client in-terfaces directly to the external digital TV encoder (STV0119).It takes a 24bit RGB non-interlaced pixel stream and converts to a multiplexed 4:2:2YCrCb 8bit output stream,the logic includes a progressive to interlaced scan converter and logic to insert appropriate CCIR656timing reference codes into the output stream.It facilitates the high quality display of VGA or full screen video streams received via the Video input port to standard NTSC or PAL televisions.The STPC Client core is compliant with the Ad-vanced Power Management (APM)specification to provide a standard method by which the BIOS can control the power used by personal comput-ers.The Power Management Unit module (PMU)controls the power consumption by providing a comprehensive set of features that control the power usage and supports compliance with the United States Environmental Protection Agency’s Energy Star Computer Program.The PMU pro-vides following hardware structures to assist the software in managing the power consumption by the system.-System Activity Detection.-3power-down timers detecting system inactivity:-Doze timer (short durations).-Stand-by timer (medium durations).-Suspend timer (long durations).-House-keeping activity detection.-House-keeping timer to cope with short bursts of house-keeping activity while dozing or in stand-by state.-Peripheral activity detection.-Peripheral timer detecting peripheral inactivity -SUSP#modulation to adjust the system per-formance in various power down states of the sys-tem including full power on state.-Power control outputs to disable power from dif-ferent planes of the board.Lack of system activity for progressively longer period of times is detected by the three power down timers.These timers can generate SMI in-terrupts to CPU so that the SMM software can put the system in decreasing states of power con-sumption.Alternatively,system activity in a power down state can generate SMI interrupt to allow the software to bring the system back up to full power on state.The chip-set supports up to three power down states:Doze state,Stand-by state and Sus-pend mode.These correspond to decreasing lev-els of power savings.Power down puts the STPC Client into suspend mode.The processor completes execution of the current instruction,any pending decoded instruc-tions and associated bus cycles.During the sus-pend mode,internal clocks are stopped.remov-ing power down,the processor resumes instruc-tion fetching and begins execution in the instruc-tion stream at the point it had stopped.A reference design for the STPC Client is availa-ble including the schematics and layout files,the design is a PC ATX motherboard design.The de-sign is available as a demonstration board for ap-plication and system development.The STPC Client is supported by several BIOS vendors,including the super I/O device used in the reference design.Drivers for 2D accelerator,video features and EIDE are available on various operating systems.The STPC Client has been designed using mod-ern reusable modular design techniques,it is pos-sible to add to or remove the standard features of the STPC Client or other variants of the 5ST86family.Contact your local STMicroelectonics sales office for further information.GENERAL DESCRIPTIONIssue 1.7-February 8,20009/48Figure 1-1.Functional description.x86Core Host I/FDRAM2D SVGA VIPPCI m/sPCI BUSCRTCHW CursorMonitorTV OutputSYNC OutputAnti-FlickerColour SpaceColour Key ChromaVideo pipeline CCIR InputISAEIDEPCI m/sISA BUSIPCEIDEGENERAL DESCRIPTION10/48Issue 1.7-February 8,2000Figure 1-2.Pictorial Block Diagram Typical ApplicationSTPC ClientISAPCI4x 16-bit EDO DRAMsSuper I/O2x EIDEFlashKeyboard /Mouse Serial Ports Parallel Port FloppyMonitorTVSTV0119VideoSVGACCIR601CCIR656S-VHS RGB PAL NTSCIRQDMA.REQDMA.ACKDMUXDMUXMUXMUXRTC2.PIN DESCRIPTION2.1.INTRODUCTIONThe STPC Client integrates most of the functional-ities of the PC architecture.As a result,many of the traditional interconnections between the host PC microprocessor and the peripheral devices are totally assimilated to the STPC Client.This offers improved performance due to the tight coupling of the processor core and its peripherals.As a result many of the external pin connections are made di-rectly to the on-chip peripheral functions.Figure2-1shows the STPC Client’s external inter-faces.It defines the main busses and their func-tion.Table2-1describes the physical implementa-tion listing signals type and their functionality.Ta-ble2-2provides a full pin listing and description ofthe pins.Table2-3provides a full listing of pin lo-cations of the STPC Client package by physical connection.Please refer to the pin allocation drawing for reference.Note:Several interface pins are multiplexed with other functions,refer to the Pin Description sec-tion for further detailsTable2-1.Signal DescriptionGroup name Qty Basic Clocks reset&Xtal(SYS)14 Memory Interface(DRAM)89PCI interface(excluding VDD5)54ISA/IDE/IPC combined interface83Video Input(VIP)9TV Output(TV)10VGA Monitor interface(VGA)10 Grounds69V DD26 Analog specific V CC/V DD14 Reserved/Test/Misc./Speaker10Total Pin Count388Figure2-1.STPC Client External InterfacesSOUTHNORTH PCIX86DRAM VGA VIP TV SYS ISA/IDE IPC891091054147310STPC CLIENTIssue1.7-February8,200011/48Table2-2.Definition of Signal PinsSignal Name Dir Description Qty BASIC CLOCKS RESETS&XTALSYSRSTI#I System Reset/Power good1 SYSRSTO#*O Reset Output to System1 XTALI I14.3MHz External Oscillator Input1 XTALO I/O14.3MHz External Oscillator Input1 PCI_CLKI I33MHz PCI Input Clock1 PCI_CLKO O33MHz PCI Output Clock(from internal PLL)1 ISA_CLK O ISA Clock Output-Multiplexer Select Line For IPC1 ISA_CLK2X O ISA Clock x2Output-Multiplexer Select Line For IPC1 OSC14M*O ISA bus synchronisation clock1 HCLK*O Host Clock(Test)1 DEV_CLK O24MHz Peripheral Clock(floppy drive)1 GCLK2X*I/O80MHz Graphics Clock1 DCLK*I/O135MHz Dot Clock1 DCLK_DIR*I Dot Clock Direction1 V DD_xxx_PLL Power Supply for PLL ClocksMEMORY INTERFACEMA[11:0]*I/O Memory Address12 RAS#[3:0]O Row Address Strobe4 CAS#[7:0]O Column Address Strobe8 MWE#O Write Enable1 MD[63:0]*I/O Memory Data64PCI INTERFACEAD[31:0]*I/O PCI Address/Data32 CBE[3:0]*I/O Bus Commands/Byte Enables4 FRAME#*I/O Cycle Frame1 TRDY#*I/O Target Ready1 IRDY#*I/O Initiator Ready1 STOP#*I/O Stop Transaction1 DEVSEL#*I/O Device Select1 PAR*I/O Parity Signal Transactions1 SERR#*O System Error1 LOCK#I PCI Lock1 PCI_REQ#[2:0]*I PCI Request3 PCI_GNT#[2:0]*O PCI Grant3 PCI_INT[3:0]*I PCI Interrupt Request4 VDD5I5V Power Supply for PCI ESD protection4ISA AND IDE COMBINED ADDRESS/DATALA[23:22]*/SCS3#,SCS1#I/O Unlatched Address(ISA)/Secondary Chip Select(IDE)2 LA[21:20]*/PCS3#,PCS1#I/O Unlatched Address(ISA)/Primary Chip Select(IDE)2 LA[19:17]*/DA[2:0]O Unlatched Address(ISA)/Address(IDE)3 RMRTCCS#*/DD[15]I/O ROM/RTC Chip Select/Data Bus bit15(IDE)1 KBCS#*/DD[14]I/O Keyboard Chip Select/Data Bus bit14(IDE)1 Note;*denotes theat the pin is V5T(see Section4.)12/48Issue1.7-February8,2000Table2-2.Definition of Signal PinsSignal Name Dir Description Qty RTCRW#*/DD[13]I/O RTC Read/Write/Data Bus bit13(IDE)1 RTCDS#*/DD[12]I/O RTC Data Strobe/Data Bus bit12(IDE)1SA[19:8]*/DD[11:0]I/O Latched Address(ISA)/Data Bus(IDE)16SA[7:0]I/O Latched Address(IDE)4SD[15:0]*I/O Data Bus(ISA)16ISA/IDE COMBINED CONTROLIOCHRDY*/DIORDY I/O I/O Channel Ready(ISA)-Busy/Ready(IDE)1ISA CONTROLALE*O Address Latch Enable1BHE#*I/O System Bus High Enable1 MEMR#*,MEMW#*I/O Memory Read and Memory Write2 SMEMR#*,SMEMW#*O System Memory Read and Memory Write2IOR#*,IOW#*I/O I/O Read and Write2 MASTER#*I Add On Card Owns Bus1MCS16#*,IOCS16#*I Memory/IO Chip Select162REF#*O Refresh Cycle.1AEN*O Address Enable1 IOCHCK#*I I/O Channel Check.1 ISAOE#*O Bidirectional OE Control1 GPIOCS#*I/O General Purpose Chip Select1IDE CONTROLPIRQ*I Primary Interrupt Request1SIRQ*I Secondary Interrupt Request1 PDRQ*I Primary DMA Request1 SDRQ*I Secondary DMA Request1 PDACK#*O Primary DMA Acknowledge1 SDACK#*O Secondary DMA Acknowledge1PIOR#*I/O Primary I/O Read1 PIOW#*O Primary I/O Write1SIOR#*I/O Secondary I/O Read1 SIOW#*O Secondary I/O Write1IPCIRQ_MUX[3:0]*I Multiplexed Interrupt Request4 DREQ_MUX[1:0]*I Multiplexed DMA Request2 DACK_ENC[2:0]*O DMA Acknowledge3TC*O ISA Terminal Count1MONITOR INTERFACERED,GREEN,BLUE O Red,Green,Blue3 VSYNC*O Vertical Synchronization1 HSYNC*O Horizontal Synchronization1 VREF_DAC I DAC Voltage reference1 RSET I Resistor Set1 COMP I Compensation1SCL/DDC[1]*I/O I C Interface-Clock/Can be used for VGA DDC[1]signal1 Note;*denotes theat the pin is V5T(see Section4.)Issue1.7-February8,200013/48Table2-2.Definition of Signal PinsSignal Name Dir Description Qty SDA/DDC[0]*I/O I C Interface-Data/Can be used for VGA DDC[0]signal1VIDEO INPUTVCLK*I Pixel Clock1 VIN[7:0]*I YUV Video Data Input CCIR601or6568DIGITAL TV OUTPUTTV_YUV[7:0]*O Digital Video Outputs8 ODD_EVEN*O Frame Synchronisation1 VCS*O Horizontal Line Synchronisation1MISCELLANEOUSST[6:0]I/O Test/Misc.pins7 CLKDEL[2:0]*I/O Reserved(Test/Misc pins)3 Note;*denotes theat the pin is V5T(see Section4.)14/48Issue1.7-February8,20002.2.SIGNAL DESCRIPTIONS2.2.1.BASIC CLOCKS RESETS&XTALPWGD System Reset/Power good.This input is low when the reset switch is depressed.Other-wise,it reflects the power supply’s power good signal.PWGD is asynchronous to all clocks,and acts as a negative active reset.The reset circuit initiates a hard reset on the rising edge of PWGD.XTALI14.3MHz Pull Down(10kΩ)XTALO14.3MHz External Oscillator Input These pins are the14.318MHz external oscillator input; This clock is used as the reference clock for the in-ternal frequency synthesizer to generate the HCLK,CLK24M,GCLK2X and DCLK clocks.HCLK Host Clock.This is the host1X clock.Its frequency can vary from25to75MHz.All host transactions and PCI transactions are synchro-nized to this clock.This clock drives the DRAM controller to execute the host transactions.In nor-mal mode,this output clock is generated by the in-ternal PLL.GCLK2X80MHz Graphics Clock.This is the Graphics2X clock,which drives the graphics en-gine and the DRAM controller to execute the graphics and display cycles.Normally GCLK2X is generated by the internal fre-quency synthesizer,and this pin is an output.By setting a bit in Strap Register2,this pin can be made an input so that an external clock can re-place the internal frequency synthesizer.DCLK135MHz Dot Clock.This is the dot clock, which drives graphics display cycles.Its frequency can go from8MHz(using internal PLL)up to135 MHz,and it is required to have a worst case duty cycle of60-40.DCLK_DIR Dot Clock Direction.Specifies if DCLK is an input(0)or an output(1).DEV_CLK24MHz Peripheral Clock Output.This 24MHZ signal is provided as a convenience for the system integration of a floppy disk driver func-tion in an external chip.2.2.2.MEMORY INTERFACEMA[11:0]Memory Address Output.These12mul-tiplexed memory address pins support external DRAM with up to4K refresh.These include all 16M x N and some4M x N DRAM modules.The address signals must be externally buffered to support more than16DRAM chips.The timing of these signals can be adjusted by software to match the timings of most DRAM modules.MD[63:0]Memory Data I/O.This is the64-bit memory data bus.If only half of a bank is populat-ed,MD63-32is pulled high,data is on MD31-0. MD[40-0]are read by the device strap option reg-isters during rising edge of PWGD.RAS#[3:0]Row Address Strobe Output.There are4active low row address strobe outputs,one for each bank of the memory.Each bank contains 4or8-Bytes of data.The memory controller allows half of a bank(4Bytes)to be populated to enable memory upgrade at finer granularity.The RAS#signals drive the SIMMs directly with-out any external buffering.These pins are always outputs,but they can also simultaneously be in-puts,to allow the memory controller to monitor the value of the RAS#signals at the pins.CAS#[7:0]Column Address Strobe Output.There are8active low column address strobe outputs, one for each Byte of the memory.The CAS#signals drive the SIMMs either directly or through external buffers.These pins are always outputs,but they can also simultaneously be inputs,to allow the memory controller to monitor the value of the CAS#signals at the pins.MWE#Write Enable Output.Write enable speci-fies whether the memory access is a read(MWE# =H)or a write(MWE#=L).This single write ena-ble controls all DRAMs.It can be externally buff-ered to boost the maximum number of loads (DRAM chips)supported.The MWE#signals drive the SIMMs directly with-out any external buffering.2.2.3.VIDEO INPUTVCLK Pixel Clock Input.VIN[7:0]YUV Video Data Input CCIR601or656. Time multiplexed4:2:2luminance and chromi-nance data as defined in ITU-R Rec601-2and Rec656(except for TTL input levels).This bus in-terfaces with an MPEG video decoder output port and typically carries a stream of Cb,Y,Cr,Y digit-al video at VCLK frequency,clocked on the rising edge(by default)of VCLK.A54-Mbit/s‘double’Cb,Y,Cr,Y input multiplex is supported for double encoding applications(rising and falling edge of CKREF are operating). OUTPUTTV_YUV[7:0]Digital video outputs.Issue1.7-February8,200015/48。
CY7C1516AV18-200BZC资料
PRELIMINARY72-Mbit DDR-II SRAM 2-Word BurstArchitectureCY7C1516AV18CY7C1527AV18CY7C1518AV18CY7C1520AV18Features•72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36)•300-MHz clock for high bandwidth•2-Word burst for reducing address bus frequency •Double Data Rate (DDR) interfaces(data transferred at 600 MHz) @ 300 MHz•Two input clocks (K and K) for precise DDR timing —SRAM uses rising edges only•Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches•Echo clocks (CQ and CQ) simplify data capture in high-speed systems•Synchronous internally self-timed writes•DDR-II operates with 1.5 cycle read latency when DLL is enabled•Operates like a DDR I device with 1 cycle read latency in DLL off mode•1.8V core power supply with HSTL inputs and outputs •Variable drive HSTL output buffers •Expanded HSTL output voltage (1.4V–V DD )•Available in 165-ball FBGA package (15 x 17 x 1.4 mm)•Offered in both lead-free and non lead-free packages •JTAG 1149.1 compatible test access port•Delay Lock Loop (DLL) for accurate data placementConfigurationsCY7C1516AV18 – 8M x 8CY7C1527AV18 – 8M x 9CY7C1518AV18 – 4M x 18CY7C1520AV18 – 2M x 36Functional DescriptionThe CY7C1516AV18, CY7C1527AV18, CY7C1518AV18 and CY7C1520AV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for Read and Write are latched on alternate rising edges of the input (K) clock.Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Each address location is associated with two 8-bit words in the case of CY7C1516AV18 and two 9-bit words in the case of CY7C1527AV18 that burst sequentially into or out of the device. The burst counter always starts with a “0” internally in the case of CY7C1516AV18 and CY7C1527AV18. On CY7C1518AV18 and CY7C1520AV18, the burst counter takes in the least significant bit of the external address and bursts two 18-bit words in the case of CY7C1518AV18 and two 36-bit words in the case of CY7C1520AV18 sequentially into or out of the device.Asynchronous inputs include output impedance matching input (ZQ). Synchronous data outputs (Q, sharing the same physical pins as the data inputs D) are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR SRAM in the system design. Output data clocks (C/C) enable maximum system clocking and data synchronization flexibility.All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.PRELIMINARYCY7C1518AV18CY7C1520AV18Logic Block Diagram (CY7C1516AV18)CLK A (21: 0)Gen.K K Control LogicAddress RegisterR e a d A d d . D e c o d eRead Data Reg.R/W DQ [7:0]Output Logic Reg.Reg.Reg.88168NWS [1 : 0]V REF W r i t e A d d . D e c o d e8CC 8LDControl224M x 8 Array4M x 8 ArrayWrite Reg Write Reg CQCQ R/W DOFFLogic Block Diagram (CY7C1527AV18)CLK A (21:0)Gen.K K Control LogicAddress RegisterR e a d A d d . D e c o d eRead Data Reg.R/W DQ [8: 0]Output Logic Reg.Reg.Reg.99189BWS [0]V REF W r i t e A d d . D e c o d e9CC 9LDControl224M x 9 Array4M x 9 ArrayWrite Reg Write Reg CQCQ R/W DOFFPRELIMINARYCY7C1518AV18CY7C1520AV184M x 18 ArrayWrite RegWrite Reg Logic Block Diagram (CY7C1518AV18)CLK A (21: 0)Gen.K K Control LogicAddressRegisterR e a d A d d . D e c o d eRead Data Reg.R/W DQ [17: 0]Output Logic Reg.Reg.Reg.18183618BWS [1: 0]V REF W r i t e A d d . D e c o d e1822CC 18LD ControlBurst Logic A0A (21:1)21CQ CQR/W DOFFLogic Block Diagram (CY7C1520AV18)CLK A (20:0)Gen.K K Control LogicAddressRegisterR e a d A d d . D e c o d eRead Data Reg.R/W DQ [35: 0]Output Logic Reg.Reg.Reg.36367236BWS [3:0]V REF W r i t e A d d . D e c o d e3621CC 36LD ControlBurst LogicA0A (20:1)202M x 36 ArrayWrite RegWrite Reg CQCQ36R/W DOFFSelection Guide300 MHz278 MHz 250 MHz 200 MHz 167 MHz Unit Maximum Operating Frequency 300278250200167MHz Maximum Operating Current900860800700650mAPRELIMINARYCY7C1518AV18CY7C1520AV18Pin Configurations [1]Note:1.V SS /144M and V SS /288M are not connected to the die and can be tied to any voltage level.CY7C1516AV18 (8M x 8)2345671A B C D E F G H J K L M N P RA CQ NC NC NC NC DOFF NC A A NWS 1 K R/W NC NC NC NC NC NC TDONC NC NC NC NC NC TCKNC NC A NC K NWS 0V SS A A A NC V SS V SS V SS V SS V DD A V SS V SS V SS V DD DQ4NC V DDQ NC NC NC NC DQ7AV DDQ V SS V DDQ V DD V DD DQ5V DDQ V DD V DDQ V DD V DDQ V DD V SS V DD V DDQ V DDQ V SS V SS V SS V SS A ACV SS A A ANC V SS NC V SS NC NC V REF V SS V DD V SS V SS A V SS C NC DQ6NC NC NC V DD A891011NC A A LDCQ A NC NC DQ3V SS NC NC NC NC V SS NC DQ2NC NC NC V REF NC NC V DDQ NC V DDQ NC NC V DDQ V DDQ V DDQ NC V DDQ NC DQ1NC V DDQ V DDQ NC V SS NC NC NC TDITMSV SS A NC ANC NC NC ZQ NC DQ0NC NC NC NC ACY7C1527AV18 (8M x 9)2345671A B C D E F G H J K L M N P RA CQ NC NC NC NC DOFF NC A A NC K R/WNC NC NC NC NC NC TDONC NC NC NC NC NC TCKNC NC A NC K BWS 0V SS A A A NC V SS V SS V SS V SS V DD A V SS V SS V SS V DD DQ4NC V DDQ NC NC NC NC DQ7AV DDQ V SS V DDQ V DD V DD DQ5V DDQ V DD V DDQ V DD V DDQ V DD V SS V DD V DDQ V DDQ V SS V SS V SS V SS A ACV SS A A ANC V SS NC V SS NC NC V REF V SS V DD V SS V SS A V SS C NC DQ6NC NC NC V DD A891011DQ8A A LDCQ A NC NC DQ3V SS NC NC NC NC V SS NC DQ2NC NC NC V REF NC NC V DDQ NC V DDQ NC NC V DDQ V DDQ V DDQ NC V DDQ NC DQ1NC V DDQ V DDQ NC V SS NC NC NC TDITMSV SS A NC ANC NC NC ZQ NC DQ0NC NC NC NC A165-ball FBGA (15 x 17 x 1.4 mm) PinoutPRELIMINARY CY7C1518AV18 CY7C1520AV18Pin Configurations [1] (continued)CY7C1518AV18 (4M x 18)234567 1ABCDEFGHJKLMNP RACQNCNCNCNCDOFFNCA A BWS1KR/W NCDQ9NCNCNCNCTDONCNCNCNCNCNCTCKNCNCA NC K BWSV SS A A0ADQ10V SSV SS V SSV SSV DDAV SSV SSV SSV DDDQ11NCV DDQNCDQ14NCDQ16DQ17AV DDQ V SSV DDQ V DD V DDDQ13V DDQV DDV DDQV DDV DDQ V DD V SSV DDV DDQV DDQ V SSV SS V SS V SSAACV SSA AANC V SSNC V SSDQ12NCV REFV SSV DDV SSV SSAV SSCNCDQ15NCNCNCV DDA891011DQ0A ALD CQA NC NC DQ8V SS NC DQ7NCNCV SS NCDQ6NCNCNCV REFNCDQ3V DDQ NCV DDQ NC DQ5V DDQV DDQV DDQNCV DDQ NC DQ4NCV DDQV DDQ NCV SS NC NCNCTDITMSV SSA NCANCNCNCZQNCDQ2NCDQ1NCNCA2345671A B C D E F G H J K L M NP RACQNCNCNCNCDOFFNCV SS/144M A BWS2KR/W BWS1DQ27DQ18NCNCNCTDONCNCDQ31NCNCNCTCKNCDQ28A BWS3K BWSV SS A A0ADQ19V SSV SS V SSV SSV DDAV SSV SSV SSV DDDQ20DQ21V DDQDQ32DQ23DQ34DQ25DQ26AV DDQ V SSV DDQ V DD V DDDQ22V DDQV DDV DDQV DDV DDQ V DD V SSV DDV DDQV DDQ V SSV SS V SS V SSAACV SSA AADQ29V SSNC V SSDQ30NCV REFV SSV DDV SSV SSAV SSCNCDQ33NCDQ35DQ24V DDA891011DQ0A ALD CQA NC NC DQ8V SS NC DQ17DQ7NCV SS NCDQ6DQ14NCNCV REFNCDQ3V DDQ NCV DDQ NC DQ5V DDQV DDQV DDQDQ4V DDQ NC DQ13NCV DDQV DDQ NCV SS NC DQ1NCTDITMSV SSA NCADQ16DQ15NCZQDQ12DQ2DQ10DQ11DQ9NCACY7C1520AV18 (2M x 36)165-ball FBGA (15 x 17 x 1.4 mm) PinoutPRELIMINARY CY7C1518AV18 CY7C1520AV18Pin DefinitionsPin Name I/O Pin DescriptionDQ[x:0]Input/Output-Synchronous Data Input/Output signals. Inputs are sampled on the rising edge of K and K clocks during valid Write operations. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising edge of both the C and C clocks during Read operations or K and K when in single clock mode. When read access is deselected, Q[x:0] are automatically tri-stated.CY7C1516AV18 − DQ[7:0]CY7C1527AV18 − DQ[8:0]CY7C1518AV18 − DQ[17:0]CY7C1520AV18 − DQ[35:0]LD Input-Synchronous Synchronous Load. This input is brought LOW when a bus cycle sequence is to be defined. This definition includes address and Read/Write direction. All transactions operate on a burst of 2data.NWS0, NWS1Input-Synchronous Nibble Write Select 0, 1 − active LOW(CY7C1516AV18 only).Sampled on the rising edge of the K and K clocks during Write operations. Used to select which nibble is written into the device during the current portion of the Write operations. Nibbles not written remain unaltered.NWS0 controls D[3:0] and NWS1 controls D[7:4].All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select will cause the corresponding nibble of data to be ignored and not written into the device.BWS0, BWS1, BWS2, BWS3Input-SynchronousByte Write Select 0, 1, 2, and 3 − active LOW. Sampled on the rising edge of the K and K clocksduring Write operations. Used to select which byte is written into the device during the currentportion of the Write operations. Bytes not written remain unaltered.CY7C1527AV18 − BWS0 controls D[8:0]CY7C1518AV18 − BWS0 controls D[8:0] and BWS1 controls D[17:9].CY7C1520AV18 − BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3controls D[35:27].All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte WriteSelect will cause the corresponding byte of data to be ignored and not written into the device.A, A0Input-Synchronous Address Inputs. These address inputs are multiplexed for both Read and Write operations. Internally, the device is organized as 8M x 8 (2 arrays each of 4M x 8) for CY7C1516AV18 and 8M x 9 (2 arrays each of 4M x9) for CY7C1527AV18, a single 4M x 18 array for CY7C1518AV18, and a single array of 2M x 36 for CY7C1520AV18.CY7C1516AV18 – Since the least significant bit of the address internally is a “0,” only 22 external address inputs are needed to access the entire memory array.CY7C1527AV18 – Since the least significant bit of the address internally is a “0,” only 22 external address inputs are needed to access the entire memory array.CY7C1518AV18 – A0 is the input to the burst counter. These are incremented in a linear fashion internally. 22 address inputs are needed to access the entire memory array.CY7C1520AV18 – A0 is the input to the burst counter. These are incremented in a linear fashion internally. 21 address inputs are needed to access the entire memory array. All the address inputs are ignored when the appropriate port is deselected.R/W Input-Synchronous Synchronous Read/Write Input. When LD is LOW, this input designates the access type (Read when R/W is HIGH, Write when R/W is LOW) for loaded address. R/W must meet the set-up and hold times around edge of K.C Input-Clock Positive Input Clock for Output Data. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details.C Input-Clock Negative Input Clock for Output Data. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details.K Input-Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising edge of K.K Input-Clock Negative Input Clock Input. K is used to capture synchronous data being presented to the device and to drive out data through Q[x:0] when in single clock mode.PRELIMINARYCY7C1518AV18CY7C1520AV18CQOutput-Clock CQ is referenced with respect to C . This is a free running clock and is synchronized to the Input clock for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks are shown in the AC Timing table.CQOutput-Clock CQ is referenced with respect to C . This is a free running clock and is synchronized to the Input clock for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks are shown in the AC Timing table.ZQInputOutput Impedance Matching Input . This input is used to tune the device outputs to the system data bus impedance. CQ, CQ, and Q [x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternatively, this pin can be connected directly to V DDQ , which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.DOFF InputDLL Turn Off - Active LOW . Connecting this pin to ground will turn off the DLL inside the device. The timings in the DLL turned off operation will be different from those listed in this data sheet. For normal operation, this pin can be connected to a pull-up through a 10-Kohm or less pull-up resistor. The device will behave in DDR-I mode when the DLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz with DDR-I timing. TDO Output TDO for JTAG .TCK Input TCK pin for JTAG .TDI Input TDI pin for JTAG .TMS Input TMS pin for JTAG .NC N/A Not connected to the die . Can be tied to any voltage level.V SS /144M Input Address expansion for 144M . Can be tied to any voltage level.V SS /288M Input Address expansion for 288M . Can be tied to any voltage level.V REF Input-Reference Reference Voltage Input . Static input used to set the reference level for HSTL inputs and Outputs as well as AC measurement points.V DD Power Supply Power supply inputs to the core of the device . V SS GroundGround for the device .V DDQPower Supply Power supply inputs for the outputs of the device .Pin Definitions (continued)Pin Name I/O Pin DescriptionPRELIMINARY CY7C1518AV18 CY7C1520AV18Functional OverviewThe CY7C1516AV18, CY7C1527AV18, CY7C1518AV18, and CY7C1520AV18 are synchronous pipelined Burst SRAMs equipped with a DDR interface which operates with a read latency of one and half cycles when DOFF pin is tied HIGH. When DOFF pin is set LOW or connected to V SS the device will behave in DDR-I mode with a read latency of one clock cycle.Accesses are initiated on the rising edge of the positive input clock (K). All synchronous input timing is referenced from the rising edge of the input clocks (K and K) and all output timing is referenced to the rising edge of the output clocks (C/C or K/K when in single clock mode).All synchronous data inputs (D[x:0]) pass through input registers controlled by the rising edge of the input clocks (K and K). All synchronous data outputs (Q[x:0]) pass through output registers controlled by the rising edge of the output clocks (C/C or K/K when in single-clock mode).All synchronous control (R/W, LD, BWS[0:X]) inputs pass through input registers controlled by the rising edge of the input clock (K).CY7C1518AV18 is described in the following sections. The same basic descriptions apply to CY7C1516AV18, CY7C1527AV18, and CY7C1520AV18.Read OperationsThe CY7C1518AV18 is organized internally as a single array of 4M x 18. Accesses are completed in a burst of two sequential 18-bit data words. Read operations are initiated by asserting R/W HIGH and LD LOW at the rising edge of the positive input clock (K). The address presented to Address inputs is stored in the Read address register and the least significant bit of the address is presented to the burst counter. The burst counter increments the address in a linear fashion. Following the next K clock rise the corresponding 18-bit word of data from this address location is driven onto the Q[17:0] using C as the output timing reference. On the subsequent rising edge of C the next 18-bit data word from the address location generated by the burst counter is driven onto the Q[17:0]. The requested data will be valid 0.45 ns from the rising edge of the output clock (C or C, or K and K when in single clock mode, 200-MHz, 250-MHz and 300-MHz device). In order to maintain the internal logic, each read access must be allowed to complete. Read accesses can be initiated on every rising edge of the positive input clock (K).When read access is deselected, the CY7C1518AV18 will first complete the pending read transactions. Synchronous internal circuitry will automatically tri-state the outputs following the next rising edge of the positive output clock (C). This will allow for a seamless transition between devices without the insertion of wait states in a depth expanded memory.Write OperationsWrite operations are initiated by asserting R/W LOW and LD LOW at the rising edge of the positive input clock (K). The address presented to Address inputs is stored in the Write address register and the least significant bit of the address is presented to the burst counter. The burst counter increments the address in a linear fashion. On the following K clock rise the data presented to D[17:0] is latched and stored into the 18-bit Write Data register provided BWS[1:0] are both asserted active. On the subsequent rising edge of the Negative Input Clock (K) the information presented to D[17:0] is also stored into the Write Data register provided BWS[1:0] are both asserted active. The 36 bits of data are then written into the memory array at the specified location. Write accesses can be initiated on every rising edge of the positive input clock (K). Doing so will pipeline the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks (K and K).When write access is deselected, the device will ignore all inputs after the pending Write operations have been completed.Byte Write OperationsByte Write operations are supported by the CY7C1518AV18.A Write operation is initiated as described in the Write Operation section above. The bytes that are written are deter-mined by BWS0 and BWS1 which are sampled with each set of 18-bit data word. Asserting the appropriate Byte Write Select input during the data portion of a Write will allow the data being presented to be latched and written into the device. Deasserting the Byte Write Select input during the data portion of a write will allow the data stored in the device for that byte to remain unaltered. This feature can be used to simplify Read/Modify/Write operations to a Byte Write operation. Single Clock ModeThe CY7C1518AV18 can be used with a single clock that controls both the input and output registers. In this mode the device will recognize only a single pair of input clocks (K and K) that control both the input and output registers. This operation is identical to the operation if the device had zero skew between the K/K and C/C clocks. All timing parameters remain the same in this mode. To use this mode of operation, the user must tie C and C HIGH at power-on. This function is a strap option and not alterable during device operation. DDR OperationThe CY7C1518AV18 enables high-performance operation through high clock frequencies (achieved through pipelining) and double data rate mode of operation. The CY7C1518AV18 requires a single No Operation (NOP) cycle when transitioning from a Read to a Write cycle. At higher frequencies, some applications may require a second NOP cycle to avoid contention.If a Read occurs after a Write cycle, address and data for the Write are stored in registers. The write information must be stored because the SRAM cannot perform the last word Write to the array without conflicting with the Read. The data stays in this register until the next Write cycle occurs. On the first Write cycle after the Read(s), the stored data from the earlier Write will be written into the SRAM array. This is called a Posted Write.If a Read is performed on the same address on which a Write is performed in the previous cycle, the SRAM reads out the most current data. The SRAM does this by bypassing the memory array and reading the data from the registers. Depth ExpansionDepth expansion requires replicating the LD control signal for each bank. All other control signals can be common between banks as appropriate.PRELIMINARYCY7C1518AV18CY7C1520AV18Programmable ImpedanceAn external resistor, RQ, must be connected between the ZQ pin on the SRAM and V SS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the SRAM, The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175Ω and 350Ω, with V DDQ =1.5V. The output impedance is adjusted every 1024cycles upon power-up to account for drifts in supply voltage and temperature.Echo ClocksEcho clocks are provided on the DDR-II to simplify data capture on high-speed systems. Two echo clocks are generated by the DDR-II. CQ is referenced with respect to C and CQ is referenced with respect to C. These are free-running clocks and are synchronized to the output clock of the DDR-II. In the single clock mode, CQ is generated withrespect to K and CQ is generated with respect to K. The timings for the echo clocks are shown in the AC Timing table.DLLThese chips utilize a Delay Lock Loop (DLL) that is designed to function between 80 MHz and the specified maximum clock frequency. During power-up, when the DOFF is tied HIGH, the DLL gets locked after 1024 cycles of stable clock. The DLL can also be reset by slowing or stopping the input clock K and K for a minimum of 30 ns. However, it is not necessary for the DLL to be specifically reset in order to lock the DLL to the desired frequency. The DLL will automatically lock 1024 clock cycles after a stable clock is presented.the DLL may be disabled by applying ground to the DOFF pin. When the DLL is turned off, the device will behave in DDR-I mode (with one cycle latency and a longer access time). For information refer to the application note “DLL Considerations in QDRII™/DDRII”.Notes:2.The above application shows two DDR-II used.3.X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, ↑represents rising edge.4.Device will power-up deselected and the outputs in a tri-state condition.5.On CY7C1518AV18 and CY7C1520AV18, “A1” represents address location latched by the devices when transaction was initiated and A2 represents the addresses sequence in the burst. On CY7C1516AV18, “A1” represents A +‘0’ and A2 represents A +‘1.’6.“t” represents the cycle at which a Read/Write operation is started. t+1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.7.Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.8.charging symmetrically.Application Example [2]Truth Table [3, 4, 5, 6, 7, 8]OperationK LD R/W DQDQWrite Cycle: Load address; wait one cycle; input write data on consecutive K and K rising edges.L-H L L D(A1) at K(t + 1) ↑D(A2) at K(t + 1) ↑Read Cycle: Load address; wait one and a half cycle; read data on consecutive C and C rising edges.L-H L H Q(A1) at C(t + 1) ↑Q(A2) at C(t + 2) ↑NOP: No Operation L-H H X High-Z High-Z Standby: Clock StoppedStoppedXXPrevious StatePrevious StateBurst Address Table (CY7C1518AV18, CY7C1520AV18)First Address (External)Second Address (Internal)X..X0X..X1X..X1X..X0PRELIMINARY CY7C1518AV18 CY7C1520AV18Write Cycle Descriptions(CY7C1516AV18 and CY7C1518AV18)[3, 9]BWS0, NWS0BWS1, NWS1K K CommentsL L L-H–During the Data portion of a Write sequence :CY7C1516AV18 − both nibbles (D[7:0]) are written into the device,CY7C1518AV18 − both bytes (D[17:0]) are written into the device.L L–L-H During the Data portion of a Write sequence :CY7C1516AV18 − both nibbles (D[7:0]) are written into the device,CY7C1518AV18 − both bytes (D[17:0]) are written into the device.L H L-H–During the Data portion of a Write sequence :CY7C1516AV18 − only the lower nibble (D[3:0]) is written into the device. D[7:4]will remain unaltered,CY7C1518AV18 − only the lower byte (D[8:0]) is written into the device. D[17:9]will remain unaltered.L H–L-H During the Data portion of a Write sequence :CY7C1516AV18 − only the lower nibble (D[3:0]) is written into the device. D[7:4]will remain unaltered,CY7C1518AV18 − only the lower byte (D[8:0]) is written into the device. D[17:9]will remain unaltered.H L L-H–During the Data portion of a Write sequence :CY7C1516AV18 − only the upper nibble (D[7:4]) is written into the device. D[3:0]will remain unaltered,CY7C1518AV18 − only the upper byte (D[17:9]) is written into the device. D[8:0]will remain unaltered.H L–L-H During the Data portion of a Write sequence :CY7C1516AV18 − only the upper nibble (D[7:4]) is written into the device. D[3:0]will remain unaltered,CY7C1518AV18 − only the upper byte (D[17:9]) is written into the device. D[8:0]will remain unaltered.H H L-H–No data is written into the devices during this portion of a Write operation.H H–L-H No data is written into the devices during this portion of a Write operation.Write Cycle Descriptions[3, 9](CY7C1527AV18)BWS0K K CommentsL L-H–During the Data portion of a Write sequence, the single byte (D[8:0]) iswritten into the device.L–L-H During the Data portion of a Write sequence, the single byte (D[8:0]) iswritten into the device.H L-H–No data is written into the device during this portion of a Write operation.H–L-H No data is written into the device during this portion of a Write operation. Note:9.Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. NWS0, NWS1,BWS0, BWS1,BWS2 and BWS3 can be altered on differentportions of a write cycle, as long as the set-up and hold requirements are achieved.PRELIMINARY CY7C1518AV18 CY7C1520AV18Write Cycle Descriptions[3, 9] (CY7C1520AV18)BWS0BWS1BWS2BWS3K K CommentsL L L L L-H–During the Data portion of a Write sequence, all four bytes (D[35:0]) arewritten into the device.L L L L–L-H During the Data portion of a Write sequence, all four bytes (D[35:0]) arewritten into the device.L H H H L-H–During the Data portion of a Write sequence, only the lower byte (D[8:0]) iswritten into the device. D[35:9] will remain unaltered.L H H H–L-H During the Data portion of a Write sequence, only the lower byte (D[8:0]) iswritten into the device. D[35:9] will remain unaltered.H L H H L-H–During the Data portion of a Write sequence, only the byte (D[17:9]) iswritten into the device. D[8:0] and D[35:18]will remain unaltered.H L H H–L-H During the Data portion of a Write sequence, only the byte (D[17:9]) iswritten into the device. D[8:0] and D[35:18]will remain unaltered.H H L H L-H–During the Data portion of a Write sequence, only the byte (D[26:18]) iswritten into the device. D[17:0] and D[35:27]will remain unaltered.H H L H–L-H During the Data portion of a Write sequence, only the byte (D[26:18]) iswritten into the device. D[17:0] and D[35:27]will remain unaltered.H H H L L-H During the Data portion of a Write sequence, only the byte (D[35:27]) iswritten into the device. D[26:0] will remain unaltered.H H H L–L-H During the Data portion of a Write sequence, only the byte (D[35:27]) iswritten into the device. D[26:0] will remain unaltered.H H H H L-H–No data is written into the device during this portion of a Write operation.H H H H–L-H No data is written into the device during this portion of a Write operation.。
SC1486AITSTR资料
SC1486A
Features
1% DC accuracy Compatible with DDR & DDR2 memory power
requirements
Constant on-time for fast dynamic response VIN range = 1.8V – 25V DC current sense using low-side RDS(ON) sensing
Parameter TON1 to VSSA1, TON2 to VSSA2 DH1, BST1 to PGND1 and DH2, BST2 to PGND2 LX1 to PGND1 and LX2 to PGND2 VSSA1 to PGND1, and VSSA2 to PGND2 BST1 to LX1 and BST2 to LX2 DL1, ILIM1, VDDP1 to PGND1 and DL2, ILIM2, VDDP2 to PGND2 EN/PSV1, FB1, PGOOD1, VCCA1, VOUT1 to VSSA1 FB2, PGOOD2, VCCA2, REFIN, REFOUT to VSSA2 VCCA1 to EN/PSV1, FB1, PGOOD1, VOUT1 VCCA2 to FB2, PGOOD2, REFIN, REFOUT Thermal Resistance Junction to Ambient(5) Operating Junction Temperature Range Storage Temperature Range Lead Temperature (Soldering) 10 Sec.
Parameter
Conditions Min
- 1、下载文档前请自行甄别文档内容的完整性，平台不提供额外的编辑、内容补充、找答案等附加服务。
- 2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
- 3、如文档侵犯您的权益，请联系客服反馈,我们会尽快为您处理(人工客服工作时间：9:00-18:30)。
Material/Emitted Color GaP/GaP/Bright Red GaAsP/GaP/Hi-Eff Red GaAlAs/SH Red GaP/GaP/Green GaAsP/GaP/Hi-Eff Green GaAsP/GaP/Yellow GaAsP/GaP/Orange GaP/GaP/Bright Red GaAsP/GaP/Hi-Eff Red GaAlAs/SH Red GaP/GaP/Green GaP/GaP/Hi-Eff Green GaAsP/GaP/Yellow GaAsP/GaP/Orange GaP/GaP/Bright Red GaAsP/GaP/Hi-Eff Red GaAlAs/SH Red GaP/GaP/Hi-Eff Green GaP/GaP/Green GaAsP/GaP/Yellow GaAsP/GaP/Orange GaP/GaP/Bright Red GaAsP/GaP/Hi-Eff Red GaAlAs/SH Red GaP/GaP/Hi-Eff Green GaP/GaP/Green GaAsP/GaP/Yellow GaAsP/GaP/Orange GaP/GaP/Bright Red GaAsP/GaP/Hi-Eff Red GaAlAs/SH Red GaP/GaP/Hi-Eff Green GaP/GaP/Green GaAsP/GaP/Yellow GaAsP/GaP/Orange GaP/GaP/Bright Red GaAlAs/SH Red GaAlAs/DH Red GaP/GaP/Green GaP/GaP/Hi-Eff Green GaAsP/GaP/Yellow GaAsP/GaP/Orange GaP/GaP/Bright Red GaAsP/GaP/Orange GaAlAs/DH Red GaP/GaP/Green GaP/GaP/Hi-Eff Green GaAsP/GaP/Yellow GaP/GaP/Bright Red GaAsP/GaP/Orange GaAlAs/DH Red GaP/GaP/Green GaAsP/GaP/Yellow
35
L-055
50
L-056
50
L-057
Water Clear
12
L-058
Red Diffused
Green Diffused Yellow Diffused Red Diffused Green Diffused Yellow Diffused
180
L-059
Remark: 1. Hi-Eff Red/High-Efficiency Red. 2. Trans/Transparent. 3. 2θ 1/2 The off-axis angle at which the luminous intensity is half the axial luminouseen Diffused Yellow Diffused Water Clear Red Diffused
L-053
20
50
Green Diffused Yellow Diffused Water Clear Red Diffused
L-054
25
Green Diffused Yellow Diffused Orange Diffused Red Diffused Green Diffused Yellow Diffused Orange Diffused Red Diffused Green Diffused Yellow Diffused Orange Diffused
BL-B5139 BL-B4539 BL-B6139 Round BL-B2139 φ 8.0 BL-BX139 BL-B3139 BL-B4339 BL-B5139B BL-B4539B BL-B6139B Round BL-B2139B φ 8.0 BL-BX139B BL-B3139B BL-B4339B BL-R513G 8.0x8.0x BL-R453G 12.0mm BL-R613G 1.0″ BL-BX113G Lead Rectangular BL-R213G Round Head BL-R313G BL-R413G BL-B5130A BL-B4530A BL-B6130A Round BL-BX1130A φ 10.0 BL-B2130A BL-B3130A BL-B4130A BL-B513C BL-B453C BL-B613C Round BL-BX113C φ 12.0 BL-B213C BL-B313C BL-B413C BL-B5330M BL-B6330M BL-BD330M Round BL-B2330M φ 10.0 BL-BX1330M BL-B3330M BL-B4330M BL-B6H120U BL-B6E520U BL-B6D120U Round φ 20.0 BL-B6G120U BL-B6X1120U BL-B6Y120U BL-B6H120-1S BL-B6E520-1S Round BL-B6D120-2P φ 20.0 BL-B6G120-2P BL-B6Y120-3P
元器件交易网
STANDARD LED LAMPS (ROUND TYPES)
L-053 BL-Bxx39 Series L-054 BL-Bxx39B Series
L-055
BL-Rxx3G Series
L-056
BL-Bxx30A Series
L-057
BL-Bxx3C Series
元器件交易网
BIGGER SIZE LED LAMPS (ROUND TYPES)
Chip Package Part No. Peak Wave Length λp (nm) 700 635 660 568 568 585 635 700 635 660 568 568 585 635 700 635 660 568 568 585 635 700 635 660 568 568 585 635 700 635 660 568 568 585 635 700 660 660 568 568 585 635 700 635 660 568 568 585 700 635 660 568 585 Lens Appearance Absolute Maximum Ratings ∆λ Pd If Peak (nm) (mw) (mA) (mA) 90 45 20 30 30 35 45 90 45 20 30 30 35 45 90 45 20 30 30 35 45 90 45 20 30 30 35 45 90 45 20 20 30 35 45 90 20 20 30 20 35 45 90 45 20 30 30 35 90 45 20 30 35 40 80 60 80 80 80 80 40 80 60 80 80 80 80 50 80 60 80 80 80 80 50 80 60 80 80 80 80 50 80 60 80 80 80 80 50 60 60 80 80 80 80 300 480 360 480 480 480 300 480 480 480 480 15 30 30 30 30 30 30 15 30 30 30 30 30 30 15 30 30 30 30 30 30 15 30 30 30 30 30 30 15 30 30 30 30 30 30 15 30 30 30 30 30 30 15 30 30 30 30 30 15 30 30 30 30 50 150 150 150 150 150 150 50 150 150 150 150 150 150 50 150 150 150 150 150 150 50 150 150 150 150 150 150 50 150 150 150 150 150 150 50 150 150 150 150 150 150 50 150 150 150 150 150 50 150 150 150 150 Electro-optical Data (At 20mA) Vf (V) Typ 2.2 2.0 1.7 2.2 2.2 2.1 2.0 2.2 2.0 1.7 2.2 2.2 2.1 2.0 2.2 2.0 1.7 2.2 2.2 2.1 2.0 2.2 2.0 1.7 2.2 2.2 2.1 2.0 2.2 2.0 1.7 1.7 2.2 2.1 2.0 2.2 1.7 1.7 2.2 1.7 2.1 2.0 2.2 2.0 1.7 2.2 2.2 2.1 13.2 13.2 5.1 6.6 4.2 Max 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 15.6 15.6 7.8 7.8 5.2 Viewing Angle Drawing No. 2θ 1/2 Iv (mcd) (deg) Typ. 20.0 50.0 100.0 50.0 60.0 40.0 350.0 15.0 40.0 100.0 40.0 50.0 30.0 300.0 30.0 100.0 150.0 180.0 150.0 90.0 100.0 20.0 100.0 140.0 130.0 100.0 90.0 100.0 20.0 60.0 100.0 120.0 60.0 50.0 60.0 120.0 450.0 600.0 350.0 120.0 250.0 300.0 50.0 180.0 200.0 180.0 250.0 170.0 50.0 180.0 200.0 180.0 170.0
L-058
BL-Bx330M Series