4306-004LF;中文规格书,Datasheet资料
MW6S004NT1;中文规格书,Datasheet资料
RF Power Field Effect TransistorN-Channel Enhancement-Mode Lateral MOSFETDesigned for Class A or Class AB base station applications with frequencies up to 2000 MHz. Suitable for analog and digital modulation and multicarrier amplifier applications.•Typical Two-Tone Performance @ 1960 MHz, 28 Volts, I DQ = 50 mA, P out = 4 Watts PEP Power Gain — 18 dB Drain Efficiency — 33%IMD — -34 dBc•Typical Two-Tone Performance @ 900 MHz, 28 Volts, I DQ = 50 mA, P out = 4 Watts PEP Power Gain — 19 dB Drain Efficiency — 33%IMD — -39 dBc•Capable of Handling 5:1 VSWR, @ 28 Vdc, 1960 MHz, 4 Watts CW Output Power Features•Characterized with Series Equivalent Large-Signal Impedance Parameters •On-Chip RF Feedback for Broadband Stability •Integrated ESD Protection •RoHS Compliant•In Tape and Reel. T1 Suffix = 1000 Units per 12 mm, 7 inch Reel.Table 1. Maximum RatingsRatingSymbol Value Unit Drain-Source Voltage V DSS -0.5, +68Vdc Gate-Source Voltage V GS -0.5, +12Vdc Storage Temperature Range T stg -65 to +150°C Operating Junction TemperatureT J150°CTable 2. Thermal CharacteristicsCharacteristicSymbol Value (1,2)Unit Thermal Resistance, Junction to CaseCase Temperature 76°C, 4 W PEP , Two-Tone Case Temperature 79°C, 4 W CWR θJC8.88.5°C/WTable 3. ESD Protection CharacteristicsTest MethodologyClass Human Body Model (per JESD22-A114)1C (Minimum)Machine Model (per EIA/JESD22-A115) A (Minimum)Charge Device Model (per JESD22-C101)IV (Minimum)1.MTTF calculator available at /rf. Select Software & Tools/Development Tools/Calculators to access MTTF calculators by product.2.Refer to AN1955, Thermal Measurement Methodology of RF Power Amplifiers. Go to /rf. Select Documentation/Application Notes - AN1955.Document Number: MW6S004NRev. 4, 6/2009Freescale Semiconductor Technical DataMW6S004NT1Table 4. Moisture Sensitivity LevelTest MethodologyRating Package Peak TemperatureUnit Per JESD 22-A113, IPC/JEDEC J-STD-0203260°CTable 5. Electrical Characteristics (T A = 25°C unless otherwise noted)CharacteristicSymbolMinTypMaxUnitOff CharacteristicsZero Gate Voltage Drain Leakage Current (V DS = 68 Vdc, V GS = 0 Vdc)I DSS ——10μAdc Zero Gate Voltage Drain Leakage Current (V DS = 28 Vdc, V GS = 0 Vdc)I DSS ——10μAdc Gate-Source Leakage Current (V GS = 5 Vdc, V DS = 0 Vdc)I GSS——500nAdcOn CharacteristicsGate Threshold Voltage(V DS = 10 Vdc, I D = 50 mAdc)V GS(th) 1.22 2.7Vdc Gate Quiescent Voltage(V DS = 28 Vdc, I D = 50 mAdc)V GS(Q)— 2.7—Vdc Fixture Gate Quiescent Voltage (1)(V DD = 28 Vdc, I D = 50 mAdc, Measured in Functional Test)V GG(Q) 2.23 4.2Vdc Drain-Source On-Voltage(V GS = 10 Vdc, I D = 50 mAdc)V DS(on)—0.270.37VdcDynamic CharacteristicsReverse Transfer Capacitance(V DS = 28 Vdc ± 30 mV(rms)ac @ 1 MHz, V GS = 0 Vdc)C rss —21—pF Output Capacitance(V DS = 28 Vdc ± 30 mV(rms)ac @ 1 MHz, V GS = 0 Vdc)C oss —25—pF Input Capacitance(V DS = 28 Vdc, V GS = 0 Vdc ± 30 mV(rms)ac @ 1 MHz)C iss—30—pFFunctional Tests (In Freescale Test Fixture, 50 ohm system) V DD = 28 Vdc, I DQ = 50 mA, P out = 4 W PEP , f1 = 1960 MHz, f2 = 1960.1 MHz, Two-Tone Test Power Gain G ps 16.51820dB Drain EfficiencyηD 2833—%Intermodulation Distortion IMD —-34-28dBc Input Return LossIRL—-12-10dBTypical Performance (In Freescale 900 MHz Demo Board, 50 ohm system) V DD = 28 Vdc, I DQ = 50 mA, P out = 4 W PEP , f = 900 MHz, Two-Tone Test, 100 kHz Tone Spacing Power Gain G ps —19—dB Drain EfficiencyηD —33—%Intermodulation Distortion IMD —-39—dBc Input Return LossIRL—-12—dB1.V GG = 11/10 x V GS(Q). Parameter measured on Freescale Test Fixture, due to resistive divider network on the board. Refer to Test Circuit Schematic.MW6S004NT1Figure 1. MW6S004NT1 Test Circuit SchematicZ70.210″ x 1.220″ Microstrip Z80.054″ x 0.680″ Microstrip Z90.054″ x 0.260″ Microstrip Z100.025″ x 0.930″ MicrostripPCBArlon CuClad 250GX-0300-55-22, 0.020″, εr = 2.5Z10.054″ x 0.430″ Microstrip Z20.054″ x 0.137″ Microstrip Z30.580″ x 0.420″ Microstrip Z40.580″ x 0.100″ Microstrip Z50.025″ x 0.680″ Microstrip Z60.210″ x 0.100″ MicrostripV SUPPLYTable 6. MW6S004NT1 Test Circuit Component Designations and ValuesPartDescriptionPart Number Manufacturer C1100 nF Chip Capacitor CDR33BX104AKYS Kemet C2, C3, C6, C79.1 pF Chip Capacitors ATC100B9R1CT500XT ATC C4, C510 μF, 50 V Chip Capacitors GRM55DR61H106KA88B Murata C810 μF, 35 V Tantalum Chip Capacitor T490D106K035AT Kemet R1 1 k Ω, 1/4 W Chip Resistor CRCW12061001FKEA Vishay R210 k Ω, 1/4 W Chip Resistor CRCW12061002FKEA Vishay R310 Ω, 1/4 W Chip ResistorCRCW120610R0FKEAVishayMW6S004NT1Figure 2. MW6S004NT1 Test Circuit Component LayoutMW6S004NT1TYPICAL CHARACTERISTICS1420191716G p s , P O W E R G A I N (d B )100.1TWO−TONE SPACING (MHz)1100Figure 6. Intermodulation Distortion Productsversus Tone Spacing 26P in , INPUT POWER (dBm)1618222414Figure 7. Pulsed CW Output Power versusInput PowerI M D , I N T E R M O D U L A T I O N D I S T O R T I O N (d B c )181520MW6S004NT1TYPICAL CHARACTERISTICSA C P R (dB )−70P out , OUTPUT POWER (WATTS) AVG.50−2040−3030−4020−5010−600.01110Figure 8. Single-Carrier CDMA ACPR, Power Gainand Drain Efficiency versus Output PowerP out , OUTPUT POWER (WATTS) CWFigure 10. Power Gain versus Output Power 7151906171618234G p s , P O W E R G A I N (d B )1800−250f, FREQUENCY (MHz)Figure 11. Broadband Frequency Response−5−10−15−20210020502000195019001850S 11 (d B )851ηD , D R A I N E F F I C I E N C Y (%), G p s , P O W E R G A I N (d B )0.118.517.516.515.5MW6S004NT1TYPICAL CHARACTERISTICS25010790T J , JUNCTION TEMPERATURE (°C)Figure 12. MTTF versus Junction TemperatureThis above graph displays calculated MTTF in hours when the device is operated at V DD = 28 Vdc, P out = 4 W PEP, and ηD = 33%.MTTF calculator available at /rf. Select Software & Tools/Development Tools/Calculators to access MTTF calculators by product.106105104110130150170190M T T F (H O U R S )210230MW6S004NT1f = 1930 MHzZ o = 10 ΩZ loadZ sourcef = 1990 MHzf = 1930 MHzf = 1990 MHzV DD = 28 Vdc, I DQ = 50 mA, P out = 4 W PEPfMHzZ sourceWZ loadW1930 1.96 - j5.348.78 + j6.961960 1.89 - j5.108.93 + j7.461990 1.82 - j4.859.11 + j7.97Z source=Test circuit impedance as measured fromgate to ground.Z load=Test circuit impedance as measured fromdrain to ground.Z source Z loadOutputMatchingNetworkFigure 13. Series Equivalent Source and Load ImpedanceMW6S004NT1Table 7. Common Source Scattering Parameters (V DD = 28 V, 50 ohm system)I DQ = 50 mAf MH S 11S 21S 12S 22MHz |S 11|∠φ|S 21|∠φ|S 12|∠φ|S 22|∠φ5000.649-116.3407.902105.4200.056-73.7500.548-33.5705500.695-121.6807.50298.7900.053-80.5700.593-41.4806000.733-126.5607.11192.3800.049-87.0100.632-48.8906500.770-131.340 6.69986.2900.045-93.2800.669-56.0007000.800-135.740 6.30280.4500.041-99.1200.701-62.8107500.827-140.030 5.92274.8500.038-104.8500.727-69.2908000.848-143.950 5.55269.6300.035-110.1100.750-75.3508500.866-147.690 5.22064.5800.032-115.2200.770-81.1309000.882-151.140 4.89159.9700.029-119.9600.786-86.5709500.895-154.560 4.59755.4900.026-124.7900.800-91.73010000.907-157.590 4.31551.2400.024-129.0900.813-96.66010500.916-160.540 4.06047.1700.022-133.3700.824-101.34011000.923-163.310 3.81943.3400.020-137.4600.833-105.79011500.929-165.930 3.60139.6500.018-141.4400.840-110.05012000.935-168.430 3.39836.1100.017-145.3300.847-114.17012500.938-170.770 3.21032.7400.015-149.5400.851-118.06013000.942-173.030 3.03629.4900.014-153.4300.856-121.88013500.945-175.140 2.87526.3600.013-157.4600.859-125.52014000.948-177.170 2.72823.3300.012-161.9100.863-129.02014500.951-179.090 2.59020.4400.011-166.1800.866-132.39015000.953179.030 2.46417.6400.010-170.6300.869-135.65015500.954177.270 2.34714.9200.009-174.8900.872-138.76016000.955175.570 2.24012.3200.008179.9500.875-141.75016500.956173.980 2.1399.7400.008173.9200.877-144.65017000.957172.350 2.0477.2500.007167.7100.880-147.48017500.957170.800 1.958 4.8100.007161.8100.882-150.18018000.958169.340 1.879 2.4400.006155.3700.884-152.76018500.959167.920 1.8060.2600.006148.9400.886-155.23019000.959166.510 1.736-1.9800.005142.6300.887-157.58019500.960165.200 1.668-4.3100.005136.7400.888-160.05020000.959163.800 1.611-6.2400.005129.9100.890-162.07020500.959162.420 1.555-8.2900.005123.8100.891-164.19021000.958161.170 1.504-10.2700.005118.2000.892-166.14021500.958159.840 1.456-12.2100.005112.7400.893-168.06022000.957158.560 1.412-14.1300.005108.4600.894-169.84022500.957157.160 1.372-16.0100.005103.8400.896-171.61023000.955155.870 1.334-17.8700.00599.3100.896-173.26023500.954154.510 1.300-19.7000.00595.3600.897-174.83024000.953153.120 1.268-21.5100.00591.0300.898-176.39024500.953151.7301.238-23.2500.00587.4600.899-177.840MW6S004NT1Table 7. Common Source Scattering Parameters (V DD = 28 V, 50 ohm system) (continued)I DQ = 50 mAf MH S 11S 21S 12S 22MHz |S 11|∠φ|S 21|∠φ|S 12|∠φ|S 22|∠φ25000.952150.340 1.211-25.1200.00684.1600.899-179.27025500.950149.010 1.187-26.9200.00680.7800.897179.42026000.949147.380 1.166-28.6500.00677.8800.897178.12026500.948145.920 1.144-30.4200.00774.6700.898176.84027000.944144.200 1.121-32.3100.00771.3600.896175.48027500.944142.790 1.105-34.2300.00767.9800.897174.06028000.943141.020 1.088-36.0000.00763.9500.897172.93028500.941139.410 1.073-37.8700.00761.2300.896171.63029000.940137.640 1.058-39.7600.00859.8100.896170.33029500.938135.900 1.045-41.6800.00858.2800.896169.04030000.937133.8601.032-43.6100.00856.7400.895167.510分销商库存信息: FREESCALEMW6S004NT1。
HY4306B6 datasheet_v1.0
Pin1Pin7Pin1Pin2,3,5,6,7 Pin4Feature Description Pin Description●60V/290AR DS(ON)= 1.8m Ω(typ.)@V GS = 10V● 100% Avalanche Tested ● Reliable and Rugged●Lead Free and Green Devices Available (RoHS Compliant)Applications● Switch application ● Brushless Motor DriveOrdering and Marking InformationHY4306 YYXXXJWW G Note: HOOYI lead-free products contain molding compounds/die attach materials and 100% matte tin plate Termi- Nation finish;which are fully compliant with RoHS. HOOYI lead-free products meet or exceed the lead-Free require- ments of IPC/JEDEC J-STD-020 for MSL classification at lead-free peak reflow temperature. HOOYI defines “Green ” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight).HOOYI reserves the right to make changes, corrections, enhancements, modifications, and improvements to this pr -oduct and/or to this document at any time without notice.TO-263-6LN-Channel MOSFETAbsolute Maximum RatingsNote: * Repetitive rating；pulse width limited by max.junction temperature.** Surface mounted on FR-4 board.*** Limited by T J max , starting T J=25°C, L =0.5mH, R G= 25Ω, V GS =10V. Electrical Characteristics(Tc =25°C Unless Otherwise Noted)Electrical Characteristics (Cont.) (Tc =25°C Unless Otherwise Noted)Note: *Pulse test，pulse width ≤ 300us，duty cycle ≤ 2%Typical Operating CharacteristicsFigure 1: Power Dissipation Figure 2: Drain CurrentTc-Case Temperature(℃) Tc-Case Temperature(℃)Figure 3: Safe Operation Area Figure 4: Thermal Transient ImpedanceV DS -Drain-Source Voltage(V)Maximum Effective Transient ThermalImpedance, Junction-to-CaseFigure 5: Output Characteristics Figure 6: Drain-Source On ResistanceV DS -Drain-Source Voltage (V) I D -Drain Current(A)I D -D r a i n C u r r e n t (A )I D -D r a i n C u r r e n t (A )R D S (O N )-O N -R e s i s t a n c e (Ω)Typical Operating Characteristics(Cont.)Figure 7: On-Resistance vs. Temperature Figure 8: Source-Drain Diode ForwardTj-Junction Temperature (℃)V SD -Source-Drain Voltage(V)Figure 9: Capacitance Characteristics Figure 10: Gate Charge CharacteristicsV DS -Drain-Source Voltage (V) Q G -Gate Charge (nC )C -C a p a c i t a n c e (p F )N o r m a l i z e d O n -R e s i s t a n c eI S -S o u r c e C u r r e n t (A )Avalanche Test Circuit and WaveformsSwitching Time Test Circuit and WaveformsGate Charge Test Circuit and WaveformsDevice Per UnitPackage Information TO-263-6LClassification ProfileClassification Reflow ProfilesCustomer ServiceWorldwide Sales and Service: sales@Technical Support: technical @Xi’an Hooyi Semiconductor Technology Co., Ltd.No.105,5th Fengcheng Road, Economic and Technological Development Zone, Xi'an,China TEL: (86-029) 86685706FAX: (86-029) 86685705E-mail: sales@Web net: 。
TP4056_中文资料_datasheet
4
ms
2.0
μA
典型性能特征
恒定电流模式下 PROG 引脚 电压与电源电压的关系曲线
PROG 引脚电压与温度的 关系曲线
充电电流与 PROG 引脚电 压的关系曲线
稳定输出（浮充）电压与充 电电流的关系曲线
稳定输出（浮充）电压与温 度的关系曲线
稳定输出（浮充）电压与电 压的关系曲线
涓流充电门限与温度的关系 曲线
态，将电池漏电流降至 2uA 以下。TP4056 在有电源时也可置于停机模式以而将供电
电流降至 55uA。TP4056 的其他特点包括电池温度检测、欠压闭锁、自动再充电和两个
用于指示充电、结束的 LED 状态引脚。
特点
·高达 1000mA 的可编程充电电流 ·无需 MOSFET、检测电阻器或隔离二极管 ·用于单节锂离子电池、采用 SOP 封装的完整
100mV
以下的时间超过
t TERM
(一般为
1.8ms)
时，充电被终止。充电电流被锁断，TP4056 进
入待机模式，此时输入电源电流降至 55μA。
（注：C/10 终止在涓流充电和热限制模式中失
效）。
充 电 时 ， BAT 引 脚 上 的 瞬 变 负 载 会 使
PROG 引脚电压在 DC 充电电流降至设定值的
行。如果电池电压低于 3V，充电器用小电流对 电池进行预充电。当电池电压超过 3V 时，充电 器采用恒流模式对电池充电，充电电流由 PROG 管脚和 GND 之间的电阻 RPROG 确定。当电池电 压接近 4.2V 电压时，充电电流逐渐减小，TP4056 进入恒压充电模式。当充电电流减小到充电结 束阈值时，充电周期结束， 端输出高阻态，
典型应用
封装/订购信息
0444280406;中文规格书,Datasheet资料
This document was generated on 08/20/2012PLEASE CHECK FOR LATEST PART INFORMATIONPart Number:44428-0406Status:ActiveOverview:Micro-Fit 3.0™ ConnectorsDescription:3.00mm Pitch Micro-Fit 3.0 BMI™ Header, Surface Mount Compatible, Dual Row, Right Angle, without Snap-in Plastic Peg PCB Lock, 4 Circuits, 0.76µm Gold (Au) Selective PlatingDocuments:3D ModelRoHS Certificate of Compliance (PDF)Drawing (PDF)Product Literature (PDF)Product Specification PS-44300-001 (PDF)Agency CertificationCSA LR19980TUV R72081037ULE29179GeneralProduct Family PCB Headers Series44428Application Board-to-Board, Power, Wire-to-BoardCommentsHigh Temperature|Square Pin|Solder Type|Polarized to Mating PartOverviewMicro-Fit 3.0™ Connectors Product Literature Order No 987650-5984Product Name Micro-Fit 3.0 BMI™UPC756054345894PhysicalBreakawayNo Circuits (Loaded)4Circuits (maximum)4Color - ResinBlack Durability (mating cycles max)30First Mate / Last Break No Flammability94V-0Glow-Wire Compliant No Guide to Mating Part No Keying to Mating Part None Lock to Mating Part Yes Material - MetalBrass Material - Plating MatingGold Material - Plating Termination TinMaterial - Resin High Temperature Thermoplastic Net Weight1.394/g Number of Rows 2Orientation Right Angle PC Tail Length 3.50mm PCB Locator Yes PCB RetentionYes PCB Thickness - Recommended 1.60mm Packaging TypeTray Pitch - Mating Interface 3.00mm Plating min - Mating0.762µm Plating min - Termination 2.540µm Polarized to PCBYesSeriesimage - Reference onlyEU RoHSChina RoHSELV and RoHS Compliant REACH SVHCContains SVHC: No Low-Halogen Status Not Low-HalogenNeed more information on product environmental compliance?Email productcompliance@For a multiple part number RoHS Certificate of Compliance, click herePlease visit the Contact Us section for any non-product compliance questions.Search Parts in this Series 44428SeriesMates With44133 , 44764 , 44769Shrouded FullyStackable NoSurface Mount Compatible (SMC)YesTemperature Range - Operating-40°C to +105°CTermination Interface: Style Through HoleElectricalCurrent - Maximum per Contact5AVoltage - Maximum250VSolder Process DataDuration at Max. Process Temperature (seconds)5Lead-free Process Capability Wave Capable (TH only)Max. Cycles at Max. Process Temperature1Process Temperature max. C260Material InfoReference - Drawing NumbersProduct Specification PS-44300-001, RPS-44300-001Sales Drawing SD-44428-001This document was generated on 08/20/2012PLEASE CHECK FOR LATEST PART INFORMATION分销商库存信息: MOLEX 0444280406。
IRGP4086PBF;中文规格书,Datasheet资料
tf
Fall time
td(on)
Turn-On delay time
tr
Rise time
— 65 —
— 30 —
IC = 25A, VCC = 196V
— 33 — ns RG = 10Ω, L=200μH, LS= 200nH
td(off) tf tst
EPULSE
Turn-Off delay time Fall time Shoot Through Blocking Time
2
/
240
VGE = 18V
200
VGE = 15V
VGE = 12V
160
VGE = 10V VGE = 8.0V
120
VGE = 6.0V
ICE (A)
80
40
0
0
4
8
12
16
VCE (V)
Fig 1. Typical Output Characteristics @ 25°C
––– 29 ––– ––– 65 ––– ––– 22 ––– — 36 — — 31 — — 112 —
S VCE = 25V, ICE = 25A nC VCE = 200V, IC = 25A, VGE = 15Ve
IC = 25A, VCC = 196V ns RG = 10Ω, L=200μH, LS= 200nH
Parameter Thermal Resistance Junction-to-Case-(each IGBT) d Case-to-Sink (flat, greased surface) Junction-to-Ambient (typical socket mount) d Weight
HEF4046BT,653;HEF4046BT,652;HEF4046BP,652;中文规格书,Datasheet资料
HEF4046B MSI
15. Zener diode input for regulated supply. Fig.2 Pinning diagram.
FUNCTIONAL DESCRIPTION VCO part The VCO requires one external capacitor (C1) and one or two external resistors (R1 or R1 and R2). Resistor R1 and capacitor C1 determine the frequency range of the VCO. Resistor R2 enables the VCO to have a frequency off-set if required. The high input impedance of the VCO simplifies the design of low-pass filters; it permits the designer a wide choice of resistor/capacitor ranges. In order not to load the low-pass filter, a source-follower output of the VCO input voltage is provided at pin 10. If this pin (SFOUT) is used, a load resistor (RSF) should be connected from this pin to VSS; if unused, this pin should be left open. The VCO output (pin 4) can either be connected directly to the comparator input (pin 3) or via a frequency divider. A LOW level at the inhibit input (pin 5) enables the VCO and the source follower, while a HIGH level turns off both to minimize stand-by power consumption. Phase comparators The phase-comparator signal input (pin 14) can be direct-coupled, provided the signal swing is between the standard HE4000B family input logic levels. The signal must be capacitively coupled to the self-biasing amplifier at the signal input in case of smaller swings. Phase comparator 1 is an EXCLUSIVE-OR network. The signal and comparator input frequencies must have a 50% duty January 1995 3
IRLML0040TRPBF;中文规格书,Datasheet资料
100 D = 0.50
0.20
10
0.10
0.05
0.02
1
0.01
0.1
0.01
0.001 1E-006
1E-005
Fig 4. Normalized On-Resistance Vs. Temperature 3
ID, Drain-to-Source Current (A)
/
IRLML0040TRPbF
C, Capacitance (pF)
10000 1000 100
VGS = 0V, f = 1 MHZ Ciss = C gs + Cgd, C ds SHORTED Crss = Cgd Coss = Cds + Cgd
IRLML0040TRPbF
ID, Drain Current (A)
4.2
3.6
3
2.4
1.8
1.2
0.6
0 25
50
75
100 125 150
TA , Ambient Temperature (°C)
Fig 9. Maximum Drain Current Vs. Ambient Temperature
4
1
1msec
0.1 TA = 25°C Tj = 150°C Single Pulse
10msec
0.01
0
1
10
100
VDS, Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
/
PD @TA = 25°C
Maximum Power Dissipation
LTC4306中文资料
V CC = 3.3VVCARD1 = 3.3VVCARD4 = 5VVBACK = 2.5V SCL42V/DIVSCL12V/DIVSCLIN 2V/DIV(Note 1)Supply Voltage (V CC )...................................–0.3V to 7V Input Voltages (ADR0, ADR1, ADR2,ENABLE, ALERT1, ALERT2, ALERT3,ALERT4)..................................................–0.3V to 7V Output Voltages (ALERT, READY)...............–0.3V to 7V Input/Output Voltages (SDAIN, SCLIN,SCL1, SDA1, SCL2, SDA2, SCL3,SDA3, SCL4, SDA4, GPIO1, GPIO2)........–0.3V to 7VOperating Temperature RangeLTC4306C ...............................................0°C to 70°C LTC4306I.............................................–40°C to 85°C Storage Temperature RangeSSOP.................................................–65°C to 150°C QFN ...................................................–65°C to 125°C Lead Temperature (Soldering, 10 sec)SSOP................................................................300°CConsult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.ABSOLUTE AXI U RATI GSW W WU The ● denotes specifications which apply over the full specified temperaturerange, otherwise specifications are at T A = 25°C. V CC = 3.3V unless otherwise noted.ELECTRICAL CHARACTERISTICSThe ● denotes specifications which apply over the full specified temperature range, otherwise specifications are at T A = 25°C. V CC = 3.3V unless otherwise noted.Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired.Note 2: Guaranteed by design and not subject to test.Note 3: The boosted pull-up currents are regulated to prevent excessively fast edges for light loads. See the Typical Performance Characteristics for rise time as a function of V CC and parasitic bus capacitance C BUS and for I BOOST as a function of V CC and temperature.Note 4: When a logic low voltage, V LOW, is forced on one side of the Upstream-Downstream Buffers, the voltage on the other side is regulated to a voltage V LOW2 = V LOW + V OS, where V OS is a positive offset voltage. V OS,UP-BUF is the offset voltage when the LTC4306 is driving the upstream pin (e.g., SDAIN) and V OS,DOWN-BUF is the offset voltage when theLTC4306 is driving the downstream pin (e.g., SDA1). See the Typical Performance Characteristics for V OS,UP-BUF and V OS,DOWN-BUF as a function of V CC and bus pull-up current.Note 5: When floating, the ADR0-ADR2 pins can tolerate pin leakage currents up to I ADR(FLOAT) and still convert the address correctly.ELECTRICAL CHARACTERISTICSUUUPI FU CTIO S (GN24 Package/UFD24 Package)ALERT (Pin 3/Pin 1): Fault Alert Output. An open-drain output that is pulled low when a fault occurs to alert the host controller. The LTC4306 pulls ALERT low when any of the ALERT1-ALERT4 pins is low, when the 2-wire bus is stuck low, or when the Connection Requirement bit of Register 2 is low and a master tries to connect to a downstream channel that is low. See Operation section for the details of how ALERT is set and cleared. The LTC4306 is compatible with the SMBus Alert Response Address protocol. Connect a 10k resistor to a power supply voltage to provide the pull-up. Tie to ground if unused. SDAIN (Pin 4/Pin 2): Serial Bus Data Input and Output. Connect this pin to the SDA line on the master side. An external pull-up resistor or current source is required. GND (Pin 5/Pin 3): Device Ground.SCLIN (Pin 6/Pin 4): Serial Bus Clock Input. Connect this pin to the SCL line on the master side. An external pull-up resistor or current source is required.ENABLE (Pin 7/Pin 5): Digital Interface Enable and Regis-ter Reset. Driving ENABLE high enables I2C communica-tion to the LTC4306. Driving this pin low disables I2C communication to the LTC4306 and resets the registers to their default state as shown in the Operation section. When ENABLE returns high, masters can read and write the LTC4306 again. If unused, tie ENABLE to V CC.V CC (Pin 8/Pin 6): Power Supply Voltage. Connect a bypass capacitor of at least 0.01µF directly between V CC and GND for best results.GPIO1-GPIO2 (Pins 10, 11/Pins 8, 9): General Purpose Input/Output. These two pins can be used as logic inputs, open-drain outputs or push-pull outputs. The N-channel MOSFET pull-down devices are capable of driving LEDs. When used in input or open-drain output mode, the GPIOs can be pulled up to a supply voltage ranging from 1.5V to 5.5V independent of the V CC voltage. GPIOs default to a high impedance open-drain output mode. There are GPIO configuration and status bits in Register 1 and Register 2. Float if unused.ADR0-ADR2 (Pins 12, 13, 14/Pins 10, 11, 12): Three-State Serial Bus Address Inputs. Each pin may be floated, tied to ground or tied to V CC. There are therefore 27 possible addresses. See Table 1 in applications informa-tion. When the pins are floated, they can tolerate ±5µA of leakage current and still convert the address correctly. READY (Pin 15/Pin 13): Connection Ready Digital Output. An N-channel MOSFET open-drain output transistor that pulls down when none of the downstream channels is connected to the upstream bus and turns off when one or more downstream channels is connected to the upstream bus. Connect a 10k resistor to a power supply voltage to provide the pull-up. Tie to ground if unused.SCL1-SCL4 (Pins 18, 23, 1, 17/Pins 16, 21, 23, 15): Serial Bus Clock Outputs Channels 1-4. Connect pins SCL1-SCL4 to the SCL lines on the downstream channels 1-4, respectively. It is acceptable to float any pin that will never be connected to the upstream bus. Other-wise, an external pull-up resistor or current source is required on each pin.SDA1-SDA4 (Pins 19, 22, 2, 16/Pins 17, 20, 24, 14): Serial Bus Data Output Channels 1-4. Connect pins SDA1-SDA4 to the SDA lines on downstream channels 1-4, respectively. It is acceptable to float any pin that will never be connected to the upstream bus. Otherwise, an external pull-up resistor or current source is required on each pin.ALERT1-ALERT4 (Pins 20, 24, 21, 9/Pins 18, 22, 19, 7): Fault Alert Inputs, Channels 1-4. Devices on each of the four output channels can pull their respective pin low to indicate that a fault has occurred. The LTC4306 then pulls the ALERT low to pass the fault indication on to the host. See Operation section below for the details of how ALE RT is set and cleared. Connect unused fault alert inputs to V CC.Exposed Pad (Pin 25, UFD Package Only): Power Ground. Exposed Pad may be left open or connected to device ground.Control Register Bit Definitions OPERATIORegister 0 (00h)BIT NAME TYPE*DESCRIPTIONd7Downstream R Indicates if upstream bus is connected Connected to any downstream buses0 = upstream bus disconnected fromall downstream buses1 = upstream bus connected to one ormore downstream busesd6ALERT1 Logic State R Logic state of ALERT1 pin, noninverting d5ALERT2 Logic State R Logic state of ALERT2 pin, noninverting d4ALERT3 Logic State R Logic state of ALERT3 pin, noninverting d3ALERT4 Logic State R Logic state of ALERT4 pin, noninverting d2Failed Connection R Indicates if an attempt to connect to a Attempt downstream bus failed because the“Connection Requirement” bit inRegister 2 was low and thedownstream bus was low0 = Failed connection attempt occurred1 = No failed attempts at connectionoccurredd1Latched Timeout R Latched bit indicating if a timeout hasoccurred and has not yet been cleared.0 = no latched timeout1 = latched timeoutd0Timeout Real Time R Indicates real-time status of Stuck LowTimeout Circuitry0 = no timeout is occurring1 = timeout is occurringNote: Masters write to Register 0 to reset the fault circuitry after a fault has occurred and been resolved. Because Register 0 is Read-Only, no other functionality is affected.* For Type, “R/W” = Read Write, “R” = Read Only Register 1 (01h)BIT NAME TYPE*DESCRIPTIONd7Upstream R/W Activates upstream rise time Accelerators accelerator currentsEnable0 = upstream rise time acceleratorcurrents inactive (default)1 = upstream rise time acceleratorcurrents actived6Downstream R/W Activates downstream rise time Accelerators accelerator currentsEnable0 = downstream rise time acceleratorcurrents inactive (default)1 = downstream rise time acceleratorcurrents actived5GPIO1 Output R/W GPIO1 output driver state,Driver State noninverting, default = 1d4GPIO2 Output R/W GPIO2 output driver state,Driver State noninverting, default = 1d3-d2Reserved R Not Usedd1GPIO1 Logic R Logic state of GPIO1 pin,State noninvertingd0GPIO2 Logic R Logic state of GPIO2 pin,State noninverting* For Type, “R/W” = Read Write, “R” = Read OnlyRegister 2 (02h)BIT NAME TYPE*DESCRIPTIONd7GPIO1 ModeR/W Configures Input/Output mode ofConfigureGPIO10 = output mode (default)1 = input mode d6GPIO2 ModeR/W Configures Input/Output Mode ofConfigureGPIO20 = output mode (default)1 = input mode d5ConnectionR/W Sets logic requirements forRequirementdownstream buses to be connected to upstream bus0 = Bus Logic State bits (see register 3) of buses to be connected must be high for connection to occur (default)1 = Connect regardless of downstream logic state d4GPIO1 OutputR/W Configures GPIO1 Output ModeMode Configure 0 = open-drain pull-down (default)1 = push-pull d3GPIO2 OutputR/W Configures GPIO2 Output ModeMode Configure 0 = open-drain pull-down (default)1 = push-pull d2Mass Write EnableR/W Enable Mass Write Address usingaddress (1011 101)b 0 = Disable Mass Write1 = Enable Mass Write (default)d1Timeout Mode Bit 1R/W Stuck Low Timeout Set Bit 1**d0Timeout Mode Bit 0R/W Stuck Low Timeout Set Bit 0*** For Type, “R/W” = Read Write, “R” = Read Only **Stuck bus program tableTIMSET1TIMSET0TIMEOUT MODE 00Timeout Disabled (Default)01Timeout After 30ms 10Timeout After 15ms 11Timeout After 7.5msOPERATIORegister 3 (03h)BIT NAME TYPE*DESCRIPTIONd7Bus 1 FET StateR/W Sets and indicates state of FETswitches connected to downstream bus 10 = switch open (default)1 = switch closed d6Bus 2 FET StateR/W Sets and indicates state of FETswitches connected to downstream bus 20 = switch open (default)1 = switch closed d5Bus 3 FET StateR/W Sets and indicates state of FETswitches connected to downstream bus 30 = switch open (default)1 = switch closed d4Bus 4 FET StateR/W Sets and indicates state of FETswitches connected to downstream bus 40 = switch open (default)1 = switch closed d3Bus 1 Logic StateRIndicates logic state of downstream bus 1; only valid when disconnected from upstream bus †0 = SDA1, SCL1 or both are below 1V 1 = SDA1 and SCL1 are both above 1Vd2Bus 2 Logic StateRIndicates logic state of downstream bus 2; only valid when disconnected from upstream bus †0 = SDA2, SCL2 or both are below 1V 1 = SDA2 and SCL2 are both above 1Vd1Bus 3 Logic State RIndicates logic state of downstream bus 3; only valid when disconnected from upstream bus †0 = SDA3, SCL3 or both are below 1V 1 = SDA3 and SCL3 are both above 1Vd0Bus 4 Logic State RIndicates logic state of downstream bus 4; only valid when disconnected from upstream bus †0 = SDA4, SCL4 or both are below 1V 1 = SDA4 and SCL4 are both above 1V* For Type, “R/W” = Read Write, “R” = Read Only† These bits give the logic state of disconnected downstream buses to the master, so that the master can choose not to connect to a low downstream bus. A given bit is a “don’t care” if its associated downstream bus is already connected to the upstream bus.The LTC4306 is a 4-channel, 2-wire bus multiplexer/ switch with bus buffers to provide capacitive isolation between the upstream bus and downstream buses. Mas-ters on the upstream 2-wire bus (SDAIN and SCLIN) can command the LTC4306 to any combination of the 4 downstream buses. Masters can also program the LTC4306 to disconnect the upstream bus from the downstream buses if the bus is stuck low.Undervoltage Lockout (UVLO) and ENABLE FunctionalityThe LTC4306 contains undervoltage lockout circuitry that maintains all of its SDA, SCL, GPIO and ALERT pins in high impedance states until the device has sufficient V CC supply voltage to function properly. It also ignores any attempts to communicate with it via the 2-wire buses in this condi-tion. When the ENABLE pin voltage is low (below 0.8V), all control bits are reset to their default high impedance states, and the LTC4306 ignores 2-wire bus commands. However, with ENABLE low, the LTC4306 still monitors the ALERT1-ALERT4 pin voltages and pulls the ALERT pin low if any of ALERT1-ALERT4 is low. When ENABLE is high, devices can read from and write to the LTC4306. Connection CircuitryMasters on the upstream SDAIN/SCLIN bus can write to the Bus 1 FET State through Bus 4 FET State bits of register 3 to connect to any combination of downstream channels 1 to 4. By default, the Connection Circuitry shown in the Block Diagram will only connect to downstream channels whose corresponding Bus Logic State bits in register3 are high at the moment that it receives the connection com-mand. If the LTC4306 is commanded to connect to mul-tiple channels at once, it will only connect to the channels that are high. Masters can override this feature by setting the Connection Requirement bit of register 2 high. With this bit high, the LTC4306 executes connection com-mands without regard to the logic states of the down-stream channels.Upon receiving the connection command, the Connec-tion Circuitry will activate the Upstream-Downstream Buffers under two conditions: first, the master must be commanding connection to one or more downstream channels, and second, there must be no stuck low condition (see Stuck Low Timeout Fault discussion). If the connection command is successful, the Upstream-Downstream Buffers pass signals between the upstream bus and the connected downstream buses. The LTC4306 also turns off its N-channel MOSFET open-drain pull-down on the READY pin, so that READY can be pulled high by its external pull-up resistor.Upstream-Downstream BuffersOnce the Upstream-Downstream Buffers are activated, the functionality of the SDAIN and any connected down-stream SDA pins is identical. A low forced on any con-nected SDA pin at any time results in all pins being low. External devices must pull the pin voltages below 0.4V worst-case with respect to the LTC4306’s ground pin to ensure proper operation. The SDA pins enter a logic high state only when all devices on all connected SDA pins force a high. The same is true for SCLIN and the connected downstream SCL pins. This important feature ensures that clock stretching, clock arbitration and the acknowl-edge protocol always work, regardless of how the devices in the system are connected to the LTC4306.The Upstream-Downstream Buffers provide capacitive isolation between SDAIN/SCLIN and the downstream con-nected buses. Note that there is no capacitive isolation between connected downstream buses; they are only separated by the series combination of their switches’ on resistances.While any combination of downstream buses may be connected at the same time, logic high levels are corrupted if multiple downstream buses are active and both the V CC voltage and one or more downstream bus pull-up voltages are larger than the pull-up supply voltage for another downsteam bus. An example of this issue is shown in Figure 1. During logic highs, DC current flows from V BUS1 through the series combination of R1, N1, N2 and R2 and into V BUS2, causing the SDA1 voltage to drop and current to be sourced into V BUS2. To avoid this problem, do not activate bus 1 or any other downstream bus whose pull-up voltage is above 2.5V when bus 2 is active.OPERATIO114306f12In all other cases, the LTC4306 communicates with the master to resolve the fault. After the master broadcasts theconnect to bus 2, so that it can communicate with the source of the fault. At this point, the master writes to OPERATIOOPERATIOTable 1. LTC4306 I2C Device AddressingHEX DEVICE LTC4306 DESCRIPTION ADDRESS BINARY DEVICE ADDRESS ADDRESS PINSh a6a5a4a3a2a1a0R/W ADR2ADR1ADR0Mass Write BA10111010X X X Alert Response1900011001X X X 0801000000X L NC L 1821000001X L H NC 2841000010X L NC NC 3861000011X L NC H 4881000100X L L L 58A1000101X L H H 68C1000110X L L NC 78E1000111X L L H 8901001000X NC NC L 9921001001X NC H NC 10941001010X NC NC NC 11961001011X NC NC H 12981001100X NC L L 139A1001101X NC H H 149C1001110X NC L NC 159E1001111X NC L H 16A01010000X H NC L 17A21010001X H H NC 18A41010010X H NC NC 19A61010011X H NC H 20A81010100X H L L 21AA1010101X H H H 22AC1010110X H L NC 23AE1010111X H L H 24B01011000X H H L 25B21011001X L H L 26B41011010X NC H Lusers follow the Write Byte protocol exactly, the new data contained in the Data Byte is written into the register selected by bits r1 and r0 on the Stop Bit.General Purpose Input/Outputs (GPIOs)The LTC4306 provides two general purpose input/output pins (GPIOs) that can be configured as logic inputs, open-drain outputs or push-pull outputs. The GPIO1 and GPIO2Mode Configure bits in register 2 determine whether the GPIOs are used as inputs or outputs. When the GPIOs are used as outputs, the GPIO1 and GPIO2 Output Mode Configure bits of register 2 configure the GPIO outputs either as open-drain N-channel MOSFET pull-downs or push-pull stages.In push-pull mode, at V CC = 3.3V, the typical pull-up impedance is 670Ω and the typical pull-down impedance134306f4306f14OPERATIOis 35Ω, making the GPIO pull-downs capable of driving LEDs. At V CC = 5V, the typical pull-up impedance is 320Ωand the typical pull-down impedance is 20Ω. In open-drain output mode, the user provides the logic high by connecting a pull-up resistor between the GPIO pin and an external supply voltage. The external supply voltage can range from 1.5V to 5.5V independent of the V CC voltage.In input mode, the GPIO input threshold voltage is 1V.The GPIO1 and GPIO2 Logic State bits in register 1indicate the logic state of the two GPIO pins. The logic-level threshold voltage for each pin is 1V. The GPIO1 and GPIO2 Output Driver State bits in register 1 indicate the logic state that the LTC4306 is attempting to write to the GPIO pins. This is useful when the GPIOs are being usedFigure 4. Protocols Accepted by LTC4306Figure 3. Data Transfer Over I 2C or SMBusSCLSDASTART CONDITIONSTOP CONDITIONADDRESS ACK DATA ACK DATA ACK1-7894306 F03a6-a0d7-d0d7-d01-7891-789PS4306 F04S 0M 1ALERT RESPONSE ADDRESS PROTOCOL1in open-drain output mode and one or more external devices are connected to the GPIOs. If the LTC4306 is trying to write a high to a GPIO pin, but the pin’s actual logic state is low, then the LTC4306 knows that the low is being forced by an external device.Glitch FiltersThe LTC4306 provides glitch filters on the SDAIN and SCLIN pins as required by the I 2C Fast Mode (400kHz)Specification. The filters prevent signals of up to 50ns (minimum) time duration and rail-to-rail voltage magnitude from passing into the two-wire bus digital interface circuitry.154306f16Assume in Figure 5 that the total parasitic bus capacitance on SDA1 due to trace and device capacitance is 100pF. To ensure that the boost currents are active during rising edges, the pull-up resistor must be strong enough to cause the SDA1 pin voltage to rise at a rate of 0.8V/µs as the pin voltage is rising above 0.8V. The equation is:R k V V ns V PULL UP MAX BUSMIN −Ω[]=⎡⎣⎢,(–.)•081250⎤⎦⎥⎧⎨⎩⎫⎬⎭[]C pF BUS (1)where V BUSMIN is the minimum operating pull-up supply voltage, and C BUS is the bus parasitic capacitance. In our example, V BUS1 = V CC = 3.3V, and assuming ±10% supply tolerance, V BUS1MIN = 2.97V. With C BUS = 100pF,R PULL-UP,MAX = 27.1k. Therefore, we must choose a pull-up resistor smaller (i.e., stronger pull-up) than 27.1k, so a 10k resistor works fine.ALERT, READY and GPIO Component Selection The pull-up resistors on the ALERT and READY pins must provide a maximum pull-up current of 3mA, so that the LTC4306 is capable of holding the pin at logic low voltages below 0.4V. When choosing LE Ds to be driven by the LTC4306’s GPIO pins, make sure that the required LED sinking current is less than 5mA, and add a current-limiting resistor in series with the LED.Level Shifting ConsiderationsIn the design example of Figure 5, the LTC4306 V CC voltage is less than or equal to both of the downstream bus pull-up voltages, so buses 1 and 4 can be active at the same time. Likewise, the rise time accelerators can be turned on for the downstream buses, but must never be activated on SCLIN and SDAIN, because doing so would result in significant current flow from V CC to V BACK during rising edges.Other Application CircuitsFigure 6 illustrates how the LTC4306 can be used to expand the number of devices in a system by using nested addressing. Each I/O card contains a temperature sensorhaving device address 1001 000. If the four I/O cards were plugged directly into the backplane, the four sensors would require four unique addresses. However, if masters use the LTC4306 in multiplexer mode, where only one downstream channel is connected at a time, then each I/O card can have a device with address 1001 000 and no problems will occur.Figures 7 and 8 show two different methods for hot-swapping I/O cards onto a live two-wire bus using the LTC4306. The circuitry of Figure 7 consists of an LTC4306residing on the edge of an I/O card having four separate downstream buses. Connect a 200k resistor to ground from the E NABLE pin and make the E NABLE pin the shortest pin on the connector, so that the ENABLE pin remains at a constant logic low while all other pins are connecting. This ensures that the LTC4306 remains in its default high impedance state and ignores connection transients on its SDAIN and SCLIN pins until they have established solid contact with the backplane 2-wire bus. In addition, make sure that the ALE RT connector pin is shorter than the V CC pin, so that V CC establishes solid contact with the I/O card pull-up supply pin and powers the pull-up resistors on ALERT1–ALERT4 before ALERT makes contact.Figure 8 illustrates an alternate SDA and SCL hot-swap-ping technique, where the LTC4306 is located on the backplane and an I/O card plugs into downstream channel 4. Before plugging and unplugging the I/O card, make sure that channel 4’s downstream switch is open, so that it does not disturb any 2-wire transaction that may be occurring at the moment of connection/disconnection. Note that pull-up resistor, R17, on ALERT4 should be located on the backplane and not the I/O card to ensure proper operation of the LTC4306 when the I/O card is not present. The pull-up resistors on SCL4 and SDA4, R15 and R16 respec-tively, may be located on the I/O card, provided that downstream bus 4 is never activated when the I/O card is not present. Otherwise, locate R15 and R16 on the backplane.APPLICATIO S I FOR ATIOW UUU174306f18Figure 7. Hot-Swapping ApplicationAPPLICATIO S I FOR ATIOW UUUBACKPLANE CONNECTOR CARD CONNECTORV CARD_SCL1CARD_SDA1CARD_ALERT1CARD_SCL2CARD_SDA2CARD_ALERT2CARD_SCL3CARD_SDA3CARD_ALERT3CARD_SCL4CARD_SDA4CARD_ALERT4ADDRESS = 1010 000Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.194306f20Linear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417(408) 432-1900 ● FAX: (408) 434-0507 ● © LINEAR TECHNOLOGY CORPORA TION 2005LT/LWI/TP 0805 500 • PRINTED IN USAAPPLICATIO S I FOR ATIOW UUU RELATED PARTSPART NUMBER DESCRIPTIONCOMMENTSLTC1380/LTC1393Single-Ended 8-Channel/Diffierential 4-Channel Analog Low R ON : 35Ω Single-Ended/70Ω Differential, Expandable to Mux with SMBus Interface32 Single or 16 Differential ChannelsLTC1427-50Micropower, 10-Bit Current Output DAC with SMBus Precision 50µA ±2.5% Tolerance Over Temperature, 4 Selectable InterfaceSMBus Addresses, DAC Powers Up at Zero or MidscaleLTC1694/LTC1694-1SMBus AcceleratorImproved SMBus/I 2C Rise Time, Ensures Data Integrity with Multiple SMBus/I 2C DevicesLT ®1786F SMBus Controlled CCFL Switching Regulator 1.25A, 200kHz, Floating or Grounded Lamp Configurations LTC1695SMBus/I 2C Fan Speed Controller in ThinSOT TM 0.75Ω PMOS 180mA Regulator, 6-Bit DACLTC1840Dual I 2C Fan Speed Controller Two 100µA 8-Bit DACs, Two Tach Inputs, Four GPIO LTC4300A-1/LTC4300A-2Hot Swappable 2-Wire Bus Buffer Isolates Backplane and Card Capacitances LTC4300A-3Hot Swappable 2-Wire Bus BufferProvides Level Shifting and Enable Functions LTC4301Supply Independent Hot Swappable 2-Wire Bus Buffer Supply IndependentLTC4301LHot Swappable 2-Wire Bus Buffer with Low Voltage Allows Bus Pull-Up Voltages as Low as 1V on SDAIN and SCLIN Level TranslationLTC4303/LTC4304How Swappable Bus Buffers with Stuck Bus Recovery Recover Stuck Buses with Automatic ClockingLTC43052-Channel 2-Wire Multiplexer with Capacitance2 Selectable Downstream Buses, Stuck Bus Disconnect, Rise Time BufferingAccelerators, Fault Reporting, ±10kV HBM ESD ToleranceThinSOT is a trademark of Linear Technology Corporation.Figure 8. Downstream Side Hot-Swapping Application。
LTC4306IUFD-DC906A-用户手册说明书
QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 906A4-CHANNEL, 2-WIRE BUS MULTIPLEXER WITH CAPACITANCE BUFFERINGLTC4306IUFDDESCRIPTIONDemonstration circuit 906A features the LTC ®4306IUFD, a 4-channel, 2-wire I2C bus and SMBus compatible multiplexer having bus buffers that provide capacitive isolation between the up-stream bus and downstream buses. Through soft-ware control, the LTC4306IUFD connects the up-stream 2-wire bus to any desired combination of downstream buses. Each bus can be pulled up to a supply voltage ranging from 2.2V to 5.5V, independ-ent of the LTC4306IUFD supply voltage. The down-stream buses are also provided with ALERT1B – ALERT4B inputs for fault reporting.Programmable timeout circuitry disconnects the downstream buses if the bus is stuck low. When acti-vated, rise time accelerators source currents into the 2-wire bus pins during rising edges to reduce rise time. Two general purpose input/output (GPIO) pins can be configured as inputs, open-drain outputs or push-pull outputs. Green LED’s D3 and D2 light up when GPIO1 and GPIO2, respectively, are low. Driv-ing the ENABLE pin low restores all device features totheir default states. Three address pins provide 27 distinct addresses.Design files for this circuit board are available. Call the LTC factory.LTC is a registered trademark of Linear Technology CorporationTable 1. Performance Summary (T A = 25°C)PARAMETERCONDITION VALUE V CC Voltage Operating Range2.7V – 5.5V Bus Pull-up Supply Voltage Range (V BUS1-V BUS4) 2.2V – 5.5V 2-Wire Bus Frequency Range0 - 400kHzBus Stuck Low Disconnect TimesV CC = 2.7V - 5.5V7.5ms, 15ms, 30ms optionsall times +/-16.7% feature can also be disabledBus Buffer V OL Offset Voltage R BUS = 10K 100mV (maximum) V CC = 3.3V 5.5mA (typical) Rise Time Accelerator Pull-up Current V CC = 5V9mA (typical) ALERTB and READY Output V OL VoltagesV CC = 2.7V - 5.5V; I ALERTB = I READY = 3mA0.4V (maximum)OPERATING PRINCIPLESFor operation with the DC906A, connect the host con-troller’s SDA and SCL pins to the LTC4306IUFD’s SDAIN and SCLIN pins (hereafter referred to as the upstream bus), and connect the upstream bus supply of 2.7V to 5.5V to Vcc (as shown in Figure 1). The host controller on the upstream side first addresses and configures the LTC4306IUFD to connect the up-stream bus to one or more of the four downstreambuses. Communications between the upstream and downstream components are then established and a host controller on any bus can then control the LTC4306IUFD.Use turrets VBUS1-VBUS4 and jumpers JP1-JP4 to pull up the downstream buses to supply voltages dif-ferent than VCC (i.e., to provide level-shifting). Forexample, in Figure1, JP1 is set to the right position and a supply voltage is connected between VBUS1 and ground. Voltages on VBUS1-VBUS4 must range between 2.2V and 5.5V. To connect a downstream bus’s pull-up supply to VCC, set its jumper to the left position.Additional configurations include enabling and dis-abling the rise time accelerators on the backplane side and/or the card side, setting the GPIO’s to open-drain output, push-pull output, or input mode, setting or resetting the GPIO’s outputs, disabling the Bus Stuck Low disconnect feature or setting the discon-nect time to 7.5ms, 15ms, 30ms. A host controller can also read the internal registers of the LTC4306IUFD to determine the settings of these fea-tures as well as fault statuses. All of these features are accessed by sending commands on the 2-wire bus.The ENABLE pin, when pulled low, resets the LTC4306IUFD to its registers default state and dis-ables communication to it. Communication can be reestablished when ENABLE is released high. There-fore, set jumper JP5 to the left position for normal operation, and set it to the right position to disable the LTC4306IUFD.Slave devices that are capable of fault reporting and that are located on downstream buses 1-4 should connect their fault pins to ALERT1B-ALERT4B, re-spectively. The LTC4306IUFD passes downstream faults to the upstream host by pulling down on the ALERTB pin, so this host’s fault input should be con-nected to the LTC4306IUFD ALERTB pin.When the upstream bus is connected to one or more downstream buses, the READY pin voltage is pulled up to VCC. When the upstream bus is disconnected from all downstream buses, the READY voltage is low (~0.2V).On the DC906A, the board’s default setting for jump-ers JP6, JP7 and JP8 is the center position, which sets the address of the LTC4306IUFD to (1001 010)2. To set a different address, configure the jumpers ac-cording to Table 1 of the data sheet (note: left posi-tion = H, middle position = NC, right position = L; de-fault = NC for all three jumpers).QUICK START PROCEDUREDemonstration circuit 906A is easy to set up to evalu-ate the performance of the LTC4306IUFD. Refer toFigure 1 for proper measurement equipment setup and follow the procedure below:KEY NOTES: a. Do not activate rise time acceleratorson buses whose pull-up supply voltages are lower than VCC. b. Make sure logic low voltages forced onall clock and data pins are < 0.4V. c. When activatingmultiple downstream buses that are powered from separate supply voltages, make sure that theLTC4306IUFD’s VCC voltage is less than or equal tothe lowest downstream bus pull-up supply voltage. 1.Jumpers JP1-JP4 choose the pull-up supply volt-ages VBUS1 – VBUS4 for downstream buses 1-4.For unused buses and buses pulled up to VCC, set the jumpers in the left position. To pull up a down-stream bus to a different voltage than VCC, set itsjumper to the right position, and connect the sup-ply voltage to the appropriate turret on the left side of the board.2.Set jumper J5 in the left position to enable communication to the LTC4306IUFD.3.Configure jumpers JP6 – JP8 to set the desired 2-wire bus address for the LTC4306IUFD according to Table 1 on page 13 of the datasheet (note: left position = H, middle position = NC, right position = L; default = NC for all three jumpers).4.Connect a cable from 6-pin header J2 to a board containing the master device(s).5.Connect a 20-pin ribbon cable from J1 to a board that contains downstream slave devices. Note: the downstream buses can contain masters, but the original command to connect must come from amaster connected to the upstream SDAIN/SCLIN bus.6. Connect power supplies to VCC and, if required,one or more of VBUS1 – VBUS4.7. Turn on the power supplies.NOTE: Make sure that the power supply voltages donot exceed 5.5V.8. Use the SMBus Read Byte and Write Byte proto-cols in conjunction with the register definitions on pages 8 and 9 of the datasheet to experiment with the LTC4306IUFD’s features and to establish up-stream-downstream communications between the master and slave devices.Figure 1.Proper Measurement Equipment Setup。
STS4DNF60L;中文规格书,Datasheet资料
March 2010Doc ID 6121 Rev 91/12STS4DNF60LN-channel 60 V , 0.045 Ω, 4 A, SO-8STripFET™ Power MOSFETFeatures■Standard outline for easy automated surface mount assembly ■Low threshold driveApplication■Switching applicationsDescriptionThis Power MOSFET is the latest development of STMicroelectronics unique “single feature size” strip-based process. The resulting transistor shows extremely high packing density for low on-resistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility.Type V DSS R DS(on)I D STS4DNF60L60V<0.055Ω4ATable 1.Device summaryOrder code Marking Package Packaging STS4DNF60L4DF60LSO-8Tape & reelContents STS4DNF60LContents1Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.1Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112/12Doc ID 6121 Rev 9STS4DNF60L Electrical ratingsDoc ID 6121 Rev 93/121 Electrical ratingsTable 2.Absolute maximum ratingsSymbol ParameterValue Unit V DS Drain-source voltage (V GS = 0)60V V GS Gate- source voltage± 15V I D Drain current (continuous) at T C = 25 °C 4A I D Drain current (continuous) at T C = 100 °C 2.5A I DM (1)1.Pulse width limited by safe operating area Drain current (pulsed)16A P TOT (2)2.P TOT =1.6 W for single operation T otal dissipation at T C = 25 °C 2W E AS (3)3.Starting T J = 25 °C, I D = 4 A, V DD = 30 VSingle pulse avalanche energy 80mJ T jT stgOperating junction temperature Storage temperature- 55 to 150°CTable 3.Thermal dataSymbolParameterValue Unit Rthj-pcb Thermal resistance junction-pcb D.O.(1)1.When mounted on inch² FR-4 board, 2 Oz Cu, t < 10sec, dual operation62.5°C/WElectrical characteristics STS4DNF60L4/12Doc ID 6121 Rev 92 Electrical characteristics(T C = 25 °C unless otherwise specified)Table 4.On /off statesSymbol Parameter Test conditionsMin.Typ.Max.Unit V (BR)DSS Drain-sourcebreakdown voltageI D = 250 µA, V GS = 060V I DSS Zero gate voltagedrain current (V GS = 0)V DS = Max rating V DS = Max rating, T C =125 °C 110µA µA I GSS Gate-body leakage current (V DS = 0)V GS = ± 15 V± 100nA V GS(th)Gate threshold voltage V DS = V GS , I D = 250 µA 11.72.5V R DS(on)Static drain-source on resistance V GS = 10 V , I D = 2 A V GS = 4.5 V , I D = 2 A0.0450.0500.0550.065ΩΩTable 5.DynamicSymbol Parameter Test conditionsMin.Typ.Max.Unit g fs Forwardtransconductance V DS =25 V , I D =2 A-25-S C issC oss C rss Input capacitance Output capacitance Reverse transfer capacitance V DS = 25 V , f = 1 MHz, V GS = 0-103014040-pF pF pF Q g Q gs Q gdT otal gate charge Gate-source charge Gate-drain chargeV DD = 48 V , I D = 4 A,V GS = 4.5 V (see Figure 13)-1544-nC nC nCSTS4DNF60L Electrical characteristicsDoc ID 6121 Rev 95/12Table 6.Switching timesSymbol ParameterTest conditions Min.Typ.Max.Unit t d(on)t r Turn-on delay time Rise timeV DD = 30 V , I D = 2.2 A, R G = 4.7 Ω, V GS = 10 V (see Figure 12)-1528-ns ns t d(off)t fTurn-off delay time Fall time-4510-ns nsTable 7.Source drain diodeSymbol ParameterTest conditionsMin.Typ.Max.Unit I SD I SDM (1)1.Pulse width limited by safe operating area Source-drain currentSource-drain current (pulsed)-416A A V SD (2)2.Pulsed: Pulse duration = 300 µs, duty cycle 1.5%Forward on voltage I SD = 4 A, V GS = 0- 1.2V t rr Q rr I RRMReverse recovery time Reverse recovery charge Reverse recovery currentI SD = 4 A, di/dt = 100 A/µs V DD = 20 V (see Figure 17)-85852ns nC AElectrical characteristics STS4DNF60L6/12Doc ID 6121 Rev 92.1 Electrical characteristics (curves)Figure 2.Safe operating area Figure 3.Thermal impedanceFigure 4.Output characteristics Figure 5.Transfer characteristicsFigure 6.Source-drain diode forwardFigure 7.Static drain-source on resistanceSTS4DNF60L Electrical characteristicsDoc ID 6121 Rev 97/12Figure 8.Gate charge vs gate-source voltage Figure 9.Capacitance variationsFigure 10.Normalized gate threshold voltageFigure 11.Normalized on resistance vsTest circuits STS4DNF60L8/12Doc ID 6121 Rev 93 Test circuitsFigure 12.Switching times test circuit forFigure 13.Gate charge test circuitFigure 14.Test circuit for inductive loadFigure 15.Unclamped Inductive load testFigure 16.Unclamped inductive waveformFigure 17.Switching time waveformSTS4DNF60L Package mechanical data 4 Package mechanical dataIn order to meet environmental requirements, ST offers these devices in different grades ofECOPACK® packages, depending on their level of environmental compliance. ECOPACK®specifications, grade definitions and product status are available at: . ECOPACKis an ST trademark.Doc ID 6121 Rev 99/12Package mechanical data STS4DNF60L10/12Doc ID 6121 Rev 9分销商库存信息: STMSTS4DNF60L。
HEF4046BD中文资料
Figure 4 shows the typical waveforms for a PLL employing phase comparator 1 in locked condition of fo.
Fig.4 Typical waveforms for phase-locked loop employing phase comparator 1 in locked condition of fo.
HEF4046B MSI Phase-locked loop
Product specification File under Integrated Circuits, IC04 January 1995
元器件交易网
Philips Semiconductors
Product specification
factor to obtain the maximum lock range. The average output voltage of the phase comparator is equal to 1⁄2 VDD when there is no signal or noise at the signal input. The average voltage to the VCO input is supplied by the low-pass filter connected to the output of phase comparator 1. This also causes the VCO to oscillate at the centre frequency (fo). The frequency capture range (2 fc) is defined as the frequency range of input signals on which the PLL will lock if it was initially out of lock. The frequency lock range (2 fL) is defined as the frequency range of input signals on which the loop will stay locked if it was initially in lock. The capture range is smaller or equal to the lock range. With phase comparator 1, the range of frequencies over which the PLL can acquire lock (capture range) depends on the low-pass filter characteristics and this range can be made as large as the lock range. Phase comparator 1 enables the PLL system to remain in lock in spite of high amounts of noise in the input signal. A typical behaviour of this type of phase comparator is that it may lock onto input frequencies that are close to harmonics of the VCO centre frequency. Another typical behaviour is, that the phase angle between the signal and comparator input varies between 0° and 180° and is 90° at the centre frequency. Figure 3 shows the typical phase-to-output response characteristic.
TP4056_中文资料_datasheet
● 150 200
300
60
100
140
5
30
50
● 60
70
80
● 120 130
140
● 0.9
1.0
1.1
单位 V
μA μA μA
V mA mA μA μA μA mA V mV V mV mV mV mA mA V
V CHRG
引脚输出低电压
I =5mA CHRG
0.3
0.6
V
V STDBY
引脚输出低电平
最小值 典型值 最大值
● 4.0
5
8.0
●
150
500
●
55
100
●
55
100
55
100
4．137 ● 450 ● 950 ●0
● 120
4．2 500 1000 －2.5 ±1 －1 130
4．263 550 1050 －6 ±2 －2 140
2.8
2.9
3.0
60
80
100
● 3.5
3.7
3.9
1/10 之间短暂地降至 100mV 以下。终止比较器
上的
1.8ms
滤波时间（
t TERM
）确保这种性质的
瞬变负载不会导致充电循环过早终止。一旦平
均充电电流降至设定值的 1/10 以下，TP4056
即终止充电循环并停止通过 BAT 引脚提供任何
电流。在这种状态下，BAT 引脚上的所有负载
都必须由电池来供电。
线性充电器 ·恒定电流/恒定电压操作，并具有可在无过热
危险的情况下实现充电速率最大化的热调节 功能 ·精度达到±1.5%的 4.2V 预设充电电压 ·用于电池电量检测的充电电流监控器输出 ·自动再充电 ·充电状态双输出、无电池和故障状态显示 ·C/10 充电终止 ·待机模式下的供电电流为 55uA ·2.9V涓流充电器件版本
Littelfuse ULTRAMOV Datasheet力特压敏电阻规格书
Features
• Lead–free, Halogen-Free • Custom voltage
and RoHS compliant
types available
• High peak surge
• Standard lead form and
ctour1r0eknAt ,rastiinnggle(IT8M)xup 20 pulse, (20mm)
91788 BSIIE1C4Q.0-0C011
J 503242422
Notes: . Epoxy coated only. 2. Phenolic coated only. 3. All epoxy coated sizes are UL Recognized while only 10mm, 14mm, and 20mm phenolic
UltraMOV® Series Ratings & Specifications
Epoxy Coated Models
Phenolic Coated Models
Part Number
Branding
Part Number
Branding
V07E130P P7V130 V07P130P P7P130 V10E130P P10V130 V10P130P P10P130 V14E130P P14V130 V14P130P P14P130 V20E130P P20V130 V20P130P P20P130 V07E140P P7V140 V07P140P P7P140 V10E140P P10V140 V10P140P P10P140 V14E140P P14V140 V14P140P P14P140 V20E140P P20V140 V20P140P P20P140 V07E150P P7V150 V07P150P P7P150 V10E150P P10V150 V10P150P P10P150 V14E150P P14V150 V14P150P P14P150 V20E150P P20V150 V20P150P P20P150 V07E175P P7V175 V07P175P P7P175 V10E175P P10V175 V10P175P P10P175 V14E175P P14V175 V14P175P P14P175 V20E175P P20V175 V20P175P P20P175 V07E230P P7V230 V07P230P P7P230 V10E230P P10V230 V10P230P P10P230 V14E230P P14V230 V14P230P P14P230 V20E230P P20V230 V20P230P P20P230 V07E250P P7V250 V07P250P P7P250 V10E250P P10V250 V10P250P P10P250 V14E250P P14V250 V14P250P P14P250 V20E250P P20V250 V20P250P P20P250 V07E275P P7V275 V07P275P P7P275 V10E275P P10V275 V10P275P P10P275 V14E275P P14V275 V14P275P P14P275 V20E275P P20V275 V20P275P P20P275 V07E300P P7V300 V07P300P P7P300 V10E300P P10V300 V10P300P P10P300 V14E300P P14V300 V14P300P P14P300 V20E300P P20V300 V20P300P P20P300 V07E320P P7V320 V07P320P P7P320 V10E320P P10V320 V10P320P P10P320 V14E320P P14V320 V14P320P P14P320 V20E320P P20V320 V20P320P P20P320 V07E385P P7V385 V07P385P P7P385 V10E385P P10V385 V10P385P P10P385 V14E385P P14V385 V14P385P P14P385 V20E385P P20V385 V20P385P P20P385 V07E420P P7V420 V07P420P P7P420 V10E420P P10V420 V10P420P P10P420 V14E420P P14V420 V14P420P P14P420 V20E420P P20V420 V20P420P P20P420 V07E440P P7V440 V07P440P P7P440 V10E440P P10V440 V10P440P P10P440 V14E440P P14V440 V14P440P P14P440 V20E440P P20V440 V20P440P P20P440 V07E460P P7V460 V07P460P P7P460 V10E460P P10V460 V10P460P P10P460
4056;4057;4058;4059;4060;中文规格书,Datasheet资料
T E R M I N A L B O A R D S &S T R I P S142Tel (718)956-8900•Fax (718)956-9040(800)221-5510•kec@31-0720th Road –Astoria,NY 11105-2017RoHS COMPLIANT ~ISO 9001CERTIFIED®QUICK-FIT TERMINAL STRIPSA.375[9.5].187[4.8]L .500[12.7].128[3.3] DIA .(2)PLS.062 [1.57]BACKING INSULATOR .031(.79)FIBERA NO.TERM.BACKING STRIPL MTG.EACH CAT.CAT.LENGTHCENTERS SIDENO.NO.1.500(38.1) 1.125(28.6)2411644012.250(57.2) 1.875(47.6)4411744023.000(76.2) 2.625(66.7)6411844033.750(95.3) 3.375(85.7)8411944044.500(114.3) 4.125(104.8)1041204405MATERIAL:Fiberglass -NEMA GRADE GPO-3.A glass polyester rated for continuous operation at 300°F (155°C).062(1.57)Backing Strips:.031(.79)fibre with mounting holes drilled only Terminals:BrassCAT.NO.1257.032(.81)Bright Brass Other platings available on special orderNO.OF L A TERMS CAT.NO.CAT.NO.CAT.NO.CAT.NO.1.125(28.6).750(19.1)1603-1609-1604-1607-11.500(38.1) 1.125(28.6)2603-2609-2604-2607-21.875(47.6) 1.500(38.1)3603-3609-3604-3607-32.250(57.2) 1.875(47.6)4603-4609-4604-4607-42.625(66.7) 2.250(57.2)5603-5609-5604-5607-53.000(76.2) 2.625(66.7)6603-6609-6604-6607-63.375(85.7) 3.000(76.2)7603-7609-7604-7607-73.750(95.3) 3.375(85.7)8603-8609-8604-8607-84.125(104.8) 3.750(95.3)9603-9609-9604-9607-94.500(114.3)4.125(104.8)10603-10609-10604-10607-10NO.OF MATERIAL MATERIAL TERMS PBEGEE W S L EACH SIDE CAT.NO.CAT.NO.2.625(66.7)515101153015.250(133.4)121510215302.500[12.7]Single Row 7.875(200.0)19151031530310.500(266.7)26151041530413.125(333.4)3315105153052.625(66.7)515106153065.250(133.4)1215107153071.188(30.2).750(19.1)7.875(200.0)19151081530810.50(266.7)26151091530913.125(333.4)3315110153102.625(66.7)515111153115.250(133.4)1215112153121.500(38.1)1.000(25.4)7.875(200.0)19151131531310.500(266.7)26151141531413.125(333.4)3315115153152.625(66.7)515116153165.250(133.4)1215117153172.000(50.8)1.500(38.1)7.875(200.0)19151181531810.500(266.7)26151191531913.125(333.4)3315120153202.625(66.7)515121153215.250(133.4)1215122153222.500(63.5)2.000(50.8)7.875(200.0)19151231532310.500(266.7)26151241532413.125(333.4)3315125153252.625(66.7)515126153265.250(133.4)1215127153273.000(76.2)2.500(63.5)7.875(200.0)19151281532810.500(266.7)26151291532913.125(333.4)331513015330BOARDS ON THIS PAGE ARE NOT SCOREDReady-Made Terminal Boards:Low cost,meets commercial and military specifications.Produced in large quantities,making it possible to eliminate tooling and setup charges usually applied to non-standard boards.Terminals are staked in all holes except end mounting holes.Hole thru 1503W S.375[9.5].187[4.8].093 [2.36].120[3.1]DIA.WLA.375[9.5].187[4.8]L .500[12.7].120[3.1]DIA .(2)PLS.093[2.36]Hole thru1503150915451507MATERIAL:Choice of either PBE or GEE.PBE:Paper base electrical,MIL-1-24768/20,Type XP natural,Temp.250°F (121°C)max.GEE:Glass epoxy,MIL-I-24768/27,Type G-10,Temp.300ºF (155°C)max.Terminals:Brass,ASTM-B16.Tin Plate,MIL-T-10727.Other plating can be furnished .MATERIAL:PBEPBE:Paper base electrical,FED.LP-513,Type XP natural,Temp.250°F (121°C)max.Terminals:Brass,ASTM-B16.Tin Plate,MIL-T-10727.Other plating can be furnished .MODIFICATIONSBoards can be modified with other materials or terminals of your choice.Marking can also be added.Quotations upon request..250(6.4)TABS分销商库存信息:KEYSTONE-ELECTRONICS405640574058 40594060603-1 609-1604-1607-1 603-2609-2607-2 603-3607-3604-2 609-3603-4609-4 607-415101603-5 609-5604-3609-6 603-615301607-5 609-7603-7607-6 604-4609-8603-8 609-9603-9607-8 609-10604-5603-10 607-91510615102 15111604-6607-10 607-71511615121 153021********* 604-715126604-8 1531615103604-9 1532115326604-10 153031********* 151041511715122 153071********* 153121531715105 153221532715108 153051511315118 151231512815308 153181531315109 151141511915323 153091512415328 151291********* 153141512015319 151251513015324 153291********* 153201532515330。
6054;6056;6042;6060;6055;中文规格书,Datasheet资料
MATERIAL:
Body: Nylon per ASTM D4066 Contact: Beryllium Copper, Silver Plate
CAT. NO. 6048 6049 6050 6051 6052 6053
COLOR WHITE RED BLACK YELLOW GREEN BLUE
1
分销商库存信息:
KEYSTONE-ELECTRONICS 6054 6056 6060 6055 6050 6049 6043 6062 6057 6058 6051 6052 6066 6067 6069 6070 6045 6046 6063 6064 11012-R 11012-B 11014 11016-B 11001 11005 11008 11004 11002 11003 11011 11012 11015 11016-R 11013 6042 6048 6044 6061 6059 6053 6068 6071 6047 6065 11016 11014-R 11010 11009 11006 11007 11014-B
VERTICAL
.187 [4.8] DIA.
SNAP-FIT VERTICAL
.187 [4.8] DIA.
.312 [7.9]
.312 [7.9]
.125 [3.2] .048 [1.2] DIA.
MATERIAL:
Body: Nylon per ASTM D4066 Contact: Brass, Silver Plate
.048 [1.2]
.200 [5.1]
.048 [1.2]
GOLD PLATE CAT. NO. 6060 6061 6062 6063 6064 6065
400566, 规格书,Datasheet 资料
10.4” LCD Monitor with Projected Capacitive Touch SolutionBergquist presents you the projected capacitive touch solution covering a 10.4” TFT touch monitor in a metal enclosure attached to Bergquist’s projected capacitive touch panel, PenMount 1300 projected capacitive touch control board with fine-tuned firmware. This touch monitor module connects to the computers directly by USB port. On Windows 7 O.S. it accesses the Windows 7 inbox driver to perform using single and dual –touch inputs. A utility program is included form customizing the touch sensitivity and various touch performances.Touch Monitor Features∙10.4” TFT LCD monitor with projected capacitive touch solution∙Supporting single and dual touch∙Bergquist 10.4” projected capacitive t ouch panel∙PenMount 1300 projected capacitive touch control board∙VGA interface to communicate with the host computer for LCD display∙USB interface to communicate with the host computer for touch controllerLCD Monitor Specification∙LCD Diagonal Size: 10.4” TFT LCD∙LCD Resolution: 1024x768∙LCD Active Area 210.4 (W) x 157.8 (H) mm∙Interface: TTL Digital Display Board∙Monitor Power Consumption: 8W (Typ.)∙Interface to Main System: VGA Port∙Power Cord Included∙Weight: 1500g (including touch panel and control board)∙Dimensions: 262 (W) x 202 (H) x 45 (D) mm∙Operating Temperature: -10˚C to +60˚C∙Storage Temperature: -20˚C to +70˚C301 Washington St, Cannon Falls MN 55009 · (507) 263-3766 Fax (507) 263-5085 · w Bergquist 400614 Projected Capacitive Touch Panel Specification∙Technology: Projected Capacitive∙Measurement Resolution: 1024∙Response Time: <20ms∙Touch Function: Single and Dual Touch∙Light Transmission: >88%∙Haze: <3%∙Sensor Thickness: 1.75±0.2mm∙Top Glass Thickness: 1.1mm∙Glass Hardness: Mohs 5∙Tail Design: FPC Tail∙Activation Force: Forceless∙Operating Temperature: -20˚C to +70˚C∙Storage Temperature: -40˚C to +80˚C∙Humidity: 10% to 90% RH∙Touch Panel Dimensions: 228.2 (W) x 180.1 (H) x 1.75 (D) mmPenMount 1300 Projected Capacitive Touch Controller Specification∙Power Consumption: DC +5V, Max 50mA, Typ 25-40mA∙Interface: USB 2.0 compatible, full speed∙Resolution: 1024x1024∙Accuracy: <1mm∙Single Touch: 200 points/sec∙Dual Touch: 100 points/sec∙Response Time: Max 40ms∙Operating Temperature: -25˚C to +80˚C∙Storage Temperature: -40˚C to +90˚C∙Relative Humidity: 90% RH at 40˚C (non-condensing)∙Control Board Dimensions: 40 x 70mm∙USB Cable Included∙RoHS Compliant∙5300 Edina Industrial Boulevard Edina, MN 55439 · (800) 347-4572 Fax (612) 835-0430 · w 5300 Edina Industrial Boulevard Edina, MN 55439 · (800) 347-4572 Fax (612) 835-0430 · w 。
10-89-4602;中文规格书,Datasheet资料
ENG. NO: A-70216-0391/0404
DIM. C DIM. E (REF.) FINISH CONNECTOR END PLATING DIM. D (MEASURE PT.) P.C. BOARD END PLATING DIM. F (MEASURE PT.) PACKAGING CKTS EDP NUMBER 04 10-89-4046 06 10-89-4066 08 10-89-4086 10 10-89-4106 12 10-89-4126 14 10-89-4146 16 10-89-4166 18 10-89-4186 20 10-89-4206 22 10-89-4226 24 10-89-4246 26 10-89-4266 28 10-89-4286 30 10-89-4306 (6.10)/.240 (2.79)/.110 30 GOLD GOLD (2.54)/.100 TIN (1.27)/.050 SEE NOTE 4 ON SHT. 1 ENG. NUMBER A-70216-0391 A-70216-0392 A-70216-0393 A-70216-0394 A-70216-0395 A-70216-0396 A-70216-0397 A-70216-0398 A-70216-0399 A-70216-0400 A-70216-0401 A-70216-0402 A-70216-0403 A-70216-0404
SHEET No.
-3APPROVED BY:
DOCUMENT NUMBER:
SD-70216-001
/
ADERR
FSMITH
TEMPLATE FILENAME: PRODUCT_SPEC[SIZE_A](V.1).DOC
0399800406;中文规格书,Datasheet资料
This document was generated on 09/13/2012PLEASE CHECK FOR LATEST PART INFORMATIONPart Number:39980-0406Status:ActiveDescription:5.08mm Pitch Beau™ Eurostyle™ Surface Mount Compatible Locking Header, 6CircuitsDocuments:3D ModelRoHS Certificate of Compliance (PDF)Drawing (PDF)Agency CertificationULE48521GeneralProduct Family Terminal Blocks Series39980Application N/ACommentsGold plating available Component Type PCB HeaderProduct Name Eurostyle™Pluggable Type Euro Block UPC800753316621PhysicalCircuits (Loaded)6Color - Resin Black Entry Angle N/A Flammability94V-0Lock to Mating PartYes Material - Plating MatingTin Material - Plating Termination Tin Material - Resin Nylon Net Weight3.474/g Number of Rows 1Orientation Vertical PC Tail Length 3.81mm PCB RetentionNone PCB Thickness - Recommended 1.60mm Panel MountNoPitch - Mating Interface5.08mm Pitch - Termination Interface 5.08mm Plating min - Mating3.810µm Plating min - Termination 3.810µm Polarized to Mating Part Yes Shrouded No StackableNo Surface Mount Compatible (SMC)No Temperature Range - Operating 140°C Wire Size AWGN/A ElectricalCurrent - Maximum per Contact 10A Voltage - Maximum300V Material InfoOld Part Number981506Reference - Drawing NumbersSeriesimage - Reference onlyEU RoHSChina RoHSELV and RoHS Compliant REACH SVHCContains SVHC: No Low-Halogen Status Low-HalogenNeed more information on product environmental compliance?Email productcompliance@For a multiple part number RoHS Certificate of Compliance, click herePlease visit the Contact Us section for any non-product compliance questions.Search Parts in this Series 39980SeriesMates With399802106 Spring Clamp Plug, 399800306Screw Clamp PlugSales Drawing SD-39980-006This document was generated on 09/13/2012PLEASE CHECK FOR LATEST PART INFORMATION分销商库存信息: MOLEX 0399800406。