东南大学CPU设计报告(附源程序vhdl)

Computer Organization and Architecture
Course Design
Microprogrammed CPU Design
School of Information Science and Engineering
Southeast University
2012-04-07
CONTENTS
1. Purpose (2)
2. Tasks (2)
2.1 Instruction Set (2)
Table 1 List of instructions and relevant opcodes
2.2 Internal Registers and Memory (3)
2.3 ALU (3)
Table 2 ALU Operations
2.4 Microprogrammed Control Unit (4)
Table 3 The meaning of each bit of the microinstruction
Table 4 The Sequence of Microinstructions(appendix)
Table 5 The meaning of each bit of the 8-bit flag.
3. Top-Level Structure (6)
3.1 Symbols of internal registers ,ALU,CU and memory (6)
3.2Top-Level Structure of CPU (7)
4. The Simulation Input Waveforms (10)
5. Test (9)
Test problem 1: test LOAD, STORE, AND, SHR, SHL, SAR, SAL (9)
Table 7 Test of program of problem 1
Test problem 2: test SUB, ADD, JMPGEZ, HALT (11)
Table 8 Test of program to calculate 1+2+ (100)
Test problem 3: test JMP,MPY, OR,NOT (13)
Table 9 Test of program to calculate （（543-800） 3）OR（（543 +125））,not 543
6. Conclusions and Discussions (16)
7. Appendix (17)
Microprogrammed CPU Design
1. Purpose:
The purpose of this project is to design a simple CPU (Central Processing Unit). This CPU has basic instruction set, and we will utilize its instruction set to generate a very simple program to verify its performance. For simplicity, we will only consider the relationship among the CPU, registers, memory and instruction set. That is to say we only need consider the following items: Read/Write Registers, Read/Write Memory and Execute the instructions.
2. Tasks:
At least four parts constitute a simple CPU: the instruction set, the internal registers, the ALU and the control unit.
2.1 Instruction Set
Single-address instruction format is used in my simple CPU design. The instruction word contains two sections: the operation code (opcode), which defines the function of instructions (addition, subtraction, logic operations, etc.); the address part, in most instructions, the address part contains the memory location of the datum to be operated, we called it direct addressing. In some instructions, the address part is the operand, which is called immediate addressing.
Table 1 List of instructions and relevant opcodes
2.2 Internal Registers and Memory
MAR (Memory Address Register)
MAR contains the memory location of the word to be read from the memory or written into the memory. Here, READ operation is denoted as the CPU reads from memory, and WRITE operation is denoted as the CPU writes to memory. In my design, MAR has 8 bits to access one of 256 addresses of the memory.
MBR (Memory Buffer Register)
MBR contains the value to be stored in memory or the last value read from memory. MBR is connected to the address lines of the system bus. In my design, MBR has 16 bits.
PC (Program Counter)
PC keeps track of the instructions to be used in the program. In my design, PC has 8 bits.
IR (Instruction Register)
IR contains the opcode part of an instruction. In my design, IR has 8 bits.
BR (Buffer Register)
BR is used as an input of ALU, it holds other operand for ALU. In my design, BR has 16 bits.
ACC (Accumulator)
ACC holds one operand for ALU, and generally ACC holds the calculation result of ALU. In my design, ACC has 16 bits.
In this designment, ACC is set in ALU for simplification.
MR (Multiplier Register)
MR is used for implementing the MPY instruction, holding the multiplier at the beginning of the instruction. When the instruction is executed, it holds part of the product (the high part of the 32-bit product).
LPM_RAM_DQ
LPM_RAM_DQ is a RAM with separate input and output ports, it works as memory, and its size is 256× 16. Although it’s not an internal register of CPU, we need it to simulate and test the performance of CPU.
2.3 ALU
ALU (Arithmetic Logic Unit) is a calculation unit which accomplishes basic arithmetic and logic operations. In our design, some operations must be supported which are
listed as follows
Table 2 ALU Operations
2.4 Microprogrammed Control Unit
In the Microprogrammed control, the microprogram consists of some microinstructions and the microprogram is stored in control memory that generates all the control signals required to execute the instruction set correctly. The microinstruction contains some micro-operations which are executed at the same time.
Figure 1 The architecture of CU(control unit)
CAR(Control Address Register)
The control address register contains the address of the next microinstructions to be read. When a microinstruction is read from the control memory, it is transferred to a control buffer register. The register connects to the control lines emanating from the control unit. Thus, reading a microinstruction from the control memory is the same as executing that microinstruction.
LPM_ROM
LPM_ROM is a ROM with separate input and output ports, it works as control memory in this control unit, and its size is 256×32. Each unit contains a microinstruction to control all the performance of the registers.
Table 3 shows the meaning of each bit of the microinstruction. And Table 4(showing in the Appendix) exhibits how the set of microinstructions implements the whole operation of the CPU system, which is contents of ROM.
Table 3 The meaning of each bit of the microinstruction
Table 5 The meaning of each bit of the 8-bit flag.
3. Top-Level Structure:
3.1 Symbols of internal registers ,ALU,CU and memory
MAR (MemoryAddressRegister) MBR (Memory Buffer Register)
PC (Program Counter) IR (Instruction Register)
BR(Buffer Register) ALU(Arithmetic Logic Unit)
3.2Top-Level Structure of CPU
Inputs:
clk: The system clock for all the registers except RAM and ROM.
clock:The system clock for RAM and ROM, which is 2 times as fast as clk.
reset:The signal to restart CPU system.
Outputs:
MAR_out, MBR_out, PC_ouy, IR_out, A, ACC_out, MR: The output of corresponding register.
c: To exhibit the current control signals.
Flag1,3,4: To exhibit the state flag of the system.
4. The Simulation Input Waveforms
Figure 3 The simulation input waveform
Reset=0 from 0 to 10ns.
Clk is set as 10ns per cycle while clock is set as 5 ns per cycle.
5.Test
Test problem 1:test LOAD, STORE, AND, SHR, SHL, SAR, SAL
Table 7 Test of program of problem 1
Program with instructions
Contents of Memory (RAM) in HEX
Address Contents
LOAD 30H 00 0230 SHR 01 0D00 STORE 40H 02 0140 LOAD 31H 03 0231 SAR 04 0F00 AND 40H 05 0A40 SHL 06 0E00 SAL 07 1000 30 BC32(1011 1100 0011 0010) 31 C99C(1100 1001 1001 1100)
The contents of ROM:
Figure 4 The contents of ROM
Simulation results:
Fetch microinstrustion
LOAD 30H
ACC<0,flag1>1
MAR<=PC IR<=MBR(H8)
MBR<=MEM PC<=PC+1
MBR<=MEM
ACC<=MBR
Test problem 2: test SUB, ADD, JMPGEZ, HALT
calculate 1+2+ (100)
Table 8 Test of program to calculate 1+2+ (100)
Program with C
Program with
instructions Contents of Memory (RAM) in HEX Address Contents sum=0; LOAD A0 00 02A0
STORE A4 01 01A4
temp=100; LOAD A2 02 02A2
STORE A3 03 01A3
loop :sum=sum+temp;
LOOP:LOAD A4 04 (so LOOP=04) 02A4
SHR Fetch microinstruction
Operation finished,flag4=1
SHR 1011 1100 0011 0010
SAL
SHL
AND 40H
SAR 1100 1001 1001 1100 Final result
ADD A3 05 03A3 STORE A4 06 01A4 temp=temp-1;
LOAD A3
07 02A3 SUB A1 08 04A1 STORE A3 09 01A3 if temp>=0 goto loop; JMPGEZ LOOP
0A 0504 End HALT 0B 0700 . A0 0000 A1 0001 A2 0064
.
Simulation results:
LOOP:LOAD A4 STORE A3
STORE A4 LOAD A3
JMPGEZ LOOP
SUB A1
SUB A1
ADD A3 ADD A3
PC<=MBR(L8) Final result
Test problem 3: test JMP,MPY, OR,NOT （（543-800）⨯3）OR（（543 +125））,Not 543
Simulation results:
JMP 20H
LOAD A0 LOAD A1
LOAD A0
PC<=MBR(L8)
543-900=-257
ACC<0,flag1>1
MPY A2
-257*3=-771
ACC contains the low part of the product. ACC= x ”FCFD ”;
MR contains the high part of the product. MR= x ”FFFF ”;
So the product is x “FFFFFCFD ”, which is ‘-771’ in the signed decimal format.
543+125=668
ACC_out in binary format:
668 expressed in binary is 0000 0010 1001 1100, -771 expressed in binary is 1111
1100 1111 1101, so 668 OR -771 is1111 1110 1111 1101, which changed into signed decimal is -259
543 expressed in binary is 0000 0010 0001 1111, so NOT 543 is1111 1101 1110 0000, which changes into signed decimal is -544
6. Conclusions and Discussions:
1. Because of using “*” to accomplish the multiply instruction, there is no need using MR as an outside register, MR is just used as storing the high part of the multiply result. So in this design, MR is an inside register in ALU and it has its own output port.
2. In this design, reset signal is used to restart CPU, and reset=’0’ revert the CPU system to the initialized state.
3. SAR(Shift Arithmetic Left) and SAR(Shift Arithmetic Right)are added in this design. They can be used to multiply or devise 2 for a singed data, which simplifies the CPU’s operation of multiplication and division
4. As we can see , in input waveforms, the clock signal used for ROM and RAM is one time faster than the clk signal for the other blocks. The reason is showing in the RAM and ROM timing diagram below, which are generated automatically when ROM and RAM are created. It is clearly that ROM and RAM is slower than the other blocks, so in order to simulate CPU normally, the clock signal must be faster than the clk signal.
Figure 5 The sequence in time of RAM
5.Improvements can be made in this design. In the state of execution instruction, the microinstructions displayed in yellow shadow can be re-used in other opcodes, because they are same in other beginning of execute cycle. With the flag signals defined which kind of the operation, jump to the corresponding location in ROM and execute the operation, then space can be saved.
6. In this design, the micro-operation PC<=PC+1 is completed in the Execution Cycle, which can be put in the Fetch Cycle to simplify the Execution Cycle.
7. Appendix:
Table 4 The Sequence of Microinstructions
VHDL programme:
---------------/////-----------------------MAR----------------------/////--------------------------- library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity MAR is
port
( clk,reset,c5,c10:in std_logic;
PC_in:in std_logic_vector(7 downto 0);
MBR_in:in std_logic_vector(7 downto 0); --15 has been changed to 7.
MAR_out: out std_logic_vector(7 downto 0) --address bus(8 bits) );
end;
architecture behave of MAR is
begin
process(clk)
begin
if (rising_edge(clk)) then
if reset='0' then
MAR_out<="00000000";
elsif c10='1' then
MAR_out<=PC_in;
elsif c5='1' then
MAR_out<=MBR_in; --MAR<=MBR(7 downto 0)
end if;
end if;
end process;
end behave;
---------------/////-----------------------MBR----------------------/////--------------------------- library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity MBR is
port
(
clk,reset,c3,c11: in std_logic;
MEM_in: in std_logic_vector(15 downto 0);
ACC_in: in std_logic_vector(15 downto 0);
MBR_out: out std_logic_vector(15 downto 0)
);
end MBR;
architecture behave of MBR is
begin
process(clk)
begin
if(rising_edge(clk)) then
if reset='0' then
MBR_out<=x"0000"; -----------Hexadecimal
elsif(c3='1') then
MBR_out<=MEM_in;
elsif(c11='1') then
MBR_out<=ACC_in;
end if;
end if;
end process;
end behave;
---------------/////-----------------------PC----------------------/////--------------------------- library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity PC is
port
(
clk,reset,c6,c14: in std_logic;
MBR_in: in std_logic_vector(7 downto 0);
PC_out: buffer std_logic_vector(7 downto 0)
);
end PC;
architecture behave of PC is
begin
process(clk)
begin
if(rising_edge(clk)) then
if(reset='0') then
PC_out<="00000000";
elsif(c6='1') then
PC_out<=PC_out+1;
elsif(c14='1') then
PC_out<=MBR_in; --PC<=MBR(7 downto 0)
end if;
end if;
end process;
end behave;
---------------/////-----------------------IR----------------------/////--------------------------- library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity IR is
port
(
clk,reset,c4: in std_logic;
MBR_in: in std_logic_vector(7 downto 0); --[15..7].
IR_out: out std_logic_vector(7 downto 0)
);
end IR;
architecture behave of IR is
begin
process(clk)
begin
if(rising_edge(clk)) then
if reset='0' then
IR_out<=x"00";
end if;
if(c4='1') then
IR_out<=MBR_in; --------IR<=MBR(15 downto 8)
end if;
end if;
end process;
end behave;
---------------/////-----------------------BR----------------------/////--------------------------- library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity BR is
port( clk,reset,c7 :in std_logic;
MBR_in :in std_logic_vector(15 downto 0);
BR_out :out std_logic_vector(15 downto 0));
end BR;
architecture behave of BR is
begin
process(clk)
begin
if (rising_edge(clk)) then
if reset='0' then
BR_out<=x"0000";
elsif c7='1' then
BR_out<=MBR_in;
end if;
end if;
end process;
end behave;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ACC is
port(
clk,c8,c24,c27: in std_logic;
reset:in std_logic;
ALU_in,MBR_in:in std_logic_vector(15 downto 0);
ACC_out:buffer std_logic_vector(15 downto 0);
flag1,flag4:out std_logic
);
end ACC;
architecture behave of ACC is
begin
process(reset,ALU_in)
begin
if(rising_edge(clk)) then
if reset='0' then
ACC_out<="0000000000000000";
elsif (c8='1') then
ACC_out<="0000000000000000";
end if;
if (c24='1') then
ACC_out<=ALU_in;
flag4<='1';
else
flag4<='0';
end if;
if (c27='1') then
ACC_out<=MBR_in;
end if;
if ACC_out(15)='0' then
flag1<='0';--------ACC<0
else
flag1<='1';--------ACC>0
end if;
end if;
end process;
end behave;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity ALU is
port(
clk,reset:in std_logic;
c_in:in std_logic_vector(31 downto 0);
ACC_in,BR_in:in std_logic_vector(15 downto 0);
flag3:out std_logic;
MR:out std_logic_vector(15 downto 0);
ALU_out:buffer std_logic_vector(15 downto 0)
);
end ALU;
architecture behave of ALU is
signal mult: std_logic_vector(31 downto 0);
signal alu:std_logic_vector(15 downto 0);
begin
process(clk,reset)
begin
alu<=ALU_out;
if(rising_edge(clk)) then
if reset='0' then
ALU_out<="0000000000000000";
elsif c_in(22)='1' then
ALU_out<=BR_in;
elsif c_in(23)='1' then
ALU_out<=ACC_in;
elsif c_in(9)='1' then
ALU_out<=ACC_in+BR_in; --ADD elsif c_in(13)='1' then
ALU_out<=ACC_in-BR_in; --SUB elsif c_in(15)='1' then
ALU_out<=ACC_in and BR_in; --AND elsif c_in(16)='1' then
ALU_out<=ACC_in or BR_in; --OR elsif c_in(17)='1' then
ALU_out<=not BR_in; --NOT elsif c_in(18)='1' then
ALU_out<='0'&alu(15 downto 1); --SHR
elsif c_in(19)='1' then
ALU_out<=alu(14 downto 0)&'0'; --SHL
elsif c_in(20)='1' then
ALU_out<=alu(15)&alu(15 downto 1); --SAR
elsif c_in(29)='1' then
ALU_out<=alu(14 downto 0)&'0'; --SAL
elsif c_in(26)='1' then
ALU_out<=mult(15 downto 0);
MR<=mult(31 downto 16);
elsif c_in(28)='1' then
mult<=ACC_in*BR_in; --mult
flag3<='1'; ---mult operation finished
end if;
end if;
end process;
end behave;
---------------/////-----------------------CAR----------------------/////--------------------------- library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity CAR is
port
(
clk,reset:in std_logic;
IR_in:in std_logic_vector(7 downto 0);
c: in std_logic_vector(31 downto 0);
flag: in std_logic_vector(7 downto 0);----flag(1) '1' acc<0;'0' acc>0
addr: out std_logic_vector(7 downto 0)
);
end CAR;
architecture behave of CAR is
begin
process(clk)
variable addtemp: std_logic_vector(7 downto 0);-----------address of the control memory
variable opcode: std_logic_vector(7 downto 0);
begin
if(rising_edge(clk)) then
opcode:=IR_in;
if(c(0)='1') then
addtemp:=addtemp+1;
end if;
if(c(2)='1') then --clear
addtemp:="00000000";
end if;
if flag(4)='1' then
addtemp:="00000000";
end if;
if (c(21)='1') then-------------for JMPGEZ addtemp:=addtemp+1+flag(1);
end if;
if (c(30)='1') then------------for MPY
addtemp:=addtemp+flag(3);
end if;
if c(1)='1' and opcode/="00000000" then case opcode is
when "00000001"=>------------store
addtemp:="00001000";-----------------08h when "00000010"=>------------load
addtemp:="00010000";-----------------10h when "00000011"=>------------add
addtemp:="00011000";-----------------18h when "00000100"=>------------sub
addtemp:="00100000";-----------------20h when "00001010"=>------------and
addtemp:="00101000";-----------------28h when "00001011"=>------------or
addtemp:="00110000";-----------------30h when"00001100"=>-------------not
addtemp:="00111000";-----------------38h when"00001101"=>------------shr
addtemp:="01000000";-----------------40h when"00001110"=>------------shl
addtemp:="01000011";-----------------43h when"00000101"=>------------jmpgez
addtemp:="01001000";-----------------48h when"00000110"=>-------------jmp
addtemp:="01010000";-----------------50h
when"00001000"=>-------------mpy
addtemp:="01011000";-----------------58h when"00001111"=>-------------sar
addtemp:="01100000";-----------------60h
when"00010000"=>-------------sal
addtemp:="01100011";-----------------63h
when"00000111"=>-------------halt
addtemp:="01101000";-----------------68h
when others=>
NULL;
end case;
end if;
if(reset='0') then
addtemp:="00000000";
end if;
addr<=addtemp;
end if;
end process;
end behave;
---------------/////-------------part of LPM_ROM.mif’---------/////---------------------------。