COMPLEMENTARY MOS INTEGRATED CIRCUIT DEVICE
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专利名称：COMPLEMENTARY MOS INTEGRATED CIRCUIT DEVICE
发明人：WAKIMOTO AKIHIKO
申请号：JP12745983
申请日：19830711
公开号：JPH0526345B2
公开日：
19930415
专利内容由知识产权出版社提供
摘要：PURPOSE:To obtain a CMOS IC having large latchup withstand amount by forming a p<+> type region from the surface of a p type substrate adjacent to an n<+> type region for forming the source of an n-channel MOST formed directly from the substrate over under the n<+> type region. CONSTITUTION:The first p<+> type region 3a disposed at the source side of an n-MOST is deeply implanted to be superposed on the first n<+> type region 4 for forming a source, the first p<+> type region 3a of the same potential as a p<-> type substrate 1 thereby increases in the area, and a current feasibly flows between the substrate 1 and the source wirings 13 of the n-MOST. In other words the base resistance R2 of a parasitic bipolar transistor Tr2 decreases. Thus, positive surge is applied to drain wirings 14, 15 side, a transistor Tr1 is turned ON, and even if the potential of the substrate 1 varies, the variation in the potential of the base of the transistor Tr2 is small, and the transistor Tr2 is not turned ON. Accordingly, the transistor Tr2 is not turned ON, and a latchup does not occur.
申请人：MITSUBISHI ELECTRIC CORP
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