FPGA可编程逻辑器件芯片EP2A25F672I8N中文规格书

C YCLIC R EDUNDANCY C HECK (CRC)
CRC P ROGRAMMING M ODEL
ADSP-BF60X B LACKFIN P ROCESSOR H ARDWARE R EFERENCE
Core Driven Memory Scan Compute Compare Mode
Performs CRC signature calculation and verification for a region of memory using core transactions. The CRC peripheral is configured such that it operates in the burst mode of operation due to the stalling options configured via CRC_CTL being disabled.
P REREQUISITE :
The task assumes that the polynomial has been loaded and the look-up table is fully initialized, that all CRC interrupts have been serviced (none pending), and the CRC block is currently disabled as per CRC_CTL.BLKEN .
1.Initialize CRC_DCNT .
A DDITIONAL I NFORMATION :The value loaded must represent the number of 32-bit words in the memory region for which the CRC signature is to be calculated and verified.
2.Initialize CRC_DCNTRLD .
A DDITIONAL I NFORMATION :This is the value that is used to reload the CRC_DCNT register upon completion of current CRC operation. If no further operation is required then this register may be initialized to zero.
3.Initialize CRC_RESULT_CUR .
A DDITIONAL I NFORMATION :This register may be initialized to provide an initial seed for the CRC opera-tion that is about to take place.
4.Initialize CRC_COMP .
A DDITIONAL I NFORMATION :This register contains the pre-calculated final CRC signature result for the memory region that is used in the final compare operation.
5.Initialize CRC_INEN .
A DDITIONAL I NFORMATION :This register is used to enable the generation of the CRC interrupts for notifi-cation of compare errors and block completion. Configure these interrupts as required. If enabled ensure the corresponding interrupt handlers are also configured.
6.Initialize CRC_CTL with CRC_CTL.OPMODE set to Memory Scan Compute Compare Mode and CRC_CTL.
BLKEN configured to enable the CRC peripheral.
•CRC_CTL.OBRSTALL and CRC_CTL.IRRSTALL options must be disabled for this task example.•All mirroring and bit reversal options should also be configured.
•CRC auto clear options should also be configured.
S TEP R ESULT :The CRC peripheral is now enabled and ready for data to be written by the core or DMA channel.
D YNAMIC M EMORY C ONTROLLER (DMC)
ADSP-BF60X DMC R EGISTER D ESCRIPTIONS
ADSP-BF60X B LACKFIN P ROCESSOR H ARDWARE R EFERENCE 11
(R/W)CLKOE CLK Output Enable.The DMC_PADCTL.CLKOE bit selects the CLK pads output enable
value.
Actvie OE Value 1Inactive OE Value
10
(R/W)CLKPWD CLK Powerdown.The DMC_PADCTL.CLKPWD bit selects whether the CLK pads receiver
is powered up or down.
Pad Receiver Powered Up 1Pad Receiver Powered Down
9:8
(R/W)CLKODS Clock Output Drive Strength.The DMC_PADCTL.CLKODS bits select clock pad output drive strength.
SSTL18 full drive / LPDDR 10mA 1
SSTL 18 half drive / LPDDR 4mA 2
LPDDR 8 mA 3LPDDR 2 mA
6
(R/W)DQSPWD DQ/DQS Powerdown.The DMC_PADCTL.DQSPWD bit selects whether the DQ and DQS pads
receiver is powered up or down.
Pad Receiver Powered Up 1Pad Receiver Powered Down
5:4
(R/W)DQSODS DQS Output Drive Strength.The DMC_PADCTL.DQSODS bits select the DQS pads output drive
strength. Note that DMC_PADCTL.DQSODS [3] is connected to S1 of
PAD, and DMC_PADCTL.DQSODS [4] is connected to S0 of PAD.
SSTL18 full drive / LPDDR 10mA 1
SSTL 18 half drive / LPDDR 4mA 2
LPDDR 8mA Reserved for DDR2 mode 3LPDDR 2mA
2
(R/W)DQPWD DQ Powerdown..The DMC_PADCTL.DQPWD bit selects whether the DQ pads receiver is
powered up or down.
Pad Receiver Powered Up 1Pad Receiver Powered Down
Table 11-20:
DMC_PADCTL Register Fields (Continued)Bit No.
(Access)Bit Name Description/Enumeration
C YCLIC R EDUNDANCY C HECK (CRC)
CRC F UNCTIONAL D ESCRIPTION CRC peripheral or read data from the FIFO of the CRC peripheral as an alternative to the operation being
performed by the DMA channels.
Data received by MMR writes can transfer to destination DMA. Similarly, data received by source DMA can be output through the MMR interface. Optionally, intermediate results can be made available to the MMR interface.
Mirror Block
The mirror block individually controls bit reversing of the polynomial, the computation results and the expected result. Endian and reflection of processed data can be controlled by bit mirroring, byte mirroring, word swapping and any combination of these operations.
Data FIFO
The CRC data FIFO is a 32-bit-wide 4-entry FIFO. The FIFO is accessible to both the Peripheral DMA bus and the MMR Access bus. The FIFO status is accessible from the CRC_STAT register.
DMA Request Generator
The DMA Request Generator is responsible for granting incoming DMA requests from the source DMA channel and issuing outgoing DMA requests to the destination DMA channel.
CRC Engine
The CRC Engine is a 32-bit CRC engine that implements the Reduced Table Lookup scheme. The CRC engine provides support for a user-programmable 32-bit polynomial that is used to load the lookup table parameters required for the CRC calculation. The CRC engine is a 2-cycle implementation operating on
16 bits of data per cycle.
Compare Logic
The compare logic takes the final CRC signature and compares this to the expected CRC signature, gener-ating a CRC compare error if the signatures do not match. A compare error can flag a system fault. CRC Architectural Concepts
The CRC peripheral includes a 32-bit CRC engine that implements the reduced table lookup scheme oper-ating on 16 bits of data per cycle, resulting in a 2-cycle implementation for each 32 bits of data written to the peripheral. The upper 16 bits of the data are processed in the first cycle, followed by the lower 16 bits.
A 32-bit polynomial is required before calculation of the CRC signature can occur. The polynomial is used
to generate the contents of an internal lookup table that is required by the reduced table lookup implemen-ADSP-BF60X B LACKFIN P ROCESSOR H ARDWARE R EFERENCE。