Memory address control unit
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专利名称：Memory address control unit 发明人：村上 達雄
申请号：JP特願平7-333062
申请日：19951221
公开号：JP第2806849号B2
公开日：
19980930
专利内容由知识产权出版社提供
摘要：PROBLEM TO BE SOLVED: To eliminate a noise caused at a switching time by setting initial values of a row address counter and a column address counter in the same and eliminating the row/column switching. SOLUTION: This device is constituted of the row address counter(LAC) 1, the column address counter(CAC) 2 and a memory 3. The LAC 1 counts a first clock to form a row address. The CAC 2 loads the row address from the LAC 1, and inputs an initial value setting signal LOAD, and counts a second clock from the same count value as the row address to form a column address. Then, the memory 3 is accessed making the CAC 2, an RAS inversion signal, a CAS inversion signal and the output of the CAC 2 address inputs.
申请人：日本電気アイシーマイコンシステム株式会社
地址：神奈川県川崎市中原区小杉町1丁目403番53
国籍：JP
代理人：京本 直樹 (外2名)
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