HT82K94E_07资料

HT82K94E/HT82K94A
USB Multimedia Keyboard Encoder 8-Bit MCU
Rev.1.501October 11,2007
General Description
This device is an 8-bit high performance RISC architec-ture microcontroller designed for USB product applica-tions.It is particularly suitable for use in products such as keyboards and keyboard with calculator.A HALT fea-ture is included to reduce power consumption.
The mask version HT82K94A is fully pin and function-ally compatible with the OTP version HT82K94E device.The HT82K94A is under development and will be avail-able soon.
Features
·Operating voltage:
f SYS =6M/12MHz:2.2V~5.5V
·40bidirectional I/O lines (max.)
·8-bit programmable timer/event counter with
overflow interrupt (shared with PD4,vector 08H)
·16-bit programmable timer/event counter and
overflow interrupts (shared with PA7,vector 0CH)
·Crystal oscillator (6MHz or 12MHz)·Watchdog Timer
·PS2and USB modes supported ·USB 2.0low speed function
·4endpoints supported (endpoint 0included)·6144´16program memory ROM ·224´8data memory RAM
·One internal USB interrupt (vector 04H)·All I/O ports support wake-up options
·HALT function and wake-up feature reduce power
consumption
·8-level subroutine nesting
·Up to 0.33m s instruction cycle with 12MHz system
clock at V DD =5V
·Bit manipulation instruction ·16-bit table read instruction ·63powerful instructions
·All instructions in one or two machine cycles ·Optional 3-battery mode 2.4V LVR/2.6V LVD (±0.1V)
by option,Low battery detector with internal bit
·Optional 2-battery mode 2.2V LVR/2.4V LVD (±0.1V)
by option,Low battery detector with internal bit
·Operating voltage from 4.0V to 5.5V
(For Connect USB/PS2Mode)
·Operating voltage from 2.2V to 3.3V
(For Pure Cal.Mode)
·48-pin SSOP
package
Technical Document
·Tools Information ·FAQs
·Application Note
Block Diagram
Rev.1.502October11,2007
Pin Assignment Pin Description
Pin Name I/O ROM Code
Option
Description
PA0~PA6 PA7/TMR1I/O
Pull-high
Wake-up
CMOS/NMOS/PMOS
Bidirectional8-bit input/output port.Each bit can be configured as a
wake-up input by ROM code option.The input or output mode is con-
trolled by PAC(PA control register).
Pull-high resistor options:PA0~PA7
CMOS/NMOS/PMOS options:PA0~PA7
Wake-up options:PA0~PA7
PA7is pin-shared with TMR1input,respectively.
PB0~PB7I/O Pull-high
Wake-up
Bidirectional8-bit input/output port.Software instructions determine the
CMOS output or Schmitt trigger input with pull-high resistor(determined
by pull-high options).
Wake-up options:PB0~PB7
PC0~PC7I/O Pull-high
Wake-up
Bidirectional I/O lines.Software instructions determine the CMOS out-
put or Schmitt trigger input with pull-high resistor(determined by
pull-high options).
Wake-up options:PC0~PC7
PD0~PD3
PD4/TMR0 PD5~PD7I/O
Pull-high
Wake-up
Bidirectional I/O
lines.Software instructions determine the CMOS out-
put or Schmitt trigger input with pull-high resistor(determined by
pull-high options).
Wake-up options:PD0~PD7
PD4is pin-shared with TMR0input.
PE0~PE7I/O Pull-high
Wake-up
Bidirectional I/O lines.Software instructions determine the CMOS out-
put or Schmitt trigger input with pull-high resistor(determined by
pull-high options).
Wake-up options:PE0~PE7
Rev.1.503October11,2007
Pin Name I/O ROM Code
Option
Description
VSS¾¾Negative power supply,ground
RES I¾Schmitt trigger reset input.Active low VDD¾¾Positive power supply
V33O O¾ 3.3V regulator output
USBD+/CLK I/O¾USBD+or PS2CLK I/O line
USB or PS2function is controlled by software control register
USBD-/DATA I/O¾USBD-or PS2DATA I/O line
USB or PS2function is controlled by software control register
OSC1 OSC2I
O
¾OSC1,OSC2are connected to a6MHz or12MHz Crystal/resonator
(determined by software instructions)for the internal system clock.
Absolute Maximum Ratings
Supply Voltage...........................V SS-0.3V to V SS+6.0V Storage Temperature............................-50°C to125°C Input Voltage..............................V SS-0.3V to V DD+0.3V Operating Temperature...............................0°C to70°C
Note:These are stress ratings only.Stresses exceeding the range specified under²Absolute Maximum Ratings²may cause substantial damage to the device.Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C.Characteristics Ta=25°C
Symbol Parameter
Test Conditions
Min.Typ.Max.Unit V DD Conditions
V DD Operating Voltage ¾f SYS=6MHz 2.2¾ 5.5V ¾f SYS=12MHz 2.2¾ 5.5V
I DD1Operating Current(6MHz Crystal)5V No load,f SYS=6MHz¾ 6.512mA I DD2Operating Current(12MHz Crystal)5V No load,f SYS=12MHz¾7.516mA I STB1Standby Current(WDT Enabled)5V No load,system HALT,
USB suspend
¾¾250m A
I STB2Standby Current(WDT Disabled)5V No load,system HALT,
USB suspend
¾¾230m A
I STB3Standby Current(WDT Enabled)5V No load,system HALT,
input/output mode,
set SUSPEND2[1EH]
¾¾15m A
V IL1Input Low Voltage for I/O Ports5V TTL level0¾0.8V
V IH1Input High Voltage for I/O Ports5V TTL level2¾5V
V IL2Input Low Voltage(RES)5V CMOS level0¾0.4V DD V
V IH2Input High Voltage(RES)5V CMOS level0.9V DD¾V DD V
I OL1I/O Port Sink Current for PA1~PA7,
PB,PC,PD
5V V OL=3.4V101520mA
I OL2I/O Port Sink Current for PA1~PA7,
PB,PC,PD
5V V OL=0.4V248mA
I OL3I/O Port Sink Current for PA05V V OL=0.4V71013mA Rev.1.504October11,2007
Symbol Parameter
Test Conditions
Min.Typ.Max.Unit V DD Conditions
I OH1I/O Port Source Current for PA1~PA7,
PB,PC,PD
5V V OH=3.4V-2-4-8mA I OH2I/O Port Source Current for PA05V V OH=3.4V-12-18-24mA R PH Pull-high Resistance for PA,PB,PC,PD5V¾255080k W
V LVR Low Voltage Reset¾2-battery option 2.1 2.2 2.3
V 3-battery option 2.3 2.4 2.5
V LVD Low Battery Detecting Voltage¾2-battery option 2.3 2.4 2.5
V 3-battery option 2.5 2.6 2.7
V V33O 3.3V Regulator Output5V I V33O=-5mA 3.0 3.3 3.6V A.C.Characteristics Ta=25°C
Symbol Parameter
Test Conditions
Min.Typ.Max.Unit V DD Conditions
f SYS System Clock(Crystal OSC)5V¾6¾12MHz f TIMER Timer I/P Frequency(TMR)5V¾0¾12MHz t WDTOSC Watchdo
g Oscillator5V¾153170m s t WDT1Watchdog Time-out Period(WDT OSC)5V Without WDT prescaler4816ms t WDT2Watchdog Time-out Period
(System Clock)
¾Without WDT prescaler¾1024¾t SYS t RES External Reset Low Pulse Width¾¾1¾¾m s
t SST System Start-up Timer Period¾Wake-up from HALT¾1024¾t SYS Power-up,Watchdog
Time-out from normal
¾1024¾t WDTOSC
t INT Interrupt Pulse Width¾¾1¾¾m s Rev.1.505October11,2007
Functional Description
Rev.1.506October 11,2007
Execution Flow
The system clock for the microcontroller is derived from a crystal (6or 12MHz).The system clock is internally di-vided into four non-overlapping clocks.One instruction cycle consists of four system clock cycles.
Instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while de-coding and execution takes the next instruction cycle.However,the pipelining scheme allows each instruction to be effectively executed in a cycle.If an instruction changes the program counter,two cycles are required to complete the instruction.Program Counter -PC
The program counter (PC)controls the sequence in which the instructions stored in the program ROM are executed and its contents specify a full range of pro-gram memory.
After accessing a program memory word to fetch an in-struction code,the contents of the program counter are
incremented by one.The program counter then points to the memory word containing the next instruction code.When executing a jump instruction,conditional skip ex-ecution,loading PCL register,subroutine call or return from subroutine,initial reset,internal interrupt,USB in-terrupt or return from interrupts,the PC manipulates the program transfer by loading the address corresponding to each instruction.
The conditional skip is activated by instructions.Once the condition is met,the next instruction,fetched during the current instruction execution,is discarded and a dummy cycle replaces it to get the proper instruction.Otherwise proceed to the next instruction.
The lower byte of the program counter (PCL)is a read-able and writeable register (06H).Moving data into the PCL performs a short jump.The destination will be within the current program ROM page.
When a control transfer takes place,an additional dummy cycle is required.
Execution Flow
Mode
Program Counter
*12*11*10*9*8*7*6*5*4*3*2*1*0Initial Reset 0000000000000USB Interrupt
0000000000100Timer/Event Counter 0Overflow 0000000001000Timer/Event Counter 1Overflow 0
1
1
Skip Program Counter+2
Loading PCL *12*11*10*9*8@7@6@5@4@3@2@1@0Jump,Call Branch #12#11#10#9#8#7#6#5#4#3#2#1#0Return from Subroutine
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note:*12~*0:Program counter bits
S12~S0:Stack register bits #12~#0:Instruction code bits
@7~@0:PCL bits
Program Memory-ROM
The program memory is used to store the program in-structions which are to be executed.It also contains data,table,and interrupt entries,and is organized into 6144´16bits,addressed by the program counter and ta-ble pointer.
Certain locations in the program memory are reserved for special usage:
·Location000H
This area is reserved for program initialization.After chip reset,the program always begins execution at lo-cation000H.
·Location004H
This area is reserved for the USB and external inter-rupt service program.If the USB interrupt is activated, the interrupt is enabled and the stack is not full,the program begins execution at location004H.
·Location008H
This area is reserved for the Timer/Event Counter0in-terrupt service program.If a timer interrupt results from a Timer/Event Counter0overflow,and if the in-terrupt is enabled and the stack is not full,the program begins execution at location008H.·Location00CH
This location is reserved for the Timer/Event Counter 1interrupt service program.If a timer interrupt results from a Timer/Event Counter1overflow,and the inter-rupt is enabled and the stack is not full,the program begins execution at location00CH.
·Table location
Any location in the program memory can be used as look-up tables.There are three method to read the ROM data by two table read instructions:²TABRDC²and²TABRDL²,transfer the contents of the lower-order byte to the specified data memory,and the higher-order byte to TBLH(08H).
The three methods are shown as follows:
¨The instructions²TABRDC[m]²(the current page, one page=256words),where the table locations is defined by TBLP(07H)in the current page.And the ROM code option TBHP is disabled(default).
¨The instructions²TABRDC[m]²,where the table lo-cations is defined by registers TBLP(07H)and TBHP(01FH).And the ROM code option TBHP is enabled.
¨The instructions²TABRDL[m]²,where the table lo-cations is defined by Registers TBLP(07H)in the last page(1700H~17FFH).
Only the destination of the lower-order byte in the ta-ble is well-defined,the other bits of the table word are transferred to the lower portion of TBLH,and the re-maining1-bit words are read as²0².The Table Higher-order byte register(TBLH)is read only.The ta-ble pointer(TBLP,TBHP)is a read/write register(07H, 1FH),which indicates the table location.Before ac-cessing the table,the location must be placed in the TBLP and TBHP(If the OTP option TBHP is disabled, the value in TBHP has no effect).The TBLH is read only and cannot be restored.If the main routine and the ISR(Interrupt Service Routine)both employ the table read instruction,the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR.Errors can occur.In other words,using the table read instruction in the main rou-tine and the ISR simultaneously should be avoided. However,if the table read instruction has to be applied in both the main routine and the ISR,the interrupt should be disabled prior to the table read instruction.
Program Memory
Instruction
Table Location
*12*11*10*9*8*7*6*5*4*3*2*1*0
TABRDC[m]P12P11P10P9P8@7@6@5@4@3@2@1@0 TABRDL[m]11111@7@6@5@4@3@2@1@0
Table Location
Note:*12~*0:Table location bits P12~P8:Current program counter bits when TBHP is disabled @7~@0:Table pointer bits TBHP register bit3~bit0when TBHP is enabled
Rev.1.507October11,2007
It will not be enabled until the TBLH has been backed up.All table related instructions require two cycles to complete the operation.These areas may function as normal program memory depending on the require-ments.
Once TBHP is enabled,the instruction²TABRDC[m]²reads the ROM data as defined by TBLP and TBHP value.Otherwise,the ROM code option TBHP is dis-abled,the instruction²TABRDC[m]²reads the ROM data as defined by TBLP and the current program counter bits.
Stack Register-STACK
This is a special part of the memory which is used to save the contents of the program counter only.The stack is organized into8levels and is neither part of the data nor part of the program space,and is neither read-able nor writeable.The activated level is indexed by the stack pointer(SP)and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal,the contents of the program counter are pushed onto the stack.At the end of a subroutine or an interrupt routine, signaled by a return instruction(RET or RETI),the pro-gram counter is restored to its previous value from the stack.After a chip reset,the SP will point to the top of the stack.
If the stack is full and a non-masked interrupt takes place,the interrupt request flag will be recorded but the acknowledge signal will be inhibited.When the stack pointer is decremented(by RET or RETI),the interrupt will be serviced.This feature prevents stack overflow al-lowing the programmer to use the structure more easily. In a similar case,if the stack is full and a²CALL²is sub-sequently executed,stack overflow occurs and the first entry will be lost(only the most recent8return ad-dresses are stored).
Data Memory-RAM for Bank0
The data memory is designed with255´8bits.The data memory is divided into two functional groups:spe-cial function registers and general purpose data mem-ory(224´8).Most are read/write,but some are read only.
The general purpose data memory,addressed from 20H to FFH,is used for data and control information under instruction commands.All of the data memory areas can handle arithmetic,logic,increment,decre-ment and rotate operations directly.Except for some dedicated bits,each bit in the data memory can be set and reset by²SET[m].i²and²CLR[m].i².They are also indirectly accessible through memory pointer registers (MP0or MP1).
Data Memory-RAM for Bank1
The special function registers used in USB interface are located in RAM bank1.In order to access the Bank1register,only the Indirect addressing pointer MP1can be used and the Bank register BP should be set to²1². The mapping of RAM bank1is as shown.
Bank0RAM Mapping
Bank1RAM Mapping
Rev.1.508October11,2007
Indirect Addressing Register
Location00H and02H are indirect addressing registers that are not physically implemented.Any read/write op-eration of[00H]([02H])will access data memory pointed to by MP0(MP1).Reading location00H(02H)itself indi-rectly will return the result00H.Writing indirectly results in no operation.
The indirect addressing pointer(MP0)always point to Bank0RAM addresses regardless of the value of the Bank Register(BP).
The indirect addressing pointer(MP1)can access Bank0or Bank1RAM data according to the value of BP which is set to²0²or²1²respectively.
The memory pointer registers(MP0and MP1)are8-bit registers.
Accumulator
The accumulator is closely related to ALU operations.It is also mapped to location05H of the data memory and can carry out immediate data operations.The data movement between two data memory locations must pass through the accumulator.
Arithmetic and Logic Unit-ALU
This circuit performs8-bit arithmetic and logic opera-tions.The ALU provides the following functions:
·Arithmetic operations(ADD,ADC,SUB,SBC,DAA)·Logic operations(AND,OR,XOR,CPL)·Rotation(RL,RR,RLC,RRC)
·Increment and Decrement(INC,DEC)
·Branch decision(SZ,SNZ,SIZ,SDZ)
The ALU not only saves the results of a data operation but also changes the status register.Status Register-STATUS
This8-bit register(0AH)contains the zero flag(Z),carry flag(C),auxiliary carry flag(AC),overflow flag(OV), power down flag(PDF),and watchdog time-out flag (TO).It also records the status information and controls the operation sequence.
With the exception of the TO and PDF flags,bits in the status register can be altered by instructions like most other registers.Any data written into the status register will not change the TO or PDF flag.In addi-tion operations related to the status register may give different results from those intended.
The TO flag can be affected only by system power-up,a WDT time-out or executing the²CLR WDT²or²HALT²instruction.The PDF flag can be affected only by ex-ecuting the²HALT²or²CLR WDT²instruction or dur-ing a system power-up.
The Z,OV,AC and C flags generally reflect the status of the latest operations.
In addition,on entering the interrupt sequence or exe-cuting the subroutine call,the status register will not be pushed onto the stack automatically.If the contents of the status are important and if the subroutine can cor-rupt the status register,precautions must be taken to save it properly.
Interrupt
The device provides internal timer/event counter and USB interrupts.The Interrupt Control Register (INTC;0BH)contains the interrupt control bits to set the enable/disable and the interrupt request flags.
Once an interrupt subroutine is serviced,all the other in-terrupts will be blocked(by clearing the EMI bit).This scheme may prevent any further interrupt nesting.Other interrupt requests may occur during this interval but only
Bit bel Function
0C C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation;otherwise C is cleared.C is also affected by a rotate through carry instruction.
1AC AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction;otherwise AC is cleared.
2Z Z is set if the result of an arithmetic or logic operation is zero;otherwise Z is cleared.
3OV OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit,or vice versa;otherwise OV is cleared.
4PDF PDF is cleared by system power-up or executing the²CLR WDT²instruction.PDF is set by executing the²HALT²instruction.
5TO TO is cleared by system power-up or executing the²CLR WDT²or²HALT²instruction.TO is set by a WDT time-out.
6~7¾Unused bit,read as²0²
Status(0AH)Register
Rev.1.509October11,2007
the interrupt request flag is recorded.If a certain inter-rupt requires servicing within the service routine,the EMI bit and the corresponding bit of the INTC may be set to allow interrupt nesting.If the stack is full,the interrupt request will not be acknowledged,even if the related in-terrupt is enabled,until the SP is decremented.If immedi-ate service is desired,the stack must be prevented from becoming full.
All these kinds of interrupts have a wake-up capability. As an interrupt is serviced,a control transfer occurs by pushing the program counter onto the stack,followed by a branch to a subroutine at specified location in the pro-gram memory.Only the program counter is pushed onto the stack.If the contents of the register or status register (STATUS)are altered by the interrupt service program which corrupts the desired control sequence,the con-tents should be saved in advance.
USB interrupts are triggered by the following USB events and the related interrupt request flag(USBF;bit 4of the INTC)will be set.
·The corresponding USB FIFO is accessed from the PC
·The USB suspends signal from the PC
·The USB resumes signal from the PC
·The USB sends Reset signal
When the interrupt is enabled,the stack is not full and the USB interrupt is active,a subroutine call to location 04H will occur.The interrupt request flag(USBF)and EMI bits will be cleared to disable other interrupts.
When the PC Host access the FIFO of the HT82K94E/ HT82K94A,the corresponding request bit of the USR is set,and a USB interrupt is triggered.So user can easily decide which FIFO is accessed.When the interrupt has been served,the corresponding bit should be cleared by firmware.When the HT82K94E/HT82K94A receives a USB Suspend signal from the Host PC,the suspend line (bit0of the USC)of the HT82K94E/HT82K94A is set and a USB interrupt is also triggered.
Also when the HT82K94E/HT82K94A receives a Re-sume signal from the Host PC,the resume line(bit3of the USC)of HT82K94E/HT82K94A is set and a USB in-terrupt is triggered.
Whenever a USB reset signal is detected,the USB in-terrupt is triggered.
The internal Timer/Event Counter0interrupt is initial-ized by setting the Timer/Event Counter0interrupt re-quest flag(;bit5of INTC),caused by a timer0overflow. When the interrupt is enabled,the stack is not full and the T0F bit is set,a subroutine call to location08H will occur.The related interrupt request flag(T0F)will be re-set and the EMI bit cleared to disable further interrupts.
The internal Timer/Even Counter1interrupt is initialized by setting the Timer/Event Counter1interrupt request flag(;bit6of INTC),caused by a timer1overflow.When the interrupt is enabled,the stack is not full and the T1F is set,a subroutine call to location0CH will occur.The related interrupt request flag(T1F)will be reset and the EMI bit cleared to disable further interrupts.
During the execution of an interrupt subroutine,other in-terrupt acknowledge signals are held until the²RETI²in-struction is executed or the EMI bit and the related interrupt control bit are set to²1²(if the stack is not full). T o return from the interrupt subroutine,²RET²or²RETI²may be invoked.RETI will set the EMI bit to enable an in-terrupt service,but RET will not.
Bit bel Function
0EMI Controls the master(global)interrupt(1=enabled;0=disabled)
1EUI Controls the USB interrupt(1=enabled;0=disabled)
2ET0I Controls the Timer/Event Counter0interrupt(1=enabled;0=disabled)
3ET1I Controls the Timer/Event Counter1interrupt(1=enabled;0=disabled)
4USBF USB interrupt request flag(1=active;0=inactive)
5T0F Internal Timer/Event Counter0request flag(1=active;0=inactive)
6T1F Internal Timer/Event Counter1request flag(1=active;0=inactive)
7¾Unused bit,read as²0²
INTC(0BH)Register
Rev.1.5010October11,2007
Interrupts,occurring in the interval between the rising edges of two consecutive T2pulses,will be serviced on the latter of the two T2pulses,if the corresponding inter-rupts are enabled.In the case of simultaneous requests the following table shows the priority that is applied. These can be masked by resetting the EMIbit.
Interrupt Source Priority Vector USB interrupt104H Timer/Event Counter0overflow208H Timer/Event Counter1overflow30CH
Once the interrupt request flags(TF,USBF)are set, they will remain in the INTC register until the interrupts are serviced or cleared by a software instruction.It is recommended that a program does not use the²CALL subroutine²within the interrupt subroutine.Interrupts of-ten occur in an unpredictable manner or need to be ser-viced immediately in some applications.If only one stack is left and enabling the interrupt is not well controlled,the original control sequence will be damaged once the ²CALL²operates in the interrupt subroutine.
Oscillator Configuration
There is an oscillator circuits in the microcontroller.
This oscillator is designed for system clocks.The HALT mode stops the system oscillator and ignores an exter-nal signal to conserve power.
A crystal across OSC1and OSC2is needed to provide the feedback and phase shift required for the oscillator. No other external components are required.In stead of a crystal,a resonator can also be connected between OSC1and OSC2to get a frequency reference,but two external capacitors in OSC1and OSC2are required.
The WDT oscillator is a free running on-chip RC oscilla-tor,and no external components are required.Even if the system enters the power down mode,the system clock is stopped,but the WDT oscillator still works within a period of approximately31m s.The WDT oscillator can be disabled by ROM code option to conserve power.
Watchdog Timer-WDT
The WDT clock source is implemented by a dedicated RC oscillator(WDT oscillator),or instruction clock(sys-tem clock divided by4),determines the ROM code op-tion.This timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results.The Watchdog Timer can be disabled by ROM code option.If the Watchdog Timer is disabled,all the executions related to the WDT result in no operation.
Once the internal WDT oscillator(RC oscillator,nor-mally with a period of31m s/5V)is selected,it is first di-vided by256(8-stage)to get the nominal time-out period of8ms/5V.This time-out period may vary with temperatures,VDD and process variations.By invoking the WDT prescaler,longer time-out periods can be real-ized.Writing data to WS2,WS1,WS0(bits2,1,0of the WDTS)can give different time-out periods.If WS2, WS1,and WS0are all equal to1,the division ratio is up to1:128,and the maximum time-out period is1s/5V.If the WDT oscillator is disabled,the WDT clock may still come from the instruction clock and operates in the same manner except that in the HALT state the WDT may stop counting and lose its protecting purpose.In this situation the logic can only be restarted by external logic.The high nibble and bit3of the WDTS are re-served for user¢s defined flags,which can only be set to ²10000²(WDTS.7~WDTS.3).
Watchdog Timer
System Oscillator
Rev.1.5011October11,2007
If the device operates in a noisy environment,using the on-chip32kHz RC oscillator(WDT OSC)is strongly rec-ommended,since the HALT will stop the system clock.
WS2WS1WS0Division Ratio
0001:1
0011:2
0101:4
0111:8
1001:16
1011:32
1101:64
1111:128
WDTS(09H)Register
The WDT overflow under normal operation will initialize a²chip reset²and set the status bit²TO².But in the HALT mode,the overflow will initialize a²warm reset²and only the Program Counter and SP are reset to zero. To clear the contents of the WDT(including the WDT prescaler),three methods are employed;external reset (a low level to RES),software instruction and a²HALT²instruction.The software instruction include²CLR WDT²and the other set-²CLR WDT1²and²CLR WDT2².Of these two types of instruction,only one can be active depending on the ROM code option-²CLR WDT times selection option².If the²CLR WDT²is se-lected(i.e.CLRWDT times equal one),any execution of the²CLR WDT²instruction will clear the WDT.In the case wherein²CLR WDT1²and²CLR WDT2²are cho-sen(i.e.CLRWDT times is equal to two),these two in-structions must be executed to clear the WDT, otherwise,the WDT may reset the chip as a result of time-out.
Power Down Operation-HALT
The HALT mode is initialized by the²HALT²instruction and results in the following:
·The system oscillator will be turned off but the WDT oscillator remains running(if the WDT oscillator is se-lected).
·The contents of the on-chip RAM and registers remain unchanged.
·WDT and WDT prescaler will be cleared and re-counted again(if the WDT clock is from the WDT os-cillator).
·All of the I/O ports maintain their original status.·The PDF flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an external reset,an interrupt,an external falling edge sig-nal on I/O ports or a WDT overflow.An external reset causes a device initialization and the WDT overflow per-forms a²warm reset².After the TO and PDF flags are examined,the cause for chip reset can be determined. The PDF flag is cleared by a system power-up or exe-cuting the²CLR WDT²instruction and is set when exe-cuting the²HALT²instruction.The TO flag is set if the WDT time-out occurs,and causes a wake-up that only resets the Program Counter and Stack Pointer,the oth-ers remain in their original status.
The I/O ports wake-up and interrupt methods can be considered as a continuation of normal execution.Each bit in the Port A can be independently selected to wake-up the device by option.PB,PC and PD can also be selected to wake-up the device by option.Upon awakening from an I/O port stimulus,the program will resume execution of the next instruction.If it awakens from an interrupt,two sequence may occur.If the related interrupt is disabled or the interrupt is enabled but the stack is full,the program will resume execution at the next instruction.If the interrupt is enabled and the stack is not full,the regular interrupt response takes place.If an interrupt request flag is set to²1²before entering the HALT mode,the wake-up function of the related inter-rupt will be disabled.Once a wake-up event occurs,it takes1024t SYS(system clock period)to resume normal operation.In other words,a dummy period will be in-serted after a wake-up.If the wake-up results from an in-terrupt acknowledge signal,the actual interrupt subroutine execution will be delayed by one or more cy-cles.If the wake-up results in the next instruction execu-tion,this will be executed immediately after the dummy period is completed.
To minimize power consumption,all the I/O pins should be carefully managed before entering the HALT status.
Reset
There are three ways in which a reset can occur:·RES reset during normal operation
·RES reset during HALT
·WDT time-out reset during normal operation
The WDT time-out during HALT is different from other chip reset conditions,since it can perform a²warm re-set²that resets only the Program Counter and SP,leav-ing the other circuits in their original state.Some regis-ters remain unchanged during other reset conditions. Most registers are reset to the²initial condition²when the reset conditions are met.By examining the PDF and TO flags,the program can distinguish between different ²chip resets².
TO PDF RESET Conditions
00RES reset during power-up
u u RES reset during normal operation
00RES wake-up HALT
1u WDT time-out during normal operation 11WDT wake-up HALT
Note:²u²stands for²unchanged²
Rev.1.5012October11,2007。