FPGA可编程逻辑器件芯片EP3C16F256A7N中文规格书

Using the PHY Reconfiguration Interface
•Refer to the section PHY Reconfiguration Interface on page 81 for details on this interface and the address map.
6.2. Debug Toolkit
6.2.1. Overview
The P-Tile Debug Toolkit is a System Console-based tool for P-Tile that provides real-time control, monitoring and debugging of the PCIe links at the Physical, Data Link and Transaction layers.The P-Tile Debug Toolkit allows you to:•View protocol and link status of the PCIe links per port.•View PLL and per-channel status of the PCIe links per port.•Control the channel analog settings.•View the receiver eye and measure the eye height and width.•Indicate the presence of a re-timer connected between the link partners.The following figure provides an overview of the P-Tile Debug Toolkit in the P-Tile Avalon-MM IP for PCI Express.Figure 38.Overview of the P-Tile Debug Toolkit
When you enable the P-Tile Debug Toolkit, the intel_pcie_ptile_avmm module of
the generated IP includes the Debug Toolkit modules and related logic as shown in the figure above.
Drive the Debug Toolkit from a System Console. The System Console connects to the Debug Toolkit via an Native PHY Debug Master Endpoint (NPDME). Make this connection via an Intel FPGA Download Cable.
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This PHY reconfiguration interface clock (xcvr_reconfig_clk ) is used to clock the
following interfaces:
•
The NPDME module •
PHY reconfiguration interface (xcvr_reconfig)•Hard IP reconfiguration interface (hip_reconfig)
Provide a clock source (50 MHz - 125 MHz, 100 MHz recommended clock frequency) to drive the xcvr_reconfig_clk clock. Use the output of the Reset Release Intel FPGA IP to drive the ninit_done , which provides the reset signal to the NPDME module.
Note: When using the port bifurcation feature, always connect the xcvr_reconfig_clk of
Port0 to a clock source. This signal is used to provide the clock to the Debug Toolkit.
Note:
When you enable the P-Tile Debug Toolkit, the Hard IP reconfiguration interface is enabled by default.
When you run a dynamically-generated design example on the Intel Development Kit,make sure that clock and reset signals are connected to their respective sources and
appropriate pin assignments are made. Here are some sample .qsf assignments for
the Debug Toolkit for Intel Stratix 10 DX devices:
•
set_location_assignment PIN_A31 -to p0_hip_reconfig_clk_clk •set_location_assignment PIN_C23 -to xcvr_reconfig_clk_clk 6.2.2. Enabling the P-Tile Debug Toolkit
To enable the P-Tile Debug Toolkit in your design, enable the option Enable Debug Toolkit in the PCIe Configuration, Debug and Extension options tab of the Intel FPGA P-Tile Avalon-MM IP for PCI Express.
When using bifurcated ports, you can enable the Debug Toolkit for each bifurcated port by enabling the option Enable Debug Toolkit on each of the bifurcated ports.
Note: When you enable the P-Tile Debug Toolkit in the IP , the Hard IP reconfiguration interface and the PHY reconfiguration interface will be used by the Debug Toolkit.Hence, you will not be able to drive logic on these interfaces from the FPGA fabric.
6.2.3. Launching the P-Tile Debug Toolkit
Use the design example you compiled by following the Quick Start Guide to familiarize yourself with the P-Tile Debug Toolkit. Follow the steps in the Generating the Design Example and Compiling the Design Example to generate the SRAM Object File, (.sof)for this design example.
To use the P-Tile Debug Toolkit, download the .sof to the Intel Development Kit. Then,open the System Console and load the design to the System Console as well. Loading the .sof to the System Console allows the System Console to communicate with the design using NPDME. NPDME is a JTAG-based Avalon-MM master . It drives Avalon-MM slave interfaces in the PCIe design. When using NPDME, the Intel Quartus Prime software inserts the debug interconnect fabric to connect with JTAG.
Here are the steps to complete these tasks:
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e the Intel Quartus Prime Programmer to download the .sof to the Intel FPGA Development Kit.
Note: To ensure correct operation, use the same version of the Intel Quartus Prime Programmer and Intel Quartus Prime Pro Edition software that you used to generate the .sof.
2.To load the design into System Console:
a.
Launch the Intel Quartus Prime Pro Edition software.b.
Start System Console by choosing Tools , then System Debugging Tools ,then System Console .c.On the System Console File menu, select Load design and browse to the .sof
file.
d.
Select the .sof and click OK . The .sof loads to the System Console.3.The System Console Toolkit Explorer window will list all the DUTs in the design that have the P-Tile Debug Toolkit enabled.
a.Select the DUT with the P-Tile Debug Toolkit you want to view. This will open the Debug Toolkit instance of that DUT in the Details window.
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