FPGA可编程逻辑器件芯片5CGXFC5C6U19C6N中文规格书

Configuration
f See the Configurin
g Stratix II & Stratix II GX Devices chapter in volume 2
of the Stratix II Device Handbook or the Stratix II GX Device Handbook for
more information about configuration schemes in Stratix II and
Stratix II GX devices.
Device Security Using Configuration Bitstream Encryption
Stratix II FPGAs are the industry’s first FPGAs with the ability to decrypt
a configuration bitstream using the Advanced Encryption Standard
(AES) algorithm. When using the design security feature, a 128-bit
security key is stored in the Stratix II FPGA. To successfully configure a
Stratix II FPGA that has the design security feature enabled, it must be
configured with a configuration file that was encrypted using the same
128-bit security key. The security key can be stored in non-volatile
memory inside the Stratix II device. This non-volatile memory does not
require any external devices, such as a battery back-up, for storage.PPA
MAX II device or microprocessor and flash device v
JTAG Download cable (4)
MAX II device or microprocessor and
flash device Notes for Table 3–5:
(1)
In these modes, the host system must send a DCLK that is 4× the data rate.(2)
The enhanced configuration device decompression feature is available, while the Stratix II decompression feature is not available.(3)
Only remote update mode is supported when using the AS configuration scheme. Local update mode is not supported.(4)The supported download cables include the Altera USB Blaster universal serial bus (USB) port download cable,
MasterBlaster serial/USB communications cable, ByteBlaster II parallel port download cable, and the
ByteBlasterMV parallel port download cable.
Table 3–5.Stratix II Configuration Features (Part 2 of 2)
Configuration
Scheme
Configuration Method Design Security Decompression Remote System Upgrade
Advanced Features
switchover circuit is edge-sensitive, the falling edge of the clkswitch
signal does not cause the circuit to switch back from inclk1 to inclk0.
When the clkswitch signal goes high again, the process repeats.
clkswitch and automatic switch only work if the clock being switched
to is available. If the clock is not available, the state machine waits until
the clock is available.
Figure1–20.Clock Switchover Using the CLKSWITCH Control Note(1)
Note to Figure1–20:
(1)Both inclk0 and inclk1 must be running when the clkswitch signal goes high to initiate a manual clock
switchover event. Failing to meet this requirement causes the clock switchover to not function properly.
Figure1–21 shows a simulation of using switchover for two different
reference frequencies. In this example simulation, the reference clock is
=100 MHz and is allowed
either 100 or 66 MHz. The PLL begins with f
IN
to lock. At 20 s, the clock is switched to the secondary clock, which is at
66 MHz.
Passive Serial Configuration
Figure7–23.Concurrent PS Configuration of Multiple Devices Using an
Enhanced Configuration Device
Notes to Figure7–23:
(1)The pull-up resistor should be connected to the same supply voltage as the
configuration device.
(2)The nINIT_CONF pin is available on enhanced configuration devices and has an
internal pull-up resistor that is always active, meaning an external pull-up resistor
should not be used on the nINIT_CONF-nCONFIG line. The nINIT_CONF pin does
not need to be connected if its functionality is not used. If nINIT_CONF is not used,
nCONFIG must be pulled to V CC either directly or through a resistor.
(3)The enhanced configuration devices’ OE and nCS pins have internal
programmable pull-up resistors. If internal pull-up resistors are used, external
pull-up resistors should not be used on these pins. The internal pull-up resistors
are used by default in the Quartus II software. To turn off the internal pull-up
resistors, check the Disable nCS and OE pull-ups on configuration device option
when generating programming files.。