飞思卡尔MCU时钟模块设置
飞思卡尔单片机快速上手指南说明书
Freescale Semiconductor, Inc.Document Number: 用户指南 Rev. 0, 09/2014Confidentiality statement, as appropriate to document/part status.___________________________________________________________________飞思卡尔单片机快速上手指南作者：飞思卡尔半导体IMM FAE 团队飞思卡尔半导体是全球领先的单片机供应商，其单片机产品包含多种内核，有数百个系列。
为支持用户使用这些产品，飞思卡尔提供了丰富的网站资源、文档及软硬件工具，另外，我们还有众多的第三方合作伙伴及公共平台的支持。
对于不熟悉飞思卡尔产品和网站的初学者来说，了解和使用这些资源这无疑是一个令人望而生畏的浩瀚工程。
本指南的目的，就是给初学者提供一个指导，让他们不被这些海量信息淹没；用户根据本指导提供的操作步骤，能迅速找到所需的资源，了解如何使用相关的工具。
在本指南中，我们以飞思卡尔的新一代Kinetis 单片机K22系列为例，介绍了如何获取与之相关的资源，如何对其进行软硬件设计和开发。
实际上，这些方法也适用于其它的单片机系列。
当然，对于其它有较多不同之处的产品，我们也会继续推出相应的文档，供广大用户参考。
目录1 如何获取技术资料与支持 ..........................................................2 2 如何选择产品、申请样片及购买少量芯片和开发工具 ........... 93 飞思卡尔单片机的开发环境、开发工具和生态系统 ............. 224 如何阅读飞思卡尔的技术文档 ................................................ 45 5 飞思卡尔单片机硬件设计指南 ................................................ 55 6飞思卡尔单片机软件开发指南 (67)飞思卡尔单片机快速上手指南, Rev. 1, 09/20142Freescale Semiconductor, Inc.1 如何获取技术资料与支持1.1 概述当用户使用飞思卡尔单片机芯片时，如何获取芯片的数据手册（Datasheet ）、参考设计（Reference Manual ）和官方例程等资源呢？另外当用户遇到了技术问题该如何获得帮助和解答呢？这里以Kinetis 的K22系列芯片为例为大家介绍如何解决这些问题。
飞思卡尔单片机S12使用方法及程序
飞思卡尔单片机S12使用方法及程序单片机简介：9S12XS128MAA单片机是16位的单片机80个引脚，CPU是CPU12X，内部RAM 8KB,EEPROM:2KB,FLASH:128KB,外部晶振16M，通过内部PLL可得40M总线时钟。
9S12XS128MAA单片机拥有：CAN:1个，SCI:2个，SPI:1个，TIM：8个，PIT：4个，A/D：8个，PWM:8个下面介绍下我们项目用到的几个模块给出初始化代码1、时钟模块初始化单片机利用外部16M晶振，通过锁相环电路产生40M的总线时钟（9S12XS128系列标准为40M），初始化代码如下：view plaincopy to clipboardprint?/******************系统时钟初始化****************/void Init_System_Clock(){asm { // 这里采用汇编代码来产生40M的总线LDAB #3STAB REFDVLDAB #4STAB SYNRBRCLR CRGFLG,#$08,*//本句话含义为等待频率稳定然后执行下一条汇编语句，选择此频率作为总线频率BSET CLKSEL,#$80}}/******************系统时钟初始化****************/void Init_System_Clock(){asm { // 这里采用汇编代码来产生40M的总线LDAB #3STAB REFDVLDAB #4STAB SYNRBRCLR CRGFLG,#$08,*//本句话含义为等待频率稳定然后执行下一条汇编语句，选择此频率作为总线频率BSET CLKSEL,#$80}上面的代码是汇编写的，这个因为汇编代码量比较少，所以用它写了，具体含义注释已经给出，主函数中调用此函数即可完成时钟初始化，总线时钟为40M.2、SCI模块初始化单片机电路做好了当然少不了和PC之间的通信，通信通过单片机串口SCI链接到PC 端的COM口上去。
飞思卡尔嵌入式课件 KL25第十三章 时钟与其他模块
13.2 电源模块
13.2 电源模块
13.2.1电源模式控制 系统模式控制器（SMC）提供多种可选电源模式，用 户可以根据不同的功能需求来选择不同的模式。 根据用户应用的功耗需求，提供了多种功耗模式，用户 可以根据需要选择保留逻辑单元和存储单元的上电状态；或 关闭某些逻辑单元和存储单元电源；或关闭所有逻辑单元和 存储单元电源。I/O状态在所有模式操作中都会保留。 下表描述了可使用的电源模式。
多用途多用途时钟信号生成器（MCG）模块为MCU提 供多种时钟源选择。这个模块由一个锁频环（FLL）和一个 锁相环（PLL）组成。 这个模块可以选择FLL或PLL输出时钟，或者内部或者 外部参考时钟作为MCU系统时钟源。 MCG共有9种运行模式：FEI，FEE，FBI，FBE， PBE，PEE，PEE，BLPI，BLPE，和STOP。需要注意的 是：这9 种模式不是可以任意切换的，模式的切换需要遵守 下面的图，只有下图中给出的切换才是允许的。
每个运行模式都有等待和停止的配合。等待模式对应于 ARM的睡眠模式。停止模式(VLPS,STOP)对应于ARM深度 睡眠模式。 当最大总线频率不是必须的时候，低功耗运行操作模式 能最大减少电源消耗。 芯片通过运行、等待和停止三种模式的不同排列来实现 低功耗。
RUN模式包含：RUN、VLPR。 WAIT模式包含：WAIT、VLPW。 STOP模式包含：STOP、VLPS、LLS、VLLS3、 VLLS1、VLLS0。 各模式在工作电压3.0V，温度为25°C时的功耗值如下：
MCG模块各种模式的含义如下：
本节测试实例选择从FEI进入FBE，再进入PBE，最后 达到PEE状态。具体步骤请参见教材P374-P375，其中涉及 到的MCG模块各位的含义及设置方法请参考《KL25参考手 册》第24章（多功能时钟发生器）相关内容。
飞思卡尔电机控制模块详解
M=2.一、关键点1、MC 模块驱动电机的PWM 波频率在20K 左右时效果比较好。
DITH 位等于0时，计算方法如下：DITH=1时，其中，左对齐和有对齐方式下 M=1，中间对齐是2、MC 模块定时计数器的中断最好禁止，如果开启，在相应的中断服务程序中至少要添加一条“清楚中断标志位”的指令。
3、电机控制模块共8个通道，每个通道有2个Pin 脚组成。
4、Fast 位控制精度，7位或者11位。
5、给周期寄存器写入数值，可启动 MC 计数器，写0关闭所有通道的计数器。
6、MCAM[1:0]写入0x00可关闭某个channel ，写入非零值不是启动MC 计数器，而是控制对齐方式。
为了精确周期寄存器的值应尽量大，Ftc 应尽量小。
二、寄存器寄存器讲解讲解讲解：：1 MCCTL0 (Motor Controller Control Register 0)第7位保留；第6、5位是MCPRE[1:0]控制电机控制器定时计数器时钟f TC 预分频系数。
如下：第4位 MCSWAI 置1，等待模式中电机控制器正常运行，清0，在等待模式中电机控制模块时钟关闭。
第3位，FAST ，清0，电机控制器PWM 模块占空比寄存器分辨率设置为11位，置1，电机控制器PWM 模块占空比寄存器分辨率设置为7位。
第2位，DITH ，清零，电机控制器dith 特性禁止，置1电机控制器dith 特性使能。
第1位保留；第0位MCTOIF ，为1表示，电机控制模块定时计数器溢出；为0，表示自上次复位或清零以来，电机控制模块定时计数器没有发生溢出。
2 MCCTL1 (Motor Controller Control Register 1)第7位，RECIRC控制PWM波极性。
0表示—，1表示+ ；第6到第1位系统保留；第0位，MCTOIE，为0表示Motor Controller Timer Counter Overflow Interrupt禁止，为1标志使能。
飞思卡尔8位单片机-第7章 定时器和比较器模块
二、TPM中的寄存器
（三）TPM模寄存器（TPMMODH:TPMMODL)
TPMMOD高位 TPMMODH
TPMMOD低位 TPMMODL
两个可读/写8位寄存器，定义计数器的最大值 加法计数器（CPWMS=0），当计数器计数到与模寄存 器数值相等时，TPMCNT翻转至0x0000 加/减计数器(CPWMS = 1)，当计数器计数到与模寄存器 数值相等时，计数器开始递减。
表7-5 模式、沿和电平选择
CPWMS MSnB: MSnA ELSnB: ELSnA
模式
功能
x 0
xx 00
00 01 10 11 00 01 10 11 10 x1
通道未使用外部管脚，可能是管脚作为TPM的外部时钟 输入或者是将管脚作为通用I/O使用。 输入捕捉 仅上升沿捕捉 仅下降沿捕捉 上升沿或下降沿都捕捉 仅软件比较，无管脚输出 比较匹配时，外部管脚翻转 比较匹配时，外部管脚清0 比较匹配时，外部管脚置1 脉宽有效期间高电平(比较匹配时， 外部管脚清0) 脉宽有效期间低电平(比较匹配时， 外部管脚置1) 脉宽有效期间高电平(比较匹配时， 外部管脚清0) 脉宽有效期间低电平(比较匹配时， 外部管脚置1)
触发：外部引脚发生有效电平跳变
响应： CHnF=1 ， 主计数器TPMCNT值→通道辅助寄存器TPMCnV
三、TPM模块的功能模式
（二）输出比较
功能：从外部引脚输出可编程脉冲
模式设定方式：
CPWMS 0 MSnB: MSnA 01 ELSnB: ELSnA 00 01 10 11 模式 输出比较 功能描述 仅软件比较，无管脚输出 比较匹配时，外部管脚翻转 比较匹配时，外部管脚清0 比较匹配时，外部管脚置1
飞思卡尔MCU时钟模块配置
飞思卡尔（FREESCALE）低功耗模式下微控制器时钟配置应用在微控制器的低功耗应用中，对时钟的设置是很重要的一个方面。
不同类型的微控制器在低功耗模式下对时钟的配置也各有不同。
飞思卡尔公司推出的增强型8位微控制器HCS08系列具有很强的低功耗性能。
其中，HCS08系列里的MC9S08QG8在同类产品的基础上对低功耗应用下的时钟又有了进一步的改进。
1 MC9S08QG8及其内部时钟模块介绍微控制器MC9S08QG8是飞思卡尔公司新推出的一款8位增强型微控制器。
它是小封装、低功耗的产品，但这并不意味着它是“低端”的产品；相反，它是一个高度集成的、功能丰富的、适用于各种应用的低价位单片机。
MC9S08QG8采用高性能、低功耗的HCS08内核，具有很高的集成度，还包括更长的电池寿命(即使工作电压低至1．8V，也能发挥最大效能)、业界领先的Flash技术以及创新的开发支持。
MC9S08QG8集成了背景调试系统(BDM)以及可进行实时总线捕捉的内置在线仿真(ICE)功能，具有单线的调试及仿真接口。
MC9S08QG8微控制器的运行模式有很多种，包括正常运行模式、等待模式、背景调试模式以及停止模式。
其中，与低功耗应用关系密切的停止模式又分为3个阶段：停止模式l——内部电路全部断电，以最大限度地节省电源；停止模式2——可选择部分断电，RAM内容保持；停止模式3——内部电路都可快速恢复运行，RAM、Flash内容保持。
MC9S08QG8内部时钟模块由4个子模块组成：锁频环、内部参考时钟、外部振荡器、时钟选择逻辑模块，如图l所示。
锁频环的输出频率为参考时钟频率的512倍，包括3个主要部分：参考频率选择、数字控制振荡器和用于比较这两个部分输出的滤波器。
锁频环是通过比较数字控制振荡器时钟与参考时钟的频率来工作的。
锁频环对一个参考时钟周期内的数字控制振荡器时钟脉冲边沿数进行计数，因此，对于512倍的倍频器，锁频环应该在参考时钟的每两个上升沿之间得到512个数字控制振荡器输出的上升沿。
飞思卡尔半导体 如何在M68HC08、HCS08和HCS12 微控制器上应用IIC模块 说明书
飞思卡尔半导体文件编号：AN3291 应用笔记第1版，03/2007Specifications and information herein are subject to change without notice. ©Freescale Semiconductor，Inc., 2007. All rights reserved.General Business Information如何在M68HC08、HCS08和HCS12微控制器上应用IIC模块作者： Stanislav Arendarik应用工程师捷克共和国，罗斯诺夫1 简介此应用笔记是如何在飞思卡尔的微控制器上应用IIC模块的一个示例。
IIC模块可以分别在主模式或从模式下使用。
在这种情况下，由于IIC 总线主要用于在微控制器（MCU）和IIC外设之间的通信，因此在主模式时与串行EEPROM进行通信。
IIC总线可以在两个微控制器（MCU）之间直接进行通信，然而SPI总线却更适用于这种应用。
此应用笔记总结了通用IIC总线状态和定义，并提供了如何与串行EEPROM进行通信的示例（24C16和24C512）。
您可以轻松地用另外一个IIC器件取代EEPROM，但是必须改变将其标识为从器件的IIC地址字节。
目录1 简介…………… . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . 12 IIC 总线摘要………….. . . . …. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.1 IIC总线术语.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.2 位传输. ………….. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 22.3 起始条件和停止条件(START and STOP Conditions)...... . 32.4 总线通信. . ……………………….. . . . . . . . . . . . . . . . . . . . 32.5 控制字节………………………. . . . . . . . . . . . . . . . . . . . .. . . 32.6 地址字节……….... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.7 应答………… . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . 42.8 读/写格式………………………………......…..…... . . . . . . .. 53 用于微控制器的IIC软件程序. ………. . . . . . . . . . . . . . . . . . . . . . . 53.1 IIC的初始化. … . . . …….. . . . . . . . . .. .. . . . .. .. .. . . . . . . . 63.2 写入功能. . . . . . . . . . . . . . . . . . . . . .. . . . . . .. . . . . . . . . . . 73.3 读取功能 .. . . . . . . . . . . . . . . . . . . . .. . .. . . . . .. . . . . . . . . 93.4 中断应用举例. . . . . . ……………. . . . . . . . . . . .. . . . . . . . . 133.4.1 MCU作为主机.. . . . . . . . . . . .. .. . . . . . . . . . . . . . . 133.4.2 MCU作为从机. . . . . . .. . . . . . . .. . . . . . .. . . . . . . 164 结论. . . ……... . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .. . . . . . . .. . . 17IIC总线摘要2 IIC 总线摘要IIC总线是基于主机和从机间线与（开漏）连接的双向、两线式总线。
飞思卡尔MC9S12XS128单片机各模块使用方法及寄存器配置
飞思卡尔MC9S12XS128单片机各模块使用方法及寄存器配置手把手教你写S12XS128程序--PWM模块介绍该教程以MC9S12XS128单片机为核心进行讲解，全面阐释该16位单片机资源。
本文为第一讲，开始介绍该MCU的PWM模块。
PWM 调制波有8个输出通道，每一个输出通道都可以独立的进行输出。
每一个输出通道都有一个精确的计数器（计算脉冲的个数），一个周期控制寄存器和两个可供选择的时钟源。
每一个P WM 输出通道都能调制出占空比从0—100% 变化的波形。
PWM 的主要特点有：1、它有8个独立的输出通道，并且通过编程可控制其输出波形的周期。
2、每一个输出通道都有一个精确的计数器。
3、每一个通道的P WM 输出使能都可以由编程来控制。
4、PWM 输出波形的翻转控制可以通过编程来实现。
5、周期和脉宽可以被双缓冲。
当通道关闭或PWM 计数器为0时，改变周期和脉宽才起作用。
6、8 字节或16 字节的通道协议。
7、有4个时钟源可供选择（A、SA、B、SB），他们提供了一个宽范围的时钟频率。
8、通过编程可以实现希望的时钟周期。
9、具有遇到紧急情况关闭程序的功能。
10、每一个通道都可以通过编程实现左对齐输出还是居中对齐输出。
1、PWM启动寄存器PWMEPWME 寄存器每一位如图1所示：复位默认值：0000 0000B图1 PWME 寄存器每一个PWM 的输出通道都有一个使能位P WMEx 。
它相当于一个开关，用来启动和关闭相应通道的PWM 波形输出。
当任意的P WMEx 位置1，则相关的P WM 输出通道就立刻可用。
用法：PWME7=1 --- 通道7 可对外输出波形PWME7=0 --- 通道7 不能对外输出波形注意：在通道使能后所输出的第一个波形可能是不规则的。
当输出通道工作在串联模式时（PWMCTL 寄存器中的CONxx置1），那么）使能相应的16位PWM 输出通道是由PWMEx 的高位控制的，例如：设置PWMCTL_CON01 = 1,通道0、1级联，形成一个16位PWM 通道，由通道 1 的使能位控制PWM 的输出。
飞思卡尔单片机电子钟课程设计方案
目录第一章系统概要 (2)1.1 系统背景 (2)1.2 系统功能 (2)第二章系统硬件设计 (2)2.1 系统原理图 (2)2.2 单片机（MCU）模块 (3)2.2.1 MC9S08AW60单片机性能概述 (3)2.2.2 内部结构简图 (4)2.3 串行通信模块 (5)2.3.1 MAX232引脚图 (5)2.3.2 串行通信的电路原理 (6)2.4 液晶显示模块 (7)第三章系统软件设计 (8)3.1 MCU方（C）程序...................................... 错误!未定义书签。
3.1.1串行通信子程序................................. 错误!未定义书签。
3.1.2 LCD子程序..................................... 错误!未定义书签。
第四章系统测试.. (8)第五章总结展望 (23)5.1 总结 (23)5.2 展望 (23)参考文献 (23)第一章系统概要1.1 系统背景数字时钟，当我们听到这几个字时，第一反应就是我们所说的数字，不错数字钟就是以数字显示取代模拟表盘的钟表，在显示上它用数字反应出此时的时间，相比模拟钟能给人一种一目了然的感觉，不仅如此它还能同时显示时、分、秒。
而且能对时、分、秒准确校时，这是普通钟所不及的。
由于单片机集成度高、功能强、可靠性高、体积小、功耗地、使用方便、价格低廉等一系列优点，目前已经渗入到人们工作和生活的方方面面，几乎“无处不在，无所不为”。
单片机的应用领域已从面向工业控制、通讯、交通、智能仪表等迅速发展到家用消费产品、办公自动化、汽车电子、PC机外围以及网络通讯等广大领域。
1.2 系统功能在实验箱上有一个启动键，当按下启动键给以一个低电平，电子时钟从当前设定值开始走时。
按秒刷新，要求在LCD屏上显示。
若按启动键给以高电平，则时间暂停，再按，时间继续按秒刷新。
飞思卡尔单片机PLL时钟总线模块
要设定PWM模块首先要确定片内总线时钟，MC9S12XS系列单片机增加了时钟产生器模块，锁定内部频率更高的压控振荡器VCO频率，作为系统时钟，单片机的内部时钟可达80MHz，片内总线时钟可达40MHz。
先给出一段例程Code:1.REFDV=0x07; //REFDIV=72.SYNR=0x53; //SYNDIV=193.while(LOCK!=1); //等待VCO稳定4.POSTDIV=0; //POSTDIV=0,VCO时钟=80MHz5.CLKSEL_PLLSEL=1; //选择由Fpll产生总线时钟，Fbus=Fpll/2=40MHz注：LOCK之前省去了寄存器名，这里是屏蔽不给发出来。
下面开始简单分析一下寄存器（1）时钟分频寄存器（CRG Reference Divider Register ，REFDV）REFDV寄存器的高两位REFFRQ[ 1：0 ]表示参考时钟范围REFDV的低六位为分频因子REFDV的值，有效值的范围为0~63.（2）时钟合成寄存器（CRG Synthesizer Register , SYNR）SYNR高两位控制压控振动器VCO的增益SYNR寄存器的低六位可写入0~63.可将锁相环时钟倍频1~64倍。
锁相环产生的时钟频率可由下面的公式得到PLLCLK=2 * OSCCLK * ( SYNR+1 ) / ( REFDV+1 )（3）锁相环寄存器（PLL Control Register , PLLCTL）CME：时钟监控允许位。
PLLON：锁相环电路允许位。
FM [ 1 : 0 ]：选择附加调频滤波器以降低VCO噪声，默认值表示不使用该滤波器，可写入01,10或11，表示参考频率相对于VCO偏高1%,2%,4%时自动调整。
FSTWKP：时钟快速唤醒CPU功能位。
PRE：CPU伪停止状态时，实时中断（RT1）允许位。
PCE：CPU虚拟停止时，看门狗（COP）允许位。
飞思卡尔系统时钟设计
飞思卡尔系统时钟设计Freescale SemiconductorApplication NoteThis application note describes basic jitter terminology and the aspects pertaining to the SYSCLK clock design requirements, when designing with the PowerQUICC? III processors.1Introduction to JitterJitter is a time deviation of a signal transition from its ideal position in time. It can be caused by many different factors, including PLL loop noise, thermal noise, cross talk, power supply ripply. It can be characterized by using multiple terminology.The jitters—cycle-to-cycle (short-term jitter), andperiod(long-term jitter)—are the most common and familiar specifications.This application note provides a brief overview of basic terminology and is not intended to provide a comprehensive overview of jitter.Document Number:AN4056Rev.1, 02/2010Contents1.Introduction to Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1. C ycle-to-Cycle Jitter. . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2. P eriod Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3. T ime Interval Error Jitter . . . . . . . . . . . . . . . . . . . . . 31.4. R andom Versus Deterministic Jitter . . . . . . . . . . . . . 42.SYSCLK Specification on PowerQUICC III Processors63.Phase Jitter on PowerQUICC III Processors. . . . . . . . 74.References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85.Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Understanding SYSCLK JitterIntroduction to Jitter1.1Cycle-to-Cycle JitterCycle-to-cycle jitter is defined as the maximum difference between any two adjacent clock periods. It is is always specified as an absolute magnitude and not by positive or negative value. Figure 1 shows the cycle-to-cycle jitter.Figure 1. Cycle-to-Cycle JitterCycle-to-cycle jitter is important for specifying the performance of PLL however, it does not establish a relationship between non-adjacent clocks. Specifically, it does not address frequency drift over time.For example, the clock shown in Figure 2 meets 100ps of cycle-to-cycle jitter specifications. However, over the time, frequency of the clock has drifted significantly.Figure 2. Cycle-to-Cycle Jitter with Frequency DriftT 1T 2T 3| T 2 – T 1 | = 100 ps, | T 3 – T 2 | = 100 ps, ... , | T n – T (n-1) | = 100 psP2P3P1| T 2 – T 1 | = 100 ps, | T 3 – T 2 |= 100ps, | T n – T (n-1) | = 100 ps...T 110.0 nsT 29.9 nsT 39.8 nsT 49.7 nsT 90T 911.1ns 1.0nsP1P3P4P90P91Introduction to Jitter1.2Period JitterPeriod jitter is defined as the maximum deviation of any clock period from its mean clock period . It compares the length of each period to the average period of an ideal clock at a long-term average frequency of the signal.Period jitter is typically specified over a set number of clock cycles. Jedec Specification, JESD65B, suggests, measuring jitter over 10,000cycles when the clock is in a range of 10 to 100MHz. However, if clock cycles are not specified, it is recommended to measure period jitter over 100,000cycles to better represent jitter over an “infinite” time span.For example, the clock shown in Figure 3 can be specified as a comparison of n periods to the ideal period. In practice, it is difficult to quantify an ideal period, thus average period is used. Therefore, compare n periods to the reference “average period.”Figure 3. Period JitterThis describes jitter over time, and ensures that the clock does not drift.1.3Time Interval Error JitterTime Interval Error (TIE) is the difference between observed clock edge time and expected clock edge time for each clock edge present. It is measured by subtracting the actual clock edge from the ideal clock edge. It is important to note that TIE refers to clock edges, while period jitter refers to clock period.P1P3PnT 1T 2T 3T n-1T nPn-1Ideal ClockClockIntroduction to JitterFigure 4 shows an example of actual clock compared to an ideal clock and is derived per cycle jitter of an actual clock.Figure 4. TIE as Related to Cycle-to-Cycle and Period JitterIn Figure 4, the period of an ideal clock is assumed as 10ns and jitter is always +/–1ns deviated from an ideal clock. From first to second cycle, short-term (cycle-to-cycle) jitter is –1ns. This equates to a period jitter of T m –1ns (where T m is the ideal or mean clock period).From 2nd to 3rd cycle, short-term jitter is 1ns (this is a measurement of change in two adjacent clock cycles of non-ideal clock). Rounding to the nearest ns, the equation for period jitter over the course of two cycles becomes T m –[(T 1+T 2)/2]=T m –1. TIE compares the actual signal to ideal clock, and thus is equal to –1 for the 2nd cycle.TIE is related to both cycle-to-cycle and period jitter. In fact, cycle-to-cycle jitter and period jitter can be calculated from TIE.1.4Random Versus Deterministic JitterJitter (total jitter) is typically composed of a random jitter (RJ) component and a deterministic jitter (DJ) component. Deterministic jitter is caused by impedance mismatch, power supply ripple, crosstalk, ground bounce, intersymbol interferenc, ringing, and reference clock feed through. It is an artifact ofboard design and is typically controllable. DJ can be reduced by proper board design or IC selection.The remaining components of jitter are random. Random jitter is caused by factors like thermaloscillations, thermal noise that result in levels of jitter and cannot be predicted on a cycle-by-cycle basis. It is not bounded. The longer you observe, wider the period variation appears; therefore, RJ is bestdescribed as a Gaussian distribution. The tails of a Guassian distribution extends indefinitely on either side10 ns9 ns 10 ns 11 ns 10 ns10 nsCycle 1Cycle 2Cycle 3Cycle 4Ideal ClockClockCycle-to-CyclePeriod TIE–1001–1–120–1–221–01Cycle 5Introduction to Jitterof the mean. This implies that it is impossible to specify a peak-to-peak jitter range that bounds RJ 100% of the time. Instead, bound a range that contains the jitter for x percent ofthe time. Typically, long-haul optical systems specify jitter in terms of RMS over N cycles, or peak-to-peak cycle-to-cycle jitter over N cycles (N can be 200,000–300,000 cycles). SONET is specified at 14×RMS, which equates to 10–12 bit error rate (BER). Figure 5 shows the Gaussian distribution.Figure 5. Gaussian DistributionFor example, one standard deviation is a point from the mean that contains 68.26% of all measurements (standard deviation is same as RMS ).Table 1 shows time to outlier clock for various standard deviation, considering a 100-MHz clock.Table 1. Standard Deviation and BER for 100-MHz ClockStandard Deviation (+/–)% of Total Population Time to Outlier for 100-MHz ClockBit Error Rate168.270000000000000%32ns0.16295.450000000000000%220ns 2.28×10–2399.730000000000000% 3.7μs 1.35 ×10–3499.993666000000000%157μs 0.32×10–4599.999942670000000%17ms 2.87×0–7699.999999802700000% 5.1sec 0.98×10–9799.999999999744000%65min 1.28 × 10–12899.999999999987600%~22hours0.62 ×10–15P = 68 %P = 95 %x σ+1σ+2σSYSCLK Specification on PowerQUICC III ProcessorsTotal jitter (TJ) is the sum effect of RJ and DJ over a number of cycles.Since RJ is a Gaussian distribution, and there are no bounds, the calculation is not simply an addition of RJ and DJ. Total jitter can be specified as follows:TJ = (σ x RJ) + DJEqn.1Figure 6 shows probability outside of peak-to-peak approximation.Figure 6. Probability Outside of Peak-to-Peak Approximation In order to bound TIE over a number of cycles, statistically meaningful number of clock cycles arerequired (for example, 1012 or an approximation of it). Assuming that all RJ on a board is Gaussian, and there is a finite probability that any independent sample would be outside an approximated peak-to-peak value, a peak-to-peak total jitter can be extrapolated. Probability decreases as the number of standard deviations used to aproximate the peak-to-peak value increases, and in the end, a total jitter calculation becomes a statistical calculation.For this example of a BER equal to 1012 cycles, TJ =(14.262×RJ) + DJ. It is interesting to note that RJ plays a much more significant role in the total jitter than DJ; in this case 14.262 times more.2SYSCLK Specification on PowerQUICC III ProcessorsFor example, on MPC8548 microcontroller, SYSCLK jitter is specified as 150ps of total jitter. This is a TIE jitter specification, from which cycle-to-cycle and period jitter requirements can be calculated. It is recommended to measure TIE over at least 100,000 cycles and the thumb rule is to measure over 1012 cycles. However, as per Table 1, this measurement can take some time.On some oscilloscopes, it may be easier to measure TJ. TIE over n cycles is the equivalent measurement to TJ, as σ is proportinal to the number of cycles.579111315Peak-to-Peak Approximation ( )σ1.E+00P r o b a b i l i t y1.E-021.E-041.E-061.E-081.E-101.E-121.E-14Phase Jitter on PowerQUICC III ProcessorsTable 2 provides the system clock (SYSCLK) AC timing specifications.Since the SYSCLK input is not used for long-haul transmission of large data packets to a device running on a separate clock domain, a measurement like BER is not really applicable. SYSCLK impacts internal timing budgets, and the ability of internal PLL to track the clock. The PC B designer’s main concern is to ensure that jitter on SYSCLK is such that it is outside the bandwidth in which the PowerQUICC III PLL can amplify it.In Table 2, note 5 specifies the internal PLL’s closed loop jitter. This specification further narrows down the jitter requirement for SYSCLK and specifies 500kHz to 10MHz as the range at which the gain curve of the internal PLL is positive and has a peak (this means jitter can be amplified). At lower frequencies, PLL tracks precisely and at higher frequencies PLL response is damped and jitter is attenuated. Therefore, spreadspectrum clock inputs (~30kHz) work as SYSCLK inputs.3Phase Jitter on PowerQUICC III ProcessorsPeriod jitter and phase jitter are often confused. Phase jitter, as specified on PowerQUICC III products, is a deviation in edge location with respect to mean edge location.Table 3 lists the AC requirements for the PCI Express SerDes clocks.Table 2. SYSCLK Timing Specifications(At recommended operating conditions with OVDD = 3.3 V ± 165 mV .)Parameter/Condition Symbol Min Typical Max.Unit Notes SYSCLK frequency f SYSCLK 16—133MHz 1, 6SYSCLK cycle time t SYSCLK 7.5—60ns 6SYSCLK rise and fall time t KH , TKL 0.6 1.0 1.2ns 2SYSCLK duty cycle t KHK /t SYSCLK40—60%3SYSCLK jitter———+150ps4. 5Notes:1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum operating frequencies.2. Rise and fall times for SYSCLK are measured at 0.6 and 2.7 V .3. Timing is guaranteed by design and characterization.4. This represents the total input jitter—short-term and long-term—and is guaranteed by design.5. The SYSCLK driver’s c losed loop jitter bandwidth should be <500 KHz at –20 dB. The bandwidth must be set low to allow cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter.6. This parameter has been adjusted slower according to the workaround for device erratum GEN 13.Table Symbol Parameter DescriptonMin Typ Max Unit Notes t REF REFCLK cycle time—10—ns 1t REFCJ REFCLK cycle-to-cycle jitter. Difference in the period of any two adjacent REFCLK cycles.——100ps —t REFPJPhase jitter, Deviation in edge location with respect to mean edge location.–50—50ps—ReferencesSo, phase jitter as specified is a TIE or TJ measurement over 100,000 cycles.4References/doc/a020240f763231126edb11f0.ht ml /tm/Library/WhitePapers/PDF/WP_TechBrief_Dif_Ref_Jit.pdf /doc/a020240f763231126edb11f0.ht ml /arpdf/AppNotes/3hfan402.pdf5Revision HistoryTable4 provides a revision history for this application note.Table4. Document Revision HistoryRev.Date Substantive Change(s)Number102/19/2010Updated Figure3 in Section1.2, “Period Jitter.”Removed Equation from the Section1.2, “Period Jitter.”Revised Figure4in Section1.3, “Time Interval Error Jitter.”Added Equation1 in Section1.4, “Random Versus Deterministic Jitter” and updated contentaccordingly.Added Figure6 Probability Outside of Peak-to-Peak Approximation Section1.4, “Random VersusDeterministic Jitter.”Updated Section2, “SYSCLK Specification on PowerQUICC III Processors.”Updated Section3, “Phase Jitter on PowerQUICC III Processors,” regarding phase jitter as TIEspecification.001/20/2010Initial Release.Revision History THIS PAGE INTENTIONALLY LEFT BLANKDocument Number:AN4056 Rev.102/2010Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. 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Silicon Laboratories AN663 精确32位MCU家族时钟选项说明书
Rev. 0.1 2/12Copyright © 2012 by Silicon LaboratoriesAN6631. IntroductionThe 32-bit Precision32™ MCU family features a highly configurable clock structure. The advanced high-performance bus (AHB) and advanced peripheral bus (APB) have many options available for clocking. In addition,firmware can disable most peripheral clocks to save power.The clock to the module must be enabled before firmware can modify the registers. The first initialization step in all peripheral initialization routines should enable the clock to the module.The corresponding Precision32 family reference manual contains detailed descriptive and usage information on each of the clock sources mentioned in this document.2. Clock SourcesThe AHB drives the core and memory on ARM ® Cortex™-M3 devices. The APB drives the peripherals and peripheral registers.The AHB on the Precision32 devices has several options for clock sources: Low Power Oscillator, Low Frequency Oscillator, RTC Oscillator, External Oscillator, PLL Oscillator, and USB Oscillator. The APB clock is either equal to AHB or a divide by 2 version of it, so it is always synchronized with the AHB clock.Table 1 describes the oscillators that can serve as clock sources for the AHB bus. Figure 1 shows an example clock control block diagram.Table 1. AHB Clock Source SummaryOscillator Name Short Name Module Frequency Use CaseLow Power Oscillator LPOSCnLPOSCn20MHz or 2.5MHzHigh frequency and lower power consumption required.Low Frequency Oscillator LFOSCn RTCn 16.4kHzLow power, slow frequency required; no room for exter-nal RTC watch crystal.RTC OscillatorRTCnOSC RTCn 32.768kHzLow power, slow, accurate frequency required; room for external RTC watch crystal.External Oscillator EXTOSCn EXTOSCnCrystal: 10kHz to 25MHz CMOS: 10kHz to 50MHz RC or C: up to 1.6MHzVery accurate frequency required; room for external components.PLL Oscillator PLLnOSC PLLn 23MHz to maximum device frequency Flexible, fast, and accuratefrequency required.USB OscillatorUSBnOSCUSBn48MHzVery accurate fast fre-quency required; no flexibil-ity needed.AN663AN6632.1. Low Power Oscillator (LPOSCn)The low power oscillator is the default oscillator after reset. The default, factory-calibrated frequency of this oscillator is 20MHz, but a divide by 8 version is also available as an AHB clock source.This oscillator starts very quickly and automatically turns on and off as needed. This oscillator consumes less power than other oscillators, but may not be as accurate over voltage and temperature.There are no configuration bits for this oscillator. Figure2 shows the block diagram for the low power oscillator.2.2. Low Frequency Oscillator (LFOSCn)The low frequency oscillator is part of the RTC module and can be selected as an RTC timer clock source in addition to the AHB clock source. The factory-calibrated output frequency of this oscillator is 16.4kHz.This oscillator consumes less power than other oscillators, but will not be as accurate as the external RTC watch crystal. Figure3 shows the block diagram for the low frequency and RTC oscillators.AN6632.3. RTC Oscillator (RTCnOSC)The RTC oscillator is part of the RTC module and is derived from the 32.768kHz watch crystal or CMOS oscillator. This oscillator can be a source for the AHB or selected as the RTC timer clock source.The load capacitance for the watch crystal is internal and adjustable, so no external components other than the crystal are required. The crystal should be connected directly across the RTC1 and RTC2 pins on the device, and these pins should be configured for analog input mode.The RTC oscillator is more accurate than the low frequency oscillator, allowing for precision timekeeping with the 32-bit RTC timer.Figure3 shows the block diagram for the low frequency and RTC oscillators.AN6632.4. External Oscillator (EXTOSCn)The AHB clock may be derived from the external oscillator module. The external oscillator supports four different external oscillators: crystal, CMOS, RC, and C.Figure4 depicts a block diagram for the external oscillator module.AN6632.4.1. Crystal ModeWhen operating in crystal mode, the external oscillator module supports crystals ranging from 10kHz to 25MHz.The module requires a 10M Ω resistor across the crystal pins and two loading capacitors between the crystal pins and ground. Both of the crystal pins must be configured for analog input mode. Figure 5 shows the external crystal oscillator hardware configuration.The capacitors provide the load capacitance required by the crystal for correct oscillation. These capacitors are “in series” as seen by the crystal and “in parallel” with the stray capacitance of the XTAL1 and XTAL2 pins.Note:The recommended load capacitance depends upon the crystal and the manufacturer. Refer to the crystal data sheetwhen completing these calculations.Equation 1 describes the equation for determining the load capacitance for the two capacitors. The C A and C B values are the capacitors connected to the crystal leads. The C S value is the total stray capacitance of the PCB,which is typically between 2pF and 5pF per pin for a typical layout where the crystal is as close as possible to the pins.Equation 1.Crystal Load CapacitorsIf C A and C B are the same (C), the resulting equation is shown in Equation 2.Equation 2.Simplified Crystal Load CapacitorsFor example, using Equation 2 with a 32.768kHz tuning-fork crystal with a recommended load capacitance of 12.5pF placed as close to the pins as possible (3pF per pin) results in crystal load capacitors of 13pF each.Crystal oscillator circuits are quite sensitive to PCB layout. The crystal should be placed as close as possible to the XTAL pins on the device. The traces should be as short as possible and shielded with ground plane from any other traces that could introduce noise or interference.C L C A C B⨯C A C B+---------------------C S +=C L C2---C S+=AN6632.4.2. CMOS ModeWhen operating in CMOS mode, the external oscillator module supports CMOS oscillators with output frequencies ranging from 10kHz to 50MHz. The external CMOS clock should be connected directly to the XTAL2 pin configured in digital input mode. The XTAL1 pin should be left floating.The CMOS oscillator mode is available with a divide by 2 stage, ensuring the clock has a 50% duty cycle.2.4.3. RC ModeThe external oscillator module supports output frequencies up to 1.6MHz when operating in RC mode. The RC components should be connected to XTAL2 configured for analog mode, while XTAL1 should be left floating.Figure 6 shows the external RC oscillator hardware configuration.The capacitor used in the RC network should have a value no greater than 100pF, and the resistor should be no smaller than 10k Ω. For very small capacitors, the parasitic capacitance in the PCB layout may dominate the total capacitance. The oscillation frequency can be determined by Equation 3, where f is the frequency in MHz, R is the pull-up resistor value in k Ω., and C is the capacitor value in the XTAL2 pin in pF.Equation 3.RC Oscillation FrequencyThe RC Oscillator mode is only available with a divide by 2 stage, which ensures that the clock derived from the external oscillator has a duty cycle of 50%. The equation for the EXTOSCn output frequency is shown in Equation 4.Equation 4.EXTOSCn Output Frequency in RC Modef 1.23103⨯R C⨯--------------------------=f OUT f 2-- 1.23103⨯2R ⨯C⨯--------------------------==AN6632.4.4. C ModeWhen operating in C mode, the external oscillator module supports frequencies up to 1.6MHz. The capacitor should connect directly to XTAL2 configured for analog mode. XTAL1 should be left floating. Figure 7 shows the external C oscillator hardware configuration.To determine the required module settings, select the capacitor to be used and find the frequency of oscillation according to Equation 5, where f is the frequency of oscillation in MHz, C is the capacitor value in pF, V DD is the device power supply in Volts, and KF is the K Factor.Equation 5.C Oscillation FrequencyThe C oscillator mode is only available with a divide by 2 stage, which ensures that the clock derived from the external oscillator has a duty cycle of 50%. The equation for the EXTOSCn output frequency is shown in Equation 6.Equation 6.EXTOSCn Output Frequency in C Modef KFC V DD⨯---------------------=f OUT f 2--KF2C ⨯V DD⨯------------------------------==AN6632.5. PLL Oscillator (PLLnOSC)The PLLn module available on SiM3xxxx devices is a digital PLL capable of generating output frequencies between 23MHz and the maximum device operating frequency. The PLL has configurable output ranges and frequencies, multiple reference clock inputs, locking on either the falling or rising edge of the reference, DCO frequency LSB dithering to provide finer average output frequencies, spectrum spreading to reduce generated system noise, low jitter, and fast lock times.The PLLn module also supports three output modes: free-running DCO, frequency-locked, and phase-locked. The PLL can lock on a reference frequency and then switch to free-running DCO mode to save power.Figure8 displays the PLLn module block diagram.Figure8.PLL Module Block DiagramAN6632.6. USB Oscillator (USBnOSC)The USB oscillator is part of the USBn module and operates at a factory-calibrated 48MHz. When connected to the USB bus, the clock recovery mechanism can constantly adjust the oscillator frequency relative to the full-speed frame reference, creating a very accurate clock source. This oscillator is within the USB specification across voltage and temperature, allowing the application system to be hardware USB certified without an external oscillator. This oscillator can be used as the AHB clock source even if the USB peripheral is not used.Figure9 displays the USBn module block diagram.AN663 3. Clocks and the PeripheralsThe APB clock drives most peripherals and their registers. The exceptions to this are lower power peripherals that run from the RTC Oscillator or the Low Frequency Oscillator directly.For peripherals that run from the APB clock, disabling the clock to the module in the device clock control module (CLKCTRL) will disable the clock to both the module and the module’s registers. For peripherals that run from another clock source, disabling the clock to the module will disable the clock to the module’s registers only and the module will continue to run.4. Reset BehaviorOn SiM3xxxx devices, the low power oscillator (LPOSCn) is the default oscillator after a reset. In addition, the clocks to most peripherals are disabled to save power. The clock to the module must be enabled before firmware can modify the registers. The first initialization step in all peripheral initialization routines should enable the clock to the module. Silicon Laboratories Inc.400 West Cesar ChavezAustin, TX 78701USASimplicity StudioOne-click access to MCU andwireless tools, documentation,software, source code libraries &more. Available for Windows,Mac and Linux!IoT Portfolio/IoT SW/HW /simplicity Quality /quality Support and CommunityDisclaimerSilicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Silicon Labs shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any Life Support System without the specific written consent of Silicon Labs. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. Silicon Labs products are not designed or authorized for military applications. Silicon Labs products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.Trademark InformationSilicon Laboratories Inc.® , Silicon Laboratories®, Silicon Labs®, SiLabs® and the Silicon Labs logo®, Bluegiga®, Bluegiga Logo®, Clockbuilder®, CMEMS®, DSPLL®, EFM®, EFM32®, EFR, Ember®, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZRadio®, EZRadioPRO®, Gecko®, ISOmodem®, Precision32®, ProSLIC®, Simplicity Studio®, SiPHY®, Telegesis, the Telegesis Logo®, USBXpress® and others are trademarks or registered trademarks of Silicon Labs. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited. All other products or brand names mentioned herein are trademarks of their respective holders.。
飞思卡尔单片机电子钟课程设计
飞思卡尔单片机电子钟课程设计目录第一章系统概要 (3)1.1 系统背景 (3)1.2 系统功能 (3)第二章系统硬件设计 (3)2.1 系统原理图 (3)2.2 单片机（MCU）模块 (4)2.2.1 MC9S08AW60单片机性能概述. 42.2.2 内部结构简图 (5)2.3 串行通信模块 (6)2.3.1 MAX232引脚图 (6)2.3.2 串行通信的电路原理 (7)2.4 液晶显示模块 (9)第三章系统软件设计 (10)3.1 MCU方（C）程序. 错误!未定义书签。
3.1.1串行通信子程序错误!未定义书签。
3.1.2 LCD子程序错误!未定义书签。
第四章系统测试 (10)第五章总结展望 (25)5.1 总结 (25)5.2 展望 (25)参考文献 (25)第一章系统概要1.1 系统背景数字时钟，当我们听到这几个字时，第一反应就是我们所说的数字，不错数字钟就是以数字显示取代模拟表盘的钟表，在显示上它用数字反应出此时的时间，相比模拟钟能给人一种一目了然的感觉，不仅如此它还能同时显示时、分、秒。
而且能对时、分、秒准确校时，这是普通钟所不及的。
由于单片机集成度高、功能强、可靠性高、体积小、功耗地、使用方便、价格低廉等一系列优点，目前已经渗入到人们工作和生活的方方面面，几乎“无处不在，无所不为”。
单片机的应用领域已从面向工业控制、通讯、交通、智能仪表等迅速发展到家用消费产品、办公自动化、汽车电子、PC机外围以及网络通讯等广大领域。
1.2 系统功能在实验箱上有一个启动键，当按下启动键给以一个低电平，电子时钟从当前设定值开始走时。
按秒刷新，要求在LCD屏上显示。
若按启动键给以高电平，则时间暂停，再按，时间继续按秒刷新。
第二章系统硬件设计2.1 系统原理图该系统由AW60最小系统电路为主要结构，利用串口进行数据的控制与采集。
首先将开关接在AW60上的PORT_D口上，用于控制数字时钟系统的开关。
然后将LCD的数据线7-14引脚（D0-D7）分别与MCU的PTA0-PTA7连接，LCD的控制线RS、R/W、E(4、5、6引脚)分别于MCU的PTC4、PTC6、PTF6连接，用于输出时间。
MCU的时钟校准
校准时钟可以使用HP53132A仪表。
MCU的时钟校准在以下情况需进行MCU时钟的校准：1．在OMC发现每小时超出一个滑帧时。
2．当系统要求校准时。
（告警消息要求校准时）注意：MCU时钟的校准需由受过此方面培训的工程师操作。
gclk_cal_mode命令只能在BTS中使用。
进行MCU时钟的校准时要在没有呼叫发生时进行。
在上电后OCXO要有30分钟的预热时间，以使其达到正常工作温度。
仪器：1。
一台IBM兼容的PC机。
2．9转9的串口线。
3．铯或铷时钟源（1M到10M输出）。
4．能使用外部时钟源的频率计，例如：HP5385A或其它同功能设备。
准备工作：按以下步骤进行准备工作：1．用9转9串口线连接PC与MCU的TTY。
2．在PC上启动终端仿真程序。
3．将10M频率发生仪输出作为频率计的外部参考时钟源。
4．设置频率计的frequency gate time为10秒，显示数值的有效位为10位。
5．用测试线将MCU的时钟输出信号接至频率计的输入口。
MCU时钟输出口：第一针：地第三针：8KHZ输出。
步骤：1。
在MMI_RAM 1015提示符下键入以下命令：gclk_cal_mode此命令通知MCU的软件和同步功能将要进行时钟校准。
（在备用MCU处于激活状态时，此命令对主用MCU无效）此命令执行后将出现以下提示及确认信息：Site <local site number> starting GCLK CALIBRATION MODE. If this is a single MCU site, the site will be down until calibration is complete.Are you sure (y=yes, n=no)? Y如输入‘y’以外的键，此命令将无效。
如输入‘y’，MCU将进入频率校准模式。
2．系统将出现以下提示：Frequency Counter Connected, Enter y when ready, or a to abort test y如输入‘y’以外的键，此命令将无效，MCU将进入退出频率校准模式。
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• 8个独立的定时器通
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Freescale
HCS12 微控制器 MC9S12DP256
2005年8月
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定时器结构
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ECT 模块结构
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在PRM文件中，加入 VECTOR ADDRESS 0xFFDE Int_TimerOverFlow
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