OrCAD PSpice 建模实例教程

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OrCAD 中文入门教程——附件(三极管的Pspice模型参数和PSpice特征函数)

附件A、三极管的Pspice模型参数.Model <model name> NPN(PNP、LPNP) [model parameters]第 1 页共9页第 2 页共9页附件B、PSpice Goal Function第 3 页共9页附件CModeling voltage-controlled and temperature-dependent resistorsAnalog Behavioral Modeling (ABM) can be used to model a nonlinear resistor through use of Ohm抯 law and tables and expressions which describe resistance. Here are some examples.Voltage-controlled resistorIf a Resistance vs. Voltage curve is available, a look-up table can be used in the ABM expression. This table contains (Voltage, Resistance) pairs picked from points on the curve. The voltage input is nonlinearly mapped from the voltage values in the table to the resistance values. Linear interpolation is used between table values.Let抯 say that points picked from a Resistance vs. Voltage curve are:Voltage ResistanceThe ABM expression for this is shown in Figure 1.第 4 页共9页Figure 1 - Voltage controlled resistor using look-up tableTemperature-dependent resistorA temperature-dependent resistor (or thermistor) can be modeled with a look-up table, or an expression can be used to describe how the resistance varies with temperature. The denominator in the expression in Figure 2 is used to describe common thermistors. The TEMP variable in the expression is the simulation temperature, in Celsius. This is then converted to Kelvin by adding 273.15. This step is necessary to avoid a divide by zero problem in the denominator, when T=0 C.NOTE: TEMP can only be used in ABM expressions (E, G devices).Figure 3 shows the results of a DC sweep of temperature from -40 to 60 C. The y-axis shows the resistance or V(I1:-)/1A.Figure 2 - Temperature controlled resistor第 5 页共9页Figure 3 - PSpice plot of Resistance vs. Temperature (current=1A)Variable Q RLC networkIn most circuits the value of a resistor is fixed during a simulation. While the value can be made to change for a set of simulations by using a Parametric Sweep to move through a fixed sequence of values, a voltage-controlled resistor can be made to change dynamically during a simulation. This is illustrated by the circuit shown in Figure 5, which employs a voltage-controlled resistor.第 6 页共9页Figure 4 - Parameter sweep of control voltageThis circuit employs an external reference component that is sensed. The output impedance equals the value of the control voltage times the reference. Here, we will use Rref, a 50 ohm resistor as our reference. As a result, the output impedance is seen by the circuit as a floating resistor equal to the value of V(Control) times the resistance value of Rref. In our circuit, the control voltage value is stepped from 0.5 volt to 2 volts in 0.5 volt steps, therefore, the resistance between nodes 3 and 0 varies from 25 ohms to 100 ohms in 25 ohm-steps.第7 页共9页Figure 5 - Variable Q RLC circuitA transient analysis of this circuit using a 0.5 ms wide pulse will show how the ringing differs as the Q is varied.Using Probe, we can observe how the ringing varies as the resistance changes. Figure 6 shows the input pulse and the voltage across the capacitor C1. Comparing the four output waveforms, we can see the most pronounced ringing occurs when the resistor has the lowest value and the Q is greatest. Any signal source can be used to drive the voltage-controlled resistance. If we had used a sinusoidal control source instead of a staircase, the resistance would have varied dynamically during the simulation.第8 页共9页Figure 6 - Output waveforms of variable Q RLC circuit第9 页共9页。

orcad仿真教程实例 -回复

orcad仿真教程实例-回复“orcad仿真教程实例”：Orcad是一种常用的电子设计自动化（EDA）工具，被广泛应用于电子电路设计领域。

它提供了丰富的仿真和分析功能，可以帮助工程师们对电路进行准确的仿真和优化。

在本篇文章中，我们将一步一步地介绍如何在Orcad中进行仿真，并以一个具体的电路设计实例进行说明。

第一步：创建工程首先，在Orcad软件中创建一个新的工程。

在菜单栏中选择“File”，然后点击“New Project”来新建一个工程。

选择一个合适的目录，为工程命名，并选择“Create project”选项。

第二步：添加原理图在新建的工程中，我们需要添加原理图。

在左侧面板中，可以看到一个“Hierarchy”选项。

右击该选项，选择“Add New Sheet”，然后为原理图命名。

为了简化，我们假设我们要设计一个简单的LED闪烁电路，我们将原理图命名为“LED_blink”。

第三步：绘制原理图打开新创建的原理图，在Orcad中，可以通过拖拽组件来绘制电路图。

在绘制LED闪烁电路的原理图时，我们需要添加以下组件：一个555定时器芯片、几个电阻、一个电容和一个LED。

将它们添加到原理图中适当的位置。

第四步：设置参数一旦将组件添加到原理图中，我们需要设置每一个组件的参数。

以555定时器芯片为例，右击芯片并选择“Edit Properties”。

在弹出的对话框中，可以设置芯片的型号、电源电压和其他参数。

对其他组件也进行类似的操作。

第五步：连接电路在原理图中连接每个组件。

在Orcad中，可以使用“Net”工具来绘制线路。

点击工具栏中的“Net”按钮，然后点击一个组件的引脚，再点击另一个引脚来连接它们。

以LED为例，将其正极连接到555定时器芯片的输出引脚，负极连接到地。

第六步：设置仿真配置在完成电路连接后，需要设置仿真的配置参数。

在菜单栏中选择“PSpice”，然后点击“Edit Simulation Profile”。

如何在ORCAD中自建仿真模型

如何在ORCAD中自建仿真模型(由lib文件生成olb文件并加入到库中)当需要对一个完全陌生的电子或光纤元器件建立其电路模型时，有时pspice自带的元件库可能完全派不上用场，特别是在对非线性有源器件进行模拟分析时，使用pspice library中的基本模型如vcvs，vccs，ccvs，cccs等也许根本无法建立达到使用要求的特殊器件模型，或者建立不了足够准确的模型。

pspice在设计之初就是完全靠数学方程的建立和求解来解决电路模拟问题的，也就是说原本只要有数学解析表达式存在，就一定能够建立起任何需要的电路模型。

随着产品的商用，功能越来越多，元件库越来越大。

图形界面代替了原本纯文本代码描述的电路结构。

这种变革在为人们带来使用上的方便的同时，却也让后来的使用者无法从该软件的本质核心看待。

因为人们习惯于调用设计者封装好的大量元器件模型和高级函数来进行运算分析，却疏于了解这些被调用的对象在设计之初是怎样形成的，问题是当所有可以调用的对象都无法满足用户的需要时，用户该怎样自己动手建立可用的准确的模型呢？这绝对成为困扰普通用户的障碍。

实际上即使发展到今天，在繁多的人机交互功能和漂亮的图形界面下pspice仍然贯彻着最初设计的建模分析的手段。

因此我们在掌握了所研究的对象的数学表达式之后，可以建立起满意的电路模型。

现在以最新的OrCAD/Pspice v9.2为平台简要介绍用户自建模型的方法。

首先新建一个文本文件，写入所要建模对象的数学模型。

注意输入文件语法还是有比较严格的规范的。

简单来说，文件结构是由注释，子电路模型声明，参数声明，函数声明，电路结构声明，结束声明构成。

子电路声明必须由关键字.subckt 起始，描述子电路名、端口名和顺序；参数声明由.param起始，描述参数名和参数值；函数声明由.func起始，描述函数名和函数解析式；电路结构声明由电路结构关键字C电容，R电阻，E电压源，F电流源，G电导，Q晶体管， D二极管，X子电路等起始，描述元件名、连接节点、元件值。

Orcad PSpice

Orcad PSpiceOrCAD PSpice培训教材培训目标:熟悉PSpice的仿真功能,熟练掌握各种仿真参数的设置方法,综合观测并分析仿真结果,熟练输出分析结果,能够综合运用各种仿真对电路进行分析,学会修改模型参数。

一、 PSpice分析过程设置仿真参数绘制原理图运行仿真观测并分析仿真结果二、绘制原理图原理图的具体绘制方法已经在Capture中讲过了，下面主要讲一下在使用PSpice时绘制原理图应该注意的地方。

1、新建Project时应选择Analog or Mixed-signal Circuit2、调用的器件必须有PSpice模型首先，调用OrCAD软件本身提供的模型库，这些库文件存储的路径为Capture\Library\pspice，此路径中的所有器件都有提供PSpice模型，可以直接调用。

其次，若使用自己的器件，必须保证*.olb、*.lib两个文件同时存在，而且器件属性中必须包含PSpice Template属性。

3、原理图中至少必须有一条网络名称为0，即接地。

4、必须有激励源。

原理图中的端口符号并不具有电源特性，所有的激励源都存储在Source和SourceTM库中。

5、电源两端不允许短路，不允许仅由电源和电感组成回路，也不允许仅由电源和电容组成的割集。

解决方法:电容并联一个大电阻，电感串联一个小电阻。

6、最好不要使用负值电阻、电容和电感，因为他们容易引起不收敛。

三、仿真参数设置2PSpice能够仿真的类型在OrCAD PSpice中，可以分析的类型有以下8种，每一种分析类型的定义如下:直流分析:当电路中某一参数(称为自变量)在一定范围内变化时，对自变量的每一个取值，计算电路的直流偏置特性(称为输出变量)。

交流分析:作用是计算电路的交流小信号频率响应特性。

噪声分析:计算电路中各个器件对选定的输出点产生的噪声等效到选定的输入源(独立的电压或电流源)上。

即计算输入源上的等效输入噪声。

OrCAD PSpice仿真实验

OrCAD PSpice仿真实验实验5.1 直流扫描分析实验实验目的:1)学会使用电路绘制程序在Capture CIS环境内绘制所需要的电路图.2)学习偏压点分析和直流扫描分析.3)练习使用电路仿真程序执行仿真并显示出波形,将仿真结果与理论计算值比较加以验证.实验设备:1)个人电脑2)OrCAD 9.2Release软件实验内容与步骤:1.听指导教师讲解OrCAD基本知识及基本操作方法.2.按下列操作步骤依次完成仿真和结果预测.1)偏压点分析并观察输出文件的内容.1.绘出电路图.2.设置参数.3.保存.4.启动Pspice仿真及观察输出文件的内容.2)直流扫描分析并观察输出波形1.调出原电路图文件并设置DC Sweep直流扫描分析参数.2.存档并执行仿真.3.观察仿真输出结果.4.打印输出波形.5.将输出波形存成图形文件.实验电路图:输出结果:**** INCLUDING wz___3-SCHEMA ***** source WZ___3V_V1 N00113 0 15VdcR_R1 N00113 N00143 12R_R2 0 N00207 10R_R3 0 N00157 40I_I1 N00157 0 DC 4AdcV_PRINT1 N00143 N00221 0V.PRINT DC I(V_PRINT1)V_PRINT2 N00221 N00157 0V.PRINT DC I(V_PRINT2)V_PRINT3 N00207 N00221 0V.PRINT DC I(V_PRINT3)NODE VOL TAGE NODE VOL TAGE NODE VOL TAGE NODE VO L TAGE(N00113) 15.0000 (N00143) -13.2000 (N00157) -13.2000 (N00207) -13.2000(N00221) -13.2000VOL TAGE SOURCE CURRENTSNAME CURRENTV_V1 -2.350E+00V_PRINT1 2.350E+00V_PRINT2 3.670E+00V_PRINT3 1.320E+00实验结果分析:I1=2.350A I2=3.670A I3=1.320AI2=I1+I3 所以结果符合叠加原理实验5.3 交流扫描分析实验实验目的:练习使用Pspice的交流扫描分析(AC sweep)功能,进行交流电路的分析计算,以及电路频率的特性分析.实验设备:1)个人电脑2)OrCAD 9.2Release软件实验内容与步骤:1)绘制电路图.设置参数:分析类型设置为交流扫描(AC sweep),并选择原始频率为1Hz,终止频率为100kHz,每十倍频程的扫描点数Points/decade设置为100.2)执行Pspice仿真完成后,自动进入图形处理界面.3)添加曲线命令.观察波形,打印输出波形.4)查看输出文件.实验电路图:输出图形：输出结果:V_V1 N01192 0 DC 0 AC 220V acR_R2 0 N01110 280L_L2 N01192 N01169 1.65V_PRINT1 N01169 N011430V.PRINT AC IM(V_PRINT1)R_R1 N01143 N01110 20NODE VOL TAGE NODE VOL TAGE NODE VO L TAGE NODE VOL TAGE (N01110) 0.0000 (N01143) 0.0000 (N01169) 0.0000 (N01192) 0.0000VOL TAGE SOURCE CURRENTSNAME CURRENTV_V1 0.000E+00V_PRINT1 0.000E+00TOTAL POWER DISSIPA TION 0.00E+00 W A TTS。

OrCAD-PSPICE-仿真入门

采用PSPICE电路仿真引擎， ORCAD-PSPICE能够提供高精度的电路性能分析和仿真结果。
强大的分析工具
ORCAD-PSPICE提供了丰富的分析工具，如波形分析、频谱分析、噪声分析等，帮助用户深入了解电路性能。
灵活的参数化分析
用户可以通过参数化分析功能，对电路元件参数进行扫描和优化，找到最佳的电路性能。
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orcad-pspice仿真入门
目录
• 引言 • ORCAD-PSPICE概述 • ORCAD-PSPICE仿真流程 • 常见电路仿真分析 • 高级仿真技术 • ORCAD-PSPICE仿真实例
01 引言
目的和背景
学习和掌握ORCAD-PSPICE仿真软件，能够为电子工程师提供强大的电路设计和分析工具，帮助他们快速验证电路原理、优化电路参数和提高设计效率。
ORCAD-PSPICE支持模拟、数字和混合信号电路的仿真，能够进行电路性能分析和优化，帮助工程师快速、准确地完成电路设计和验证。
ORCAD-PSPICE的功能和特点
丰富的元件库
ORCAD-PSPICE提供了广泛的元件库，包括各种模拟、数字和混合信号元件，方便用户进行电路设计和仿真。
高精度仿真
蒙特卡洛分析
蒙特卡洛分析是一种基于概率统计的仿真技术，用于分析电路性能的统计分布情况。在Orcad-Pspice中，可以通过在仿真设置中设置蒙特卡洛分析参数，对电路性能进行概率统计。
VS
蒙特卡洛分析可以帮助设计者了解电路性能的统计分布情况，从而评估电路性能的可靠性。
最坏情况分析
最坏情况分析是一种仿真技术，用于分析电路性能在元件参数最坏情况下的表现。在 Orcad-Pspice中，可以通过在仿真设置中设置最坏情况分析参数，对电路性能进行最坏情况分析。

第二讲ORCAD之PSPICEAD数模混合仿真模块-文档资料

请看演示…….
PSpice 交流分析
运行仿真程序，放置电压探针在out端（或者在 Probe 演示窗口中加入V(out)波形 ) 仿真结果如下：

PSpice 中的噪声分析

噪声分析是针对电路中固有噪声（如电阻和半导体的工作噪声）所做的分析，它的计算结果时所求节点相对于输入独立源的等效噪声。伴随AC交流分析而进行所涉及的噪声种类：
PSpice 中的噪声分析

V(INOISE)和V(ONOISE) （菜单 Trace>Add Trace…或快捷键 ) INOISE 即INPUT NOISE ONOISE 即OUTPUT NOISE
5.确定后，运行仿真。在PSpice A/D窗口中加入波形
噪声的计算方法: 输出节点的总噪声除以相对输入激励源的电路的总增益

编写VHDL （EXPRESS）绘制电路图（CAPTURE）进行电路混合仿真（PSPICE A/D）设计电路板（LAYOUT）
VHDL仿真（EXPRESS）
运用 PSpice 的基本条件
1.待仿真的元器件模型必须是PSpice的仿真模型 2.电路中应该含有激励源，并且符合相应的电路特性分析类型的要求 3.必须设置好合适的电路特性分析类型
热噪声：电子的无序运动引起散弹噪声：单位时间通过PN结的载流子数目变化造成闪烁噪声：能量主要集中在低频段，由于生产工艺的缺陷而引起

等效噪声：将整个电路中的噪声源都集中折算到选定的独立源处，然后计算在等效的噪声源的激励下，所求节点处产生的噪声。 PSpice可以分析每个频率点上指定节点的等效输出噪声电压和指定输入端的等效输入噪声电压。噪声电压的单位是 V A 或 Hz ，即把噪声电平对噪声带宽的均方根进行归 Hz 一化

OrCAD_PSpice简明教程

OrCAD_PSpice简明教程PSPICE简明教程宾西法尼亚⼤学电⽓与系统⼯程系University of PennsylvaniaDepartment of Electrical and Systems Engineering编译：陈拓2009年8⽉4⽇原⽂作者：Jan Van der Spiegel, ?2006 jan_at_/doc/92ba9b2de2bd960590c67752.html Updated March 19, 2006⽬录1. 介绍2. 带OrCAD Capture的Pspice⽤法2.1 第⼀步：在Capture 中创建电路2.2 第⼆步：指定分析和仿真类型偏置或直流分析（BIAS or DC analysis）直流扫描仿真（DC Sweep simulation）2.3 第三步：显⽰仿真结果2.4 其他分析类型：2.4.1瞬态分析（Transient Analysis）2.4.2 交流扫描分析（AC Sweep Analysis）3. 附加的使⽤Pspice电路的例⼦3.1变压器电路3.2 使⽤理想运算放⼤器的滤波器交流扫描（滤波器电路)3.3 使⽤实际运算放⼤器的滤波器交流扫描（滤波器电路)3.4 整流电路（峰值检波器）和参量扫描的使⽤3.4.1 峰值检波器仿真（Peak Detector simulation）3.4.2 参量扫描（Parametric Sweep）3.5 AM 调制信号3.6 中⼼抽头变压器4. 添加和创建库：模型和元件符号⽂件4.1 使⽤和添加⼚商库4.2 从⼀个已经存在的Pspice模型⽂件创建Pspice符号4.3 创建你⾃⼰的Pspice模型⽂件和符号元件参考书⽬1. 介绍是⼀种强⼤的通⽤模拟混合模式电路仿真器，可以⽤于验证电路设计并且预知 SPICE电路的⾏为，这对于集成电路特别重要，1975年SPICE最初在加州⼤学伯克利分校被开发时也是基于这个原因，正如同它的名字所暗⽰的那样：S imulation P rogram for I ntegrated C ircuits E mphasis.PSpice 是⼀个PC版的SPICE（Personal-SPICE），可以从属于Cadence设计系统公司的OrCAD公司获得。

orCAD仿真使用说明

在O r CAD/PSpice 9.2平台上电子电路设计与仿真Pspice实践练习一：设计与仿真一个单级共射放大电路（提供的参考电路如图一所示）。

要求：放大电路有合适静态工作点、电压放大倍数30左右、输入阻抗大于1KΩ、输出阻抗小于5.1KΩ及通频带大于1MHZ 。

请参照下列方法及步骤，自学完成Pspice实践练习一。

一、启动Pspice9.2 →Capture →在主页下创建一个工程项目exa1。

⒈选File/New/ Project⒉建立一个子目录→Create Dir (键入e:\zhu)，并双击、打开子目录；⒊选中●Analog or Mixed- Signal Circuit OK!⒋键入工程项目名exa1；⒌在设计项目创建方式选择对话下，选中●Create a blank pro OK!⒍画一直线，将建立空白的图形文件(exa1.sch)存盘。

二、画电路图（以单级共射放大电路为例，电路如图一所示）⒈打开库浏览器选择菜单Place/Part → Add Library提取：三极管Q2N2222（bipolar库）、电阻R、电容C（analog库）、电源VDC（source库）、模拟地0/Source、信号源VSIN。

⒉移动元、器件。

鼠标选中元、器件并单击（元、器件符号变为红色），然后压住鼠标左键拖到合适位置，放开鼠标左键即可。

⒊删除某一元、器件。

鼠标选中该元、器件并单击（元、器件符号变为红色），选择菜单Edit/delete 。

⒋翻转或旋转某一元、器件符号。

鼠标选中该元、器件并单击（元、器件符号变为红色），可按键Ctrl +R 即可。

⒌画电路连线选择菜单中Place/wire，此时将鼠标箭头变成为一支笔（自己体会）。

⒍为了突出输出端，需要键入标注Vo 字符，选择菜单Place/Net Alias → Vo OK!三、修改元、器件的标号和参数⒈.用鼠标箭头双击该元件符号（R 或C），此时出现修改框，即可进入标号和参数的设置。

OrCAD PSPICE 仿真入门

原理图绘制
修改后原理图变为: 修改后原理图变为:
电路原理图保存
执行File/Save命令执行File/Save命令
电路图的仿真 (三)电路的仿真(瞬态分析) 电路的仿真(瞬态分析)
1、建立电路网表(执行PSpice/Create Netlist命令)
电路图的仿真
2、仿真参数类型设置
执行PSpice/New 执行PSpice/New Simulation Profile命令 Profile命令
放置二极管符号
执行P1ace/Part命令执行P1ace/Part命令在 “Libraries”列表框中选 Libraries”列表框中选择“diode”库择“diode”库在 “Part”列表框中选择 Part”列表框中选择 “ D1N4002”，单击“OK” D1N4002”，单击“OK” 将该二极管移至合适位置，（按键盘中的R （按键盘中的R键，器件旋转）按鼠标左键放置按ESC键（或鼠标右键点 ESC键（或鼠标右键点 end mode）结束绘制元器 mode）结束绘制元器ce/Part命令执行P1ace/Part命令在 “Libraries”列表框中 Libraries”列表框中选择“SOURCE” 选择“SOURCE” 在 “Part”列表框中选择 Part”列表框中选择 “ VSIN”，或 VSIN”，或 “VPULSE”, 或“VPWL” 或“VPWL” 单击“OK” 单击“OK” 将激励源移至合适位置，按鼠标左键按ESC键或鼠标右键点 ESC键或鼠标右键点 end mode以结束绘制元 mode以结束绘制元器件状态
放置电容符号
执行P1ace/Part命令执行P1ace/Part命令在 “Libraries”列表框中选 Libraries”列表框中选择“ANALOG” 择“ANALOG” 在 “Part”列表框中选择 Part”列表框中选择 “ C” 单击“OK” 单击“OK” 将电阻C 将电阻C移至合适位置，（按键盘中的R （按键盘中的R键，器件旋转）按鼠标左键放置按ESC键（或鼠标右键点 ESC键（或鼠标右键点 end mode）结束绘制元器 mode）结束绘制元器件状态

OrCAD_PSpice_Tutorial Orcad仿真原理图创建指导手册

OrCAD Flow Tutorial, Product Version 16.02Creating a schematic designThis chapter consists of the following sections:ObjectiveDesign exampleCreating a design in CaptureProcessing a designSummaryWhat's nextRecommended readingObjectiveTo create a schematic design in OrCAD Capture. In this chapter, you will be introduced to basic design steps, such as placing a part, connecting parts using wires, adding ports, generating parts, and so on.The steps for preparing your design for simulation using PSpice and for taking your design for placement and routing to OrCAD Layout or OrCAD PCB Editor are also covered in this chapter.Design exampleIn this chapter, you will create a full adder design in OrCAD Capture. The full adder design covered in this tutorial is a complex hierarchical design that has two hierarchical blocks referringto the same half adder design.Duration:40 minutesCreating a design in CaptureGuidelinesWhen creating a new circuit design in OrCAD Capture, it is recommended that you follow the guidelines listed below.1.Avoid spaces in pathnames and filenames. This is necessary to get your design intodownstream products, such as SPECCTRA for OrCAD.2.Avoid using special characters for naming nets, nodes, projects, or libraries. While namingnets, use of illegal characters listed below might cause the netlister to fail.? (question mark)@ (at symbol)~ (telda)#(hash)& (ampersand)% (percent sign)" (quotation marks)! (exclamation mark)( )(parenthesis)< (smaller than)= (equal)> (greater than)[ ](square parenthesis),* (asterisk)Creating a projectTo create a new project, we will use Capture's Project Wizard. The Project Wizard provides you with the framework for creating any kind of project.unch Capture.2.From the File menu, choose New > Project.3.In the New Project dialog box, specify the project name as FullAdd.4.To specify the project type, select Analog or Mixed A/D.Note: An Analog or Mixed A/D project can easily be simulated using PSpice. It alsoensures that your design flows smoothly into OrCAD Layout for your board design.5.Specify the location where you want the project files to be created and click OK.6.In the Create PSpice Project dialog box, select the Create a blank project option button.Note: When you create a blank project, the project can be simulated in PSpice, butlibraries are not configured by default. When you base your project on an existing project, the new project has same configured libraries.7.Click OK to create the FullAdd project with the above specifications.In case you already have a schematic design file (.dsn) that you want tosimulate using PSpice, you need to create an Analog or Mixed A/D project usingthe File > New > Project command and then add your design to it.The FullAdd project is created. In the Project Manager window, a design file, fulladd.dsn, is created. Below the design file, a schematic folder with the name SCHEMATIC1 is created. This folder has a schematic page named PAGE1.Renaming the schematic folder and the schematic pageYou will now modify the design to change the name of both the schematic folder and the schematic page, to HALFADD.1.In the Project Manager window, right-click on SCHEMA TIC1.2.From the pop-up menu, select Rename.3.In the Rename Schematic dialog box, specify the name as HALFADD.4.Similarly, right-click on PAGE1 and from the pop-up menu select Rename.5.In the Rename Page dialog box, specify the page name as HALFADD and click OK. After renaming of the schematic folder and the schematic page, the directory structure in the Project Manager window should be to similar to the figure below.Using a design templateBefore you start with the design creation process in OrCAD Capture, you can specify the default characteristics of your project using the design template. A design template can be used to specify default fonts, page size, title block, grid references and so on. To set up a design template in OrCAD Capture, use the Design Template dialog box.- To open the Design Template dialog box, from the Options drop-down menu choose Design Template.To know more about setting up the design template, see OrCAD Capture User's Guide. Creating a flat designIn this section, we will create a simple flat half adder design with X and Y as inputs and SUM and CARRY as outputs.Adding partsTo add parts to your design:1.From the Place menu in Capture, select Part.2.In the Place Part dialog box, first select the library from which the part is to be added andthen instantiate the part on the schematic page.The gates shown in Figure 2-1 are available in the 7400.OLB.Use the Part Search button in the Place Part dialog box, to search the library towhich the required part belongs.To add 7400.OLB to the project, select the Add Library button.3.Browse to <install_dir>/tools/capture/library/pspice/7400.olb.Select 7400.OLB and click Open.The 7400 library appears in the Libraries list box.4.From the Part List, select 7408 and click OK.5.Place three instances of the AND gate, 7408, on the schematic page as shown in the figure below.6.Right-click and select End Mode.7.Similarly, place an OR gate (7432) and two NOT gates (7404) as shown in the figurebelow.Connecting partsAfter placing the required parts on the schematic page, you need to connect the parts.1.From the Place menu, choose Wire.The pointer changes to a crosshair.2.Draw the wire from the output of the AND gate, U2A, to the one of the inputs of the ORgate, U1B. To start drawing the wire, click the connection point of the output pin, pin3, on the AND gate.3.Drag the cursor to input pin, pin4, of the OR gate (7432) and click on the pin to end thewire.Clicking on any valid connection point ends a wire.4.Similarly, add wires to the design until all parts are connected as shown in the figurebelow.5.To stop wiring, right-click and select End Wire. The pointer changes to the default arrow. Adding portsTo add input and output ports to the design, complete the following sequence of steps:1.From the Place menu in Capture, select Hierarchical Port.The Place Hierarchical Port dialog box appears.Note: Alternatively, you can select the Place port button from the Tool Palette.2.From the Libraries list box, select CAPSYM.3.First add input ports. From the Symbols list, select PORTRIGHT-R and click OK.4.Place two instances of the port as shown in the figure below5.Right-click and select End Mode.6.To rename the ports to indicate input signals X and Y, double-click the port name.7.In the Display Properties dialog box, change the value of the Name property to X and clickOK.Note: You can also use the Property Editor to edit the property values of a component. To know the details, see OrCAD Capture User's Guide.8.Similarly, change the name of the second port to Y.Note: You cannot use the Place Part dialog box for placing ports, because ports inCAPSYM.OLB are only symbols and not parts. Only parts are listed in the Place Partdialog box.9.Add two output ports as shown in the figure below. To do this, select PORTLEFT-L fromthe CAPSYM library.10.Rename the ports to SUM and CARRY, respectively.11.Save the design.The half adder design is ready. The next step is to create a full adder design that will use the half adder design.Creating a hierarchical designIn Capture, you can create hierarchical designs using one of the following methods:Bottom-up methodTop-down methodAnother method of creating a hierarchical design is to create parts or symbols for the designs at the lowest level, and save the symbols in a user-defined library. You can later add the user-defined library in your projects and use these symbols in the schematic. For example, you can create a part for the half adder design and then instead of hierarchical blocks, use this part in the schematic. To know more about this approach, see Generating parts for a schematic.In this section, we will create the full adder hierarchical design. The half adder design created in the Creating a flat design section will be used as the lowest level design.Bottom-up methodWhen you create a hierarchical design using the bottom-up methodology, you need to follow these steps.Create the lowest-level design.Create higher-level designs that instantiate the lower-level designs in the form ofhierarchical blocks.In this section, we will create a full adder design using bottom-up methodology. The steps involved are:1.Creating a project in Capture. To view the steps, see Creating a project.2.Creating the lowest-level design. In the full adder design example, the lowest-level designis the half adder design. To go through the steps for creating the half adder design, seeCreating a flat design.3.Creating the higher-level design. Create a schematic for the full adder design that uses thehalf adder design created in the previous step. To go through the steps, see Creating thefull adder design.Creating the full adder design1.In the Project Manager window, right-click on fulladd.dsn and select New Schematic.2.In the New Schematic dialog box, specify the name of the new schematic folder asFULLADD and click OK.In the Project Manager window, the FULLADD folder appears below fulladd.dsn.3.Save the design.4.To make the full adder circuit as the root design (high-level design), right-click onFULLADD and from the pop-up menu select Make Root.The FULLADD folder moves up and a forward slash appears in the folder.5.Right-click on FULLADD and select New Page.6.In the New Page in schematic: FULLADD dialog box, specify the page name as FULLADD and click OK.A new page, FULLADD, gets added below the schematic folder FULLADD.7.Double-click the FULLADD page to open it for editing.8.From the Place menu, choose Hierarchical Block.9.In the Place Hierarchical Block dialog box, specify the reference as HALFADD_A1.10.Specify the Implementation Type as Schematic View.11.Specify the Implementation name as HALFADD and click OK.The cursor changes to a crosshair.12.Draw a rectangle on the schematic page.A hierarchical block with input and output ports is drawn on the page.13.If required, resize the block. Also, reposition the input and output ports on the block. Note: To verify if the hierarchical block is correct, right-click on the block and select Descend Hierarchy. The half adder design you created earlier should appear.14.Place another instance of the hierarchical block on the schematic page.a.Select the hierarchical block.b.From the Edit menu, choose Copy.c.From the Edit menu, choose Paste.d.Place the instance of the block at the desired location.Note: Alternatively, you can use the <CTRL>+<C> and <CTRL>+<V> keys to copy-paste the block.15.By default, the reference designator for the second hierarchical block is HALFADD_A2. Double-click on the reference designator, and change the reference value toHALFADD_B1.ing the Place Part dialog box, add an OR gate (7432) to the schematic. (See Figure 2-2.)17.To connect the blocks, add wires to the circuit. From the Place menu, choose Wire.18.Draw wires from all four ports on each of the hierarchical blocks.19.Add wires until all the connections are made as shown in the figure below.20.Add stimulus to the design. In the Place Part dialog box, use the Add Library button to add SOURCSTM.OLB to the design.This library is located at <install_dir>/tools/capture/library/pspice.21.From the Part List, select DigStim1 and click OK.The symbol gets attached to the cursor.22.Place the symbol at three input ports: port X of the HALFADD_A1, port X and Y of HALFADD_B1.23.Right-click on the schematic and select End Mode.24.Specify the value of the Implementation property as Carry, X, and Y, respectively. See Figure 2-2.25.Select the Place Port button, to add an output port, CARRY_OUT, to the output of the OR gate. (See Figure 2-2.)26.From the list of libraries, select CAPSYM.27.From the list of symbols, select PORTLEFT-L and click OK.28.Place the output port as shown in the Figure 2-2.29.Double-click the port name and change the port to CARRY_OUT.30.Save the design.We have only added digital components to the design so far. We will now add a bipolar junction transistor to the SUM port of the HALFADD_A1 block.1.Select the Place Part tool button.2.In the Place Part dialog box, select the Add Library button.3.Select ANALOG.OLB and BIPOLAR.OLB and click Open.4.From the part list, add resistor R. Place this resistor on the schematic and connected oneend of the resistor to the SUM port of HALFADD_A1. See Figure 2-3.5.From the BIPOLAR.OLB, select Q2N2222 and place it on the schematic. See Figure 2-3.plete the circuit by adding a collector resistance, Collector V oltage, and ground. SeeFigure 2-3.Adding Collector Voltagea.To add the voltage, add the SOURCE.OLB library to the project.b.From the Part List select VDC and click OK.c.Place the voltage source on the schematic. See Figure 2-3.d.By default, the source is of 0 volts. Using the Property Editor, change it to a voltagesource of 5V. To do this, double-click the voltage source.e.In the Property Editor window, change the value of the DC parameter to 5.f.Save and close the Property Editor window.Adding Grounda.To add ground, select the Place ground button.b.In the Place Ground dialog box, select the SOURCE library.c.From the part list, select 0 and click OK.d.Place the ground symbol on the schematic. See Figure 2-3.You must use the 0 ground part from the SOURCE.OLB part library. Youcan use any other ground part only if you change its name to 0.7.Add a connector CON2 to the circuit. To do this, add a Capture library,CONNECTOR.OLB to the project.CONNECTOR.OLB is located at <install_dir>/tools/capture/library.You have successfully created the full adder hierarchical design using the bottom-up methodology. As the components used in this design are from the PSpice library, you can simulate this design using PSpice.Top-down methodWhen you create a hierarchical design using the top-down methodology, use the followingsequence of steps:Create the top-level design using functional blocks, the inputs and outputs of which are known.Create a schematic design for the functional block used in the top-level design.This section provides an overview of the steps to be followed for creating a full adder using top-down methodology.1.Create a FullAdd project.To view the steps, see Creating a project.2.Create the top-level design, using the following steps:a.From the Place menu, choose Hierarchical Block.Note: Alternatively, you can select the Place hierarchical block buttonfrom the Tool Palette.b.In the Place Hierarchical Block dialog box, specify the reference as HALFADD_A1,Implementation Type as Schematic View, Implementation name as HALFADD,and click OK.See step 9 to step 11 in the Bottom-up method section.c.Draw the hierarchical block as required.Note that unlike the hierarchical block drawn in the bottom-up methodology, thehierarchical block in the top-down methodology does not have port informationattached to it.d.Select the hierarchical block and then from the Place menu, choose HierarchicalPins.e.In the Place Hierarchical Pin dialog box, specify the pin name as X, Type as Input,and Width as Scalar and click OK.f.Place the pin as shown in the figure below.g.Similarly, add another input pin Y and two output pins, SUM and CARRY, as shown in the figure below.h.Place another hierarchical block with the Implementation Type as HALFADD. The easiest way to do this is to copy the existing hierarchical block and paste it on the schematic page.By default, the reference value of the second hierarchical block is HALFADD_A2. Change this value to HALFADD_B1.Complete the full adder circuit by adding ports, wires, and stimuli. See The full adder circuit.Save the design.3.Draw the lowest-level design using the steps listed below. For the full adder design example, the lowest-level design is a half adder circuit.a.To draw the half adder design, right-click on any one of the HALFADD hierarchicalblock.b.From the pop-up menu, select Descend Hierarchy.c.The New Page in Schematic: 'HALFADD' dialog box appears.Specify the page name as HALFADD and click OK.A new schematic pages appears with two input ports, X and Y, and two output ports, SUM and CARRY.You can now draw the half adder circuit on this schematic page using the steps covered in the Creating a flat design. Also see Figure 2-1.In the Project Manager window, a new schematic folder HALFADD gets added belowfulladd.dsn.Generating parts for a schematicInstead of creating a hierarchical block for the half adder design, you can generate a part for the half adder design and then reuse the part in any design as and when required.In this section of the tutorial, we will generate a part for the half adder circuit that you created in the Creating a flat design section of this chapter.To generate a part from a circuit, complete the following steps.1.In the Project Manager window, select the HALFADD folder.2.From the Tools menu, choose Generate Part.3.In the Generate Part dialog box, specify the location of the design file that contains thecircuit for which the part is to be made.For this design example, specify the location of fulladd.dsn.4.In the Netlist/source file type drop-down list box, specify the source type as CaptureSchematic Design.5.In the Part Name text box, specify the name of the part that is to be created, as HALFADD.6.Specify the name and the location of the library that will contain this new part beingcreated. For the current design example, specify the library name as fulladd.olb.7.If you want the source schematic to be saved along with the new part, select the Copyschematic to library check box. For this design, select the check box.8.Ensure that the Create new part option is selected.9.To specify the schematic folder that contains the design for which the part is to be made,select HALFADD from the Source Schematic name drop-down list box.10.Click OK to generate the HalfAdd part.A new library, fulladd.olb, is generated and is visible under the Outputs folder in the Project Manager window. The new library also gets added in the Place part dialog box. You can now use the Place part dialog box to add the half adder part in any design.Navigating through a hierarchical designTo navigate to the lower levels of the hierarchy, right-click a hierarchical block and choose Descend Hierarchy.Similarly, to move up the hierarchy, right-click and select Ascend Hierarchy.The Ascend Hierarchy and Descend Hierarchy menu options are also available in the View drop-down menu.While working with hierarchical designs, you can make changes to the hierarchical blocks aswell as to the designs at the lowest level.To keep the various hierarchical levels updated with the changes, you can use the Synchronize options available in the View drop-down menu.Select Synchronize Up when you have made changes in the lowest-level design and want these changes to be reflected higher up in the hierarchy.Select Synchronize Across when you have made changes in a hierarchical block and want the changes to be reflected across all instances of the block.Select Synchronize Down when you have made changes in a hierarchical block and want these changes to be reflected in the lowest-level design.Processing a designAfter you have created your schematic design, you may need to process your design by adding information for tasks such as, simulation, synthesis, and board layout. This section covers some of the tasks that you can perform in OrCAD Capture while processing your design.Adding part referencesTo be able to take your schematic design to Layout or PCB Editor for packaging, you need to ensure that all the components in the design are uniquely identified with part references. In OrCAD Capture you can assign references either manually or by using the Annotate command. In the full adder design, annotation is not required at this stage because by default, unique part references are attached to all the components. This is so because by default, Capture adds part reference to all the components placed on the schematic page. If required, you can disable this feature by following the steps listed below.1.From the Options menu, choose Preferences.2.In the Preferences dialog box, select the Miscellaneous tab.3.In the Auto Reference section, clear the Automatically reference placed parts check box.4.Click OK to save these settings.In case the components in your design do not have unique part references attached to them, you must run the Annotate command.To assign unique part references to the components in the FULLADD design using the Annotate command, complete the following steps:1.In the Project Manager window, select the fulladd.dsn file.2.From the Tools drop-down menu, choose Annotate.Note: Alternatively, you can click the Annotate button on the toolbar.3.In the Packaging tab of the Annotate dialog box, specify whether you want the completedesign or only a part of the design to be updated. Select the Update entire design option button.4.In the Actions section, select the Incremental reference update option button.Note: To know about other available options, see the dialog box help.5.The full adder design is a complex hierarchical design. So choose the Update Occurrenceoption button.Note: When you select the Update Occurrence option, you may receive a warningmessage. Ignore this message because for all complex hierarchical designs, the occurrence mode is the preferred mode.6.For the rest of the options, accept default values and click OK to save your settings.The Undo Warning message box appears.7.Click Yes.A message box stating that the annotation will be done appears.8.Click OK.Your design is annotated and saved. You can view the value of updated cross reference designators on the schematic page.If you select the Annotate command after generating the Layout or PCBEditor netlist, you will receive an error message stating that annotating atthis stage may cause the board to go out of sync with the schematic design.This may cause further backannotation problems.Creating a cross reference reportUsing Capture, you can create cross reference reports for all the parts in your design. A cross reference report contains information, such as part name, part reference, and the library from which the part was selected.To generate a cross reference report using Capture:1.From the Tools menu choose Cross References.Alternatively, you can choose the cross reference parts button from the toolbar.2.In the Cross Reference Parts dialog box, ensure that the Cross reference entire designoption button is selected.Note: If you want to generate the cross reference report for a particular schematic folder, select the schematic folder before opening the Cross Reference Parts dialog box, and then select the cross reference selection option button.3.In the Mode section, select the Use Occurrences option button.Note: Ignore the warning that is displayed when you select the Use Occurrences mode.For complex hierarchical designs, you must always use the occurrence mode.4.Specify the report that you want to be generated.5.In case you want the report to be displayed automatically, select the View Output checkbox.6.Click OK to generate the report.A sample output report is shown below.Generating a bill of materialsAfter you have finalized your design, you can use Capture to generate a bill of materials (BOM).A bill of materials is a composite list of all the elements you need for your PCB design. Using Capture, you can generate a BOM report for electrical and as well as non-electrical parts, such as screws. A standard BOM report includes the item, quantity, part reference, and part value.To generate a BOM report:1.In the Project Manager window, select fulladd.dsn.2.From the Tools menu, select Bill of Materials.3.To generate a BOM report for the complete design, ensure that the Process entire designoption button is selected.4.For a complex hierarchical designs, the preferred mode is the occurrence mode. Therefore,select the Use Occurrences option button.Note: In case you receive a warning stating that it is not the preferred mode, ignore the warning.5.Specify the name of the BOM report to be generated. For the current design, accept thedefault name, FULLADD.BOM.Note: By default, the report is named as designname.BOM.6.Click OK.The BOM report is generated. A sample report is shown below:Getting your design ready for simulationTo be able to simulate your design using PSpice, you must have the connectivity information and the simulation settings for the analysis type to be done on the circuit design.The simulation setting information is provided by a simulation profile (*.SIM). This section covers the steps to be followed in Capture for creating a simulation profile.Note: To know more details about getting your design ready for simulation using PSpice, see Chapter 3, Preparing a design for simulation of the PSpice User's Guide.Creating a simulation profile from scratchTo create a new simulation profile to be used for transient analysis, complete the following steps:1.From the PSpice menu in Capture, choose New Simulation Profile.2.In the New Simulation dialog box, specify the name of the new simulation profile asTRAN.3.In the Inherit From text box, ensure that none is selected and click Create.The Simulation Setting dialog box appears with the Analysis tab selected.4.In the Analysis type drop-down list box, Time Domain (Transient) is selected by default.Accept the default setting.5.Specify the options required for running a transient analysis. In the Run to time text box,specify the time as 100u.6.Click OK to save your modifications and to close the dialog box.You can now run transient analysis on the circuit. Note that the Simulation Setting dialog box also provides you with the options for running advanced analysis, such as Monte Carlo (Worst Case) analysis, Parametric analysis and Temperature analysis. You may choose to run these as and when required.Note: To know details about each option in the Simulation Settings dialog box, click the Help button in the dialog box.Creating a simulation profile from an existing profileYou can create a new simulation profile from an existing simulation profile. This section covers the steps for creating a new simulation profile, SWEEP, from an existing simulation profile, named TRAN.1.From the PSpice menu, choose New Simulation Profile.2.In the New Simulation dialog box, specify the profile name as SWEEP.3.In the Inherit From drop-down list box, select FULLADD-TRAN.4.Click the Create button.The Simulation Settings dialog box appears with the general settings inherited from the existing simulation profile. You can now modify the settings as required and run PSpice to simulate your circuit.Adding Layout-specific propertiesTo be able to take your design to OrCAD Layout or OrCAD PCB Editor for placement and routing, you need to add the footprint information for each of the components in your design. By default, some footprint information is available with all the components from the PSpice-compatible libraries located at <install_dir>/tools/capture/library/pspice. However, these footprints are not valid. You need to change these values to valid footprint values. You can add footprint information either at the schematic design stage in OrCAD Capture or during the board design stage in OrCAD Layout. In this section, you will learn to add footprint information to the design components during the schematic design stage.To add footprint information to the OR gate, 7432, in the FULLADD schematic page, complete the following steps.。

OrCAD PSpice软件培训教材

OrCAD PSpice 培训教材培训目标：熟悉PSpice的仿真功能，熟练掌握各种仿真参数的设置方法，综合观测并分析仿真结果，熟练输出分析结果，能够综合运用各种仿真对电路进行分析，学会修改模型参数。

一、PSpice分析过程二、绘制原理图原理图的具体绘制方法差不多在Capture中讲过了，下面要紧讲一下在使用PSpice时绘制原理图应该注意的地点。

1、新建Project时应选择Analog or Mixed-signal Circuit2、调用的器件必须有PSpice模型首先，调用OrCAD软件本身提供的模型库，这些库文件存储的路径为Capture\Library\pspice，此路径中的所有器件都有提供PSpice模型，能够直接调用。

其次，若使用自己的器件，必须保证*.olb、*.lib两个文件同时存在，而且器件属性中必须包含PSpice Template属性。

3、原理图中至少必须有一条网络名称为0，即接地。

4、必须有激励源。

原理图中的端口符号并不具有电源特性，所有的激励源都存储在Source和SourceTM库中。

5、电源两端不同意短路，不同意仅由电源和电感组成回路，也不同意仅由电源和电容组成的割集。

解决方法：电容并联一个大电阻，电感串联一个小电阻。

6、最好不要使用负值电阻、电容和电感，因为他们容易引起不收敛。

三、仿真参数设置1、PSpice能够仿确实类型在OrCAD PSpice中，能够分析的类型有以下8种，每一种分析类型的定义如下：直流分析：当电路中某一参数（称为自变量）在一定范围内变化时，对自变量的每一个取值，计算电路的直流偏置特性（称为输出变量）。

交流分析：作用是计算电路的交流小信号频率响应特性。

噪声分析：计算电路中各个器件对选定的输出点产生的噪声等效到选定的输入源（独立的电压或电流源）上。

即计算输入源上的等效输入噪声。

瞬态分析：在给定输入激励信号作用下，计算电路输出端的瞬态响应。

差不多工作点分析：计算电路的直流偏置状态。

orcad pspice 仿真教程 4

VDD
RBIAS 20k
RC1 10k C1 out1 5p R1 Rbreak Q3 Q 2N2222 Q4 Q 2N2222 out2
RC2 10k
V
RS2 1k
V1
VAMPL = 0.1V FREQ = 5MEG V2
0
Q1 Q 2N2222 Q2 Q 2N2222 12V V3
0
VDD
VEE -12V
之间的参数又存在随机起伏，这就需要用DEV表示。这就是
说，对用于集成电路生产的电路设计进行MC分析时，对要考虑其变化的参数，应同时采用LOT和DEV两种变化模式。
为了反映实际生产中元器件参数的分布变化情况，PSpice提供了正态分布（又称高斯分布）和均匀分布两种分布函数，供用户选
用。在设置时，应在参数变化模式设置的后面紧跟代表选用分布
0
PARAMETERS:
c1 = 33 u
设置和运行参数分析(Parametric Sweep) 在Simulation Setting的Analysis type对话框中选择Time Domain(Transient)，在Options中选中Parametric Sweep：
400V
0V
-400V 0s 10ms V(D1:1) V(OUT) 20ms Time
Y Max Max Min Rise_edge Fall_edge
Y Max： Max： Min：
求出每个波形与额定运行值的最大差值求出每个波形的最大值求出每个波形的最小值
Rise_edge：找出第一次超出域值的波形
Fall_edge：找出第一次低于域值的波形
More setting…：点击More Setting按钮，将弹出如下对话框

ORCADPSPICE仿真学习（1）

本文链接：https:///hgzty/article/details/6571040版权用LTspice仿真有一段时间了，今天试着学学用ORCAD自带的仿真工具。

先从最简单的一阶RC低通滤波器开始。

通过F=1/（2*pi*R*C）计算截止频率为174Hz。

首先加激励源：VAC（这里我发现好像一定要加这个，其他的比如Vsin不可以使用）整体电路如下：（电路中必须有0电位的存在，否则无法进行仿真）1. 交流扫描首先建立一个新的仿真，取名为AC。

这样，你在工程下就会看到一个以“AC”命名的文件夹。

仿真的结果和输出都会在该文件夹下。

接下来是设置，我们用log的方式选取横坐标显示，频率设置从1Hz到10MHz（这里要注意，要表示成MEG才是兆，M会认为是毫）。

确认后，运行仿真。

如果没有在之前的电路上加V探针，则可以通过add trace进行添加，这里得到的V（OUT）的仿真曲线。

我们可以通过cutoff_lowpass_3dB(V(OUT))这个公式得到3db截止频率点为：174.34619Hz，和理论估算的一致。

噪声分析噪声分析不是很清楚原理，但应该和仿真的模型有关。

在设置这里选输出电压为V（OUT），I/V Source 为V1，频率点设为每隔4点计算一次。

所得到的结果输出在AC.out文件中。

这里简单讲一下。

至于options下的选项，好像都和模型相关的，以后仔细研究了再说。

2. 直流扫描选取DC Sweep，在直流扫描中，电容等效于开路，电感等效于短路。

各个信号源取其直流电平值。

确定即可，V（OUT）为斜率为1的直线。

2024版orcadPspice教程

输入信号设置
为电路输入端设置合适的信号源，如正弦波、方波、脉冲等，并调整信号的幅度、频率等参数。
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16
运行仿真并查看结果
运行仿真
在完成仿真类型和参数设置后，运行仿真程序，等待仿真完成。
查看仿真结果
仿真完成后，可以通过软件界面查看仿真结果，如波形图、数据表等。
结果分析
根据仿真结果，分析电路的性能指标，如电压、电流、功率等是否满足设计要求。
11
创建新原理图文件
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打开Orcad Pspice软件，选择“File”菜单下的“New”选项，然后选择“Schematic”创建一个新的原理图文件。
在弹出的对话框中，为新原理图文件命名并选择合适的保存位置。
选择合适的图纸大小和方向，以及所需的网格大小和捕获网格选项。
12
元器件库使用及元器件放置
22
CHAPTER 06
高级功能探索与实战案例
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蒙特卡罗分析应用举例
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蒙特卡罗分析介绍
01
简要说明蒙特卡罗分析的基本原理和其在电路仿真中的应用。
蒙特卡罗分析设置步骤
02
详细阐述在orcadPspice中进行蒙特卡罗分析的参数设置、仿真
运行及结果查看等步骤。
蒙特卡罗分析实例演示
06
输出制造文件将设计完成的PCB文件输出为制造文件，包括 Gerber文件和钻孔文件等，以供制造商生产。
20
导入网络表和布局布线
导入网络表
将原理图设计完成后生成的网络表导入到PCB设计软件中，以便
进行元器件布局和布线。
2024/1/24

ORCAD_PSPICE基础入门教程[1]

Pspice教程(基础篇)Pspice教程课程内容：在这个教程中，我们没有提到关于网络表中的Pspice的网络表文件输出，有关内容将会在后面提到!而且我想对大家提个建议：就是我们不要只看波形好不好，而是要学会分析，分析不是分析的波形，而是学会分析数据，找出自己设计中出现的问题!有时候大家可能会看到，其实电路并没有错，只是有时候我们的仿真设置出了问题，需要修改。

有时候是电路的参数设计的不合理，也可能导致一些莫明的错误!我觉得大家做一个分析后自己看看OutFile文件!点一．直流分析直流分析：PSpice可对大信号非线性电子电路进行直流分析。

它是针对电路中各直流偏压值因某一参数（电源、元件参数等等）改变所作的分析，直流分析也是交流分析时确定小信号线性模型参数和瞬态分析确定初始值所需的分析。

模拟计算后，可以利用Probe功能绘出V o- Vi曲线，或任意输出变量相对任一元件参数的传输特性曲线。

首先我们开启Capture / Capture CIS.打开如下图所示的界面( Fig.1)。

( Fig 1)我们来建立一个新的一程，如下方法打开! ( Fig.2)( Fig.2)我们来选取一个新建的工程文件!我们可以看到以下的提示窗口。

(Fig.3)(Fig.3)我们可以给这个工程取个名字，因为我们要做Pspice仿真，所以我们要勾选第一个选项，在标签栏中选中!其它的选项是什么意思呢？Analog or Mixed A/D 数模混合仿真PC Board Wizard 系统级原理图设计Programmable Logic Wizard CPLD或FPGA设计Schematic 原理图设计接下来我们看到了Pspice工程窗口，即我们的原理图窗口属性的选择。

(Fig.4)(Fig.4)我们在Creat based upon an existing project 下可以看到几个画版工程选项!其中包括：新的空的画版，带层次原理图的画版等等。

2024版OrCAD PSpice9实用教程

A 深入学习教程内容
建议学员在掌握基础操作的前提下，深入学习教程中涉及的电路设计和
仿真分析知识，提高实际应用能力。
B
C
D
交流与分享经验
建议学员在学习过程中积极参与交流和分享经验，与其他学员共同进步和提高。
实践与创新相结合
在学习过程中，鼓励学员将所学知识与实践相结合，尝试创新性的设计项目，提高解决问题的能力。
背景
随着电子技术的不断发展，电路设计和仿真已成为电子工程师必备的技能之一。 OrCAD PSpice9作为一款优秀的电路设计和仿真软件，被广泛应用于电子、通信、自动化等领域。
OrCAD PSpice9简介
1
OrCAD PSpice9是OrCAD公司推出的一款电路设计和仿真软件，具有强大的电路原理图绘制、电路仿真、波形分析等功能。
目管理器、属性栏等。
界面定制
02
讲解如何根据个人习惯定制界
03
分享一些提高操作效率的技巧，如快捷键使用、拖拽操作等。
基本电路元件库
01
02
03
元件库概述
介绍OrCAD PSpice9中提供的各类电路元件库，如电阻、电容、电感、二极管等。
元件库使用
需要确保电路在瞬态响应分析中已经达到稳定状态，否则会影响傅里叶变换结果的准确性。同时，需要选择合适的采样率和采样点数以获得更准确的频域信息。
04 数字电路仿真与分析
数字元件库介绍
基本逻辑门
包括与门、或门、非门等基本逻辑门电路元件。
组合逻辑元件
如加法器、减法器、比较器等组合逻辑电路元
06 高级功能与应用
参数扫描分析
定义扫描参数在电路图中选择要扫描的元件参数，并设置扫描范围和步长。

PSpice_AD完全教程与仿真实例

Cadence/OrCAD/PSpice_AD模拟仿真贾新章(2010. 5)引言：PSpice软件的发展Berkley:1972 首次推出SPICE(S imulation P rogram with I ntegrated C ircuit E mphasis) 1975 SPICE实用版(博士论文)免费推广使用。

1982 发展为电路模拟的“标准”软件。

开始有偿使用。

MicroSim:1983 用于P C机的P Spice1 (对应SPICE2G5版本)OrCAD:1998 MicroSim并入OrCAD，推出OrCAD/ PSpice8 Cadence：2000 OrCAD并入Cadence，推出PSpice9.22003 OrCAD/PSpice10增加“Advanced Analysis”高级分析功能。

2005 增加与MatLab的接口SLPS2009 版本16.3电路模拟软件PSpice工作原理一个电路能否用PSpice仿真，取决于3个条件：(1) 电路中的元器件必须有相应的模型和模型参数描述。

PSpice支持的器件模型PSpice提供的模型库中包括有20多类共3万多个商品化的器件模型参数，存放在100多个模型参数库中，供用户选用。

PSpice支持的器件模型PSpice提供的模型库中包括有20多类共3万多个商品化的器件模型参数，存放在100多个模型参数库中，供选用。

如果电路中采用了尚未包含在模型库中的元器件，PSpice 提供三种建立模型和提取模型参数的方法，供用户选用。

(1) 对于晶体管一类器件，可以调用Model Editor模块以及高级分析中的Optimizer模块，提取模型参数。

(2) 对于集成电路，可以调用Model Editor模块建立宏模型，描述该集成电路功能。

(3) 对于特殊器件（如光耦器件），可以调用ABM（Analog Behavioral Modeling），建立描述该器件功能的”黑匣子“模型，满足电路模拟仿真的要求。