Part_E1_SDIO_Simplified_Specification_Ver2.00

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SDIO spec

f in eo nIn fio nI n fTechnical Committee SD Card Associationf in eo nIn fi ne o n I nf in eo nIRevision HistoryDate Version Changes compared to previous issueApril 3, 2006 1.10 Simplified Version Initial ReleaseFebruary 8, 20072.00(1) Added method to change bus speed (Normal Speed up to 25MHzand High Speed up to 50 MHz)(2) Operational Voltage Requirement is extended to 2.7-3.6V(3) Combine sections 12 (Physical Properties) and 13 (MechanicalExtensions) and add miniSDIO to the new section 13 (Physical Properties)(4) Add Embedded SDIO ATA Standard Function Interface Code (5) Reference of Physical Ver2.00 supports SDHC combo card. (6) Some typos in Ver1.10 are fixed.f in eo nIn fi ne o n I nf in eo nI Release of SD Simplified SpecificationThe following conditions apply to the release of the SD simplified specification ("Simplified Specification") by the SD Card Association. The Simplified Specification is a subset of the complete SD Specification which is owned by the SD Card Association.Publisher:SD Association2400 Camino Ramon, Suite 375 San Ramon, CA 94583 USA Telephone: +1 (925) 275-6615 Fax: +1 (925) 886-4870 E-mail: office@Copyright Holder: The SD Card AssociationNotes:This Simplified Specification is provided on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified Specification may require a license from the SD Card Association or other third parties.Disclaimers:The information contained in the Simplified Specification is presented only as a standard specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any representations or warranties of any kind. No responsibility is assumed by the SD Card Association for any damages, any infringements of patents or other right of the SD Card Association or any third parties, which may result from its use. No license is granted by implication, estoppel or otherwise under any patent or other rights of the SD Card Association or any third party. Nothing herein shall be construed as an obligation by the SD Card Association to disclose or distribute any technical information, know-how or other confidential information to any third party.f in eo nIn fi ne o n I nf in eo nConventions Used in This DocumentNaming ConventionsSome terms are capitalized to distinguish their definition from their common English meaning. Words not capitalized have their common English meaning.Numbers and Number BasesHexadecimal numbers are written with a lower case “h” suffix, e.g., FFFFh and 80h. Binary numbers are written with a lower case “b” suffix (e.g., 10b).Binary numbers larger than four digits are written with a space dividing each group of four digits, as in 1000 0101 0010b.All other numbers are decimal.Key WordsMay: Indicates flexibility of choice with no implied recommendation or requirement.Shall: Indicates a mandatory requirement. Designers shall implement such mandatory requirements to ensure interchangeability and to claim conformance with the specification.Should: Indicates a strong recommendation but not a mandatory requirement. Designers should give strong consideration to such recommendations, but there is still a choice in implementation.Application NotesSome sections of this document provide guidance to the host implementers as follows: Application Note:This is an example of an application note.f in eo nIn fi ne o n I nf in eo nTable of Contents1. General Description.................................................................................................................................1 1.1 SDIO Features....................................................................................................................................1 1.2 Primary Reference Document.............................................................................................................1 1.3 Standard SDIO Functions....................................................................................................................1 2. SDIO Signaling Definition........................................................................................................................2 2.1 SDIO Card Types................................................................................................................................2 2.2 SDIO Card modes...............................................................................................................................2 2.2.1 SPI (Card mandatory support).....................................................................................................2 2.2.2 1-bit SD Data Transfer Mode (Card Mandatory Support).............................................................2 2.2.3 4-bit SD Data Transfer Mode (Mandatory for High-Speed Cards, Optional for Low-Speed).........2 2.3 SDIO Host Modes...............................................................................................................................2 2.4 Signal Pins..........................................................................................................................................3 3. SDIO Card Initialization............................................................................................................................4 3.1 Differences in I/O card Initialization.....................................................................................................4 3.2 The IO_SEND_OP_COND Command (CMD5).................................................................................10 3.3 The IO_SEND_OP_COND Response (R4)........................................................................................11 3.4 Special Initialization considerations for Combo Cards.......................................................................12 3.4.1 Re-initialize both I/O and Memory..............................................................................................12 3.4.2 Using a Combo Card as SDIO only or SD Memory only after Combo Initialization....................12 3.4.3 Acceptable Commands after Initialization..................................................................................12 3.4.4 Recommendations for RCA after Reset.....................................................................................12 3.4.5 Enabling CRC in SPI Combo Card.............................................................................................14 4. Differences with SD Memory Specification..........................................................................................15 4.1 SDIO Command List.........................................................................................................................15 4.2 Unsupported SD Memory Commands...............................................................................................15 4.3 Modified R6 Response......................................................................................................................16 4.4 Reset for SDIO..................................................................................................................................16 4.5 Bus Width..........................................................................................................................................16 4.6 Card Detect Resistor.........................................................................................................................17 4.7 Timings..............................................................................................................................................17 4.8 Data Transfer Block Sizes.................................................................................................................18 4.9 Data Transfer Abort...........................................................................................................................18 4.9.1 Read Abort.................................................................................................................................18 4.9.2 Write Abort.................................................................................................................................18 4.10 Changes to SD Memory Fixed Registers..........................................................................................18 4.10.1 OCR Register.............................................................................................................................19 4.10.2 CID Register...............................................................................................................................19 4.10.3 CSD Register.............................................................................................................................19 4.10.4 RCA Register.............................................................................................................................19 4.10.5 DSR Register.............................................................................................................................19 4.10.6 SCR Register.............................................................................................................................19 4.10.7 SD Status...................................................................................................................................19 4.10.8 Card Status Register..................................................................................................................19 5. New I/O Read/Write Commands............................................................................................................21 5.1 IO_RW_DIRECT Command (CMD52)..............................................................................................21 5.2 IO_RW_DIRECT Response (R5)......................................................................................................22 5.2.1 CMD52 Response (SD modes)..................................................................................................22 5.2.2 R5, IO_RW_DIRECT Response (SPI mode).............................................................................23 5.3 IO_RW_EXTENDED Command (CMD53). (24)f in eo nIn fi ne o n I nf in eo nI 5.3.2 Special Timing for CMD53 Multi-Block Read..............................................................................25 6. SDIO Card Internal Operation................................................................................................................26 6.1 Overview...........................................................................................................................................26 6.2 Register Access Time........................................................................................................................26 6.3 Interrupts...........................................................................................................................................26 6.4 Suspend/Resume..............................................................................................................................27 6.5 Read Wait..........................................................................................................................................27 6.6 CMD52 During Data Transfer............................................................................................................27 6.7 SDIO Fixed Internal Map...................................................................................................................27 6.8 Common I/O Area (CIA)....................................................................................................................28 6.9 Card Common Control Registers (CCCR).........................................................................................28 6.10 Function Basic Registers (FBR)........................................................................................................35 6.11 Card Information Structure (CIS).......................................................................................................37 6.12 Multiple Function SDIO Cards...........................................................................................................37 6.13 Setting Block Size with CMD53.........................................................................................................37 6.14 Bus State Diagram............................................................................................................................38 7. Embedded I/O Code Storage Area (CSA).............................................................................................39 7.1 CSA Access.......................................................................................................................................39 7.2 CSA Data Format..............................................................................................................................39 8. SDIO Interrupts.......................................................................................................................................40 8.1 Interrupt Timing.................................................................................................................................40 8.1.1 SPI and SD 1-bit Mode Interrupts ..............................................................................................40 8.1.2 SD 4-bit Mode............................................................................................................................40 8.1.3 Interrupt Period Definition ..........................................................................................................40 8.1.4 Interrupt Period at the Data Block Gap in 4-bit SD Mode (Optional)..........................................40 8.1.5 Inhibited Interrupts (Removed Section)......................................................................................40 8.1.6 End of Interrupt Cycles...............................................................................................................40 8.1.7 Terminated Data Transfer Interrupt Cycle ..................................................................................41 8.1.8 Interrupt Clear Timing.................................................................................................................41 9. SDIO Suspend/Resume Operation........................................................................................................42 10. SDIO Read Wait Operation.....................................................................................................................43 11. Power Control.........................................................................................................................................44 11.1 Power Control Overview....................................................................................................................44 11.2 Power Control support for SDIO Cards.............................................................................................44 11.2.1 Master Power Control ................................................................................................................44 11.2.2 Power Selection.........................................................................................................................45 11.2.3 High-Power Tuples.....................................................................................................................45 11.3 Power Control Support for the SDIO Host.........................................................................................45 11.3.1 Version 1.10 Host.......................................................................................................................45 11.3.2 Power Control Operation............................................................................................................46 12. High-Speed Mode...................................................................................................................................47 12.1 SDIO High-Speed Mode....................................................................................................................47 12.2 Switching Bus Speed Mode in a Combo Card...................................................................................47 13. SDIO Physical Properties......................................................................................................................48 13.1 SDIO Form Factors...........................................................................................................................48 13.2 Full-Size SDIO ..................................................................................................................................48 13.3 miniSDIO...........................................................................................................................................48 14. SDIO Power.............................................................................................................................................48 14.1 SDIO Card Initialization Voltages......................................................................................................48 14.2 SDIO Power Consumption................................................................................................................48 15. Inrush Current Limiting..........................................................................................................................50 16. CIS Formats.. (51)f in eo nIn fi ne o n I nf in eo nI 16.2 Basic Tuple Format and Tuple Chain Structure.................................................................................51 16.3 Byte Order Within Tuples ..................................................................................................................51 16.4 Tuple Version ....................................................................................................................................52 16.5 SDIO Card Metaformat......................................................................................................................52 16.6 CISTPL_MANFID: Manufacturer Identification String Tuple..............................................................53 16.7 SDIO Specific Extensions..................................................................................................................53 16.7.1 CISTPL_FUNCID: Function Identification Tuple.........................................................................53 16.7.2 CISTPL_FUNCE: Function Extension Tuple..............................................................................54 16.7.3 CISTPL_FUNCE Tuple for Function 0 (common).......................................................................54 16.7.4 CISTPL_FUNCE Tuple for Function 1-7....................................................................................55 16.7.5 CISTPL_SDIO_STD: Function is a Standard SDIO Function.....................................................58 16.7.6 CISTPL_SDIO_EXT: Tuple Reserved for SDIO Cards...............................................................58 Appendix A.....................................................................................................................................................59 A.1 SD and SPI Command List....................................................................................................................59 Appendix B.....................................................................................................................................................61 B.1 Normative References...........................................................................................................................61 Appendix C.....................................................................................................................................................62 C.1 Abbreviations and Terms...................................................................................................................62 Appendix D.. (64)f in eo nIn fi ne o n I nf in eo nI Table of TablesTable 3-1 OCR Values for CMD5.....................................................................................................................10 Table 4-1 Unsupported SD Memory Commands.............................................................................................16 Table 4-2 R6 response to CMD3.....................................................................................................................16 Table 4-3 SDIO R6 Status Bits.........................................................................................................................16 Table 4-4 Combo Card 4-bit Control................................................................................................................17 Table 4-5 Card Detect Resistor States.............................................................................................................17 Table 4-6 is blanked.........................................................................................................................................17 Table 4-7 SDIO Status Register Structure .......................................................................................................20 Table 5-1 Flag data for IO_RW_DIRECT SD Response..................................................................................23 Table 5-2 IO_RW_ EXTENDED command Op Code Definition.......................................................................24 Table 5-3 Byte Count Values ...........................................................................................................................25 Table 6-1 Card Common Control Registers (CCCR).......................................................................................29 Table 6-2 CCCR bit Definitions........................................................................................................................34 Table 6-3 Function Basic Information Registers (FBR)....................................................................................35 Table 6-4 FBR bit and field definitions.............................................................................................................36 Table 6-5 Card Information Structure (CIS) and reserved area of CIA.............................................................37 Table 11-1 Reference Tuples by Master Power Control and Power Select......................................................45 Table 16-1 Basic Tuple Format........................................................................................................................51 Table 16-2 Tuples Supported by SDIO Cards..................................................................................................52 Table 16-3 CISTPL_MANFID: Manufacturer Identification Tuple.....................................................................53 Table 16-4 CISTPL_FUNCID Tuple.................................................................................................................53 Table 16-5 CISTPL_FUNCE Tuple General Structure.....................................................................................54 Table 16-6 TPLFID_FUNCTION Tuple for Function 0 (common)....................................................................54 Table 16-7 TPLFID_FUNCTION Field Descriptions for Function 0 (common).................................................54 Table 16-8 TPLFID_FUNCTION Tuple for Function 1-7..................................................................................55 Table 16-9 TPLFID_FUNCTION Field Descriptions for Functions 1-7.............................................................57 Table 16-10 TPLFE_FUNCTION_INFO Definition...........................................................................................57 Table 16-11 TPLFE_CSA_PROPERTY Definition...........................................................................................57 Table 16-12 CISTPL_SDIO_STD: Tuple Reserved for SDIO Cards................................................................58 Table 16-13 CISTPL_SDIO_EXT: Tuple Reserved for SDIO Cards.................................................................58 Table A-14 SD Mode Command List................................................................................................................59 Table A-15 SPI Mode Command List (60)f in eo nIn fi ne o n I nf in eo nI Table of FiguresFigure 2-1 Signal connection to two 4-bit SDIO cards.......................................................................................3 Figure 3-1 SDIO response to non-I/O aware initialization..................................................................................4 Figure 3-2 Card initialization flow in SD mode (SDIO aware host)....................................................................7 Figure 3-3 Card initialization flow in SPI mode (SDIO aware host)....................................................................9 Figure 3-4 IO_SEND_OP_COND Command (CMD5).....................................................................................10 Figure 3-5 Response R4 in SD mode...............................................................................................................11 Figure 3-6 Response R4 in SPI mode..............................................................................................................11 Figure 3-7 Modified R1 Response....................................................................................................................11 Figure 3-8 Re-Initialization Flow for I/O Controller...........................................................................................13 Figure 3-9 Re-Initialization Flow for Memory controller ...................................................................................13 Figure 5-1 IO_RW_DIRECT Command...........................................................................................................21 Figure 5-2 R5 IO_RW_DIRECT Response (SD modes)..................................................................................22 Figure 5-3 IO_RW_DIRECT Response in SPI Mode.......................................................................................23 Figure 5-4 IO_RW_EXTENDED Command.....................................................................................................24 Figure 6-1 SDIO Internal Map..........................................................................................................................28 Figure 6-2 State Diagram for Bus State Machine (38)f in eo nIn fi ne o n I nf in eo nI 1. General DescriptionThe SDIO (SD Input/Output) card is based on and compatible with the SD memory card. This compatibility includes mechanical, electrical, power, signaling and software. The intent of the SDIO card is to provide high-speed data I/O with low power consumption for mobile electronic devices. A primary goal is that an SDIO card inserted into a non-SDIO aware host shall cause no physical damage or disruption of that host or it’s software. In this case, the SDIO card should simply be ignored. Once inserted into an SDIO aware host, the detection of the card proceeds via the normal means described in this specification with some extensions. In this state, the SDIO card is idle and draws a small amount of power (15 mA averaged over 1 second). During the normal initialization and interrogation of the card by the host, the card identifies itself as an SDIO card. The host software then obtains the card information in a tuple (linked list) format and determines if that card’s I/O function(s) are acceptable to activate. This decision is based on such parameters as power requirements or the availability of appropriate software drivers. If the card is acceptable, it is allowed to power up fully and start the I/O function(s) built into it.1.1 SDIO Features• Targeted for portable and stationary applications• Minimal or no modification to SD Physical bus is required • Minimal change to memory driver software• Extended physical form factor available for specialized applications • Plug and play (PnP) support• Multi-function support including multiple I/O and combined I/O and memory • Up to 7 I/O functions plus one memory supported on one card. • Allows card to interrupt host• Operational Voltage range: 2.7-3.6V (Operational Voltage is used for Initialization) • Application Specifications for Standard SDIO Functions. • Multiple Form Factors:• Full-Size SDIO • miniSDIO1.2 Primary Reference DocumentThis specification is based on and refers extensively to the SDA document:SD Memory Card SpecificationsPart 1 PHYSICAL LAYER SPECIFICATION Version 2.00 May 9, 2006The reader is directed to this document for more information on the basic operation of SD cards. In addition, other documents are referenced in this specification. A complete list can be found in appendix B.1.This specification can apply to any released versions of Physical Layer Specification after Version 2.00.1.3 Standard SDIO FunctionsAssociated with the base SDIO specification, there are several Application Specifications for Standard SDIO Functions. These common functions such as cameras, Bluetooth cards and GPS receivers have a standard register interface, a common operation method and a standard CIS extension. Implementation of the standard interfaces are optional for any card vendor, but compliance with the standard allows the use of standard drivers and applications which will increase the appeal of these cards to the consumer. Full information on these standard interfaces can be found in the Application Specifications for Standard SDIO Functions maintained by the SDA.。

Part_E1_SDIO_Simplified_Specifcation_Ver3.00_20110225

Technical Committee SD Card AssociationRevision HistoryDate Version Changes compared to previous issueApril 3, 2006 1.10 The first release of the SDIO Simplified SpecificationFebruary 8, 2007 2.00 Followings functions are added in this version(1) Added method to change bus speed (Normal Speed up to 25MHz andHigh Speed up to 50 MHz)(2) Operational Voltage Requirement is extended to 2.7-3.6V(3) Combine sections 12 (Physical Properties) and 13 (MechanicalExtensions) and add miniSDIO to the new section 13 (PhysicalProperties)(4) Add Embedded SDIO ATA Standard Function Interface Code(5) Reference of Physical Ver2.00 supports SDHC combo card.(6) Some typos in Ver1.10 are fixed.February 25, 2011 3.00 Followings functions are added in this version(1) Definition of Embedded SDIO(2) Ultra High Speed Bus Speed Mode (UHS-I)(3) Power Control Extension (Power State Control)(4) Asynchronous Interrupt in 4-bit mode(5) Shared Bus for supporting multiple devices(6) Interface Signal of Embedded Device applicable to Shared BusAsynchronous Interrupt is not included in this document.Release of SD Simplified SpecificationThe following conditions apply to the release of the SD simplified specification ("Simplified Specification") by the SD Card Association. The Simplified Specification is a subset of the complete SD Specification which is owned by the SD Card Association.Publisher and Copyright Holder:SD Card Association2400 Camino Ramon, Suite 375San Ramon, CA 94583 USATelephone: +1 (925) 275-6615,Fax: +1 (925) 886-4870E-mail: office@Notes:This Simplified Specification is provided on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified Specification may require a license from the SD Card Association or other third parties.Disclaimers:The information contained in the Simplified Specification is presented only as a standard specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any representations or warranties of any kind. No responsibility is assumed by the SD Card Association for any damages, any infringements of patents or other right of the SD Card Association or any third parties, which may result from its use. No license is granted by implication, estoppel or otherwise under any patent or other rights of the SD Card Association or any third party. Nothing herein shall be construed as an obligation by the SD Card Association to disclose or distribute any technical information, know-how or other confidential information to any third party.Conventions Used in This DocumentNaming Conventions•Some terms are capitalized to distinguish their definition from their common English meaning. Words not capitalized have their common English meaning.Numbers and Number Bases•Hexadecimal numbers are written with a lower case "h" suffix, e.g., FFFFh and 80h.•Binary numbers are written with a lower case "b" suffix (e.g., 10b).•Binary numbers larger than four digits are written with a space dividing each group of four digits, as in 1000 0101 0010b.•All other numbers are decimal.Key Words•May: Indicates flexibility of choice with no implied recommendation or requirement.•Shall: Indicates a mandatory requirement. Designers shall implement such mandatory requirements to ensure interchangeability and to claim conformance with the specification.•Should: Indicates a strong recommendation but not a mandatory requirement. Designers should give strong consideration to such recommendations, but there is still a choice in implementation. Application NotesSome sections of this document provide guidance to the host implementers as follows:Application Note:This is an example of an application note.Table of Contents1. General Description (1)1.1 Definitions (1)1.1.1 SDIO Card (1)1.1.2 Embedded SDIO (1)1.2 SDIO Features (1)1.2.1 Common SDIO Features (1)1.2.2 SDIO Card Features (1)1.2.3 Embedded SDIO Device Features (2)1.3 Document Structure (3)1.4 Standard SDIO Functions (3)2. SDIO Signaling Definition (4)2.1 SDIO Card Types (4)2.2 SDIO Card Modes (4)2.2.1 SPI (Card mandatory support) (4)2.2.2 1-bit SD Data Transfer Mode (Card Mandatory Support) (4)2.2.3 4-bit SD Data Transfer Mode (Mandatory for High-Speed Cards, Optional for Low-Speed) (4)2.3 SDIO Host Modes (4)2.4 Signal Pins (5)2.4.1 Signal Pins for SDIO Card (5)3. SDIO Card Initialization (6)3.1 Initialization Sequence (6)3.1.1 Initialization by Non-I/O Aware Host (6)3.1.2 Initialization by I/O Aware Host (7)3.2 The IO_SEND_OP_COND Command (CMD5) (13)3.3 The IO_SEND_OP_COND Response (R4) (14)3.4 Special Initialization Considerations for Combo Cards (15)3.4.1 Re-initialize Both I/O and Memory (15)3.4.2 Using a Combo Card as SDIO only or SD Memory only after Combo Initialization (15)3.4.3 Acceptable Commands after Initialization (15)3.4.4 Recommendations for RCA after Reset (15)3.4.5 Enabling CRC in SPI Combo Card (17)4. Differences with SD Memory Specification (18)4.1 SDIO Command List (18)4.2 Memory Commands and SDIO Commands (18)4.2.1 Supported SD Memory Commands (18)4.2.2 Unsupported SD Memory Commands (18)4.3 Modified R6 Response (19)4.4 Reset for SDIO (20)4.5 Bus Width (20)4.6 Card Detect Resistor (20)4.7 Timings (21)4.8 Data Transfer Block Sizes (21)4.9 Data Transfer Abort (21)4.9.1 Read Abort (21)4.9.2 Write Abort (21)4.10 Changes to SD Memory Fixed Registers (22)4.10.1 OCR Register (22)4.10.2 CID Register (22)4.10.3 CSD Register (22)4.10.4 RCA Register (22)4.10.5 DSR Register (22)4.10.6 SCR Register (23)4.10.7 SD Status (23)4.10.8 Card Status Register (23)5. New I/O Read/Write Commands (25)5.1 IO_RW_DIRECT Command (CMD52) (25)5.2 IO_RW_DIRECT Response (R5) (26)5.2.1 CMD52 Response (SD Modes) (26)5.2.2 R5, IO_RW_DIRECT Response (SPI mode) (27)5.3 IO_RW_EXTENDED Command (CMD53) (28)5.3.1 CMD53 Data Transfer Format (29)5.3.2 Special Timing for CMD53 Multi-Block Read (29)6. SDIO Card Internal Operation (30)6.1 Overview (30)6.2 Register Access Time (30)6.3 Interrupts (30)6.4 Suspend/Resume (31)6.5 Read Wait (31)6.6 CMD52 During Data Transfer (31)6.7 SDIO Fixed Internal Map (31)6.8 Common I/O Area (CIA) (32)6.9 Card Common Control Registers (CCCR) (32)6.10 Function Basic Registers (FBR) (43)6.11 Card Information Structure (CIS) (46)6.12 Multiple Function SDIO Cards (46)6.13 Setting Block Size with CMD53 (46)6.14 Bus State Diagram (47)7. Embedded I/O Code Storage Area (CSA) (48)7.1 CSA Access (48)7.2 CSA Data Format (48)8. SDIO Interrupts (49)8.1 Interrupt Timing (49)8.1.1 SPI and SD 1-bit Mode Interrupts (49)8.1.2 SD 4-bit Mode (49)8.1.3 Interrupt Period Definition (49)8.1.4 Interrupt Period at the Data Block Gap in 4-bit SD Mode (Optional) (49)8.1.5 End of Interrupt Cycles (49)8.1.6 Terminated Data Transfer Interrupt Cycle (50)8.1.7 Interrupt Clear Timing (50)8.2 Asynchronous Interrupt (50)9. SDIO Suspend/Resume Operation (51)10. Timing to Pause SDIO Read Operation (52)10.1 Pause Read Operation by Stopping SDCLK (52)10.2 Pause Read Operation by using Read Wait (52)11. Power Control (53)11.1 Power Control Overview (53)11.2 Details of SDIO Power Control (53)11.2.1 Master Power Control (53)11.2.2 Power Selection (54)11.2.3 Power State Control (54)11.2.4 High-Power Tuples (54)11.2.5 The Maximum Card Power Restricted by Tc (55)11.3 Power Control Support for the SDIO Host (56)11.3.1 Version 1.10 Host (56)11.3.2 Version 3.00 Host (56)12. High-Speed Mode (57)12.1 SDIO High-Speed Mode (57)12.2 Switching Bus Speed Mode in a Combo Card (57)13. SDIO Physical Properties (58)13.1 SDIO Form Factors (58)13.2 Full-Size SDIO (58)13.3 miniSDIO (58)13.4 microSDIO (58)14. SDIO Power (59)14.1 SDIO Card Initialization Voltages (59)14.2 SDIO Power Consumption (59)15. Inrush Current Limiting (60)16. CIS Formats (61)16.1 CIS Reference Document (61)16.2 Basic Tuple Format and Tuple Chain Structure (61)16.3 Byte Order Within Tuples (61)16.4 Tuple Version (62)16.5 SDIO Card Metaformat (62)16.6 CISTPL_MANFID: Manufacturer Identification String Tuple (63)16.7 SDIO Specific Extensions (63)16.7.1 CISTPL_FUNCID: Function Identification Tuple (63)16.7.2 CISTPL_FUNCE: Function Extension Tuple (63)16.7.3 CISTPL_FUNCE Tuple for Function 0 (Extended Data 00h) (64)16.7.4 CISTPL_FUNCE Tuple for Function 1-7 (Extended Data 01h) (65)16.7.5 CISTPL_FUNCE Tuple for Function 1-7 (Extended Data 02h) (68)16.7.6 CISTPL_SDIO_STD: Function is a Standard SDIO Function (69)16.7.7 CISTPL_SDIO_EXT: Tuple Reserved for SDIO Cards (70)17. Embedded SDIO (71)17.1 Relaxing SDIO Requirements for Embedded Device (71)17.1.1 Form Factor (71)17.1.2 CIS Information (71)17.1.3 8-Bit Bus Mode (71)17.2 Interface Signal for Embedded SDIO Device (71)17.3 Shared Bus Configuration (71)Appendix A (Normative) : Reference (73)A.1 Reference (73)Appendix B (Normative) : Special Terms (74)B.1 Terminology (74)B.2 Abbreviations (74)Appendix C (Normative) : Command List (76)C.1 SD Mode Command List (76)C.2 SPI Mode Command List (77)Appendix D (Normative) (78)Table of TablesTable 3-1 : OCR Values for CMD5 (13)Table 4-1 : Supported SD Memory Commands (18)Table 4-2 : Unsupported SD Memory Commands (19)Table 4-3 : R6 response to CMD3 (19)Table 4-4 : SDIO R6 Status Bits (19)Table 4-5 : Combo Card 4-bit Control (20)Table 4-6 : Card Detect Resistor States (21)Table 4-7 : SDIO Status Register Structure (24)Table 5-1 : Flag Data for IO_RW_DIRECT SD Response (27)Table 5-2 : IO_RW_ EXTENDED command Op Code Definition (28)Table 5-3 : Byte Count Values (29)Table 6-1 : Card Common Control Registers (CCCR) (33)Table 6-2 : CCCR bit Definitions (42)Table 6-3 : Function Basic Information Registers (FBR) (43)Table 6-4 : FBR bit and field definitions (45)Table 6-5 : Card Information Structure (CIS) and reserved area of CIA (46)Table 11-1 : Reference of Tuples Depends on Host Version (55)Table 16-1 : Basic Tuple Format (61)Table 16-2 : Tuples Supported by SDIO Cards (62)Table 16-3 : CISTPL_MANFID: Manufacturer Identification Tuple (63)Table 16-4 : CISTPL_FUNCID Tuple (63)Table 16-5 : CISTPL_FUNCE Tuple General Structure (64)Table 16-6 : TPLFID_FUNCTION Tuple for Function 0 (Common) (64)Table 16-7 : TPLFID_FUNCTION Field Descriptions for Function 0 (common) (65)Table 16-8 : TPLFID_FUNCTION Tuple for Function 1-7 (High Power Tuple) (66)Table 16-9 : TPLFID_FUNCTION Field Descriptions for Functions 1-7 (68)Table 16-10 : TPLFE_FUNCTION_INFO Definition (68)Table 16-11 : TPLFE_CSA_PROPERTY Definition (68)Table 16-12 : TPLFID_FUNCTION Tuple for Function 1-7 (Power State Tuple) (68)Table 16-13 : TPLFID_FUNCTION Field Descriptions for Functions 1-7 (Power State Tuple) (69)Table 16-14 : CISTPL_SDIO_STD: Tuple Reserved for SDIO Cards (69)Table 16-15 : TPL_CODE CISTPL_SDIO_STD Definition (69)Table 16-16 : CISTPL_SDIO_EXT: Tuple Reserved for SDIO Cards (70)Table C- 1 : SD Mode Command List (76)Table C- 2 : SPI Mode Command List (77)©Copyright 2000-2011 SD Card Association SDIO Simplified Specification Version 3.00Table of FiguresFigure 1-1 : SDIO Related Specifications (3)Figure 2-1 : Signal connection to two 4-bit SDIO cards (5)Figure 3-1 : SDIO Response to Non-I/O Aware Initialization (6)Figure 3-2 : Card Initialization Flow in SD mode (SDIO Aware Host) (9)Figure 3-3 : Card initialization flow in SPI mode (SDIO aware host) (12)Figure 3-4 : IO_SEND_OP_COND Command (CMD5) (13)Figure 3-5 : Response R4 in SD mode (14)Figure 3-6 : Response R4 in SPI mode (14)Figure 3-7 : Modified R1 Response (14)Figure 3-8 : Re-Initialization Flow for I/O Controller (16)Figure 3-9 : Re-Initialization Flow for Memory controller (16)Figure 5-1 : IO_RW_DIRECT Command (25)Figure 5-2 : R5 IO_RW_DIRECT Response (SD Modes) (26)Figure 5-3 : IO_RW_DIRECT Response in SPI Mode (27)Figure 5-4 : IO_RW_EXTENDED Command (28)Figure 6-1 : SDIO Internal Map (32)Figure 6-2 : State Diagram for Bus State Machine (47)Figure 8-1 : Continuous Interrupt Cycle (49)Figure 17-1 : Embedded SDIO Interface (71)Figure 17-2 : Example Configuration Supporting Card Slot and Shared Bus (72)Figure 17-3 : Device Select Using Clock Signal (72)1. General DescriptionThis Part E1 SDIO (SD Input/Output) Specification defines the SD bus interface specification for SDIO including register specification. Not only is the SDIO Card defined, but also the Embedded SDIO Device and Combo Card are defined. SDIO is based on the Physical Layer Specification and the SDIO Specification provides extension and modification of the Physical Layer Specification for SDIO card and device.1.1 Definitions1.1.1 SDIO CardThe SDIO (SD Input/Output) card is a removable product that utilizes the SD bus and SD commands. The same form factor as a memory card can be used and an extended form factor for SDIO card is defined by the SDIO Specification. (No extended form factor is defined for microSDIO in this version.)The SDIO Card shall comply with the Part E1 SDIO Specification and the Part 1 Physical Layer Specification (The SDIO Specification provides extension and modification of the Physical Layer specification for SDIO.The SDIO Specification takes precedence).The SDIO card shall have compatibility to the SD Memory Card regarding SD Bus pins layout, electrical, power and signaling. The SPI mode is mandatory in the SDIO Cards but not all features may be available in SPI mode.1.1.2 Embedded SDIOAn Embedded SDIO Device is a product that utilizes the SD bus and SD commands."Embedded" is defined as a permanently soldered on a PCB (Printed Circuit Board) non-removable device or mounted through a socket permanently soldered on a PCB such that the Embedded SDIO Device can't be removed by end users.The Embedded SDIO Device shall comply with the Part E1 SDIO Specification and the Part 1 Physical Layer Specification. (The SDIO Specification provides extension and modification of the Physical Layer specification for SDIO card and device. The SDIO Specification takes precedence.) When standard interface specification (for example, host interface voltage and timing) is required, SDIO card and device should follow the Part 1 eSD Addendum.The Embedded SDIO Device may be any form factor and any pin layout. The SPI mode is optional in the Embedded SDIO Devices. Not all features may be available in SPI mode.1.2 SDIO Features1.2.1 Common SDIO Features•Targeted for portable and stationary applications•Minimal or no modification to the SD Physical bus is required•Minimal change to the memory initialization sequence.•Multi-function support including multiple I/O and combined I/O and memory•Up to 7 I/O functions plus one memory function is supported on one card.•An interrupt is supported to request the host to service to an event• Standard Application Specifications for Standard SDIO Functions can be defined by Part Ex•Card information is provided by Tuples.1.2.2 SDIO Card Features•Supply Voltage range: 2.7-3.6V (Operational Voltage is used for Initialization)•Removable and Plug and play (PnP) support•Multiple Form Factors:•Standard-Size SDIO (Extended form factor can be used)•miniSDIO (Extended form factor can be used)• microSDIO• A card per slot connection1.2.3 Embedded SDIO Device Features•Supply Voltage range: 2.7-3.6V or 1.7-1.95V.•Non removable device.•Any form factor and any pin layout•Shared Bus connection is possible1.3 Document StructureReference documents are described in the Appendix A.SDIO Specification describes modifications of the Physical Layer Specification and new functions for SDIO.The standard card form factors are defined in the Part 1 Mechanical Addenda. The extended card form factors for Standard-Size SDIO card are defined in the SDIO Specification.This specification refers any released versions of the Physical Layer Specification Version 3.00 and later and the eSD Addendum Version 2.10 and later.1.4 Standard SDIO FunctionsFigure 1-1 shows the SDIO related specifications. The SDIO bus specification is defined by the Physical Layer specification and this SDIO specification. The Memory portion of a Combo card is specified by the Physical Layer specification. An SDIO and a Combo Card have an SDIO function on the backend.Associated with the base SDIO specification, there are several Application Specifications for Standard SDIO Functions. The feature of SDIO is determined by a SDIO function. Card driver and application software are required to control the function. There are two SDIO function types: standard SDIO function and non standard SDIO function.The standard functions such as cameras, Bluetooth cards and GPS receivers have a standard register interface, a common operation method and a standard CIS extension. By defining a standard register interface for a specific function, an OS vendor can provide a standard card driver, application software and API for the functions. Full information on the standard functions is defined by Part E2 to Part E6.In the case of non standard SDIO functions, a card or device manufacturer needs to provide a card driver.The user may need to install the card driver and the application software to use the non standard SDIO function. Implementation of the non standard register interfaces is optional for any card vendor, but compliance with the standard allows the use of standard drivers and applications.Figure 1-1 : SDIO Related SpecificationsIn the following Chapters and Sections, the term "card" needs to be interpreted as not only "SDIO Card and Combo Card" but also "Embedded SDIO Device" unless otherwise noted.2. SDIO Signaling Definition2.1 SDIO Card TypesThis specification defines two types of SDIO cards. The Full-Speed card supports SPI, 1-bit SD and the 4-bit SD transfer modes at the full clock range of 0-25MHz. Full-Speed SDIO cards have a data transfer rate of over 100 Mb/second (10 MB/Sec). The second version of the SDIO card is the Low-Speed SDIO card. This card requires only the SPI and 1-bit SD transfer modes. 4-bit support is optional. In addition, Low-Speed SDIO cards shall support a full clock range of 0-400 KHz. The intended use of Low-Speed cards is to support low-speed I/O capabilities with a minimum of hardware. The Low-Speed cards support such functions as modems, bar-code scanners, GPS receivers etc. If a card is a 'Combo card' (memory plus SDIO) then Full-Speed and 4-bit operation is mandatory for both the memory and SDIO portions of the card.2.2 SDIO Card ModesThere are three bus modes defined for SD memory cards that also apply to SDIO Cards:2.2.1 SPI (Card mandatory support)The SPI bus topology is defined in Section 3.5.2 and the protocol is defined in Sections 3.6.2 and Chapter 7 of the Physical Layer Specification Version 3.0x. In this mode pin 8, which is undefined for memory, is used as the interrupt pin. All other pins and signaling protocols are identical to the Physical Layer Specification.New functions defined after the SDIO Version 2.00 may not be supported in the SPI mode.2.2.2 1-bit SD Data Transfer Mode (Card Mandatory Support)This mode is identical to the 1 data bit (narrow) mode defined for SD Memory in Section 3.6.1 of the Physical Layer Specification. In this mode, data is transferred on the DAT[0] pin only. In this mode pin 8, which is undefined for memory, is used as the interrupt pin and pin 9, which is undefined for memory, is used as the read wait pin. All other pins and signaling protocols are identical to the Physical Layer Specification.2.2.3 4-bit SD Data Transfer Mode (Mandatory for High-Speed Cards, Optional forLow-Speed)This mode is identical to the 4 data bit mode (wide) defined for SD Memory in Section 3.6.1 of the Physical Layer Specification. In this mode, data is transferred on all 4 data pins (DAT[3:0]). In this mode the interrupt pin is not available for exclusive use as it is utilized as a data transfer line. Thus, if the interrupt function is required, special timing is required to provide interrupts. Refer to Section 8.1.2 for details of this operation.UHS-I bus speed mode has been added from SDIO Version 3.00 onward. The 4-bit SD mode provides the highest data transfer possible, up to 104 MB/sec.2.3 SDIO Host ModesIf a SDIO aware host supports the SD transfer mode, it is recommended that both the 1-bit and 4-bit modes be supported. While an SDIO host that supports only the 4-bit transfer mode is possible, its performance witha Low-Speed SDIO card may be reduced. This is because the only means to transfer data to and from aLow-Speed card would be the single byte per command transfer (using the IO_RW_DIRECT command (CMD52), refer to Section 5.1).2.4 Signal Pins2.4.1 Signal Pins for SDIO CardThe rest of this chapter is not included in the Simplified Specification.3. SDIO Card Initialization3.1 Initialization Sequence3.1.1 Initialization by Non-I/O Aware HostA requirement for the SDIO specification is that an SDIO card shall not cause non-I/O aware hosts to failwhen inserted. In order to prevent operation of I/O functions in non-I/O aware hosts, a change to the SD card identification mode flowchart is needed. A new command (IO_SEND_OP_COND, CMD5) is added to replace the ACMD41 for SDIO initialization by I/O aware hosts (Refer to Section 3.2).After reset or power-up, all I/O functions on the card are disabled and the I/O portion of the card shall not execute any operation except CMD5 or CMD0 with CS=low. If there is SD memory on the card (also called a combo card), that memory shall respond normally to all mandatory memory commands.An I/O only card shall not respond to the ACMD41 command. The host shall then give up and disable this card. Thus, the non-aware host receives no response from an I/O only card and forces it to the inactive state.The operation of an I/O card with a non-I/O aware host is shown in Figure 3-1 Note that the solid lines are the actual paths taken while the dashed lines are not executed.Figure 3-1 : SDIO Response to Non-I/O Aware Initialization3.1.2 Initialization by I/O Aware HostAn SDIO aware host sends CMD5 prior to the CMD55/ACMD41 pair, and thus would receive a valid OCR in the R4 response to CMD5 and continue to initialize the card. Figure 3-2 shows the operation of an SDIO aware host operating in the SD modes and Figure 3-3 shows the same operation for a host that operates in the SPI mode.If the I/O portion of a card has received no CMD5, the I/O Section remains inactive and shall not respond to any command except CMD5. A combo card stays in the memory-only mode. If no memory is included on the card, the card would not respond to any memory command. If the I/O aware host sends a CMD5 to the card, the card responds with R4. The host then reads that R4 value and knows the number of available I/O functions and if any SD memory exists.A host that supports UHS-I sets S18R to 1 in the argument of CMD5 to request a change of the signal voltage to 1.8V. If the card supports UHS-I and the current signal voltage is 3.3V, S18A is set to 1 in the R4 response. If the signal voltage is already 1.8V, the card sets S18A to 0 so that host maintains the current signal voltage. UHS-I is supported in SD mode and S18A is always 0 in SPI mode.After the host has initialized the I/O portion of the card, it then reads the Common Information Area (CIA) of the card (Refer to Section 6.8). This is done by issuing a read command, starting with the byte at address 00h, of I/O function 0. The CIA contains the Card Common Control Registers (CCCR) and the Function Basic Registers (FBR). Also included in the CIA are pointers to the card's common Card Information Structure (CIS) and each individual function's CIS. The CIS structure is defined in Chapter 16. The CIS includes information on power, function, manufacturer and other things the host needs to determine if the I/O function(s) is appropriate to power-up. If the host determines that the card should be activated, a register in the CCCR area enables the card and each individual function. At this time, all functions of the I/O card are fully available. In addition, the host can control the power consumption and enable/disable interrupts on a function-by-function basis. This access to I/O does not interfere with memory access to the card if present. Figure 3-2 shows Card Initialization Flow in SD mode and Figure 3-3 shows Card Initialization Flow in SPI mode. UHS-I is not supported in SPI mode. Initialization Flow for an embedded device can be simplified by removing unnecessary checks.When receiving CMD5 with arg=0, the SDIO card returns an R4 response but does not start initialization of the I/O function. The Version 3.00 SDIO card should start initialization sequence by receiving CMD5 without waiting for CMD5 with WV=0.Combo Cards can accept CMD15 with RCA=0000, as described in the Physical Layer Specification, but there is an exception for SD memory only cards. Memory only cards require a non-zero RCA before the host may issue CMD15. Thus, CMD15 shall be issued after CMD3 in the Standby state. In the case of ACMD41, it shall accept RCA=0000h.Application Notes:As shown in Figure 3-2 and Figure 3-3, an SDIO aware host should send CMD5 arg=0 as part of the initialization sequence after either Power On or a CMD 52 with write to I/O Reset. CMD5 arg=0 is required for using a removal card due to the following reasons:(1) There was 3.1V-3.5V voltage range legacy card and then whether host power supply can providethe voltage in this range should be checked.(2) There may be the card which requires CMD5 with WV= 0 to initialize the card.CMD5 arg=0 may not be necessary for embedded system if the device does not require it.Memory Initialization Skip Memory InitializationFigure 3-2 : Card Initialization Flow in SD mode (SDIO Aware Host)Memory Initialization Skip Memory InitializationFigure 3-3 : Card initialization flow in SPI mode (SDIO aware host)3.2 The IO_SEND_OP_COND Command (CMD5)Figure 3-4 : shows the format of the IO_SEND_OP_COND command (CMD5). The function of CMD5 for SDIO cards is similar to the operation of ACMD41 for SD memory cards. It is used to inquire about the voltage range needed by the I/O card. The normal response to CMD5 is R4 in either SD or SPI format. The R4 response in SD mode is shown in Figure 3-5 and the SPI version is shown in Figure 3-6.S D Command Index000101bStuff Bits S18R I/O OCR CRC7 E1 1 6 7 1 24 7 1Figure 3-4 : IO_SEND_OP_COND Command (CMD5)The IO_SEND_OP_COND Command contains the following fields:S(tart bit): Start bit. Always 0D(irection): Direction.Always1indicates transfer from host to card.Command Index: Identifies the CMD5 command with a value of 000101bStuff Bits: Not used, shall be set to 0.S18R: Switching to 1.8V RequestI/O OCR: Operation Conditions Register. The supported minimum and maximum values for VDD. The layout of the OCR is shown in Table 3-1. Refer to Section 4.10.1 foradditional information.CRC7: 7 bits of CRC dataE(nd bit): End bit, always 1I/O OCR bit position VDD Voltage Window(in Volts)0-3 Reserved4 Reserved5 Reserved6 Reserved7 Reserved8 2.0-2.19 2.1-2.210 2.2-2.311 2.3-2.412 2.4-2.513 2.5-2.614 2.6-2.715 2.7-2.816 2.8-2.917 2.9-3.018 3.0-3.119 3.1-3.220 3.2-3.321 3.3-3.422 3.4-3.523 3.5-3.6Table 3-1 : OCR Values for CMD5The SDIO Version 2.00 cards shall support the operational voltage range 2.7-3.6V and are not necessary to support the voltage range 2.0-2.7V for basic communication. The hosts, which support SDIO Version 2.00, shall not use voltage range 2.0-2.7V for basic communication.。

山石网科新一代NIDS硬件参考指南说明书

Version4.4Copyright2022Hillstone Networks.All rights reserved.Information in this document is subject to change without notice.The software described in this document is fur-nished under a license agreement or nondisclosure agreement.The software may be used or copied only in accord-ance with the terms of those agreements.No part of this publication may be reproduced,stored in a retrieval system,or transmitted in any form or any means electronic or mechanical,including photocopying and recording for any purpose other than the purchaser's personal use without the written permission of Hillstone Networks. Hillstone Networks本文档禁止用于任何商业用途。

关于本手册本手册为硬件参考指南，帮助用户正确安装山石网科的设备。

获得更多的文档资料，请访问：https://针对本文档的反馈，请发送邮件到：*************************联系信息北京苏州地址：北京市海淀区宝盛南路1号院20号楼5层地址：苏州市高新区科技城景润路181号邮编：100192邮编：215000联系我们：https:///about/contact_Hillstone.html山石网科https://TWNO:TW-HW-DS-A-CN-V4.4-4/19/2022目录目录1产品中有毒有害物质或元素的名称及含量5前言1内容简介1手册约定1第1章产品介绍2简介2主机硬件介绍2前面板介绍2后面板介绍4指示灯含义5系统参数7扩展模块介绍10扩展模块类型12接口扩展模块12Bypass模块13Bypass模块连接方法14指示灯含义15扩展模块的配置与使用16接口扩展模块的配置与使用16查看扩展模块的信息16端口属性16配置口（CON口）17 USB接口17千兆电口17 SFP接口18 SFP+接口19 CLR按键21电源21电源模块22硬盘24冷却系统24第2章设备安装前的准备工作26介绍26安装场所要求26温度/湿度要求26洁净度要求26防静电要求27电磁环境要求27接地要求27检查安装台27机柜要求28机柜尺寸和间距28机柜通风要求28机架要求28机架尺寸和承重要求28机架间距要求28机架固定要求29其它安全注意事项29安装设备、工具和电缆29第3章设备的安装30将设备安装在工作台上30将设备安装到标准机架中30使用托盘安装31使用导轨安装31线缆连接34连接地线34连接配置电缆34连接以太网线缆34连接以太网电口线缆35连接以太网光口线缆35连接交流电源线35连接直流电源线36连接电源适配器38安装完成后的检查38第4章设备的启动和配置39介绍39搭建配置环境39搭建配置口（CON口）的配置环境39搭建WebUI配置环境40搭建Telnet和SSH配置环境40设备的基本配置40第5章设备的硬件维护42介绍42开机42关机42电源模块的安装与拆卸43扩展模块的安装与拆卸44第6章常见故障处理46介绍46口令丢失情况下的处理46电源系统故障处理46配置系统故障处理46产品中有毒有害物质或元素的名称及含量注：并非上述所有部件都含有在内装产品中。

SDI-ASI光端机安装操作手册_V2

重要声明
无论何时本手册进行再版或修订，再版或修订的理由将会在此页进行说明。
©版权所有
四通光通信, 2006

1
Model-SDI/ASI 一、概述：
安装操作手册
ISSUE 1
(010-SDI-01G0606)
SOC-SDI⁄ASI 系列广播专业非压缩数字视频光端机，使用世界最先数字视频信号处理技术芯片，电磁兼容(EMC)设计。输入自动均衡，时钟再生，低抖动。对 SDI 和 DVB-ASI 输入信号，具有抖动自动修复功能。符合国家广电总局批准发布的 GY/T 164-2000 演播室串行数字光纤传输系统，国际 SMPTE259M、DVB-ASI、SMPTE310M、SMPTE344M 等所有 SDTV 数字视频格式的规范要求。
对应连接到 CWDM 模块的相同光波长编号。 z CWDM 模块的 COM 光接口，连接到传输光纤线路上即可。 z 光接口，SC/PC。
©版权所有
四通光通信, 2006

7
Model-SDI/ASI 五、 RS485网管协议说明
安装操作手册
ISSUE 1
(010-SDI-01G0606)
2) 光接收机
第1路
第2路
第3路
SDI/ASI OPTICAL RECEIVER
SDI/ASI 光接收机
1 PWR LOS SD DATA
2 PWR LOS SD DATA
3 PWR LOS SD DATA
电源指示灯输入光信号指示灯
信号旁通指示灯信号锁定指示灯
z 1RU 机箱支持 3 个光接收模块安装，1、2、3 数字是光接收模块的编号。 z PWR：电源指示灯，绿色 LED 亮表示电源工作正常。不亮表示无光发射模块或电源故障。 z LOS：光输入信号指示灯，红色 LED 灯灭表示光输入信号正常，红灯亮表示无光输入信号。 z SD：时钟恢复锁定指示灯，绿色 LED 亮表示接收信号时钟恢复锁定，不亮表示接收信号时

SD卡IO规范1.1

Technical CommitteeSD AssociationRevision HistoryDate Version Changes compared to previous issueOctober, 2001 1.00 Base version initial releaseAugust, 2004 1.10 Incorporated Appendix D items. Added High-Powermode, voltage range clarification, inrush current limitsand more. See Appendix C for full list.Conditions for publicationPublisher and Copyright Holder:SD Association719 San Benito St. Suite CHollister, CA 95023USAPhone: +1 831 636 7322Fax: +1 831 623 2248E-mail: president@/Confidentiality:This document shall be treated as confidential under the Non Disclosure Agreement (NDA), which has been signed by the obtainer. Reproduction in whole or in part is prohibited without prior written permission of SD AssociationExemption:The information contained herein is presented only as a standard specification for SD Card and SD Host products. No responsibility is assumed by SD Association for any damages, any infringements of patents or other right of the third parties, which may result from its use. No license is granted by implication or otherwise under any patent or rights of SD Association or others.Table of Contents1.General Description (1)1.1SDIO features (1)1.2Primary Reference Document (1)1.3Keywords (1)1.4Standard SDIO Functions (2)2.SDIO Signaling Definition (3)2.1SDIO Card Types (3)2.2SDIO Card modes (3)2.2.1SPI (Card mandatory support) (3)2.2.21-bit SD data transfer mode (Card mandatory support) (3)2.2.34-bit SD data transfer mode (mandatory for High-Speed cards, optional for Low-Speed) (3)2.3SDIO Host Modes (3)2.4Signal Pins (4)2.5Host Requirements for SDIO (4)3.SDIO Card Initialization (6)3.1Differences in I/O card initialization (6)3.2The IO_SEND_OP_COND Command (CMD5) (10)3.3The IO_SEND_OP_COND Response (R4) (10)3.4Special Initialization considerations for Combo Cards (12)3.4.1Re-initialize both I/O and Memory (12)3.4.2Using a Combo Card as SDIO only or SD Memory only after Combo Initialization (12)3.4.3Acceptable Commands after Initialization (12)3.4.4Recommendations for RCA after reset (12)3.4.5Enabling CRC in SPI Combo Card (14)4.Differences with SD Memory Specification (15)4.1SDIO Command List (15)4.2Unsupported SD Memory commands (15)4.3Modified R6 Response (16)4.4Reset for SDIO (16)4.5Bus Width (16)4.6Card Detect Resistor (17)4.7Timings (17)4.8Data Transfer Block Sizes (18)4.9Data Transfer Abort (18)4.9.1Read Abort (18)4.9.2Write Abort (18)4.10Changes to SD Memory Fixed Registers (19)4.10.1OCR Register (20)4.10.2CID Register (20)4.10.3CSD Register (20)4.10.4RCA Register (20)4.10.5DSR Register (20)4.10.6SCR Register (20)4.10.7SD Status (20)4.10.8Card Status Register (21)5.New I/O Read/Write Commands (23)5.1IO_RW_DIRECT command (CMD52) (23)5.2IO_RW_DIRECT Response (R5) (24)5.2.1CMD52 Response (SD modes) (24)5.2.2R5, IO_RW_DIRECT Response (SPI mode) (25)5.3IO_RW_EXTENDED command (CMD53) (26)5.3.1CMD53 Data Transfer Format (27)5.3.2Special Timing for CMD53 multi-block read (28)6.SDIO Card Internal Operation (29)6.1Overview (29)6.2Register Access Time (29)6.3Interrupts (29)6.4Suspend/Resume (29)6.5Read Wait (30)6.6CMD52 During Data Transfer (30)6.7SDIO Fixed Internal Map (30)6.8Common I/O Area (CIA) (31)6.9Card Common Control Registers (CCCR) (31)6.10Function Basic Registers (FBR) (38)6.11Card Information Structure (CIS) (40)6.12Multiple Function SDIO Cards (40)6.13Setting Block Size with CMD53 (40)6.14Bus State Diagram (41)7.Embedded I/O Code Storage Area (CSA) (42)7.1CSA Licensing notice (42)7.2CSA Access (42)7.3CSA Data Format (42)8.SDIO Interrupts (43)8.1Interrupt Timing (43)8.1.1SPI and SD 1-bit mode interrupts (43)8.1.2SD 4-bit mode (43)8.1.3Interrupt Period Definition (43)8.1.4Interrupt Period at the Data Block Gap in 4-bit SD Mode (Optional) (45)8.1.5Inhibited Interrupts (Removed Section) (47)8.1.6End of Interrupt Cycles (47)8.1.7Terminated Data Transfer Interrupt Cycle (48)8.1.8Interrupt Clear Timing (49)9.SDIO Suspend/Resume Operation (50)10.SDIO Read Wait Operation (54)11.Power Control (56)11.1Power Control Overview (56)11.2Power Control support for SDIO cards (56)11.2.1Master Power Control (56)11.2.2Power Selection (57)11.2.3High-Power Tuples (57)11.3Power Control Support for the SDIO Host (57)11.3.1Version 1.10 Host (57)11.3.2Power Control Operation (58)12.SDIO Physical Properties (59)12.1SDIO Size (59)12.2Small Form-Factor SDIO (59)12.3Full-Size SDIO Card Package (59)13.SDIO Full-Size Mechanical Extensions (60)13.1Additional ESD/EMI Ground Point (60)13.2Full-Size Extended Case (60)13.3Write Protect Switch (60)14.SDIO Power (62)14.1SDIO Card Initialization Voltages (62)14.2SDIO Power Consumption (62)14.3SDIO Current (62)14.4SDIO Card Operational Voltages (62)15.Inrush Current Limiting (64)15.1Current Limit Design Example (65)16.CIS Formats (66)16.1CIS Reference Document (66)16.2Basic Tuple Format and Tuple Chain Structure (66)16.3Byte Order Within Tuples (66)16.4Tuple Version (67)16.5SDIO Card Metaformat (67)16.6CISTPL_MANFID: Manufacturer Identification String Tuple (68)16.7SDIO Specific extensions (68)16.7.1CISTPL_FUNCID: Function Identification Tuple (68)16.7.2CISTPL_FUNCE: Function Extension Tuple (69)16.7.3CISTPL_FUNCE Tuple for Function 0 (common) (69)16.7.4CISTPL_FUNCE Tuple for Function 1-7 (70)16.7.5CISTPL_SDIO_STD: Function is a Standard SDIO Function (73)16.7.6CISTPL_SDIO_EXT: Tuple Reserved for SDIO Cards (73)17.Abbreviations and Terms (74)A.1 SD and SPI Command List.........................................................................................................................AB.1 Normative References.................................................................................................................................CC.1 Version History............................................................................................................................................DC.2 Version 1.00 to 1.10....................................................................................................................................DD.1 Example SDIO Controller Design................................................................................................................FTable of TablesTable 1 SDIO pin definitions (4)Table 2 OCR values for CMD5 (10)Table 3 Unsupported SD Memory Commands (16)Table 4 R6 response to CMD3 (16)Table 5 SDIO R6 Status Bits (16)Table 6 Combo Card 4-bit Control (17)Table 7 Card Detect Resistor States (17)Table 8 Timing Diagram Symbols (18)Table 9 SDIO Status Register Structure (22)Table 10 Flag data for IO_RW_DIRECT SD Response (25)Table 11 IO_RW_ EXTENDED command Op Code definition (26)Table 12 Byte Count Values (27)Table 13 Card Common Control Registers (CCCR) (32)Table 14 CCCR bit definitions (37)Table 15 Function Basic Information Registers (FBR) (38)Table 16 FBR bit and field definitions (39)Table 17 Card Information Structure (CIS) and reserved area of CIA (40)Table 18 Reference Tuples by Master Power Control and Power Select (57)Table 19 SDIO Full-Size exceptions to SD physical section 8.1 requirements (59)Table 20 Basic Tuple Format (66)Table 21 Tuples Supported by SDIO Cards (67)Table 22 CISTPL_MANFID: Manufacturer Identification Tuple (68)Table 23 CISTPL_FUNCID Tuple (68)Table 24 CISTPL_FUNCE Tuple general structure (69)Table 25 TPLFID_FUNCTION Tuple for Function 0 (common) (69)Table 26 TPLFID_FUNCTION field descriptions for function 0 (common) (70)Table 27 TPLFID_FUNCTION Tuple for Function 1-7 (70)Table 28 TPLFID_FUNCTION field descriptions for functions 1-7 (72)Table 29 TPLFE_FUNCTION_INFO definition (72)Table 30 TPLFE_CSA_PROPERTY definition (72)Table 31 CISTPL_SDIO_STD: Tuple Reserved for SDIO cards (73)Table 32 CISTPL_SDIO_EXT: Tuple Reserved for SDIO Cards (73)Table 33 SD Mode Command List.....................................................................................................................A Table 34 SPI Mode Command List....................................................................................................................BTable of FiguresFigure 1 Signal connection to two 4-bit SDIO cards (4)Figure 2 SDIO response to non-I/O aware initialization (6)Figure 3 Card initialization flow in SD mode (SDIO aware host) (8)Figure 4 Card initialization flow in SPI mode (SDIO aware host) (9)Figure 5 IO_SEND_OP_COND Command (CMD5) (10)Figure 6 Response R4 in SD mode (11)Figure 7 Response R4 in SPI mode (11)Figure 8 Modified R1 Response (11)Figure 9 Re-Initialization flow for I/O Controller (13)Figure 10 Re-Initialization flow for Memory controller (14)Figure 11 I/O Abort during Read Data Transfer (18)Figure 12 I/O Abort during Write CRC Response (Good) (19)Figure 13 I/O Abort during Write CRC Response (Bad) (19)Figure 14 I/O Abort after Write CRC Response (19)Figure 15 IO_RW_DIRECT Command (23)Figure 16 R5 IO_RW_DIRECT Response (SD modes) (24)Figure 17 IO_RW_DIRECT Response in SPI Mode (26)Figure 18 IO_RW_EXTENDED Command (26)Figure 19 Multi-Block Read Timing (28)Figure 20 SDIO Internal Map (31)Figure 21 State Diagram for Bus State Machine (41)Figure 22 Read Interrupt Cycle Timing (44)Figure 23 Alternate Read Interrupt Cycle Timing (44)Figure 24 Write Interrupt Cycle Timing (45)Figure 25 Continuous Interrupt Cycle (45)Figure 26 Multiple Block 4-Bit Read Interrupt Cycle Timing (46)Figure 27 Multiple Block 4-Bit Write Interrupt Cycle Timing (47)Figure 28 Interrupt Cycle Timing (47)Figure 29 Alternate Interrupt Cycle Timing (48)Figure 30 Terminated Read Multiple Interrupt timing (Case 1) (48)Figure 31 Terminated Read Multiple Interrupt timing (Case 2) (49)Figure 32 Card with long read latency shall accept bus suspend (50)Figure 33 Function2 read cycle inserted during Function1 multiple read cycle (50)Figure 34 Write suspended during busy (case 1) (51)Figure 35 Write suspended during busy (case 2) (51)Figure 36 Relationship between Interrupt Period and Suspend/Resume (case 1) (52)Figure 37 Relationship between Interrupt Period and Suspend/Resume (case 2) (52)Figure 38 Suspend/Resume timing (53)Figure 39 Read wait control by stopping SDCLK (54)Figure 40 Read wait delay using DAT[2] (54)Figure 41 SDIO Card DAT[2] Drive Timing for Read Wait (55)Figure 42 Full-Size SDIO Mechanical Extensions (61)Figure 43 SDIO Inrush Current (65)Figure 44 Changes from version 1.00 to 1.10....................................................................................................D Figure 45 SDIO Internal State Machine example..............................................................................................F Figure 46 State Diagram for Function State Machine........................................................................................G1. GeneralDescriptionThe SDIO (SD Input/Output) card is based on and compatible with the SD memory card. This compatibility includes mechanical, electrical, power, signaling and software. The intent of the SDIO card is to provide high-speed data I/O with low power consumption for mobile electronic devices. A primary goal is that an SDIO card inserted into a non-SDIO aware host shall cause no physical damage or disruption of that host or it’s software. In this case, the SDIO card should simply be ignored. Once inserted into an SDIO aware host, the detection of the card proceeds via the normal means described in this specification with some extensions. In this state, the SDIO card is idle and draws a small amount of power (15 mA averaged over 1 second). During the normal initialization and interrogation of the card by the host, the card identifies itself as an SDIO card. The host software then obtains the card information in a tuple (linked list) format and determines if that card’s I/O function(s) are acceptable to activate. This decision is based on such parameters as power requirements or the availability of appropriate software drivers. If the card is acceptable, it is allowed to power up fully and start the I/O function(s) built into it.features1.1 SDIOz Targeted for portable and stationary applicationsz Minimal or no modification to SD Physical bus is requiredz Minimal change to memory driver softwarez Extended physical form factor available for specialized applicationsz Plug and play (PnP) supportz Multi-function support including multiple I/O and combined I/O and memoryz Up to 7 I/O functions plus one memory supported on one card.z Allows card to interrupt hostz Initialization Voltage: 2.0 to 3.6Vz Operational Voltage range:z Standard: 2.7 – 3.6Vz Minimal: 3.1 – 3.5Vz Application Specifications for Standard SDIO Functions.1.2 PrimaryDocumentReferenceThis specification is based on and refers extensively to the SDA document:SD Memory Card SpecificationsPart 1PHYSICAL LAYER SPECIFICATIONSeptember 2000Version 1.01The reader is directed to this document for more information on the basic operation of SD cards. In addition, other documents are referenced in this specification. A complete list can be found in appendix B.1.1.3 KeywordsAs used in this documents "shall", "should", "may" and "can" are defined as follows:shall - used to indicate mandatory itemsshould - used to indicated a recommended itemmay - used to indicate something that is permissiblecan - used for statements of possibility and capabilityFunctionsSDIO1.4 StandardAssociated with the base SDIO specification, there are several Application Specifications for Standard SDIO Functions. These common functions such as cameras, Bluetooth cards and GPS receivers have a standard register interface, a common operation method and a standard CIS extension. Implementation of the standard interfaces are optional for any card vendor, but compliance with the standard allows the use of standard drivers and applications which will increase the appeal of these cards to the consumer. Full information on these standard interfaces can be found in the Application Specifications for Standard SDIO Functions maintained by the SDA.2. SDIO Signaling DefinitionTypes2.1 SDIOCardThis specification defines two types of SDIO cards. The Full-Speed card supports SPI, 1-bit SD and the 4-bit SD transfer modes at the full clock range of 0-25MHz. The Full-Speed SDIO cards have a data transfer rate of over 100 Mb/second (10 MB/Sec). A second version of the SDIO card is the Low-Speed SDIO card. This card requires only the SPI and 1-bit SD transfer modes. 4-bit support is optional. In addition, Low-Speed SDIO cards shall support a full clock range of 0-400 KHz. The intended use of Low-Speed cards is to support low-speed I/O capabilities with a minimum of hardware. The Low-Speed cards support such functions as modems, bar-code scanners, GPS receivers etc. If a card is a ‘Combo card’ (memory plus SDIO) then Full-Speed and 4-bit operation is mandatory for both the memory and SDIO portions of the card.Cardmodes2.2 SDIOThere are 3 signaling modes defined for SD Physical Specification Version 1.01 memory cards that also apply to SDIO Card:2.2.1 SPI (Card mandatory support)The SPI bus topology is defined in section 3.1.2 and the protocol is defined in sections 3.2.2 and 7 of the SD Physical Specification Version 1.01. In this mode pin 8, which is undefined for memory, is used as the interrupt pin. All other pins and signaling protocols are identical to the SD Physical Specification Version1.01.2.2.2 1-bit SD data transfer mode (Card mandatory support)This mode is identical to the 1 data bit (narrow) mode defined for SD Memory in section 3.2.1 of the SD Physical Specification Version 1.01. In this mode, data is transferred on the DAT[0] pin only. In this mode pin 8, which is undefined for memory, is used as the interrupt pin. All other pins and signaling protocols are identical to the SD Memory specification.2.2.3 4-bit SD data transfer mode (mandatory for High-Speed cards, optional for Low-Speed)This mode is identical to the 4 data bit mode (wide) defined for SD Memory in section 3.2.1 of the SD Physical Specification Version 1.01. In this mode, data is transferred on all 4 data pins (DAT[3:0]). In this mode the interrupt pin is not available for exclusive use as it is utilized as a data transfer line. Thus, if the interrupt function is required, a special timing is required to provide interrupts. See section 8.1.2 for details of this operation. The 4-bit SD mode provides the highest data transfer possible, up to 100 Mb/sec.HostModes2.3 SDIOIf a SDIO aware host supports the SD transfer mode, it is recommended that both the 1-bit and 4-bit modes be supported. While a SDIO host that supports only the 4-bit transfer mode is possible, its performance with a Low-Speed SDIO card may be reduced. This is because the only means to transfer data to and from a Low-Speed card would be the single byte per command transfer (using the IO_RW_DIRECT command (CMD52) see 5.1).2.4 Signal PinsFigure 1 Signal connection to two 4-bit SDIO cardsPin SD 4-bit mode SD 1-bit mode SPI mode 1 CD/DAT[3] Data line 3 N/C Not Used CS Card Select 2 CMD Command line CMD Command line DI Data input 3 VSS1 Ground VSS1 Ground VSS1 Ground 4 VDD Supply voltage VDD Supply voltage VDD Supply voltage 5 CLK Clock CLK Clock SCLK Clock 6 VSS2 Ground VSS2 Ground VSS2 Ground 7 DAT[0] Data line 0 DATA Data line DO Data output 8 DAT[1] Data line 1 or Interrupt (optional)IRQ Interrupt IRQ Interrupt9 DAT[2] Data line 2 or Read Wait (optional)RW Read Wait (optional) NC Not UsedTable 1 SDIO pin definitionsIt is recommended that multi-slot hosts intending to support SDIO (SDIO aware) provide a separate CLK to each slot, to allow the I/O cards to be placed in a low power state on a slot-by-slot basis. After reset, all data lines (DAT[3:0]) shall be in the hi-Z state on both the host and card(s) to avoid bus conflict. Access to the Bus Interface Control register within the CCCR (Table 13) determines DAT line mode.2.5 Host Requirements for SDIOIn order for a host to completely support all of the capabilities of the SDIO cards, some signal connections should be supported. In order to support interrupts, the host should have Pin 8 connected from the card to the host in order to provide interrupt signaling. This is true even if the host only supports the SPI or 1 bit SD mode. In addition, if the host supports more than 1 card in either SD mode, the CMD and all 4 data lines (DAT[3:0]) should not be bussed together, but rather routed separately to the host. This allows the mixing of card types in the different sockets without interference. Both the SD Physical Specification and the SDIO Specification support the concept of “unifying” (connecting together) the CMD lines in a multi-slot system after initialization.In addition, there some additional design details that the designer of a host intending to support SDIO cards must be aware of:placed on the DAT[3:1] lines. Those conditions are:1) During a multiple block write:According to the SD Physical Specification Version 1.01 figures 9 and 28, the DAT[3:1] lines are described as “don’t care” (X) during the CRC status period. If a host actively drives these lines during this period, it may interfere with interrupt signaling from an SDIO card. In order to prevent this conflict, if a host supports interrupts during 4-bit data transfers, it shall not drive DAT[3:1] during this period (hi-Z rather than don’t care.)2) During a multiple block read:According to the SD Physical Specification Version 1.01 figure 26, the DAT[1] line is described as “P” (one cycle pull-up) between read data packets. In order to support interrupts during the 4-bit mode, the host shall not drive the DAT[1] line during the 2 clock Interrupt Period defined in section 8.1.2InitializationCard3. SDIO3.1 Differences in I/O card initializationA requirement for the SDIO specification is that an SDIO card shall not cause non-I/O aware hosts to fail when inserted. In order to prevent operation of I/O functions in non-I/O aware hosts, a change to the SD card identification mode flowchart is needed. A new command (IO_SEND_OP_COND, CMD5) is added to replace the ACMD41 for SDIO initialization by I/O aware hosts (see 3.2).After reset or power-up, all I/O functions on the card are disabled and the I/O portion of the card shall not execute any operation except CMD5 or CMD0 with CS=low. If there is SD memory installed on the card (also called a combo card), that memory shall respond normally to all normal mandatory memory commands.An I/O only card shall not respond to the ACMD41 and thus appear initially as an MMC card (See appendix B.1 for information on the MMC specification). The I/O only card shall also not respond to the CMD1 used to initialize the MMC cards and appear as a non-responsive card. The host then gives up and disables this card. Thus, the non-aware host receives no response from an I/O only card and force it to the inactive state. The operation of an I/O card with a non-I/O aware host is shown in Figure 2. Note that the solid lines are the actual paths taken while the dashed lines are not executed.Figure 2 SDIO response to non-I/O aware initializationAn SDIO aware host sends CMD5 prior to the CMD55/ACMD41 pair, and thus would receive a valid OCR in the R4 response to CMD5 and continue to initialize the card. Figure 3 shows the operation of an SDIO aware host operating in the SD modes and Figure 4 shows the same operation for a host that operates in the SPI mode.If the I/O portion of a card has received no CMD5, the I/O section remains inactive and shall not respond to any command except CMD5. A combo card stays in the memory-only mode. If no memory is installed on the card (i.e. an I/O only card in a non-SDIO aware host) the card would not respond to any memory command. This satisfies the condition where a user uses some I/O function on the card such as Ethernet to load a music file to the memory function of that card. The card is then removed and inserted into a non-SDIO aware host. That host would not enable the I/O function (no CMD5) so would appear to the player as a memory-only card. If the host were I/O aware, it would send the CMD5 to the card and the card would respond with R4. The host reads that R4 value and knows the number of available I/O functions and about the existence of any SD memory. After the host has initialized the I/O portion of the card, it then reads the Common Information Area (CIA) of the card (see 6.8). This is done by issuing a read command, starting with the byte at address 0x00, of I/O function 0. The CIA contains the Card Common Control Registers (CCCR) and the Function Basic Registers (FBR). Also included in the CIA are pointers to the card’s common Card Information Structure (CIS) and each individual function’s CIS. The CIS structure is defined in section 16. The CIS includes information on power, function, manufacturer and other things the host needs to determine if the I/O function(s) is appropriate to power-up. If the host determines that the card should be activated, a register in the CCCR area enables the card and each individual function. At this time, all functions of the I/O card are fully available. In addition, the host can control the power consumption and enable/disable interrupts on a function-by-function basis. This access to I/O does not interfere with memory access to the card if present.Combo Cards can accept CMD15 with RCA=0000, as described in Figure 3, but there is an exception for SD memory only cards. Memory only cards require a non-zero RCA before the host may issue CMD15. Thus, CMD15 shall be issued after CMD3 in the Standby state. In the case of ACMD41, it shall accept RCA=0x0000. As shown in Figure 3 and Figure 4, an SDIO aware host shall send CMD5 arg=0 as part of the initialization sequence after either Power On or a CMD 52 with write to I/O Reset. Sending CMD5 arg=0 that has not been preceded by one of these two reset conditions shall not result in either the host or card entering the initialization sequence.IO=1, MEM=0IO=1, MEM=1MP=0, IO=0Start initialization with CMD0, CMD1IO=0, MEM=1IO=0, MEM=0 Start initialization with CMD0 and CMD13.2 The IO_SEND_OP_COND Command (CMD5)Figure 5 shows the format of the IO_SEND_OP_COND command (CMD5). The function of CMD5 for SDIO cards is similar to the operation of ACMD41 for SD memory cards. It is used to inquire about the voltage range needed by the I/O card. The normal response to CMD5 is R4 in either SD or SPI format. The R4 response in SD mode is shown in Figure 6 and the SPI version is shown in Figure 7.S D Command Index000101b StuffBitsI/O OCR CRC7 E1 1 6 8 24 7 1Figure 5 IO_SEND_OP_COND Command (CMD5)The IO_SEND_OP_COND Command contains the following fields:S(tart bit): Start bit. Always 0D(irection): Direction. Always1 indicates transfer from host to card.Command Index: Identifies the CMD5 command with a value of 000101bStuff Bits: Not used, shall be set to 0.I/O OCR: Operation Conditions Register. The supported minimum and maximum valuesfor VDD. The layout of the OCR is shown in Table 2. See section 4.10.1 foradditional information.CRC7: 7 bits of CRC dataE(nd bit): End bit, always 1I/O OCR bit position VDD voltage window(in Volts)0-3 Reserved4 Reserved5 Reserved6 Reserved7 Reserved8 2.0-2.19 2.1-2.210 2.2-2.311 2.3-2.412 2.4-2.513 2.5-2.614 2.6-2.715 2.7-2.816 2.8-2.917 2.9-3.018 3.0-3.119 3.1-3.220 3.2-3.321 3.3-3.422 3.4-3.523 3.5-3.6Table 2 OCR values for CMD53.3 The IO_SEND_OP_COND Response (R4)An SDIO card receiving CMD5 shall respond with a SDIO unique response, R4. The format of R4 for both the SD and SPI modes is:S D Reserved C Number of I/O functionsMemory Present StuffBitsI/O OCR Reserved E 1 1 6 1 3 1 3 24 7 1Figure 6 Response R4 in SD modeModifiedR1C Numberof I/O functionsMemory PresentStuff BitsI/O OCR8 1 3 1 3 24Figure 7 Response R4 in SPI modeThe Response, R4 contains the following data:S(tart bit): Start bit. Always 0 D(irection): Direction. Always 0. Indicates transfer from card to host. Reserved: Bits reserved for future use. These bits shall be set to 1. C: Set to 1 if Card is ready to operate after initializationI/O OCR:Operation Conditions Register. The supported minimum and maximum values for VDD. The layout of the OCR is shown in Table 2. See section 4.10.1 for additional information.Memory Present: Set to 1 if the card also contains SD memory. Set to 0 if the card is I/O only.Number of I/O Functions: Indicates the total number of I/O functions supported by this card. The range is 0-7.Note that the common area present on all I/O cards at Function 0 is not included in this count. The I/O functions shall be implemented sequentially beginning at function 1.Modified R1: The SPI R1 response byte as described in Fig 47 of the SD Physical SpecificationVersion 1.01 modified for I/O as follows:Figure 8 Modified R1 ResponseStuff Bits:Not used, shall be set to 0.1 = in idle state RFU (always 0)1 = illegal command 1 = COM CRC error1 = Function number error RFU (always 0)1 = parameter errorStart Bit (always 0)。

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目录1典型配置案例支持的设备型号 (1)2常用维护命令行介绍 (1)2.1登陆设备 (1)2.1.1 SSH方式登陆 (1)2.1.2 Telnet方式登陆 (1)2.2查看设备信息 (2)2.3软件版本升级 (2)2.3.1 Conboot模式下操作 (2)2.3.2命令行下操作 (9)2.4清除配置 (9)3基本二三层转发配置案例 (9)3.1二层转发简介 (9)3.1.1配置需求 (10)3.1.2网络拓扑 (10)3.1.3配置流程 (10)3.1.4配置步骤 (10)3.2三层转发简介 (11)3.2.1配置需求 (11)3.2.2网络拓扑 (11)3.2.3配置流程 (11)3.2.4配置步骤 (12)4端口聚合典型配置案例 (13)4.1端口聚合简介 (13)4.1.1基本概念 (13)4.1.2聚合模式 (14)4.1.3负载分担类型 (14)4.2端口聚合配置案例 (14)4.2.1配置需求 (14)4.2.2网络拓扑 (15)4.2.3配置流程 (15)4.2.4配置步骤 (15)5端口镜像典型配置案例 (17)5.1端口镜像简介 (17)5.1.1端口镜像基本概念 (17)5.1.2端口镜像分类 (18)5.2本地端口镜像配置案例 (18)5.2.1配置需求 (18)5.2.2网络拓扑 (19)5.2.3配置流程 (19)5.2.4配置步骤 (19)5.3远程端口镜像配置案例 (21)5.3.1配置需求 (21)5.3.2网络拓扑 (21)5.3.3配置流程 (21)5.3.4配置步骤 (22)6端口限速典型配置案例 (23)6.1端口限速简介 (23)6.2配置案例 (23)6.2.1配置需求 (23)6.2.2网络拓扑 (24)6.2.3配置流程 (24)6.2.4配置步骤 (24)7端口隔离典型配置案例 (25)7.1端口隔离简介 (25)7.2配置案例 (25)7.2.1配置需求 (25)7.2.2网络拓扑 (26)7.2.3配置流程 (26)7.2.4配置步骤 (26)8 ARP防护典型配置案例 (27)8.1 ARP防护简介 (27)8.1.1 ARP报文有效性检查 (27)8.1.2 ARP用户合法性检查 (27)8.1.3 ARP网关保护 (28)8.2 ARP报文一致性检测配置案例 (28)8.2.1配置需求 (28)8.2.2网络拓扑 (29)8.2.3配置流程 (29)8.2.4配置步骤 (29)8.3 ARP用户合法性配置案例 (30)8.3.1配置需求 (30)8.3.2网络拓扑 (30)8.3.3配置流程 (30)8.3.4配置步骤 (31)8.4 ARP网关保护配置案例 (32)8.4.1配置需求 (32)8.4.2网络拓扑 (32)8.4.3配置流程 (32)8.4.4配置步骤 (33)9路由协议典型配置案例 (34)9.1路由协议简介 (34)9.1.1静态路由协议简介 (34)9.1.2 RIP路由协议简介 (34)9.1.3 OSPF路由协议简介 (34)9.2静态路由配置案例 (35)9.2.1配置需求 (35)9.2.2网络拓扑 (35)9.2.3配置流程 (35)9.2.4配置步骤 (35)9.3 RIP路由配置案例 (37)9.3.1配置需求 (37)9.3.2网络拓扑 (38)9.3.3配置流程 (38)9.3.4配置步骤 (38)9.4 OSPF典型配置案例 (41)9.4.1配置需求 (41)9.4.2网络拓扑 (42)9.4.3配置流程 (42)9.4.4配置步骤 (42)10 DHCP典型配置案例 (45)10.1 DHCP简介 (45)10.2 DHCP Server配置案例 (46)10.2.1配置需求 (46)10.2.2网络拓扑 (47)10.2.3配置流程 (47)10.2.4配置步骤 (47)10.3 DHCP Snooping配置案例 (48)10.3.1配置需求 (48)10.3.2网络拓扑 (49)10.3.3配置流程 (49)10.3.4配置步骤 (50)10.4 DHCP 中继配置案例 (51)10.4.1配置需求 (51)10.4.2网络拓扑 (51)10.4.3配置流程 (52)10.4.4配置步骤 (52)11 QoS典型配置案例 (53)11.1 QoS简介 (53)11.2配置案例 (54)11.2.1配置需求 (54)11.2.2网络拓扑 (55)11.2.3配置流程 (55)11.2.4配置步骤 (55)12 802.1x典型配置案例 (56)12.1 802.1x简介 (56)12.1.1基本概念 (56)12.1.2认证方式 (56)12.1.3端口接入控制模式 (57)12.1.4 Radius认证分类 (57)12.2 802.1x本地认证配置案例 (57)12.2.1配置需求 (57)12.2.2网络拓扑 (58)12.2.3配置流程 (58)12.2.4配置步骤 (58)12.3 802.1x Radius认证配置案例 (59)12.3.1配置需求 (59)12.3.2网络拓扑 (59)12.3.3配置流程 (59)12.3.4配置步骤 (59)13生成树典型配置案例 (60)13.1生成树简介 (60)13.2 STP配置案例 (62)13.2.1配置需求 (62)13.2.2网络拓扑 (63)13.2.3配置流程 (63)13.2.4配置步骤 (63)13.3 RSTP配置案例 (65)13.3.1配置需求 (65)13.3.2网络拓扑 (66)13.3.3配置流程 (66)13.3.4配置步骤 (66)13.4 MSTP配置案例 (67)13.4.1配置需求 (67)13.4.2网络拓扑 (68)13.4.3配置流程 (68)13.4.4配置步骤 (69)14 SNMP典型配置 (72)14.1 SNMP简介 (72)14.2 SNMP配置案例 (73)14.2.1配置需求 (73)14.2.2网络拓扑 (73)14.2.3配置流程 (73)14.2.4配置步骤 (74)15 NTP配置案例 (74)15.1 NTP简介 (74)15.2 NTP配置案例 (75)15.2.1配置需求 (75)15.2.2网络拓扑 (75)15.2.3配置流程 (75)15.2.4配置步骤 (75)16日志收集配置案例 (76)16.1日志简介 (76)16.2日志收集案例 (76)16.2.1配置需求 (76)16.2.2网络拓扑 (76)16.2.3配置流程 (77)16.2.4配置步骤 (77)1典型配置案例支持的设备型号LSW3600-SI系列2常用维护命令行介绍2.1登陆设备2.1.1SSH方式登陆在交换机上开启SSH后，就可以在串口终端上输入设备的管理地址、用户名（初始用户名admin）和密码（初始密码admin_default）登录设备。

802.11abg Wireless SDIO Card 说明书

802.11abg Wireless SDIO CardUser ManualFederal Communication Commission Interference StatementThis equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one of the following measures: ●Reorient or relocate the receiving antenna.●Increase the separation between the equipment and receiver.●Connect the equipment into an outlet on a circuit different from that to which the receiver isconnected.●Consult the dealer or an experienced radio/TV technician for help.FCC Caution: Any changes or modifications not expressly approved by the party responsible for compliance could void the user’s authority to operate this equipment.This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.Table of ContentsPackage Contents & System Requirements (1)Features (1)SD WLAN Module Wireless Networks (1)SD WLAN Card Network Scenarios (1)Installing the Driver (3)Accessing WLAN Utility (7)Configuring WLAN Utility (7)Wireless tab (7)Network Adapters tab (8)IP Address tab (8)Removing the Driver (10)1.Manual (In CD-ROM )2.Drivers and configuration utilities on CD-ROM3.Quick Install Guide4.Product DeviceIf you miss any of these items please contact your agent.The 802.11abg Wireless SDIO Card is a wireless network card that complies with the IEEE 802.11abg standard on wireless LANs (Revision B).¾SDIO Card size as 40 (L) x 24 (W) x 2.1 (H) mm¾SDIO Interface¾Supports the IEEE802.11a/b/g wireless¾High radio performance¾Low power consumption¾Data rates of 6-54Mbps for 802.11a and 1-54Mbps for 802.11g¾Embedded 40MHz reference clock supported¾Sleep clock using 32 KHz clock¾Ready OS support as WinCE 5.0 and 6.0, Linux 2.6.9SD WLAN Card Network ScenariosThe 802.11abg Wireless SDIO Card enables you to:•Connect your computer to a Peer-to-Peer workgroup of wireless computing devices•Connect your computer to a Small Office/Home Office (SOHO) network that includes Wi-Fi access points•Connect your computer to a Local Area Network (LAN) Infrastructure that includes the 802.11abg Wireless SDIO Card, or other IEEE 802.11b compliant LAN systemsWireless stations can be equipped with the 802.11abg Wireless SDIO Card, but also with other WLAN PC Cards. Both of them share the same wireless functionality.Peer-to-Peer (Ad-hoc) WorkgroupThe Peer-to-Peer workgroup configuration enables you to quickly set up a small wireless workgroup, where the workgroup participants can exchange files using features like “Files and Printer Sharing” as supported by Microsoft®Networking.You can use this option to setup a temporary or Ad-hoc network in environments where no access points are available (for example in Small Office/Home Office “SOHO” environments). As long as the stations are within range of one another, this is the easiest and least expensive way to set up a wireless network.Home NetworkingWith 802.11abg Wireless SDIO Card, wireless access to the Internet or other devices is at your fingertips. All you need to do is connect the 802.11abg Wireless SDIO Card to an existing access point that may be connected to the external Cable or xDSL modems and you are ready to:Share files and printers, andAccess the InternetEnterprise NetworkingWith the Wi-Fi certified access point in the corporate network system, you can connect to a corporate Local Area Network (LAN) infrastructure to access all network facilities in wireless. LAN Infrastructures may either be:Stand-alone wireless LANsWireless network infrastructures connected to an existing Ethernet networkInstallation of the 802.11abg wireless SDIO card driver to the PDA via using Microsoft ActiveSync®1.Connect your PDA to your computer and make sure Microsoft ActiveSync® has established a connection between the two devices.Note: Do not insert the 802.11abg Wireless SDIO Card into the card slot of your PDA until the Driver installation has been performed.Important Notice:The SDIO drivers are based on following CPU type:z Intel PXA270 for Windows Mobile® 5.0z Marvell PXA310 for Windows Mobile® 6.0Please go to Start > Settings > System tab > select About icon > Version tab to check the PDA CPU type.If your PDA CPU is other type, please check with the agent of SDIO card. Due to different PDA CPU type might cause incompatible between the driver and SDIO card.2.Insert the included CD-ROM to your PC. The Wireless LAN Utility screen will appear, select the Install Driver (WM 5.0 or 6.0) to start driver installation.3.Click “OK” to complete the driver installation.4.After finished driver installing, the installed successfully message will show on the PDA screen.Note: Do not insert the 802.11abg wireless SDIO card into the card slot of your PDA until the driver installation has been performed.Go to Start>Settings> Connections tab > select the Wi-Fi icon to access the Windows CE built-in WLAN utility.Select an available AP or router from the list and tap Connect to make a connection.Wireless tab¾Configure Wireless Networks Select an availablenetwork device from the list and tap Connect.¾Networks to access:Select the type of network access from the pull-down list.z All Available: Infrastructure or Ad-hoc mode, a group ofwireless devices communicate with both access points andnetwork adapters.z Only access points: Infrastructure mode, a group ofwireless devices communicate directly with only accesspoints.z Only computer-to-computer: Ad-hoc mode, a wirelessdevice communicates directly with each other withoutusing an access point.Network Adapters tabConfigure Network Adapters¾My network card connects to:Tap Work or The Internet from the pull-downmenu.z Work: Connects to the network in your office.z The Internet: Connects to your ISP at home.¾Tap an adapter to modify settings:Tap an adapter from the list to enter itsconfiguration screen.Or select an adapter then tap Edit at the left-downcorner of the screen to enter its configurationsettings page.If 802.11abg wireless SDIO card is tapped, the following screen will appear for you to configure:IP Address tab~Use server-assigned IP addressTap Use server-assigned IP address to obtain an IP address automatically. The wireless router will act as a DHCP server. An IP address will be assigned from the wireless router.~Use specific IP addressz IP address: Enter the IP address (within the range of the wireless router’s IP address, for instance, if the IP address of the router which you would like to connect is 192.168.1.254, you may enter the IP address from 192.168.1.1 to 192.168.1.253, such as 192.168.1.123)z Subnet mask: The subnet mask, for example, 255.255.255.0, must be the same as that set on your Ethernet network.z Default gateway: Enter the IP address of your network’s gateway, such as 192.168.1.254. The gateway is the device that enables communication between your computers and the Internet. In most cases, your router acts as your gateway.If you would like to remove the driver from your PDA, please make a connection between the PDA and your computer via Microsoft ActiveSync® and then insert the CD-ROM into your PC.1.Select the Install Driver (WM 5.0 or 6.0) to start to REMOVE the driver.2.If you would like to re-install or upgrade the driver, please click “Yes”; if not, please click “No” to process removal.3.Select the 802.11abg wireless SDIO card item, and then click “Remove” button to uninstall the program.4.Click “OK” to confirm removing the application.5.Click “OK” to complete the uninstallation.。

T460HW03V1

T460HW03 V1
1/31
Document Version: 1.1 Date: 2009/1/13
Product Functional Specification 46” Full HD Color TFT-LCD Module Model Name: T460HW03 V1
() Preliminary Specification (*) Final Specification
* General Information
Items Active Screen Size Display Area Outline Dimension Driver Element Display Colors Color Gamut Number of Pixels Pixel Arrangement Pixel Pitch Display Mode Surface Treatment RoHS Specification 46 1018.08(H) x 572.67(V) 1083.0(H) x 627.0(V) x 50.6(D) a-Si TFT active matrix 16.7M 72 1920 x 1080 RGB vertical stripe 0.53025 Normally Black Haze 11%, 3H RoHS compliance mm Colors % Pixel NTSC Unit Note inches Diagonal mm mm With Balance Board
Product Description: T460HW03 TFT-LCD PANEL
AUO Model Name: T460HW03 V1 Customer Part No. / Project Name: Customer Signature AU Optronics Corp.

SDIO简介

SD/MMC/SDIO 概念区分概要发布时间：2009-02-10 11:40:47SD（Secure Digital）与 MMC（Multimedia Card）SD 是一种 flash memory card 的标准，也就是一般常见的 SD 记忆卡，而 MMC 则是较早的一种记忆卡标准，目前已经被 SD 标准所取代。

在维基百科上有相当详细的 SD/MMC 规格说明：[/wiki/Secure_Digital]。

SDIO（Secure Digital I/O）SDIO 是目前我们比较关心的技术，SDIO 故名思义，就是 SD 的 I/O 接口（interface）的意思，不过这样解释可能还有点抽像。

更具体的说明，SD 本来是记忆卡的标准，但是现在也可以把 SD 拿来插上一些外围接口使用，这样的技术便是 SDIO。

所以 SDIO 本身是一种相当单纯的技术，透过 SD 的 I/O 接脚来连接外部外围，并且透过 SD 上的 I/O 数据接位与这些外围传输数据，而且 SD 协会会员也推出很完整的 SDIO stack 驱动程序，使得 SDIO 外围（我们称为 SDIO 卡）的开发与应用变得相当热门。

现在已经有非常多的手机或是手持装置都支持 SDIO 的功能（SD 标准原本就是针对 mobile device 而制定），而且许多 SDIO 外围也都被开发出来，让手机外接外围更加容易，并且开发上更有弹性（不需要内建外围）。

目前常见的 SDIO 外围（SDIO 卡）有：∙Wi-Fi card（无线网络卡）∙CMOS sensor card（照相模块）∙GPS card∙GSM/GPRS modem card∙Bluetooth card∙Radio/TV card（很好玩）SDIO 的应用将是未来嵌入式系统最重要的接口技术之一，并且也会取代目前GPIO 式的 SPI 接口。

SD/SDIO 的传输模式SD 传输模式有以下 3 种：∙SPI mode（required）∙1-bit mode∙4-bit modeSDIO 同样也支持以上 3 种传输模式。

SD与SDA图标的使用指南_4_00版本

SD Logo Guideline/SDA Logo GuidelineVer. 4.00April 5, 2013SD-3C, LLCSD Card AssociationNotice for SD-3C, LLC and SDA Licensees: This document provides the SD Logo Guideline under license from SD-3C, LLC and the SDA Logo Guideline under license from the SD Card Association. Licensees shall use authorized digital data for printing these logos and pictographs on products, labels, packages, brochures, websites, or in manuals, etc. Digital data for the SD Logo Guideline is provided by SD-3C, LLC and digital data for the SDA Logo Guideline is provided by the SDCard Association.Table of ContentsPart 1 - SD Logo Guideline (1)1. Overview of SD Logo Guideline (4)2. Definitions (4)2.1 SD Logo Guideline (4)2.2 SDA Logo Guideline (4)2.3 SD Logos (4)2.4 SDHC Logos (4)2.5 SDXC Logos (5)2.6 smartSD Logos (5)2.7 SDIO Logo (5)2.8 SD Memory Card (5)2.9 SD Host/Ancillary Product (5)2.10 SDHC Memory Card (5)2.11 SDHC Host/Ancillary Product (5)2.12 SDXC Memory Card (5)2.13 SDXC Host/Ancillary Product (6)2.14 smartSD Memory Card (6)2.15 smartSD Host/Ancillary Product (6)2.16 SDIO Card (6)2.17 SDIO Host/Ancillary Product (6)2.18 Embedded SD Product (6)2.19 Embedded SD Host/Ancillary Product (6)2.20 SD Logo Digital Data (7)2.21 Speed Class (7)2.22 Speed Class Pictographs (7)2.23 UHS Bus Pictographs (7)2.24 UHS Speed Class (7)2.25 UHS Speed Class Pictographs (7)2.26 SD Application Formats (7)2.27 SD Application Format Pictographs (8)2.28 smart Pictograph (8)2.29 SDA Pictograph Digital Data (8)3. List of SD Logos and Authorized Products (9)4. SD Logos (10)4.1 Overview of SD Logos (10)4.1.1 SD Logo (10)4.1.2 miniSD Logo (10)4.1.3 microSD Logo (10)4.2 Permitted Use of SD Logos (10)4.3 Shape of SD Logos (11)4.4 Size of SD Logos (11)Confidential4.6 Location of SD Logos (11)4.7 Clear Zone of SD Logos (12)4.8 Trademark Notice of SD Logos (13)4.9 Additional Trademark Guidelines for SD Logos (14)5. SDHC Logos (15)5.1 Overview of SDHC Logos (15)5.1.1 SDHC Logo (15)5.1.2 miniSDHC Logo (15)5.1.3 microSDHC Logo (15)5.2 Permitted Use of SDHC Logos (16)5.3 Shape of SDHC Logos (16)5.4 Size of SDHC Logos (16)5.5 Color of SDHC Logos (16)5.6 Location of SDHC Logos (17)5.7 Clear Zone of SDHC Logos (18)5.8 Trademark Notice of SDHC Logos (19)5.9 Additional Trademark Guidelines for SDHC Logos (20)6. SDXC Logos (21)6.1 Overview of SDXC Logos (21)6.1.1 SDXC Logo (21)6.1.2 microSDXC Logo (21)6.2 Permitted Use of SDXC Logos (21)6.3 Shape of SDXC Logos (21)6.4 Size of SDXC Logos (22)6.5 Color of SDXC Logos (22)6.6 Location of SDXC Logos (22)6.7 Clear Zone of SDXC Logos (23)6.8 Trademark Notice of SDXC Logos (24)6.9 Additional Trademark Guidelines for SDXC Logos (25)7. smartSD Logos (26)7.1 Overview of smartSD Logos (26)7.1.1 smartSD Logo (26)7.1.2 smartSDHC Logo (26)7.1.3 smartSDXC Logo (26)7.2 Permitted Use of smartSD Logos (26)7.3 Shape of smartSD Logos (27)7.4 Size of smartSD Logos (27)7.5 Color of smartSD Logos (27)7.6 Location of smartSD Logos (28)7.7 Clear Zone of smartSD Logos (29)7.8 Trademark Notice of smartSD Logos (30)7.9 Additional Trademark Guidelines for smartSD Logos (31)8. SDIO Logo (32)8.1 Overview of SDIO Logo (32)Confidential8.2 Permitted Use of SDIO Logo (32)8.3 Shape of SDIO Logo (32)8.4 Size of SDIO Logo (32)8.5 Color of SDIO Logo (32)8.6 Location of SDIO Logo (33)8.7 Clear Zone of SDIO Logo (33)8.8 Trademark Notice of SDIO Logo (34)8.9 Additional Trademark Guidelines for SDIO Logo (35)9. SD Logo on Embedded SD Product (36)9.1 Overview of SD Logo on Embedded SD Product (36)9.2 Permitted Use of SD Logo on Embedded SD Product (36)9.3 Shape of SD Logo on Embedded SD Product (36)9.4 Size of SD Logo on Embedded SD Product (36)9.5 Color of SD Logo on Embedded SD Product (36)9.6 Location of SD Logo on Embedded SD Product (37)9.7 Clear Zone of SD Logo on Embedded SD Product (37)9.8 Trademark Notice of SD Logo on Embedded SD Product (37)9.9 Additional Trademark Guidelines for SD Logo on Embedded SD Product (38)10. Exceptions for Logo Shapes (39)Part 2 - SDA Logo Guideline (1)1. Overview of SDA Logo Guideline (4)2. Definitions (4)3. List of SDA Pictographs and Authorized Products (4)4. Speed Class Pictographs (5)4.1 Overview of Speed Class Pictographs (5)4.1.1 Minimum Performance Requirements (5)4.1.2 Speed Class Pictographs (6)4.2 Permitted Use of Speed Class Pictographs (6)4.3 Shape of Speed Class Pictographs (6)4.4 Size of Speed Class Pictographs (6)4.5 Color of Speed Class Pictographs (6)4.6 Location of Speed Class Pictographs (7)4.7 Clear Zone of Speed Class Pictographs (9)4.8 Trademark Notice of Speed Class Pictographs (9)4.9 Additional Trademark Guidelines for Speed Class Pictographs (9)5. UHS Bus Pictographs (10)5.1 Overview of UHS Bus Pictographs (10)5.2 Permitted Use of UHS Bus Pictographs (10)5.3 Shape of UHS Bus Pictographs (10)5.4 Size of UHS Bus Pictographs (10)Confidential5.6 Location of UHS Bus Pictographs (11)5.7 Clear Zone of UHS Bus Pictographs (13)5.8 Trademark Notice of UHS Bus Pictographs (13)5.9 Additional Trademark Guidelines for UHS Bus Pictographs (13)6. UHS Speed Class Pictographs (14)6.1 Overview of UHS Speed Class Pictographs (14)6.1.1 Minimum Performance Requirements (14)6.1.2 UHS Speed Class Pictographs (14)6.2 Permitted Use of UHS Speed Class Pictographs (15)6.3 Shape of UHS Speed Class Pictographs (15)6.4 Size of UHS Speed Class Pictographs (15)6.5 Color of UHS Speed Class Pictographs (15)6.6 Location of UHS Speed Class Pictographs (15)6.7 Clear Zone of UHS Speed Class Pictographs (17)6.8 Trademark Notice of UHS Speed Class Pictographs (17)6.9 Additional Trademark Guidelines for UHS Speed Class Pictographs (17)7. SD Application Format Pictographs (18)7.1 Overview of SD Application Format Pictographs (18)7.1.1 SD Application Formats (18)7.1.2 SD Application Format Pictographs with SD Logo (19)7.2 Permitted Use of SD Application Format Pictographs with SD Logo (19)7.3 Shape of SD Application Format Pictographs with SD Logo (19)7.4 Size of SD Application Format Pictographs with SD Logo (20)7.5 Color of SD Application Format Pictographs with SD Logo (20)7.6 Location of SD Application Format Pictographs with SD Logo (20)7.7 Clear Zone of SD Application Format Pictographs with SD Logo (20)7.8 Trademark Notice of SD Application Format Pictographs with SD Logo (21)7.9 Additional Trademark Guidelines for SD Application Format Pictographs with SD Logo (21)8. smart Pictograph (22)8.1 Overview of smart Pictograph (22)8.2 Permitted Use of smart Pictograph (22)8.3 Shape of smart Pictograph (22)8.4 Size of smart Pictograph (22)8.5 Color of smart Pictograph (23)8.6 Location of smart Pictograph (23)8.7 Clear Zone of smart Pictograph (24)8.8 Trademark Notice of smart Pictograph (24)8.9 Additional Trademark Guidelines for smart Pictograph (24)ConfidentialPart 1 - SD Logo Guideline©Copyright 2001-2013 SD-3C, LLC ConfidentialThis revision history is provided for ease of reference and does not constitute a substantive part of this logo guideline.©Copyright 2001-2013 SD-3C, LLC ConfidentialConditions for PublicationPublisher:SD-3C, LLC1209 Orange StreetWilmington, DE 19801 USAEmail: SD-3CAdmin@Copyright Owner:SD-3C, LLC1209 Orange StreetWilmington, DE 19801 USAEmail: SD-3CAdmin@Confidentiality:The contents of this document are deemed confidential information of SD-3C, LLC ("SD-3C"). As such, the contents and your right to use the contents are subject to the confidentiality obligations stated in the written agreement you entered into with the SD-3C that entitled you to receive this document, such as the SD Memory Card License Agreement (also known as “CLA”) or the SD Host/Ancillary Product License Agreement (also known as "HALA").Conventions Used in This DocumentNaming Conventions•Some terms are capitalized to distinguish their definition from their common English meaning. Words not capitalized have their common English meaning.Key Words•May: Indicates flexibility of choice with no implied recommendation or requirement.•Shall: Indicates a mandatory requirement. Designers must implement such mandatoryrequirements to ensure interchangeability and to claim conformance with the specification.•Should: Indicates a strong recommendation, but not a mandatory requirement. Designers should give strong consideration to such recommendations, but there is still a choice inimplementation.©Copyright 2001-2013 SD-3C, LLC Confidential1. Overview of SD Logo GuidelineThe SD Logo Guideline defines the following logos:•SD Logos•SDHC Logos•SDXC Logos•smartSD Logos•SDIO LogoThis document describes the permissible uses by licensees of these logos under the Host andAncillary Product License Agreement (“HALA”) and/or the Card License Agreement (“CLA”).2. Definitions2.1 SD Logo GuidelineAs used herein, the term SD Logo Guideline means this SD Logo Guideline/SDA Logo Guideline and describes the permissible uses of the SD, SDHC, SDXC, smartSD, and SDIO Logos by HALA and/or CLA licensees.2.2 SDA Logo GuidelineAs used herein, the term SDA Logo Guideline means this SD Logo Guideline/SDA Logo Guideline and describes the permissible use of the SDA Pictographs by HALA, LAMS, and/or the SD Card Association License Agreement licensees.2.3 SD LogosThe term SD Logos include the SD Logo, as well as the miniSD Logo and microSD Logo. The SD Logos are used for the SD Memory Cards and SD Host/Ancillary Products. In addition, the SD Logo is used for Embedded SD Products. The SD Logos are trademarks owned and licensed by SD-3C, LLC. The SD Logos are shown in Section 4 of the SD Logo Guideline.2.4 SDHC LogosThe term SDHC Logos includes the SDHC Logo, as well as the miniSDHC Logo and microSDHC Logo. The SDHC Logos are used for SDHC Memory Cards and SDHC Host/Ancillary Products. The SDHC Logos are trademarks owned and licensed by SD-3C, LLC. The SDHC Logos are shown in Section 5 of the SD Logo Guideline.©Copyright 2001-2013 SD-3C, LLC Confidential2.5 SDXC LogosThe term SDXC Logos includes the SDXC Logo and microSDXC Logo. These SDXC Logos are used for SDXC Memory Cards and SDXC Host/Ancillary Products. The SDXC Logos are trademarksowned and licensed by SD-3C, LLC. The SDXC Logos are shown in Section 6 of the SD LogoGuideline.2.6 smartSD LogosThe term smartSD Logos includes the smartSD Logo, smartSDHC Logo and smartSDXC Logo. The smartSD Logos are used for smartSD Memory Cards and smartSD Host/Ancillary Products. The smartSD Logos are trademarks owned and licensed by SD-3C, LLC. The smartSD Logos are shown in Section 7 of the SD Logo Guideline.2.7 SDIO LogoThe term SDIO Logo includes the SDIO Logo only. The SDIO Logo is used for SDIO Cards withstandard size SD, miniSD and microSD form factors, embedded SDIO Products that provide I/Ofunctions, and SDIO Host/Ancillary Products. The SDIO Logo is a trademark owned and licensed by SD-3C, LLC. The SDIO Logo is shown in Section 8 of the SD Logo Guideline.2.8 SD Memory CardThe term SD Memory Card is defined in the HALA, CLA, LAMS, and the SD Card AssociationLicense Agreement. In particular, this product has a memory capacity up to 2GB.2.9 SD Host/Ancillary ProductThe SD Host/Ancillary Product is defined in the HALA, CLA, LAMS, and the SD Card Association License Agreement. This product is interoperable only with SD Memory Cards up to 2GB.2.10 SDHC Memory CardThe SDHC Memory Card is a specific type of SD Memory Card. This product has a memorycapacity more than 2GB and up to 32GB.2.11 SDHC Host/Ancillary ProductThe SDHC Host/Ancillary Product is a specific type of SD Host/Ancillary Product. This product is interoperable with the SD Memory Card and SDHC Memory Card.2.12 SDXC Memory CardThe SDXC Memory Card is a specific type of SD Memory Card. This product has a memorycapacity more than 32GB and up to 2TB.©Copyright 2001-2013 SD-3C, LLC Confidential2.13 SDXC Host/Ancillary ProductThe SDXC Host/Ancillary Product is a specific type of SD Host/Ancillary Product. This product isinteroperable with the SD Memory Card, SDHC Memory Card, and SDXC Memory Card.2.14 smartSD Memory CardThe smartSD Memory Card is a specific type of SD Memory Card and provides security functions including smart card security function on full-size of SD Memory Card, SDHC Memory Card andSDXC Memory Card.2.15 smartSD Host/Ancillary ProductThe smartSD Host/Ancillary Product is a specific type of SD Host/Ancillary Product. This product is interoperable with the smartSD Memory Card, SDHC Memory Card, and SDXC Memory Card.2.16 SDIO CardThe SDIO Card is defined in the HALA, CLA, LAMS, and the SD Card Association LicenseAgreement. The SDIO Card is a specific type of SD card that provides various I/O functions using the SD bus and SD commands.2.17 SDIO Host/Ancillary ProductThe SDIO Host/Ancillary Product is a specific type of SD Host/Ancillary Product that is interoperable with the SDIO Card.2.18 Embedded SD ProductThe Embedded SD Product is an embedded storage product that utilizes the SD bus and SDcommands. The Embedded SD Product is permanently soldered on a PCB (Printed Circuit Board) as a non-removable device or mounted through a socket permanently soldered on a PCB, such that the Embedded SD Product cannot be removed by end users.2.19 Embedded SD Host/Ancillary ProductThe Embedded SD Host/Ancillary Product is a specific type of SD Host/Ancillary Product that isinteroperable with the Embedded SD Product.©Copyright 2001-2013 SD-3C, LLC Confidential2.20 SD Logo Digital DataThe SD Logo Digital Data is provided in “Adobe Illustrator” format. The SD Logo Digital Data includes the following logos:•SD Logos•SDHC Logos•SDXC Logos•smartSD Logos•SDIO Logo2.21 Speed ClassThe Speed Class indicates ratings of minimum data transfer performance, in particular the writeperformance of SD, SDHC and SDXC Memory Cards using Non-UHS Bus, and minimum datatransfer requirements, in particular the write performance of SD, SDHC and SDXC Host/AncillaryProducts using Non-UHS Bus.2.22 Speed Class PictographsThe Speed Class Pictographs are pictographs that identify the rating of minimum data transferperformance of SD, SDHC and SDXC Memory Cards using Non-UHS Bus and minimum datatransfer requirements of SD, SDHC and SDXC Host/Ancillary Products using Non-UHS Bus.2.23 UHS Bus PictographsThe UHS Bus Pictographs are pictographs that identify which UHS Bus type either the UHS-I orUHS-II is implemented in SDHC/SDXC Cards and SDHC/SDXC Host/Ancillary Products..2.24 UHS Speed ClassThe UHS Speed Class indicates ratings of minimum data transfer performance in particular the write performance of SDHC and SDXC Memory Cards using UHS Bus, and minimum data transferrequirements in particular the write performance of SDHC and SDXC Host/Ancillary Products using UHS Bus.2.25 UHS Speed Class PictographsThe UHS Speed Class Pictographs are pictographs that identify the rating of minimum data transfer performance of SDHC/SDXC Memory Cards using UHS Bus and minimum data transferrequirements of SDHC/SDXC Host/Ancillary Products using UHS Bus.2.26 SD Application FormatsSD Application Formats mean functions or technical formats which utilize, in whole or in part, SDSpecifications, whether or not such functions or technical formats utilize the security specification(Part 3 of the SD Specifications).©Copyright 2001-2013 SD-3C, LLC Confidential2.27 SD Application Format PictographsThe SD Application Format Pictographs are pictographs that identify the SD Application Formats. 2.28 smart PictographThe smart Pictograph is a pictograph that identifies smart microSD/SDHC/SDXC Cards and smart microSD/SDHC/SDXC Host/Ancillary Products, implementing smart security functions.2.29 SDA Pictograph Digital DataThe SDA Pictograph Digital Data is provided in “Adobe Illustrator” format. The SDA Pictograph Digital Data includes the following pictographs.•Speed Class Pictographs•UHS Bus Pictographs•UHS Speed Class Pictographs•SD Application Format Pictographs•smart Pictograph©Copyright 2001-2013 SD-3C, LLC Confidential3. List of SD Logos and Authorized ProductsThe following is the list of logos in the SD Logo Guideline and authorized products for each logo.©Copyright 2001-2013 SD-3C, LLC Confidential©Copyright 2001-2013 SD-3C, LLC Confidential4. SD Logos4.1 Overview of SD LogosThe term SD Logos includes the SD Logo, miniSD Logo, and microSD Logo.4.1.1 SD Logo4.1.2 miniSD Logo4.1.3 microSD Logo4.2 Permitted Use of SD LogosThe SD Logos shall be applied only to authorized products, packaging, and related materials as set forth in the applicable license. You may not use the SD Logos on unauthorized products or services. If an SD or miniSD Memory Card includes any I/O function, the SD or miniSD Logos shall be applied, respectively.In order for users to understand the interoperability of a host device and a memory card, the SD Logos may be used on packaging and in manuals for SD host devices.4.3 Shape of SD LogosThe shape of the SD Logos shall be exactly the same as the shape specified in the SD Logo Digital Data that is provided with the electronic version of the SD Logo Guideline. Embossing is permitted.No use of shadow effects, outline character (open face), gradation, decorative patterns, or anydecorative elements is permitted.The SD Logo may appear without slits on the logo “D” only if the total height of the logo is smaller than 3mm. However, when used with SD Host/Ancillary Products, the SD Logo may appear without slits on the logo “D” only if the total height of the logo is smaller than 10mm.The miniSD Logo may appear without slits on the logo “D” only if the total height of the logo issmaller than 8.5mm. When used with miniSD Host/Ancillary Products, the miniSD Logo may appear without slits on the logo “D” only if the total height of the logo is smaller than 28mm.The microSD Logo may appear without slits on the logo “D” only if the total height of the logo issmaller than 8.5mm. When used with microSD Host/Ancillary Products, the microSD Logo mayappear without slits on the logo “D” only if the total height of the logo is smaller than 21mm.4.4 Size of SD LogosThe size of the SD Logos is not regulated so long as the SD Logos are legible. The SD Logos may be enlarged or reduced in size to the exact proportionate form as specified in the SD Logo Digital Data.4.5 Color of SD LogosThe SD Logos may be represented in any single color, including a hologram effect sheet, so long as it is clearly visible against the background to which it is affixed.4.6 Location of SD LogosWhen the SD Logos are used, they shall prominently appear on the product, packaging, and/ormanual on which they are used.The SD Logos shall not be used in any style or format other than the authorized presentation shown in the SD Logo Guideline.The SD Logos shall be placed as follows:1) SD Memory Carda. Card product – Mandatoryb. Card product packaging – Mandatoryc. Card product manual – Mandatory2) SD Host/Ancillary Producta. Host/Ancillary product – Optional, but recommended.b. Host/Ancillary product packaging – Optional, but recommended.c. Host/Ancillary product manual – MandatoryNote: Although use of the SD Logos is not mandatory on the SD Host/Ancillary Products and©Copyright 2001-2013 SD-3C, LLC Confidentialpackaging, use of the SD Logos is highly recommended to avoid confusion of users.4.7 Clear Zone of SD LogosExcept as otherwise specified, the SD Logos shall not be co-joined with, superimposed on, orcombined with any other logo, trademark, trade name, or other designation. The SD Logos shall be displayed separately.The SD Logo shall always have a minimum space clearance, equal to 50% of the logo height from other printed areas.1/2h 1/2hThe miniSD Logo shall always have a minimum space clearance, equal to 25% of the logo height from other printed areas.1/4hThe microSD Logo shall always have a minimum space clearance, equal to 20% of the logo height from other printed areas.1/5h©Copyright 2001-2013 SD-3C, LLC Confidential4.8 Trademark Notice of SD Logos1) Whenever the SD Logos are displayed on authorized products, or packaging, labels or manualsfor such products, the "TM" symbol shall be displayed to the lower right of the SD Logos and the"TM" symbol shall be of sufficient size to be clearly visible to the naked eye.If the SD Logo, as displayed, is smaller than 6mm in height, the "TM" symbol may be omitted.If the miniSD Logo, as displayed, is smaller than 20mm in height, the "TM" symbol may beomitted.If the microSD Logo, as displayed, is smaller than 17mm in height, the "TM" symbol may beomitted.2) If the SD Logos are used in printed matter or on a web page, the following trademark notice(s)shall be placed on such printed matter or web page on at least one page:“SD Logo is a trademark of SD-3C, LLC.”“miniSD Logo is a trademark of SD-3C, LLC.”“microSD Logo is a trademark of SD-3C, LLC.”3) If more than one logo is used on such printed matter or web page, the trademark notice may list allof the relevant logos together in a single notice and be simplified as follows:For example, the following notice --"SD Logo is a trademark of SD-3C, LLC.""SDHC Logo is a trademark of SD-3C, LLC. ""miniSDHC Logo is a trademark of SD-3C, LLC.""microSDHC Logo is a trademark of SD-3C, LLC.""SDXC Logo is a trademark of SD-3C, LLC.""microSDXC Logo is a trademark of SD-3C, LLC."-- may be written as follows:"SD, SDHC, miniSDHC,microSDHC, SDXC and microSDXC Logos are trademarks of SD-3C,LLC.”©Copyright 2001-2013 SD-3C, LLC Confidential4.9 Additional Trademark Guidelines for SD Logos1) When referring to authorized products, the term “SD” may not be used in a possessive or pluralform or as a verb or participle.Permissible:We sell an “SD memory card.”We sell “SD memory cards.”We sell “SD memory card(s).”The “SD memory card’s” capacity is very impressive.Use the “SD memory card” for digital photography.Recording photographs with the “SD memory card.”Note: Using “SD card(s)” rather than “SD memory card(s)” is also permissible.Impermissible:We sell “SDs.”The “SD’s” capacity is very impressive.“SDing” your photographs.The same permissible and impermissible usages are applied to the terms “miniSD” and“microSD”.2) “miniSD” shall not be expressed in text as follows:“MiniSD”, “Mini-SD”, “MINI SD”, “MINI-SD”, “mini-SD”, or “mini SD.”3) “microSD” shall not be expressed in text as follows:“MicroSD”, “Micro-SD”, “MICRO SD”, “MICRO-SD”, ”micro-SD”, “micro SD”, or “µSD.”4) You shall notify SD-3C, LLC, of any suspected violations of these guidelines by merchants,newspapers, trade publications or other media, or of any suspected unlicensed or unauthorized use of the SD Logos.©Copyright 2001-2013 SD-3C, LLC Confidential©Copyright 2001-2013 SD-3C, LLC Confidential5. SDHC Logos5.1 Overview of SDHC LogosThe term SDHC Logos includes the SDHC Logo, miniSDHC Logo, and microSDHC Logo.5.1.1 SDHC Logo5.1.2 miniSDHC Logo5.1.3 microSDHC Logo5.2 Permitted Use of SDHC LogosThe SDHC Logos shall be applied only to authorized products, packaging, and related materials as set forth in the applicable license. You may not use the SDHC Logos on unauthorized products or services.If an SDHC or miniSDHC Memory Card includes any I/O function, the SDHC or miniSDHC Logo shall be applied respectively.In order for users to understand the interoperability of a host device and a memory card, the SDHC Logos and SD Logos may be used on packaging and in manuals for SDHC host devices.5.3 Shape of SDHC LogosThe shape of the SDHC Logos shall be exactly the same as the shape specified in the SD LogoDigital Data that is provided with the electronic version of the SD Logo Guideline. Embossing ispermitted. No use of shadow effects, outline character (open face), gradation, decorative patterns, or any decorative elements are permitted.The SDHC Logo may appear without slits on the logo “D” only if the total height of the logo is smaller than 6mm. When used with SDHC Host/Ancillary Products, the SDHC Logo may appear without slits on the logo “D” only if the total height of the logo is smaller than 20mm.The miniSDHC Logo may appear without slits on the logo “D” only if the total height of the logo issmaller than 14mm. When used with miniSDHC Host/Ancillary Products, the miniSDHC Logo may appear without slits on the logo “D” only if the total height of the logo is smaller than 46mm.The microSDHC Logo may appear without slits on the logo “D” only if the total height of the logo is smaller than 14mm. When used with microSDHC Host/Ancillary Products, the microSDHC Logo may appear without slits on the logo “D” only if the total height of the logo is smaller than 36mm.5.4 Size of SDHC LogosThe size of the SDHC Logos is not regulated so long as the SDHC Logos are legible. The SDHCLogos may be enlarged or reduced in size to the exact proportionate form as specified in the Logo Digital Data.5.5 Color of SDHC LogosThe SDHC Logos may be represented in any single color, including a hologram effect sheet, so long as they are clearly visible against the background to which they are affixed.©Copyright 2001-2013 SD-3C, LLC Confidential5.6 Location of SDHC LogosWhen the SDHC Logos are used, they shall prominently appear on the product, packaging, and/or manual on which they are used.The SDHC Logos shall not be used in any style or format other than the authorized presentation shown in the SD Logo Guideline.The SDHC Logos shall be placed as follows:1) SDHC Memory Carda. Card product – Mandatoryb. Card product packaging – Mandatoryc. Card product manual – Mandatory2) SDHC Host/Ancillary Producta. Host/Ancillary product – Optional, but recommended.b. Host/Ancillary product packaging – Optional, but recommended.c. Host/Ancillary product manual – MandatoryNote: Although use of the SDHC Logos is not mandatory on SDHC Host/Ancillary Products and packaging, use of the SDHC Logos is highly recommended to avoid confusion of users.SDHC Host/Ancillary Products shall be interoperable with SD and SDHC Memory Cards,however, SDHC Host/Ancillary Products, packaging and manuals may use only the SDHCLogo.©Copyright 2001-2013 SD-3C, LLC Confidential©Copyright 2001-2013 SD-3C, LLCConfidential5.7 Clear Zone of SDHC LogosExcept as otherwise specified, the SDHC Logos shall not be co-joined with, superimposed on, or combined with any other logo, trademark, trade name, or other designation. The SDHC Logos shall be displayed separately.The SDHC Logo shall always have a minimum space clearance, equal to 25% of the logo height from other printed areas.The miniSDHC Logo shall always have a minimum space clearance, equal to 25% of the logo height from other printed areas.The microSDHC Logo shall always have a minimum space clearance, equal to 20% of the logo height from other printed areas.1/4h1/4h1/4h1/4h1/4h1/4h 1/5h1/5h。

SD Card Specification

SD Card SpecificationSimplified Version of:Part E1Secure Digital Input/Output(SDIO)Card SpecificationVersion 1.00October 2001SD AssociationCopyright 2000, 2001 SD AssociationRevision HistoryDate Version Changes compared to previous issueOctober, 2001 1.0 Base version initial releaseConditions for publicationPublisher and Copyright Holder:SD Association719 San Benito St. Suite CHollister, CA 95023USAPhone: +1 831 636 7322Fax: +1 831 623 2248E-mail: president@Confidentiality:This document is a simplified version of the original. This version is not required to be treated as confidential and Non Disclosure Agreement with neither the 3C LLC nor the SDA is required.Reproduction in whole or in part is prohibited without prior written permission of SDA.Exemption:None will be liable for any damages from use of this document.Important additional information!The reader is directed to the additional information available in section Error! Reference source not found.. This information will inform the reader of changes to the SDIO specification proposed for the next revision of this specification that should be considered in the design of any SDIO device.Table of Contents1.General Description (1)1.1SDIO features (1)1.2Primary Reference Document (1)2.SDIO Signaling Definition (2)2.1SDIO Card Types (2)2.2SDIO Card modes (2)2.2.1SPI (Card mandatory support) (2)2.2.21-bit SD data transfer mode (Card mandatory support) (2)2.2.34-bit SD data transfer mode (mandatory for High-Speed cards, optional for Low-Speed) (2)2.3SDIO Host Modes (2)2.4Signal Pins (3)2.5Host Requirements for SDIO (3)3.SDIO Card Initialization (4)3.1Differences in I/O card initialization (4)4.Differences with SD Memory Specification (7)4.1Unsupported SD Memory commands (7)4.2Bus Width (8)4.3Card Detect Resistor (8)4.4Data Transfer Abort (8)4.5Changes to SD Memory Fixed Registers (8)4.5.1OCR Register (8)4.5.2CID Register (8)4.5.3RCA Register (8)5.New I/O Read/Write Commands (9)5.1IO_RW_DIRECT command (CMD52) (9)5.2IO_RW_EXTENDED command (CMD53) (9)5.2.1CMD53 Data Transfer Format (9)6.SDIO Card Internal Operation (10)6.1Overview (10)6.2Register Access Time (10)6.3Interrupts (10)6.4Suspend/Resume (11)6.5Read Wait (Optional) (11)6.6SDIO Fixed Internal Map (12)6.7Common I/O Area (CIA) (12)6.8Card Common Control Registers (CCCR) (13)6.9Function Basic Registers (FBR) (13)6.10Card Information Structure (CIS) (13)6.11Multiple Function SD Cards (13)6.12Embedded I/O Code Storage Area (CSA) (13)7.SDIO Interrupts (14)7.1Interrupt Timing (14)7.1.1SPI and SD 1-bit mode interrupts (14)7.1.2SD 4-bit mode (14)7.1.3Interrupt Clear Timing (14)8.SDIO Physical Properties (15)8.1SDIO Size (15)8.2SDIO Card Package (15)9.SDIO Mechanical Extensions (16)9.1Additional ESD/EMI Ground Point (16)9.2Extended Case (16)9.3Write Protect Switch (16)10.SDIO Power (18)10.1SDIO Card Initialization Voltage (18)10.2SDIO Power Consumption (18)10.3SDIO Current (18)11.Abbreviations and Terms (19)A.1SD and SPI Command List........................................................................................................................AB.1Normative References..............................................................................................................................CC.1Example SDIO Controller Design.............................................................................................................DTable of TablesTable 1 SDIO pin definitions (3)Table 2 Unsupported SD Memory Commands (7)Table 3 SDIO exceptions to SD physical section 8.1 requirements (15)Table 4 SD Mode Command List..........................................................................................................................A Table 5 SPI Mode Command List.........................................................................................................................BTable of FiguresFigure 1 Signal connection to two 4-bit SDIO cards (3)Figure 2 Card initialization flow in SD mode (SDIO aware host) (5)Figure 3 Card initialization flow in SPI mode (SDIO aware host) (6)Figure 4 SDIO Internal Map (12)Figure 5 SDIO Mechanical Extensions (17)Figure 6 SDIO Internal State Machine example..................................................................................................D Figure 7 State Diagram for Bus State Machine...................................................................................................D Figure 8 State Diagram for Function State Machine.............................................................................................E1. GeneralDescriptionThe SDIO (Secure Digital I/O) card is based on and compatible with the SD memory card. This compatibility includes mechanical, electrical, power, signaling and software. The intent of the SDIO card is to provide high-speed data I/O with low power consumption for mobile electronic devices. A primary goal is that an SDIO card inserted into a non-SDIO aware host will cause no physical damage or disruption of that device or it’s software. In this case, the SDIO card should simply be ignored. Once inserted into an SDIO aware host, the detection of the card will be via the normal means described in the SD specification with some extensions. In this state, the SDIO card will be idle and draw a small amount of power (15 mA averaged over 1 second). During the normal initialization and interrogation of the card by the host, the card will identify itself as an SDIO device. The host software will then obtain the card information in a tuple (linked list) format and determine if that card’s I/O function(s) are acceptable to activate. This decision will be based on such parameters as power requirements or the availability of appropriate software drivers. If the card is acceptable, it will be allowed to power up fully and start the I/O function(s) built into it.features1.1 SDIOTargeted for portable and stationary applicationsMinimal or no modification to SD Physical bus is requiredMinimal change to memory driver softwareExtended physical form factor available for specialized applicationsPlug and play (PnP) supportMulti-function support including multiple I/O and combined I/O and memoryUp to 7 I/O functions plus one memory supported on one card.Allows card to interrupt hostInitialization Voltage: 2.0 to 3.6VOperational Voltage range: 3.1 to 3.5V1.2 Primary Reference DocumentThis spec is based on and refers extensively to the SDA document:SD Memory Card SpecificationsPart 1PHYSICAL LAYER SPECIFICATIONSeptember 2000Version 1.01The reader is directed to this document for more information on the basic operation of SD devices. In addition, other documents are referenced in this specification. A complete list can be found in section B.1.2. SDIO Signaling Definition2.1 SDIO Card TypesThis specification defines two types of SDIO cards. The Full-Speed card supports SPI, 1-bit SD and the 4-bit SD transfer modes at the full clock range of 0-25MHz. The Full-Speed SDIO devices have a data transfer rate of over 100 Mb/second (10 MB/Sec). A second version of the SDIO card is the Low-Speed SDIO card. This card requires only the SPI and 1-bit SD transfer modes. 4-bit support is optional. In addition, Low-Speed SDIO cards shall support a full clock range of 0-400 KHz. The intended use of Low-Speed cards is to support low-speed IO devices with a minimum of hardware. The Low-Speed cards support such functions as modems, bar-code scanners, GPS receivers etc. If a card is a ‘Combo card’ (memory plus SDIO) then Full-Speed and 4-bit operation is mandatory for both the memory and SDIO portions of the card.2.2 SDIO Card modesThere are 3 signaling modes defined for SD physical specification version 1.01 memory cards that also apply to SDIO Card:2.2.1 SPI (Card mandatory support)The SPI bus topology is defined in section 3.1.2 and the protocol is defined in sections 3.2.2 and 7 of the SD Memory Card Specifications, PHYSICAL LAYER SPECIFICATION, Part 1,September 2000 Version1.01. In this mode pin 8, which is undefined for memory, is used as the interrupt pin. All other pins andsignaling protocols are identical to the SD Memory specification.2.2.2 1-bit SD data transfer mode (Card mandatory support)This mode is identical to the 1 data bit (narrow) mode defined for SD Memory in section 3.2.1 of the SD Memory Card specification. In this mode, data is transferred on the DAT[0] pin only. In this mode pin 8, which is undefined for memory, is used as the interrupt pin. All other pins and signaling protocols are identical to the SD Memory specification.2.2.3 4-bit SD data transfer mode (mandatory for High-Speed cards, optional for Low-Speed)This mode is identical to the 4 data bit mode (wide) defined for SD Memory in section 3.2.1 of the SD Memory Card specification. In this mode, data is transferred on all 4 data pins (DAT[3:0]). In this mode the interrupt pin is not available for exclusive use as it is utilized as a data transfer line. Thus, if the interrupt function is required, a special timing is required to provide interrupts. See section 7.1.2 for details of this Modes2.3 SDIOHostIf a SDIO aware host supports the SD transfer mode, it is recommended that both the 1-bit and 4-bit modes be supported. While a SDIO host that supports only the 4-bit transfer mode is possible, it’s performance with a Low-Speed SDIO card would be reduced. This is because the only means to transfer data to and from a Low-Speed card would be the single byte per command transfer (using the IO_RW_DIRECT command (CMD52) see 5.1).2.4 Signal PinsFigure 1 Signal connection to two 4-bit SDIO cardsPin SD 4-bit mode SD 1-bit mode SPI mode 1 CD/DAT[3] Data line 3 N/C Not Used CSCard Select 2 CMD Command line CMD Command line DI Data input 3 VSS1 Ground VSS1 Ground VSS1 Ground 4 VDD Supply voltage VDD Supply voltage VDD Supply voltage 5 CLK Clock CLK Clock SCLK Clock 6 VSS2 Ground VSS2 Ground VSS2 Ground 7 DAT[0] Data line 0 DATA Data line DO Data output 8 DAT[1] Data line 1 or Interrupt (optional)IRQ Interrupt IRQ Interrupt9 DAT[2] Data line 2 or Read Wait (optional)RW Read Wait (optional) NC Not UsedTable 1 SDIO pin definitionsIt is recommended that multi-slot hosts intending to support SDIO (SDIO aware) provide a separate CLK to each slot, to allow the I/O devices to be placed in a low power state on a slot-by-slot basis. After reset, all data lines (DAT[3:0]) shall be in the hi-Z state on both the host and card(s) to avoid bus conflict. Access to the Bus Interface Control register within the CCCR determines DAT line mode.2.5 Host Requirements for SDIOIn order for a host to completely support all of the capabilities of the SDIO cards, some signal connections must be supported. In order to support interrupts, the host shall have Pin 8 connected from the card to the host in order to provide interrupt signaling. This is true even if the host will only support the SPI or 1 bit SD mode. In addition, if the host supports more than 1 card in either SD mode, the CMD and all 4 data lines (DAT[3:0]) should not be bussed together, but rather routed separately to the host. This will allow the mixing of card types in the different sockets without interference. Both the SD Memory specification and the SDIO specification support the concept of “unifying” (connecting together) the CMD lines in a multi-slot system after initialization.3. SDIO Card Initialization3.1 Differences in I/O card initializationA requirement for the SDIO specification is that an SDIO card must not cause non-I/O aware hosts to fail when inserted. In order to prevent operation of I/O Functions in non-I/O aware hosts, a change to the SD card identification mode flowchart is needed. A new command (IO_SEND_OP_COND, CMD5) is added to replace the ACMD41 for SDIO initialization by I/O aware hosts.After reset or power-up, all I/O functions on the card are disabled and the I/O portion of the card will not respond to any operation except CMD5 or CMD0 with CS=low. If there is SD memory installed on the card (also called a combo card), that memory will respond normally to all normal mandatory memory commands.An I/O only card will not respond to the ACMD41 and thus appear initially as an MMC card (See B.1 forthe MMC cards and appear as a non-responsive card. The host will then give up and disable this device Thus, the non-aware host will receive no response from an I/O only card and force it to the inactive state.An SDIO aware host will send CMD5 prior to the CMD55/ACMD41 pair, and thus would receive a valid OCR in the R4 response to CMD5 and continue to initialize the card. Figure 2 shows the operation of an SDIO aware host operating in the SD modes and Figure 3 shows the same operation for a host that operates in the SPI mode.If the I/O portion of a card has received no CMD5, the I/O section remains inactive and will not respond to any command except CMD5. A combo card stays in the memory-only mode. If no memory is installed on the card (i.e. an I/O only card in a non-SDIO aware host) the card would not respond to any memory command. This satisfies the condition where a user uses some I/O function on the card such as Ethernet to load a music file to the memory function of that card. The card is then removed and inserted into a non-SDIO aware host. That device would not enable the I/O function (no CMD5) so would appear to the player as a memory-only card. If the host were I/O aware, it would send the CMD5 to the card and the card would respond with R4. The host reads that R4 value and knows the number of available I/O functions and about the existence of any SD memory.The function of CMD5 for SDIO cards is similar to the operation of ACMD41 for SD memory cards. It is used to inquire about the voltage range needed by the I/O card. The normal response to CMD5 is R4 in either SD or SPI format. The I/O aware host will send CMD5. If the card responds with response R4, the host determines the card’s configuration based on the data contained within the R4.After the host has initialized the I/O portion of the card, it then reads the Common Information Area (CIA) of the card (see 6.7). This is done by issuing a read command, starting at byte 00 of I/O function 0. The CIA contains CIA are pointers to the card’s common Card Information Structure (CIS) and each individual function’s CIS. The CIS includes information on power, function, manufacturer and other things the host needs to determine if the I/O function(s) is appropriate to power-up. If the host determines that the card should be activated, a register in the CCCR area enables the card and each individual function. At this time, all functions of the I/O card are fully available. In addition, the host can control the power consumption and enable/disable interrupts on a function-by-function basis. This access to I/O will not interfere with memory access to the card if present.Figure 2 Card initialization flow in SD mode (SDIO aware host)IO =1, M E M =0IO =1, M E M =1c tio n s s is re ad y (C s ta tu s is lize d fla g fla g g (in th e5)a tio n R e s p o n s eM P =0, IO =0S ta rt in itia liz a tio n w ith C M D 0, C M D 1IO =0, M E M =1{IO=0, MEM=0, PI=0}IO=0, MEM=0Start initialization withCMD0 and CMD1Figure 3 Card initialization flow in SPI mode (SDIO aware host)4. Differences with SD Memory Specification4.1 Unsupported SD Memory commandsSeveral commands required for SD Memory devices are not supported by either SDIO-only cards or the I/O portion of Combo cards. Some of these commands have no use in SDIO devices such as Erase commands and thus are not supported in SDIO. In addition, there are several commands for SD memory cards that have different commands when used with the SDIO section of a card. Table 2 lists these SD Memory commands and the equivalent SDIO commands. For a complete list of supported and unsupported commands, see Table 4 and Table 5.Table 2 Unsupported SD Memory Commands4.2 BusWidthFor a SD memory card, the bus width for SD mode is set using ACMD6. The SDIO card uses a write to the CCCR using CMD52 to select bus width. In the case of a combo card, both selection methods exist. In this case, the host shall set the bus width in both locations by issuing both the ACMD6 and the CCCR write using CMD52 with the same width before starting any data transfers. Note that Low-Speed SDIO cards support 4-bit transfer as an option. When communication with a Low-Speed SDIO card, the host must first determine if the card supports 4-bit transfer prior to attempting to select that mode.4.3 Card Detect ResistorSD memory and I/O cards use a pull-up resistor on DAT[3] to detect card insertion. The procedure to enable/disable this resistor is different between SD memory and SDIO. SD memory uses ACMD42 to control this resistor while SDIO uses writes to the CCCR using CMD52. In the case of a combo card, both control locations exist and must be managed by the host. For a combo card, the resistor is enabled unless both the memory and the I/O control registers have the resistor disabled. After power-up, both locations default to resistor enabled. Note that after an I/O reset, the I/O resistor enable is not changed.Abort4.4 DataTransferA host communicating with a SD memory device uses CMD12 to abort the transfer of read or write data to/from the card. For an SDIO device, CMD12 abort is replaced by a write to the ASx bits in the CCCR. Normally, the abort is used to stop an infinite block transfer (block count=0). If an exact number of blocks to be transferred, it is recommended that the host issue a block command with the correct block count, rather than using an infinite count and aborting the data at the correct time.4.5 Changes to SD Memory Fixed RegistersRegister4.5.1 OCRAll SD cards (memory, I/O and combo) shall have at least one OCR register. If the card is a combo card, it may have two OCR’s (one for memory and one for I/O). The memory portion of a combo card has an OCR accessed using ACMD41 and CMD58. The I/O portion of a card has an OCR with the same structure that is accessed via CMD5. If there are multiple OCR’s the voltage range may not be identical. Some I/O functions may have a wider VDD range than that reflected in the I/O OCR register. The I/O OCR will be the logical AND of the voltage ranges(s) of all I/O functions. Note that the I/O OCR format is different from the memory version in that it is only 24 bits long. The per-function voltage for each I/O function can be read in the CIS for the card.Register4.5.2 CIDThere shall be a maximum of one CID register per SD card. If the card contains both memory and I/O, the CID register information is unchanged from the SD 1.01 version and reflects the information from the memory portion of the card. If the card is I/O only, the CID register and the associated access command (CMD10) are not supported. If the host attempts to access this register in an I/O only device, a card in SPI mode will respond with an "Invalid Command" error response and a card in SD mode will not respond.Register4.5.3 RCAThere shall only be one RCA register per SD card. The RCA value shall apply to the card as a whole. All functions and any memory share the same card address.5. New I/O Read/Write CommandsTwo additional data transfer instructions have been added to support I/O. IO_RW_DIRECT, a direct I/O command similar to the MMC 'Fast I/O' command, and IO_RW_EXTENDED, which allows fast access with byte or block addresses. Both commands are in class 9 (I/O Commands).5.1 IO_RW_DIRECT command (CMD52)The IO_RW_DIRECT is the simplest means to access a single register within the total 128K of register space in any I/O function, including the common I/O area (CIA). This command reads or writes 1 byte using only 1 command/response pair. A common use is to initialize registers or monitor status values for I/O functions. This command is the fastest means to read or write single I/O registers, as it requires only a single command/response pair.The SDIO card’s response to CMD52 will be in one of two formats. If the communication between the card and host is in the 1-bit or 4-bit SD mode, the response will be in a 48-bit response (R5). If the communication is using the SPI mode, the response will be a 16-bit R5 response.5.2 IO_RW_EXTENDED command (CMD53)In order to read and write multiple I/O registers with a single command, a new command, IO_RW_EXTENDED is defined. This command is included in command class 9 (I/O Commands). This command allows the reading or writing of a large number of I/O registers with a single command. Since this is a data transfer command, it provides the highest possible transfer rate.The response from the SDIO card to CMD53 will be R5 (the same as CMD52). For CMD53, the 8-bit data field will be stuff bits and shall be read as 0x00.5.2.1 CMD53 Data Transfer FormatWhen executing the IO_RW_EXTENDED (CMD53), the multi-byte or multi-block data transfer is similar to the data transfer for memory. For the multi-byte transfer modes (block mode=0) the following applies:IO_RW_EXTENDED byte read is similar to CMD17 (READ_SINGLE_BLOCK)IO_RW_EXTENDED byte write is similar to CMD24 (WRITE_BLOCK)Note that the byte count for this transfer is set in the command, rather than the fixed block size. Thus, the size of the data payload will be in the range of 1-512 bytes. The block mode is similar to the following memory commands:IO_RW_EXTENDED block read is similar to CMD18 (READ_MULTIPLE_BLOCK)IO_RW_EXTENDED block write is similar to CMD25 (WRITE_MULTIPLE_BLOCK)For the block mode the only difference is that for a fixed block count, the host does not need to stop the transfer, as it will continue until the block count is satisfied. If the block count is set to zero, the operation is identical to the memory mode in that the host must stop the transfer.6. SDIO Card Internal OperationI/O access differs from memory in that the registers can be written and read individually and directly without a FAT file structure or the concept of blocks (although block access is supported). These registers allow access to the I/O data, control of the I/O function and report on status or transfer I/O data to/from the host. The SD memory relies on the concept of a fixed block length with commands reading/writing multiples of these fixed size blocks. I/O may or may not have fixed block lengths and the read size may be different from the write size. Because of this, I/O operations may be based on either a length (byte count) or a block size.6.1 OverviewEach SDIO card may have from 1 to 7 functions plus one memory function built into it. A function is a self contained I/O device. I/O functions may be identical or completely different from each other. All I/O functions are organized as a collection of registers. There is a maximum of 131,072 (217) registers possible for each I/O function. These registers and their individual bits may be read Only (RO), Write Only (WO) or Read/Write (R/W). These registers can be 8, 16 or 32 bits wide within the card. All addressing is based on byte access. These registers can be written and/or read one at a time, multiply to the same address or multiply to an incrementing address. The single R/W access is often used to initialize the I/O function or to read a single status or data value. The multiple reads to a fixed address are used to read or write data from a data FIFO register in the card. The read to incrementing addresses is used to read or write a collection of data to/from a RAM area inside of the card. Figure 4 shows the mapping of the CIA and optional CSA space for an SDIO card.Time6.2 RegisterAccessAll registers in SDIO only cards and the SDIO portion of Combo cards must complete read and write data transfer in less than 1 second. The host can use 1 second as the timeout value for a non-responding location. If a functions needs to support an access time greater than 1 second, the card maker will use some function specific method that is not defined in this specification. The 1-second response time is dependant on the SDCLK frequency. If the Average frequency of the SDCLK is less than 100KHz then the card may not be able to respond within the 1-second limit. The host should adjust the timeout in the case the average frequency of the SDCLK is less than 100KHz.6.3 InterruptsAll SDIO hosts shall support interrupts in both the SPI and 1-bit SD modes. Each function within an SDIO or Combo card may implement interrupts as needed. The interrupt used on SDIO functions is a type commonly called “level sensitive”. Level sensitive means that any function may signal for an interrupt at any time, but once the function has signaled an interrupt, it will not release (stop signaling) the interrupt until the cause of the interrupt is removed or commanded to do so by the host. Since there is only 1 interrupt line, it may be shared by multiple interrupt sources. The function shall continue to signal the interrupt until the host responds and clears the interrupt. Since multiple interrupts may be active at once, it is the responsibility of the host to determine the interrupt source(s) and deal with it as needed. This is done on the SDIO function by the use of two bits, the interrupt enable and interrupt pending. Each function that may generate an interrupt has an interrupt enable bit. In addition, the SDIO card has a master interrupt enable that controls all functions. An interrupt will only be signaled to the SD bus if both the function’s enable and the card’s master enable are set. The second interrupt bit is called interrupt pending. This read-only bit tells the host which function(s) may be signaling for an interrupt. There is an interrupt pending bit for each function that can generate interrupts. These bits are located in the CCCR area.6.4 Suspend/ResumeWithin a multi-function SDIO or a Combo card, there are multiple devices (I/O and memory) that must share access to the SD bus. In order to allow the sharing of access to the host among multiple devices, SDIO and combo cards can implement the optional concept of suspend/resume. If a card supports suspend/resume, the host may temporarily halt a data transfer operation to one function or memory (suspend) in order to free the bus for a higher priority transfer to a different function or memory. Once this higher-priority transfer is complete, the original transfer is re-started where it left off (resume). Support of suspend/resume is optional on a per-card basis. If suspend/resume is implemented, it shall be supported by the memory (if any) of a Combo card and all I/O functions except 0 (the CIA). Note that the host can suspend multiple transactions and resume them in any order desired. I/O function 0 does not support suspend/resume. Note that Suspend/Resume is defined only for the SD 1 and 4-bit modes. It does not apply to SPI transfers.6.5 Read Wait (Optional)Host devices built to the SD Physical specification version 1.01 must control the SDCLK to stop the read data block output from a card executing a multiple read command whenever the host cannot accept more data. During the time that the host has stopped the SDCLK, a CMD52 cannot be issued. This limitation causes a problem in that a host device built to the SD Physical specification version 1.01 cannot perform the I/O command during a multiple read cycle.In order to eliminate this limitation, the SDIO specification adds the read wait control to enable the host to issue CMD52 during a multiple read cycle. Read Wait uses the DAT[2] line to allow the host to signal the card to temporarily halt the sending of read data by a card. This feature is optional for an SDIO or combo card. However, if an SDIO or combo supports Read Wait, all functions and any memory must support read wait. Note that Read Wait is defined only for the SD 1 and 4-bit modes. It does not apply to SPI transfers.To determine if a card supports the Read Wait protocol, the host must test SRW capability bit in the Card Capability byte of the CCCR. If a card does not support the Read Wait protocol, the only means a host has to stall (not abort) data in a read multiple command is to control the SDCLK.。

SD Host Controller 2.0设计说明书

SD Host Controller 2.0设计说明书（仅供内部使用）拟制：张杰日期： 2008-8-13审核：日期：审核：日期；批准：日期；创辉电脑深圳代表处香港创辉电脑有限公司深圳代表处研究管理部文档中心产品版本密级 V1.0绝密产品名称: SD Host Controller 2.0修订记录日期修订版本描述作者2008-8-13 1.0 初稿完成张杰目录目录 .................................................................................................................................................. ３第1章总体设计. (5)§1.1 SD卡控制器综述 (5)§1.2 SD卡控制器应用结构图 (5)§1.3 顶层结构图 (6)§1.4 SD卡控制器主要功能点 (6)§1.5 SD卡控制器接口描述 (7)§1.6 SD卡控制器寄存器定义 (8)第2章模块设计与验证 (29)§2.1 命令控制模块（CCL）设计与验证 (29)§2.1.1 模块说明 (29)§2.1.2 模块接口描述 (30)§2.1.3 状态机设计 (32)§2.1.4 功能仿真 (43)§2.2 中断控制/时钟管理模块（Clockgen/INT）设计与验证 (44)§2.2.1 模块说明 (44)§2.2.2 模块接口描述 (44)§2.2.3 模块结构图 (47)§2.2.4 功能仿真 (47)§2.3 数据控制模块（DCL）设计与验证 (50)§2.3.1 模块说明 (50)§2.3.2 详细功能描述 (50)§2.3.3 模块接口描述 (52)§2.3.4 状态机设计 (56)§2.3.5 功能仿真 (56)第3章系统级功能仿真和FPGA验证 (57)§3.1 功能仿真结果表格 (57)§3.2 FPGA验证 (57)第4章LINUX下SD卡驱动程序 (59)§4.1 SDIO驱动程序流程图 (59)§4.2 SD/MMC/SDHC Host 2.0驱动程序流程图 (61)§4.3 相关Card驱动流程图（2.0标准） (67)第5章附录（SD卡控制器验证计划书） (70)§5.1 SD控制器功能验证方案 (70)§5.1.1 验证环境 (70)§5.1.2 验证平台 (70)§5.1.3 验证流程 (71)§5.2 功能点统计 (72)§5.3 详细测试步骤和寄存器设置 (73)§5.4 FPGA验证 (77)§5.4.1 验证目标 (77)§5.4.2 验证方法 (78)§5.4.3 详细验证计划 (78)第6章参与设计人员 (81)第1章总体设计§1.1SD卡控制器综述本设计遵循SD Host Controller Simplified Specification Version2.00版本。

Product Specification 产品规格书

Part Number.1121-23001-101 Date2008-08-22 Document No.CEN08015B-A Page 1 / 10Product Specification产品规格书Prepared by：Beny yao制定：Checked by：Beny yao审核：Approved by：Daniel Yu核准：Part Number.1121-23001-101 Date2008-08-22 Document No.CEN08015B-A Page 2 / 101. SCOPE（适用范围） (3)2. REFERENCE DOCUMENTS（参考文件） (3)3. FEATURE & DIMENSIONS （特征及尺寸） (3)3.1. PRODUCT DIMENSION（产品尺寸） (3)3.2. PCB/PANEL LAYOUT （印刷电路板布局） (3)3.3. MATERIAL（材料） (4)3.4. MECHANICAL & ELECTRICAL CHARACTERISTIC （机械及电气特性） (4)3.5. PACKAGING（包装） (4)3.6. MARKING（标识） (4)3.7 TRANSPORTATION（运输） (4)3.8 STORAGE（存贮） (4)4. ENVIRONMENTAL（环境要求） (5)4.1. SOLDERABILITY（可焊性） (5)4.2. RESISTANCE TO SOLDER HEAT（耐焊接热） (5)4.2.1. Wave Soldering （波峰焊） (5)4.2.1.1. Preheat（预热） (5)4.2.1.2. Soldering（焊接） (5)4.2.1.3. Cool Down （冷却） (5)4.2.2. INFRARED REFLOW（红外线回流焊）.............................................................. . (5)4.2.2.1. Preheat（预热）........................................................................................ . (5)4.2.2.2. Soldering（焊接）...................................................................................... . (5)4.2.2.3. Cool Down （冷却）.................................................................................... .. (5)4.3. CLEANING （清洗） (5)5. PERFORMANCE AND TEST DESCRIPTION （性能及测试） (6)5.1. REQUIREMENT（要求） (6)5.2. TEST CONDITION（测试条件） (6)5.3. SAMPLE SELECTION（样品选择） (6)5.4. TEST SEQUENCE（测试顺序） (6)6. QUALITY ASSURANCE PROVISIONS （品质保证） (6)TABLE I：PERFORMANCE REQUIREMENTS .......................................7~8 TABLE II：PRODUCT QUALIFICATION TEST SEQUENCE (9)TABLE III：REFLOW SOLDERING PROFILE (10)Part Number.1121-23001-101 Date2008-08-22 Document No.CEN08015B-A Page 3 / 10PRODUCT SPECIFICATION1. SCOPE（适用范围）This product specification defines the product performance and the test methods to ascertain theperformance of the SD CARD., which is designed and manufactured by CMK本产品规格书规定了由旭竑电子设计生产的 SD CARD连接器产品的特性及测试方法.2. REFERENCE DOCUMENTS（参考文件）MIL-STD-1344A Test method for electrical connector （电子连接器测试方法）MIL-STD-202F Test method for electrical components （电子零件测试方法）EIA364 Test method for electrical components （电子零件测试方法）JIS C 0051 Test method for electrical components （电子零件测试方法）MIL-G-45204C Specification for gold plating （镀金规格）IEC-512-3 IEC standard for current carrying capacity tests（IEC电流测试标准）QQ-N-290A Specification for nickel plating （镀镍规格）MIL-P-81728A Specification for tin/lead plating （镀锡铅规格）MIL-T-10727B Specification for tin plating （镀锡规格）UL498 UL standard for safety of attachment plug and receptacle（UL安规要求标准）EN/ISO5961 Determination of total lead & cadmium content ( 总铅和总镉含量测定)EN1122 Determination of total lead & cadmium content ( 总铅和总镉含量测定)EN13346 Determination of heavy metals content ( 重金属含量测定)EPA3052 Determination of total lead & cadmium content ( 总铅和总镉含量测定)3. FEATURE & DIMENSIONS （特征及尺寸）3.1. PRODUCT DIMENSION （产品尺寸）These connectors shall have the dimensions as shown in customer drawing。

88E6122_88E6121-Datasheet-Part 1

Doc. No. MV-S103526-01, Rev. -April 14, 2006 Not Approved by Document Control - For Review Only
Link Street™ 88E6122/88E6121 Datasheet Part 1 of 3: Overview, Pinout, Applications, Mechanical and Electrical Specifications
Doc. No. MV-S103526-01 Rev. -Page 2
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Document Classification: Restricted Information Not Approved by Document Control - For Review Only
Copyright © 2006 Marvell April 14, 2006, Draft

Final
This document contains specifications on a product that is in final release. Specifications may
Information change without notice. Contact Marvell Field Application Engineers for more information.
Document Status
Advance
This document contains design specifications for initial product development. Specifications may
Information change without notice. Contact Marvell Field Application Engineers for more information.

SDIO协议规范

SDIO协议规范篇一：SDIO协议简介SDIO卡SDIO卡是在SD内存卡接口的基础上发展起来的接口，SDIO接口兼容以前的SD内存卡，并且可以连接SDIO接口的设备，目前根据SDIO协议的SPEC，SDIO接口支持的设备总类有蓝牙，网卡，电视卡等。

SDIO协议是由SD卡的协议演化升级而来的，很多地方保留了SD卡的读写协议，同时SDIO协议又在SD卡协议之上添加了CMD52和CMD53命令。

由于这个，SDIO和SD卡规范间的一个重要区别是增加了低速标准，低速卡的目标应用是以最小的硬件开始来支持低速I/O能力。

低速卡支持类似调制解调器,条形码扫描仪和GPS接收器等应用。

高速卡支持网卡，电视卡还有“组合”卡等，组合卡指的是存储器+SDIO。

SDIO和SD卡的SPEC间的又一个重要区别是增加了低速标准。

SDIO卡只需要SPI和1位SD传输模式。

低速卡的目标应用是以最小的硬件开支来支持低速I/O能力，低速卡支持类似MODEM，条形扫描仪和GPS接收器等应用。

对组合卡来说，全速和4BIT操作对卡内存储器和SDIO部分都是强制要求的。

在非组合卡的SDIO设备里，其最高速度要只有达到25M，而组合卡的最高速度同SD卡的最高速度一样，要高于25M。

SDIO总线SDIO总线和USB总线类似，SDIO总线也有两端，其中一端是主机（HOST）端，另一端是设备端（DEVICE），采用HOST-DEVICE这样的设计是为了简化DEVICE的设计，所有的通信都是由HOST端发出命令开始的。

在DEVICE端只要能解溪HOST 的命令，就可以同HOST进行通信了。

SDIO的HOST可以连接多个DEVICE，如下图所示:这个是同SD的总线一样的,其中有如下的几种信号1. CLK信号:HOST给DEVICE的时钟信号.2. CMD信号：双向的信号，用于传送命令和反应。

3. DAT0-DAT3 信号:四条用于传送的数据线。

4. VDD信号:电源信号。

SDIO协议文档

SDIO协议文档SDIO1.00协议简介1目录1 目的 ..................................................................... ..................................................... - 1 - 2 备注 ..................................................................... ..................................................... - 1 - 3 SDIO SignalingDefinition ............................................................. ............................. - 1 -3.1 SDIO cardtypes .................................................................. ........................ - 1 -3.2 SDIO cardmodes .................................................................. ...................... - 1 -3.3 SDIO HostModes .................................................................. ..................... - 1 -3.4 信号引脚 ..................................................................... ............................... - 2 -3.5 Host requirements forSDIO ................................................................... ...... - 2 - 4 SDIO card初始化 ..................................................................... ................................ - 2 -4.1 IO CARD初始化的差异 ..................................................................... ........ - 2 -4.2 The IO_SEND_OP_COND Command(CMD5) ............................................ - 3 -4.3 The IO_SEND_OP_COND Response(R4) ................................................... - 4 - 5 Differences with SD Memory Specification(与SD内存标准的差异) ........................... - 4 -5.1 SDIO 命令清单 ..................................................................... .................... - 4 -5.2 Card DetectResistor ............................................................... ..................... - 5 -5.3 数据传输停止...................................................................... ....................... - 5 -5.4 Changes to SD Memory FixedRegisters ....................................................... - 5 -5.4.1 OCR寄存器 ..................................................................... ................... - 5 -5.4.2 CID寄存器 ..................................................................... .................... - 5 -5.4.3 RCA 寄存器 ..................................................................... .................. - 6 - 6 新IO读写命令 ..................................................................... .................................... - 6 -6.1 IO_RW_DIRECTcommand(CMD52) .......................................................... - 6 -6.2 IO_RW_DIRECTResponse(R5)............................................................ ....... - 6 -6.3 IO_RW_EXTENDEDcommand(CMD53) .................................................... - 7 -6.3.1 CMD53 数据传输格式 ..................................................................... .. - 7 - 7 SDIO内部操作 ..................................................................... .................................... - 8 -7.1 Register AccessTime ................................................................... ................ - 8 -7.2Interrupts ............................................................. ....................................... - 8 -7.3 SDIO Fixed InternelMap .................................................................... ......... - 8 -7.4 Common IOArea ................................................................... ..................... - 9 -7.5 CCCR(Card Common ControlRegister) ................................................... - 9 -7.6 FBR(Function BasicRegisters) ............................................................. .. - 12 -7.7 Card InformationStructure(CIS) ......................................................... ........ - 14 -7.8 Multiple Function SDIOCards ................................................................... - 14 -7.9 Setting Block Size withCMD53 ................................................................. - 14 - 8 Embedded I/O Code Storage Area(CSA) .................................................................. - 15 -21 目的本文描述的是基于SDIO标准协议1.0版本，主要描述协议中比较重要的细节信息。

MiiNePort E1 Series 固件更新说明书

Firmware for MiiNePort E1 Series Release NotesSupported Operating SystemsNotesChangesApplicable ProductsBugs Fixed• Prevents XSS attacks on web server.• Extended challenge ID to 64 bytes for security purposes.• Supports CSRF token on webpage for security purposes.• Enhanced web login security and supports 5 users logged in simultaneously.• Enabled default password for login.• Supports encrypted import/export.• Removed the echo server (port 7) function.• The "sysDescr" default value is set to the model name.• SCM client connections support TCP client mode.• In MCSC mode, MiiNePort may stop sending continuous data when using a slow baudrate.• Console showed DIO state error when DIO mode was set to input.• In Real COM mode, opening a port caused RX malfunctions while the port was receiving data.• In Real COM mode, the data port connection counter would be incorrect when only the command port was connected and a command timeout notification occurred.• Data would not be completely sent to the serial port when the TCP connection closed immediately after data was transmitted from host.EnhancementsN/AMiiNePort E1-T, MiiNePort E1-H-T, MiiNePort E1-ST, MiiNePort E1, MiiNePort E1-H• Supports SCM client connections in MCSC mode.• In TCP client, for the manual connection option in connection control, both the IP and domain name can be entered from serial.New FeaturesN/A• This version also support MiiNePort E1-SDK, MiiNePort E1-H-SDK, and MiiNePort E1-ST (w/o module)Supported Operating SystemsNotesChangesApplicable ProductsBugs Fixed• If MiiNePort receives a ARP request from another host for which an ARP entry already exists, the hardware address in the ARP entry will be updated accordingly.• RFC1213-MIB "Get Next" of sysServices will get ifIndex instead of ifNumber.EnhancementsN/AMiiNePort E1, MiiNePort E1-H, MiiNePort E1-T, MiiNePort E1-H-T, MiiNePort E1-ST• Supports MiiNePort SDK firmware.New FeaturesN/A• This version also support MiiNePort E1-SDK, MiiNePort E1-H-SDK, and MiiNePort E1-ST (w/o module)Supported Operating SystemsNotesChangesApplicable ProductsBugs FixedN/A• In Real COM mode, the alive check mechanism would not work properly.• In Windows 7 with IE8, images on the webpage may be missing.• TCP retransmission may happen immediately.EnhancementsN/AMiiNePort E1, MiiNePort E1-H, MiiNePort E1-T, MiiNePort E1-H-T, MiiNePort E1-STN/ANew FeaturesN/A• This version also support MiiNePort E1-SDK, MiiNePort E1-H-SDK, and MiiNePort E1-ST (w/o module)Supported Operating SystemsNotesChangesApplicable ProductsBugs FixedN/A• In Real COM mode, the MiiNePort E1 would reboot when users closed the port.EnhancementsN/AMiiNePort E1, MiiNePort E1-H, MiiNePort E1-T, MiiNePort E1-H-T, MiiNePort E1-STN/ANew FeaturesN/A• This version also support MiiNePort E1-SDK, MiiNePort E1-H-SDK, and MiiNePort E1-ST (w/o module)Supported Operating SystemsNotesChangesApplicable ProductsBugs Fixed• Changed the filename of configuration file for the AutoCFG process. The file name for MiiNePort E1is "MiiNePortE1.txt", for MiiNePort E1-H is "MiiNePortE1-H.txt". If the MiiNePort E1 cannot get the "MiiNePortE1.txt" file, it will try to get the "MiiNePortE1.cfg" file.• In the web console, when changing the OP mode to MCSC and submitting immediately, the OP mode would be unchanged.• Setting "Match bytes" as 2 byte by NECI command lost efficacy.• The device name would be cleared after changing miscellaneous settings from the web console.• Doing a firmware upgrade from the web console would fail occasionally.• DHCP would fail occasionally.• The gratuitous ARP period value limit range was not matched between the telnet console and web console.EnhancementsN/AMiiNePort E1, MiiNePort E1-H, MiiNePort E1-T, MiiNePort E1-H-T, MiiNePort E1-ST• Supports MiiNePort E1-H, MiiNePort E1-H-T.• When DHCP or BOOTP server does not respond properly, the Fault LED (right side of the RJ45jack) will blink amber every 0.5 seconds.New FeaturesN/A• This version also support MiiNePort E1-SDK, MiiNePort E1-H-SDK, and MiiNePort E1-ST (w/o module)Supported Operating SystemsNotesChangesApplicable ProductsBugs FixedN/A• Setting the destination port for UDP mode using the web console did not work.• The destination port for TCP Client mode only accepted 4 digits in the telnet console.• ExTrigger reset-to-default functionality sometimes failed to reset IP settings when AutoIP/AutoCfg was enabled.• The text "Configuration Tool" in the web/telnet console should be plural.• MiiNePort would continue trying to connect to peer host in TCP Client mode even if serial command mode was triggered.• Invalid destination port numbers for UDP mode could be set through the web console.• Destinations for UDP mode would be cleared when the settings of other operation modes were changed through the web console.• Destination 2-4 for UDP mode should be cleared when configuring UDP mode using simple view through the web console.• "Configuration Tools Settings OK" would be incorrectly shown after configuring Auto Configuration through the web console.• Reset-to-default via NECI did not work.• Data 0x00 would trigger serial command mode when it was set to trigger by break signal.• Retrieving MAC addresses in serial command mode returned unrecognized information.• For configuration of serial command mode SW trigger characters, the exported configuration file did not include the second and third trigger characters.• Connecting to a non-existing host caused delays for all other packets.EnhancementsN/AMiiNePort E1, MiiNePort E1-H, MiiNePort E1-T, MiiNePort E1-H-T, MiiNePort E1-STN/ANew FeaturesN/A• This version also support MiiNePort E1-SDK, MiiNePort E1-H-SDK, and MiiNePort E1-ST (w/o module)。

达维尼SDIO堆栈用户指南说明书

Custom SDIO stack DaVinciNovember 2007Document Version 1.1Read This FirstIMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue anyproduct or service without notice. Customers should obtain the latest relevant information before placing ordersand should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TIdeems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed.TI assumes no liability for applications assistance or customer product design. Customers are responsible fortheir products and applications using TI components. To minimize the risks associated with customer productsand applications, customers should provide adequate design and operating safeguards.TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or processin which TI products or services are used. Information published by TI regarding third-party products or servicesdoes not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Useof such information may require a license from a third party under the patents or other intellectual property of thethird party, or a license from TI under the patents or other intellectual property of TI.Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alterationand is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for suchaltered documentation.Resale of TI products or services with statements different from or beyond the parameters stated by TI for thatproduct or service voids all express and any implied warranties for the associated TI product or service and is anunfair and deceptive business practice. TI is not responsible or liable for any such statements.Following are URLs where you can obtain information on other Texas Instruments products and application solutions:Products ApplicationsAmplifiers Audio /audioData Converters Automotive /automotiveDSP Broadband /broadbandInterface Digital Control /digitalcontrolLogic Military /militaryPower Mgmt Optical Networking /opticalnetworkMicrocontrollers Security /securityTelephony /telephonyVideo & Imaging /videoWireless /wirelessMailing Address:Texas InstrumentsPost Office Box 655303, Dallas, Texas 75265Copyright © 2004, Texas Instruments Incorporatedii Texas Instruments ProprietaryThis document contains information that is the confidential property of Texas Instruments Inc. It is provided under Nondisclosure and License and is not to be reproduced or distributed without prior written consent of Texas Instruments Inc.November 2007 Document Version 1.1Preface Read This FirstAbout This ManualThis User’s Manual serves as a software programmer’s handbook for working with the Custom SDIO stack for DaVinci. This manual provides necessary information regarding how to effectively install, build and use Custom SDIO stack for DaVinci in user systems and applications.Terms and AbbreviationsTerm/Abbreviation DescriptionCustom SDIO stack for DaVinci This is a driver to replace the default SD/MMC drivers in the kernel.DVEVM DaVinci Evaluation ModuleTII Texas Instruments IndiaNotationsNAInformation About Cautions and WarningsNARelated DocumentationInternalNAExternalNARead This First2Texas Instruments ProprietaryThis document contains information that is the confidential property of Texas Instruments Inc. It is provided under Nondisclosure and License and is not to be reproduced or distributed without prior written consent of Texas Instruments Inc.TrademarksThe TI logo design is a trademark of Texas Instruments Incorporated. All other brand and product names may be trademarks of their respective companies.This document contains proprietary information of Texas Instruments. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an officer of Texas Instruments Incorporated.Revision HistoryDate Author Revision HistoryVersion 20/11/07Suresh Rajashekara Initial Draft Created0.103rd January 2008Sekhar NoriUpdated for 045 release 0.2Contents Custom SDIO stack DaVinci (i)IMPORTANT NOTICE (ii)1.1Introduction (4)1.2Compiling the driver (4)1.2.1Patching the kernel (4)1.2.2Enabling support in kernel (4)1.2.3Kernel Dependencies (6)1.3Using Driver Modules (6)1.3.1Driver Module parameters (6)1.4Removing Driver Modules (7)1.5Benchmark Module (7)1.6Atheros AR6000 Wireless LAN (8)1.7Limitations (8)Texas Instruments Proprietary I-3 This document contains information that is the confidential property of Texas Instruments Inc. It is provided under Nondisclosure and License and is not to be reproduced or distributed without prior written consent of Texas Instruments Inc.Contents1.1IntroductionThis driver is an alternative to the existing MMC/SD drivers1.2Compiling the driver1.2.1Patching the kernelThe custom SDIO Stack is released as a set of patches which need to be applied to the Montavista Linux kernel version 2.6.10 LSP for DaVinci DM644x EVM. Please refer to the Release Notes of the particular release you are using for detailed instructions on the patch application process.1.2.2Enabling support in kernelTo use the custom SDIO Stack and the SD/MMC memory drivers with DaVinci Platform, use the following steps:1.Configure the kernel for DM644X with the following command# make davinci_dm644x_defconfige “make menuconfig” to remove the Kernel MMC Support in the configurationDevice Drivers --->MMC/SD Card Support ---><> MMC supporte “make menuconfig” tp enable SDIO Support by selecting the Following configuration. Oneor more function drivers may also be selected.Device Drivers --->SDIO support ---><M> SDIO supportHost Controllers ---><M> TI Davinci host controllerSDIO function drivers --->4Texas Instruments ProprietaryThis document contains information that is the confidential property of Texas Instruments Inc. It is provided under Nondisclosure and License and is not to be reproduced or distributed without prior written consent of Texas Instruments Inc.<M> memory card over sdio4.Run “make uImage” to obtain the kernel images. Run “make modules” to obtain the stack andfunction driver modules.Enabling SDIO support requires the default kernel MMC support. i.e CONFIG_MMC to be disabled. The SDIO stack in its current form, does not allow the stack and and drivers to be built as part of the kernel. The drivers shall be built only as dynamically loadable modules. CONFIG_SDIO and CONFIG_SDIO_DAVINCI are mandatory for SDIO stack to be running on Davinci. Other modules are client/function driver modules required for specific cards.Configuration Option PurposeCONFIG_SDIO Enables SDIO support. Requires kernel defaultMMC support (CONFIG_MMC) is turned off. CONFIG_SDIO_DAVINCI Enables SDIO stack implementation on DavinciDM644x EVM.CONFIG_SDIO_MEMORY Enables client driver required forSD/MMC/SDHC cardsCONFIG_SDIO_AR6000_WLAN Enables client driver for Atheros AR6000 SDIOWireless LAN module.This depends onCONFIG_NET option and auto-selects CONFIG_NET_RADIO to enablewireless extensionCONFIG_SDIO_BLUETOOTH Client driver for SDIO Bluetooth Type-A card orType-B card in Type-A modeCONFIG_SDIO_BENCHMARK Client driver for functional / benchmark testing ofSD/SDIO/MMC cards. Use with care on memorycards (as it uses raw read/write)CONFIG_SDIO_SDHC [OPTIONAL]Enables SDHC support in the stack and DavinciHost controller driverCONFIG_SDIO_ENHANCE [OPTIONAL]Enables SD/MMC throughput enhancementcode for Davinci host platformTexas Instruments Proprietary I-5 This document contains information that is the confidential property of Texas Instruments Inc. It is provided under Nondisclosure and License and is not to be reproduced or distributed without prior written consent of Texas Instruments Inc.Contents1.2.3Kernel DependenciesThe SDIO stack uses Plug-and-Play (CONFIG_PNP) interface for adding/removing devices. This shall be enabled in the kernel for the stack and drivers to be loaded correctly. Linux kernel allows CONFIG_PNP to be enabled only for x86 architecture or systems with ISA Bus support. This hasbeen modified to include SDIO bus support. The 'arch/arm/defconfig' and 'arch/arm/configs/davinci_defconfig' files have been modified to enable CONFIG_PNP by default as mentioned below.CONFIG_PNP=yIf a different configuration is used other than the default configuration then the above configuration option shall be added to the kernel configuration file (.config). This option can not be enabledthrough the configuration menus due to other missing dependencies1.3Using Driver ModulesThe driver modules shall be loaded in the following sequence for proper operationinsmod sdio_lib.koinsmod sdio_busdriver.koinsmod sdio_davinci_hcd.koinsmod sdio_memory_fd.koSD/MMC Card shall be inserted at any point in time (before/during/after) of the module loading.Memory devices can be accessed using device nodes /dev/mmcblk0p1, /dev/mmcblk0p2, etc...depending on the partitions in the card1.3.1Driver Module parametersThe following parameters are available for the DaVinci host driver (sdio_davinci_hcd.ko).no_dmaThis parameter is used to enable or disable DMA. The default value is 0.To disable DMA, set this parameter to 1.high_speedThis parameter is used to enable or disable High Speed support for SD and MMC4 cards. The default value is 0. To enable high speed mode set this parameter to 1. Please note that some SD and MMC4 cards have timing issues with Davinci host and might result in DATA CRC errors in high speed mode.max_sdbus_clock6Texas Instruments ProprietaryThis document contains information that is the confidential property of Texas Instruments Inc. It is provided under Nondisclosure and License and is not to be reproduced or distributed without prior written consent of Texas Instruments Inc.This parameter is used to specify the maximum bus clock frequency for the davinci host. The default value is 25000000 (25MHz). When high speed is enabled with 'high_speed' parameter, the maximum frequency is set to 50MHz.builtin_cardThis parameter is used to inform the host driver that the SD/SDIO card is always connected to the slot. This option disables the SD/SDIO card polling mechanism of the host driver and results in improved performance.dma_channelsNumber of slave channels used for Scatter gather chaining. Default is 3. Increasing the slave channels marginally increase throughput for EXT2. For FAT filesystem, 3slave channels are sufficient.Example:# insmode sdio_davinci_hcd.ko no_dma=1 high_speed=1 max_sdbus_clock=500000001.4Removing Driver ModulesThe driver modules shall be removed in the following sequence for proper operation.rmmod sdio_memory_fd.kormmod sdio_davinci_hcd.kormmod sdio_busdriver.kormmod sdio_lib.koPlease note that removing sdio_davinci_hcd.ko before removing the sdio_memory_fd might result in the unload command being blocked if the modules are in use. The above mentioned sequence is adviced always.1.5Benchmark ModuleThe benchmark function driver may be used to verify SD/MMC memory card data transfers and also to calculate the read/write speeds. Enable the benchmark function driver and load it in place of the memory function driver.WARNING - The benchmark function driver does raw read/write transfers for testing and this will corrupt the SD/MMC card used for benchmark testing.Data in the card will be lost and use this only for testing purposes.Texas Instruments Proprietary I-7 This document contains information that is the confidential property of Texas Instruments Inc. It is provided under Nondisclosure and License and is not to be reproduced or distributed without prior written consent of Texas Instruments Inc.Contents 1.6Atheros AR6000 Wireless LANThe ar6000.ko function/client driver module is used with the Atheros AR6000SDIO Wireless LAN card. To use this card, load the drivers as mentioned below:insmod sdio_lib.koinsmod sdio_busdriver.koinsmod sdio_davinci_hcd.koinsmod ar6000.koThe AR6000 interface shall be accessible using a name "ethX". Typically this will be "eth1" if the on-board ethernet module is enabled and active. To configure the wireless interface, wireless tools can be used as mentioned below.ifconfig eth1 X.X.X.X- Enables the interface and assigns an IP address to it.iwconfig eth1 mode managed- Places the interface in Managed/Infrastructure mode. An Access Point is required for communicationiwconfig eth1 key 12345678901234567890123456- Optionally configure the interface with 104-bit WEP key.iwconfig eth1 essid TestESSID- Joint the network using the ESSID. ESSID shall be set after configuring all other parameters. 1.7LimitationsThere are some know limitations of custom SDIO stack and the AR6000 driver. Please refer to the “Known Issues” section in the Release Notes provided with the release package for a complete documentation of the known limitations.8Texas Instruments ProprietaryThis document contains information that is the confidential property of Texas Instruments Inc. It is provided under Nondisclosure and License and is not to be reproduced or distributed without prior written consent of Texas Instruments Inc.。