专用集成电路设计中科院段成华

Configuration cfg_rs_ff of RS_FF is for struct for c0: nandgate use entity work.NANDGATE generic map(N=>2, tLH=>1 ns, tHL=>5 ns, STRN=>STRN_X01) port map(input(1)=>I_1, input(2)=>I_2, output=>output); end for; for c1: nandgate use entity work.NANDGATE generic map(N=>2, tLH=>2 ns, tHL=>4 ns, STRN=>STRN_X01) port map(input(1)=>I_1, input(2)=>I_2, output=>output); end for; end for; end cfg_rs_ff;
STRN: STRENGTH := STRN_X01);-strength port (INPUT: in STD_LOGIC;-- inputs OUTPUT: out STD_LOGIC); -- output end INVERTER; architecture A of INVERTER is signal CURRENTSTATE: STD_LOGIC := 'U'; subtype TWOBIT is STD_LOGIC_VECTOR (0 to 1); begin P: process variable NEXTSTATE: STD_LOGIC; variable DELTA: Time; variable NEXT_ASSIGN_VAL: STD_LOGIC; begin -- evaluate logical function -- if one input is '0' then the andgate output is '0' NEXTSTATE := not INPUT; NEXTSTATE := STRENGTH_MAP(NEXTSTATE, STRN); if (NEXTSTATE /= NEXT_ASSIGN_VAL) then -- compute delay case TWOBIT'(CURRENTSTATE & NEXTSTATE) is when "UU"|"UX"|"UZ"|"UW"|"U-"|"XU"|"XX"|"XZ"|"XW"| "X-"|"ZU"|"ZX"|"ZZ"|"ZW"|"Z-"|"WU"|"WX"|"WZ"| "WW"|"W-"|"-U"|"-X"|"-Z"|"-W"|"--"|"00"|"0L"| "LL"|"L0"|"11"|"1H"|"HH"|"H1" => DELTA := 0 ns; when "U1"|"UH"|"X1"|"XH"|"Z1"|"ZH"|"W1"|"WH"|"-1"| "-H"|"0U"|"0X"|"01"|"0Z"|"0W"|"0H"|"0-"|"LU"| "LX"|"L1"|"LZ"|"LW"|"LH"|"L-" => DELTA := tLH; when others => DELTA := tHL; end case; -- assign new value after internal delay CURRENTSTATE <= NEXTSTATE after DELTA; OUTPUT <= NEXTSTATE after DELTA; NEXT_ASSIGN_VAL := NEXTSTATE; end if; -- wait for signal changes wait on INPUT; end process P; end A;
Assignment 2
1. (7.10) Implement a NAND gate model using the IEEE nine-valued system. For the RS flip-flop shown in Figure 7.60, assume that both
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gate outputs are initially U, and that the two inputs R and S are initially 0 and switch to 1 simultaneously. Simulate the circuit at logic gate level when: a. Both gates have identical delays. b. The two gates have different delays. Compare your results.
（4） code for testbench
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY TB_RD_FF IS END TB_RD_FF;
ARCHITECTURE behavior OF TB_RD_FF IS -- Component Declaration COMPONENT RS_FF PORT( R,S : IN std_logic; Y,NY : INOUT std_logic ); END COMPONENT; for TB_RD_FF: RS_FF use configuration work.cfg_rs_ff; signal R,S : std_logic :='0'; signal Y,NY : std_logic :='U'; -- Test Bench Statements BEGIN TB_RD_FF: RS_FF PORT MAP (R => R, S => S, Y => Y, NY => NY); stim_proc: process begin R <= transport '0'; S <= transport '0'; WAIT FOR 100 ns; R <= transport '1'; S <= transport '1'; WAIT FOR 100 ns; end process; END;
（5） test result
a、Both gates have identical delays.
b、The two gates have different delays. Compare your results.
在 cfg_rs_ff 中更改 generic map 中的延时参数 library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_MISC.all; 两与非门延时 不相同
（2） code for rs_ff
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity RS_FF is Port ( S : in STD_LOGIC; R : in STD_LOGIC; Y : inout STD_LOGIC; NY : inout STD_LOGIC); end RS_FF;
（3） code for configuration
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_MISC.all; 两与非门延时 相同 Configuration cfg_rs_ff of RS_FF is for struct for c0: nandgate use entity work.NANDGATE generic map(N=>2, tLH=>1 ns, tHL=>5 ns, STRN=>STRN_X01) port map(input(1)=>I_1, input(2)=>I_2, output=>output); end for; for c1: nandgate use entity work.NANDGATE generic map(N=>2, tLH=>1 ns, tHL=>5 ns, STRN=>STRN_X01) port map(input(1)=>I_1, input(2)=>I_2, output=>output); end for; end for; end cfg_rs_ff;
S’ C1 YR’Fra bibliotekFigure 7.60
C2
Y’
R-S flip-flop
（1） code for nand_2
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_MISC.all; entity NANDGATE is generic (N: Positive := 2;-- number of inputs tLH: Time := 10 ns; -- rise inertial delay tHL: Time := 15 ns; -- fall inertial delay STRN: STRENGTH := STRN_X01);-- output strength port (INPUT: in STD_LOGIC_VECTOR (1 to N);-- inputs OUTPUT: out STD_LOGIC); -- output end NANDGATE; architecture A of NANDGATE is signal CURRENTSTATE: STD_LOGIC := 'U'; subtype TWOBIT is STD_LOGIC_VECTOR (0 to 1); begin P: process variable NEXTSTATE: STD_LOGIC; variable DELTA: Time; variable NEXT_ASSIGN_VAL: STD_LOGIC; begin