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XCS05XL-4BG100I中文资料

© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at /legal.htm .All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.IntroductionThe Spartan ™ and the Spartan-XL families are a high-vol-ume production FPGA solution that delivers all the key requirements for ASIC replacement up to 40,000 gates.These requirements include high performance, on-chip RAM, core solutions and prices that, in high volume,approach and in many cases are equivalent to mask pro-grammed ASIC devices.The Spartan series is the result of more than 14 years of FPGA design experience and feedback from thousands of customers. By streamlining the Spartan series feature set,leveraging advanced process technologies and focusing on total cost management, the Spartan series delivers the key features required by ASIC and other high-volume logic users while avoiding the initial cost, long development cycles and inherent risk of conventional ASICs. The Spar-tan and Spartan-XL families in the Spartan series have ten members, as shown in T able 1.Spartan and Spartan-XL FeaturesNote: The Spartan series devices described in this data sheet include the 5V Spartan family and the 3.3V Spartan-XL family. See the separate data sheet for the 2.5V Spartan-II family.•First ASIC replacement FPGA for high-volume production with on-chip RAM•Density up to 1862 logic cells or 40,000 system gates •Streamlined feature set based on XC4000 architecture •System performance beyond 80MHz•Broad set of AllianceCORE ™ and LogiCORE ™ predefined solutions available •Unlimited reprogrammability •Low cost•System level features-Available in both 5V and 3.3V versions -On-chip SelectRAM ™ memory -Fully PCI compliant-Full readback capability for program verificationand internal node observability -Dedicated high-speed carry logic -Internal 3-state bus capability-Eight global low-skew clock or signal networks -IEEE 1149.1-compatible Boundary Scan logic -Low cost plastic packages available in all densities -Footprint compatibility in common packages•Fully supported by powerful Xilinx development system -Foundation Series: Integrated, shrink-wrapsoftware-Alliance Series: Dozens of PC and workstationthird party development systems supported-Fully automatic mapping, placement and routing Additional Spartan-XL Features• 3.3V supply for low power with 5V tolerant I/Os •Power down input •Higher performance •Faster carry logic•More flexible high-speed clock network•Latch capability in Configurable Logic Blocks •Input fast capture latch•Optional mux or 2-input function generator on outputs •12 mA or 24 mA output drive •5V and 3.3V PCI compliant •Enhanced Boundary Scan •Express Mode configuration •Chip scale packagingSpartan and Spartan-XL Families Field Programmable Gate ArraysDS060 (v1.6) September 19, 2001Product Specification T able 1: Spartan and Spartan-XL Field Programmable Gate Arrays1.Max values of Typical Gate Range include 20-30% of CLBs used as RAM.2DS060 (v1.6) September 19, 2001General OverviewSpartan series FPGAs are implemented with a regular, flex-ible, programmable architecture of Configurable Logic Blocks (CLBs), interconnected by a powerful hierarchy of versatile routing resources (routing channels), and sur-rounded by a perimeter of programmable Input/Output Blocks (IOBs), as seen in Figure 1. They have generous routing resources to accommodate the most complex inter-connect patterns.The devices are customized by loading configuration data into internal static memory cells. Re-programming is possi-ble an unlimited number of times. The values stored in thesememory cells determine the logic functions and intercon-nections implemented in the FPGA. The FPGA can either actively read its configuration data from an external serial PROM (Master Serial mode), or the configuration data can be written into the FPGA from an external device (Slave Serial mode).Spartan series FPGAs can be used where hardware must be adapted to different user applications. FPGAs are ideal for shortening design and development cycles, and also offer a cost-effective solution for production rates well beyond 50,000 systems per month.Figure 1: Basic FPGA Block DiagramSpartan series devices achieve high-performance, low-cost operation through the use of an advanced architecture and semiconductor technology. Spartan and Spartan-XL devices provide system clock rates exceeding 80MHz and internal performance in excess of150MHz. In contrast to other FPGA devices, the Spartan series offers the most cost-effective solution while maintaining leading-edge per-formance. In addition to the conventional benefit of high vol-ume programmable logic solutions, Spartan series FPGAs also offer on-chip edge-triggered single-port and dual-port RAM, clock enables on all flip-flops, fast carry logic, and many other features.The Spartan/XL families leverage the highly successful XC4000 architecture with many of that family’s features and benefits. T echnology advancements have been derived from the XC4000XLA process developments.Logic Functional DescriptionThe Spartan series uses a standard FPGA structure as shown in Figure1, page2. The FPGA consists of an array of configurable logic blocks (CLBs) placed in a matrix of routing channels. The input and output of signals is achieved through a set of input/output blocks (IOBs) forming a ring around the CLBs and routing channels.•CLBs provide the functional elements for implementing the user’s logic.•IOBs provide the interface between the package pins and internal signal lines.•Routing channels provide paths to interconnect the inputs and outputs of the CLBs and IOBs.The functionality of each circuit block is customized during configuration by programming internal static memory cells. The values stored in these memory cells determine the logic functions and interconnections implemented in the FPGA.Configurable Logic Blocks (CLBs)The CLBs are used to implement most of the logic in an FPGA. The principal CLB elements are shown in the simpli-fied block diagram in Figure2. There are three look-up tables (LUT) which are used as logic function generators, two flip-flops and two groups of signal steering multiplexers. There are also some more advanced features provided by the CLB which will be covered in the Advanced Features Description, page13.Function GeneratorsTwo 16x1 memory look-up tables (F-LUT and G-LUT) are used to implement 4-input function generators, each offer-ing unrestricted logic implementation of any Boolean func-tion of up to four independent input signals (F1 to F4 or G1 to G4). Using memory look-up tables the propagation delay is independent of the function implemented.A third 3-input function generator (H-LUT) can implement any Boolean function of its three inputs. Two of these inputs are controlled by programmable multiplexers (see box "A" of Figure2). These inputs can come from the F-LUT or G-LUT outputs or from CLB inputs. The third input always comes from a CLB input. The CLB can, therefore, implement cer-tain functions of up to nine inputs, like parity checking. The three LUTs in the CLB can also be combined to do any arbi-trarily defined Boolean function of five inputs.4DS060 (v1.6) September 19, 2001A CLB can implement any of the following functions:•Any function of up to four variables, plus any second function of up to four unrelated variables, plus any third function of up to three unrelated variablesNote: When three separate functions are generated, one of the function outputs must be captured in a flip-flop internal to the CLB. Only two unregistered function generator outputs are available from the CLB.•Any single function of five variables•Any function of four variables together with some functions of six variables•Some functions of up to nine variables.Implementing wide functions in a single block reduces both the number of blocks required and the delay in the signal path, achieving both increased capacity and speed. The versatility of the CLB function generators significantly improves system speed. In addition, the design-software tools can deal with each function generator independently.This flexibility improves cell usage.Flip-FlopsEach CLB contains two flip-flops that can be used to regis-ter (store) the function generator outputs. The flip-flops and function generators can also be used independently (see Figure 2). The CLB input DIN can be used as a direct input to either of the two flip-flops. H1 can also drive either flip-flop via the H-LUT with a slight additional delay.The two flip-flops have common clock (CK), clock enable (EC) and set/reset (SR) inputs. Internally both flip-flops are also controlled by a global initialization signal (GSR) which is described in detail in Global Signals: GSR and GTS ,page 20.Latches (Spartan-XL only)The Spartan-XL CLB storage elements can also be config-ured as latches. The two latches have common clock (K)and clock enable (EC) inputs. Functionality of the storage element is described in Table 2.Figure 2: Spartan/XL Simplified CLB Logic Diagram (some features not shown)Clock InputEach flip-flop can be triggered on either the rising or falling clock edge. The CLB clock line is shared by both flip-flops.However, the clock is individually invertible for each flip-flop (see CK path in Figure 3). Any inverter placed on the clock line in the design is automatically absorbed into the CLB. Clock EnableThe clock enable line (EC) is active High. The EC line is shared by both flip-flops in a CLB. If either one is left discon-nected, the clock enable for that flip-flop defaults to the active state. EC is not invertible within the CLB. The clock enable is synchronous to the clock and must satisfy the setup and hold timing specified for the device.Set/ResetThe set/reset line (SR) is an asynchronous active High con-trol of the flip-flop. SR can be configured as either set or reset at each flip-flop. This configuration option determines the state in which each flip-flop becomes operational after configuration. It also determines the effect of a GSR pulse during normal operation, and the effect of a pulse on the SR line of the CLB. The SR line is shared by both flip-flops. If SR is not specified for a flip-flop the set/reset for that flip-flop defaults to the inactive state. SR is not invertible within the CLB.CLB Signal Flow ControlIn addition to the H-LUT input control multiplexers (shown in box "A" of Figure 2, page 4) there are signal flow control multiplexers (shown in box "B" of Figure 2) which select the signals which drive the flip-flop inputs and the combinatorial CLB outputs (X and Y).Each flip-flop input is driven from a 4:1 multiplexer which selects among the three LUT outputs and DIN as the data source.Each combinatorial output is driven from a 2:1 multiplexer which selects between two of the LUT outputs. The X output can be driven from the F-LUT or H-LUT, the Y output from G-LUT or H-LUT .Control SignalsThere are four signal control multiplexers on the input of the CLB. These multiplexers allow the internal CLB control sig-nals (H1, DIN, SR, and EC in Figure 2 and Figure 4) to be driven from any of the four general control inputs (C1-C4 in Figure 4) into the CLB. Any of these inputs can drive any of the four internal control signals.T able 2: CLB Storage Element FunctionalityLegend:XDon ’t careRising edge (clock not inverted).SR Set or Reset value. Reset is default.0*Input is Low or unconnected (default value)1*Input is High or unconnected (default value)Figure 3: CLB Flip-Flop Functional Block Diagram6DS060 (v1.6) September 19, 2001The four internal control signals are:•EC: Enable Clock•SR: Asynchronous Set/Reset or H function generator Input 0•DIN: Direct In or H function generator Input 2•H1: H function generator Input 1.Input/Output Blocks (IOBs)User-configurable input/output blocks (IOBs) provide the interface between external package pins and the internal logic. Each IOB controls one package pin and can be con-figured for input, output, or bidirectional signals. Figure 6shows a simplified functional block diagram of the Spar-tan/XL IOB.IOB Input Signal PathThe input signal to the IOB can be configured to either go directly to the routing channels (via I1 and I2 in Figure 6) or to the input register. The input register can be programmed as either an edge-triggered flip-flop or a level-sensitive latch. The functionality of this register is shown in Table 3,and a simplified block diagram of the register can be seen in Figure 5.Figure 4: CLB Control Signal InterfaceFigure 5: IOB Flip-Flop/Latch Functional BlockDiagramTable 3: Input Register FunctionalityX Don ’t care.Rising edge (clock not inverted).SR Set or Reset value. Reset is default.0*Input is Low or unconnected (default value)1*Input is High or unconnected (default value)The register choice is made by placing the appropriate library symbol. For example, IFD is the basic input flip-flop (rising edge triggered), and ILD is the basic input latch (transparent-High). Variations with inverted clocks are also available. The clock signal inverter is also shown in Figure5 on the CK line.The Spartan IOB data input path has a one-tap delay ele-ment: either the delay is inserted (default), or it is not. The Spartan-XL IOB data input path has a two-tap delay ele-ment, with choices of a full delay, a partial delay, or no delay. The added delay guarantees a zero hold time with respect to clocks routed through the global clock buffers. (See Glo-bal Nets and Buffers, page12 for a description of the glo-bal clock buffers in the Spartan/XL families.) For a shorter input register setup time, with positive hold-time, attach a NODELAY attribute or property to the flip-flop.The output of the input register goes to the routing channels (via I1 and I2 in Figure6). The I1 and I2 signals that exit the IOB can each carry either the direct or registered input signal.The 5V Spartan input buffers can be globally configured for either TTL (1.2V) or CMOS (VCC/2) thresholds, using an option in the bitstream generation software. The Spartan output levels are also configurable; the two global adjust-ments of input threshold and output level are independent. The inputs of Spartan devices can be driven by the outputs of any 3.3V device, if the Spartan inputs are in TTL mode. Input and output thresholds are TTL on all configuration pins until the configuration has been loaded into the device and specifies how they are to be used. Spartan-XL inputs are TTL compatible and 3.3V CMOS compatible. Supported sources for Spartan/XL device inputs are shown in Table4.Spartan-XL I/Os are fully 5V tolerant even though the V CC is 3.3V. This allows 5V signals to directly connect to the Spar-tan-XL inputs without damage, as shown in Table4. In addi-tion, the 3.3V V CC can be applied before or after 5V signals are applied to the I/Os. This makes the Spartan-XL devices immune to power supply sequencing problems.Figure 6: Simplified Spartan/XL IOB Block Diagram8DS060 (v1.6) September 19, 2001Spartan-XL V CC ClampingSpartan-XL FPGAs have an optional clamping diode con-nected from each I/O to V CC . When enabled they clamp ringing transients back to the 3.3V supply rail. This clamping action is required in 3.3V PCI applications. V CC clamping is a global option affecting all I/O pins.Spartan-XL devices are fully 5V TTL I/O compatible if V CC clamping is not enabled. With V CC clamping enabled, the Spartan-XL devices will begin to clamp input voltages to one diode voltage drop above V CC . If enabled, TTL I/O com-patibility is maintained but full 5V I/O tolerance is sacrificed.The user may select either 5V tolerance (default) or 3.3V PCI compatibility. In both cases negative voltage is clamped to one diode voltage drop below ground.Spartan-XL devices are compatible with TTL, LVTTL, PCI 3V, PCI 5V and LVCMOS signalling. The various standards are illustrated in Table 5.Additional Fast Capture Input Latch (Spartan-XL only)The Spartan-XL IOB has an additional optional latch on the input. This latch is clocked by the clock used for the output flip-flop rather than the input clock. Therefore, two different clocks can be used to clock the two input storage elements.This additional latch allows the fast capture of input data,which is then synchronized to the internal clock by the IOB flip-flop or latch.T o place the Fast Capture latch in a design, use one of the special library symbols, ILFFX or ILFLX. ILFFX is a trans-parent-Low Fast Capture latch followed by an active High input flip-flop. ILFLX is a transparent Low Fast Capture latch followed by a transparent High input latch. Any of the clock inputs can be inverted before driving the library element,and the inverter is absorbed into the IOB.IOB Output Signal PathOutput signals can be optionally inverted within the IOB,and can pass directly to the output buffer or be stored in an edge-triggered flip-flop and then to the output buffer. The functionality of this flip-flop is shown in T able 6.T able 4: Supported Sources for Spartan/XL InputsT able 5: I/O Standards Supported by Spartan-XL FPGAsTable 6: Output Flip-Flop Functionality X Don ’t careRising edge (clock not inverted). SR Set or Reset value. Reset is default.0*Input is Low or unconnected (default value)1*Input is High or unconnected (default value)Z3-stateOutput Multiplexer/2-Input Function Generator (Spartan-XL only)The output path in the Spartan-XL IOB contains an addi-tional multiplexer not available in the Spartan IOB. The mul-tiplexer can also be configured as a 2-input function generator, implementing a pass gate, AND gate, OR gate, or XOR gate, with 0, 1, or 2 inverted inputs.When configured as a multiplexer, this feature allows two output signals to time-share the same output pad, effec-tively doubling the number of device outputs without requir-ing a larger, more expensive package. The select input is the pin used for the output flip-flop clock, OK.When the multiplexer is configured as a 2-input function generator, logic can be implemented within the IOB itself. Combined with a Global buffer, this arrangement allows very high-speed gating of a single signal. For example, a wide decoder can be implemented in CLBs, and its output gated with a Read or Write Strobe driven by a global buffer. The user can specify that the IOB function generator be used by placing special library symbols beginning with the letter "O." For example, a 2-input AND gate in the IOB func-tion generator is called OAND2. Use the symbol input pin labeled "F" for the signal on the critical path. This signal is placed on the OK pin — the IOB input with the shortest delay to the function generator. Two examples are shown in Figure7.Output BufferAn active High 3-state signal can be used to place the out-put buffer in a high-impedance state, implementing 3-state outputs or bidirectional I/O. Under configuration control, the output (O) and output 3-state (T) signals can be inverted. The polarity of these signals is independently configured for each IOB (see Figure6, page7). An output can be config-ured as open-drain (open-collector) by tying the 3-state pin (T) to the output signal, and the input pin (I) to Ground.By default, a 5V Spartan device output buffer pull-up struc-ture is configured as a TTL-like totem-pole. The High driver is an n-channel pull-up transistor, pulling to a voltage one transistor threshold below V CC. Alternatively, the outputs can be globally configured as CMOS drivers, with additional p-channel pull-up transistors pulling to V CC. This option, applied using the bitstream generation software, applies to all outputs on the device. It is not individually programma-ble.All Spartan-XL device outputs are configured as CMOS drivers, therefore driving rail-to-rail. The Spartan-XL outputs are individually programmable for 12mA or 24mA output drive.Any 5V Spartan device with its outputs configured in TTL mode can drive the inputs of any typical 3.3V device. Sup-ported destinations for Spartan/XL device outputs are shown in Table7.Three-State Register (Spartan-XL Only)Spartan-XL devices incorporate an optional register control-ling the three-state enable in the IOBs. The use of the three-state control register can significantly improve output enable and disable time.Output Slew RateThe slew rate of each output buffer is, by default, reduced, to minimize power bus transients when switching non-criti-cal signals. For critical signals, attach a FAST attribute or property to the output buffer or flip-flop.Spartan/XL devices have a feature called "Soft Start-up," designed to reduce ground bounce when all outputs are turned on simultaneously at the end of configuration. When the configuration process is finished and the device starts up, the first activation of the outputs is automatically slew-rate limited. Immediately following the initial activation of the I/O, the slew rate of the individual outputs is deter-mined by the individual configuration option for each IOB. Pull-up and Pull-down NetworkProgrammable pull-up and pull-down resistors are used fortying unused pins to V CC or Ground to minimize power con-sumption and reduce noise sensitivity. The configurablepull-up resistor is a p-channel transistor that pulls to V CC.The configurable pull-down resistor is an n-channel transis-tor that pulls to Ground. The value of these resistors is typi-cally 20KΩ − 100KΩ (See "Spartan DC Characteristics Figure 7: AND and MUX Symbols in Spartan-XL IOB10DS060 (v1.6) September 19, 2001Over Operating Conditions" on page 43.). This high value makes them unsuitable as wired-AND pull-up resistors.After configuration, voltage levels of unused pads, bonded or unbonded, must be valid logic levels, to reduce noise sensitivity and avoid excess current. Therefore, by default,unused pads are configured with the internal pull-up resistor active. Alternatively, they can be individually configured with the pull-down resistor, or as a driven output, or to be driven by an external source. To activate the internal pull-up, attach the PULLUP library component to the net attached to the pad. To activate the internal pull-down, attach the PULL-DOWN library component to the net attached to the pad.Set/ResetAs with the CLB registers, the GSR signal can be used to set or clear the input and output registers, depending on the value of the INIT attribute or property. The two flip-flops can be individually configured to set or clear on reset and after configuration. Other than the global GSR net, no user-con-trolled set/reset signal is available to the I/O flip-flops (Figure 5). The choice of set or reset applies to both the ini-tial state of the flip-flop and the response to the GSR pulse.Independent ClocksSeparate clock signals are provided for the input (IK) and output (OK) flip-flops. The clock can be independently inverted for each flip-flop within the IOB, generating eitherfalling-edge or rising-edge triggered flip-flops. The clock inputs for each IOB are mon Clock EnablesThe input and output flip-flops in each IOB have a common clock enable input (see EC signal in Figure 5), which through configuration, can be activated individually for the input or output flip-flop, or both. This clock enable operates exactly like the EC signal on the Spartan/XL CLB. It cannot be inverted within the IOB.Routing Channel DescriptionAll internal routing channels are composed of metal seg-ments with programmable switching points and switching matrices to implement the desired routing. A structured,hierarchical matrix of routing channels is provided to achieve efficient automated routing.This section describes the routing channels available in Spartan/XL devices. Figure 8 shows a general block dia-gram of the CLB routing channels. The implementation soft-ware automatically assigns the appropriate resources based on the density and timing requirements of the design.The following description of the routing channels is for infor-mation only and is simplified with some minor details omit-ted. For an exact interconnect description the designer should open a design in the FPGA Editor and review the actual connections in this tool.The routing channels will be discussed as follows;•CLB routing channels which run along each row and column of the CLB array.•IOB routing channels which form a ring (called a VersaRing) around the outside of the CLB array. It connects the I/O with the CLB routing channels.•Global routing consists of dedicated networks primarily designed to distribute clocks throughout the device with minimum delay and skew. Global routing can also be used for other high-fanout signals.CLB Routing ChannelsThe routing channels around the CLB are derived from three types of interconnects; single-length, double-length,and longlines. At the intersection of each vertical and hori-zontal routing channel is a signal steering matrix called a Programmable Switch Matrix (PSM). Figure 8 shows the basic routing channel configuration showing single-length lines, double-length lines and longlines as well as the CLBs and PSMs. The CLB to routing channel interface is shown as well as how the PSMs interface at the channel intersec-tions.T able 7: Supported Destinations for Spartan/XL OutputsNotes:1.Only if destination device has 5V tolerant inputs.CLB InterfaceA block diagram of the CLB interface signals is shown in Figure9. The input signals to the CLB are distributed evenly on all four sides providing maximum routing flexibility. In general, the entire architecture is symmetrical and regular. It is well suited to established placement and routing algo-rithms. Inputs, outputs, and function generators can freely swap positions within a CLB to avoid routing congestion during the placement and routing operation. The exceptions are the clock (K) input and CIN/COUT signals. The K input is routed to dedicated global vertical lines as well as four single-length lines and is on the left side of the CLB. The CIN/COUT signals are routed through dedicated intercon-nects which do not interfere with the general routing struc-ture. The output signals from the CLB are available to drive both vertical and horizontal channels.Programmable Switch MatricesThe horizontal and vertical single- and double-length lines intersect at a box called a programmable switch matrix (PSM). Each PSM consists of programmable pass transis-tors used to establish connections between the lines (see Figure10).For example, a single-length signal entering on the right side of the switch matrix can be routed to a single-length line on the top, left, or bottom sides, or any combination thereof, if multiple branches are required. Similarly, a dou-ble-length signal can be routed to a double-length line on any or all of the other three edges of the programmable switch matrix.Single-Length LinesSingle-length lines provide the greatest interconnect flexibil-ity and offer fast routing between adjacent blocks. There are eight vertical and eight horizontal single-length lines associ-ated with each CLB. These lines connect the switching matrices that are located in every row and column of CLBs. Single-length lines are connected by way of the program-mable switch matrices, as shown in Figure10. Routing con-nectivity is shown in Figure8.Single-length lines incur a delay whenever they go through a PSM. Therefore, they are not suitable for routing signals for long distances. They are normally used to conduct sig-nals within a localized area and to provide the branching for nets with fanout greater than one.Figure 8: Spartan/XL CLB Routing Channels and Interface Block DiagramFigure 9: CLB Interconnect Signals。

CD4040BE中文资料

Data sheet acquired from Harris Semiconductor SCHS030D − Revised December 2003The CD4020B and CD4040B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes). The CD4040B type also is supplied in 16-lead small-outline packages (M and M96 suffixes).The CD4024B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries(TI)reserve the right to make corrections,modifications,enhancements, improvements,and other changes to its products and services at any time and to discontinue any product or service without notice. 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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:Products ApplicationsAmplifiers AudioData Converters AutomotiveDSP BroadbandInterface Digital ControlLogic MilitaryPower Mgmt Optical NetworkingMicrocontrollers SecurityLow Power TelephonyWirelessVideo&ImagingWirelessMailing Address:Texas Instruments,Post Office Box655303,Dallas,Texas75265Copyright©2007,Texas Instruments IncorporatedPACKAGING INFORMATIONOrderable Device Status(1)PackageType PackageDrawingPins PackageQtyEco Plan(2)Lead/Ball Finish MSL Peak Temp(3)89271AKB3T OBSOLETE CFP WR16TBD Call TI Call TI89274AKB3T OBSOLETE CFP WR16TBD Call TI Call TICD4020BE ACTIVE PDIP N1625Pb-Free(RoHS)CU NIPDAU N/A for Pkg TypeCD4020BEE4ACTIVE PDIP N1625Pb-Free(RoHS)CU NIPDAU N/A for Pkg Type CD4020BF ACTIVE CDIP J161TBD A42SNPB N/A for Pkg Type CD4020BF3A ACTIVE CDIP J161TBD A42SNPB N/A for Pkg Type CD4020BNSR ACTIVE SO NS162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4020BNSRE4ACTIVE SO NS162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4020BNSRG4ACTIVE SO NS162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4020BPW ACTIVE TSSOP PW1690Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4020BPWE4ACTIVE TSSOP PW1690Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4020BPWG4ACTIVE TSSOP PW1690Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4020BPWR ACTIVE TSSOP PW162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4020BPWRE4ACTIVE TSSOP PW162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4020BPWRG4ACTIVE TSSOP PW162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4024BE ACTIVE PDIP N1425Pb-Free(RoHS)CU NIPDAU N/A for Pkg TypeCD4024BEE4ACTIVE PDIP N1425Pb-Free(RoHS)CU NIPDAU N/A for Pkg Type CD4024BF ACTIVE CDIP J141TBD A42SNPB N/A for Pkg Type CD4024BF3A ACTIVE CDIP J141TBD A42SNPB N/A for Pkg Type CD4024BF3AS2534OBSOLETE CDIP J14TBD Call TI Call TI CD4024BM ACTIVE SOIC D1450Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4024BM96ACTIVE SOIC D142500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4024BM96E4ACTIVE SOIC D142500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4024BM96G4ACTIVE SOIC D142500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4024BME4ACTIVE SOIC D1450Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4024BMG4ACTIVE SOIC D1450Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4024BMT ACTIVE SOIC D14250Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIM CD4024BMTE4ACTIVE SOIC D14250Green(RoHS&CU NIPDAU Level-1-260C-UNLIMOrderable Device Status(1)PackageType PackageDrawingPins PackageQtyEco Plan(2)Lead/Ball Finish MSL Peak Temp(3)no Sb/Br)CD4024BMTG4ACTIVE SOIC D14250Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4024BNSR ACTIVE SO NS142000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4024BNSRE4ACTIVE SO NS142000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4024BNSRG4ACTIVE SO NS142000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4024BPW ACTIVE TSSOP PW1490Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4024BPWE4ACTIVE TSSOP PW1490Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4024BPWG4ACTIVE TSSOP PW1490Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4024BPWR ACTIVE TSSOP PW142000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4024BPWRE4ACTIVE TSSOP PW142000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4024BPWRG4ACTIVE TSSOP PW142000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4040BE ACTIVE PDIP N1625Pb-Free(RoHS)CU NIPDAU N/A for Pkg TypeCD4040BEE4ACTIVE PDIP N1625Pb-Free(RoHS)CU NIPDAU N/A for Pkg Type CD4040BF ACTIVE CDIP J161TBD A42SNPB N/A for Pkg Type CD4040BF3A ACTIVE CDIP J161TBD A42SNPB N/A for Pkg Type CD4040BM ACTIVE SOIC D1640Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4040BM96ACTIVE SOIC D162500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4040BM96E4ACTIVE SOIC D162500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4040BM96G4ACTIVE SOIC D162500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4040BME4ACTIVE SOIC D1640Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4040BMG4ACTIVE SOIC D1640Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4040BNSR ACTIVE SO NS162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4040BNSRE4ACTIVE SO NS162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4040BNSRG4ACTIVE SO NS162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4040BPW ACTIVE TSSOP PW1690Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4040BPWE4ACTIVE TSSOP PW1690Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4040BPWG4ACTIVE TSSOP PW1690Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMOrderable Device Status(1)PackageType PackageDrawingPins PackageQtyEco Plan(2)Lead/Ball Finish MSL Peak Temp(3)CD4040BPWR ACTIVE TSSOP PW162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4040BPWRE4ACTIVE TSSOP PW162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4040BPWRG4ACTIVE TSSOP PW162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIM JM38510/05653BEA ACTIVE CDIP J161TBD A42SNPB N/A for Pkg Type JM38510/05655BCA ACTIVE CDIP J141TBD A42SNPB N/A for Pkg Type (1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan-The planned eco-friendly classification:Pb-Free(RoHS),Pb-Free(RoHS Exempt),or Green(RoHS&no Sb/Br)-please check /productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.Pb-Free(RoHS):TI's terms"Lead-Free"or"Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all6substances,including the requirement that lead not exceed0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free(RoHS Exempt):This component has a RoHS exemption for either1)lead-based flip-chip solder bumps used between the die and package,or2)lead-based die adhesive used between the die and leadframe.The component is otherwise considered Pb-Free(RoHS compatible)as defined above.Green(RoHS&no Sb/Br):TI defines"Green"to mean Pb-Free(RoHS compatible),and free of Bromine(Br)and Antimony(Sb)based flame retardants(Br or Sb do not exceed0.1%by weight in homogeneous material)(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.TAPE AND REEL INFORMATION*All dimensions are nominalDevicePackage Type Package Drawing Pins SPQReel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant CD4020BNSR SO NS 162000330.016.48.210.5 2.512.016.0Q1CD4020BPWR TSSOP PW 162000330.012.47.0 5.6 1.68.012.0Q1CD4024BM96SOIC D 142500330.016.4 6.59.0 2.18.016.0Q1CD4024BNSR SO NS 142000330.016.48.210.5 2.512.016.0Q1CD4024BPWR TSSOP PW 142000330.012.47.0 5.6 1.68.012.0Q1CD4040BM96SOIC D 162500330.016.4 6.510.3 2.18.016.0Q1CD4040BNSR SO NS 162000330.016.48.210.5 2.512.016.0Q1CD4040BPWRTSSOPPW162000330.012.47.05.61.68.012.0Q1*All dimensions are nominalDevice Package Type Package Drawing Pins SPQ Length(mm)Width(mm)Height(mm) CD4020BNSR SO NS162000346.0346.033.0 CD4020BPWR TSSOP PW162000346.0346.029.0 CD4024BM96SOIC D142500346.0346.033.0 CD4024BNSR SO NS142000346.0346.033.0 CD4024BPWR TSSOP PW142000346.0346.029.0 CD4040BM96SOIC D162500333.2345.928.6 CD4040BNSR SO NS162000346.0346.033.0 CD4040BPWR TSSOP PW162000346.0346.029.0。

VB30200C中文资料

New ProductV30200C, VB30200C & VI30200CVishay General Semiconductor Document Number: 89014For technical questions within your region, please contact one of the following: Dual High-Voltage Trench MOS Barrier Schottky RectifierUltra Low V F = 0.526 V at I F = 5 AFEATURES•Trench MOS Schottky technology•Low forward voltage drop, low powerlosses•High efficiency operation•Low thermal resistance•Meets MSL level 1, per J-STD-020, LF maximumpeak of 245 °C (for TO-263AB package)•Solder dip 260 °C, 40 s (for TO-220AB andTO-262AA package)•Component in accordance to RoHS 2002/95/ECand WEEE 2002/96/ECTYPICAL APPLICATIONSFor use in high frequency inverters, switching powersupplies, freewheeling diodes, OR-ing diode, dc-to-dcconverters and reverse battery protection.MECHANICAL DATACase: TO-220AB, TO-263AB and TO-262AAEpoxy meets UL 94V-0 flammability ratingTerminals: Matte tin plated leads, solderable perJ-STD-002 and JESD22-B102E3 suffix for consumer grade, meets JESD 201 class1A whisker testPolarity: As markedMounting Torque:10 in-lbs maximumPRIMARY CHARACTERISTICSI F(AV) 2 x 15 AV RRM200 VI FSM250 AV F at I F = 15 A0.648 VT J max.150 °C12312KMAXIMUM RATINGS (T A = 25°C unless otherwise noted)PARAME ER SYMBOLV30200C VB30200C VI30200C UNI Maximum repetitive peak reverse voltage V RRM200VMaximum average forward rectified current(Fig. 1)per deviceper diodeI F(AV)3015APeak forward surge current 10 ms single half sine-wavesuperimposed on rated load per diodeI FSM250ANon-repetitive avalanche energy at I AS = 2.0 A, T J = 25 °C E AS100mJPeak repetitive reverse current at t p = 2 µs, 1 kHz per diode I RRM 1.0AVoltage rate of change (rated V R)dV/dt10 000V/µsOperating junction and storage temperature range T J, T STG- 40 to + 150°C元器件交易网New ProductV30200C, VB30200C & VI30200CVishay General Semiconductor For technical questions within your region, please contact one of the following:Document Number: 89014Notes:(1) Pulse test: 300 µs pulse width, 1 % duty cycle (2) Pulse test: Pulse width ≤ 40 msRATINGS AND CHARACTERISTICS CURVES(T A = 25 °C unless otherwise noted)ELECTRICAL CHARACTERISTICS (T A = 25°C unless otherwise noted)PARAME ER T ES T CONDI T IONS SYMBOL TYP.MAX.UNI TBreakdown voltageI R = 10 mA T J = 25 °C V BR205 (minimum)-VInstantaneous forward voltage per diode (1)I F = 5 AI F = 10 A I F = 15 A T J = 25 °CV F0.6910.7700.841--1.10VI F = 5 A I F = 10 AI F = 15 A T J = 125 °C 0.5260.5940.648--0.72Reverse current per diode (2)V R = 180 VT J = 25 °C T J = 125 °C I R2.43.8--µA mA V R = 200 VT J = 25 °C T J = 125 °C5.36.016012µA mATHERMAL CHARACTERISTICS (T A = 25°C unless otherwise noted)PARAME ER SYMBOL V30200CVB30200CVI30200CUNI TTypical thermal resistance per diodeR θJC2.0°C/WORDERING INFORMATION (Example)PACKAGE PREFERRED P/N UNIT WEIGHT (g)PACKAGE CODEBASE QUANTITYDELIVERY MODETO-220AB V30200C-E3/4W2.2484W50/tubeT ubeTO-263AB VB30200C-E3/4W 1.394W50/tube T ubeTO-263AB VB30200C-E3/8W 1.398W800/reel T ape and reel TO-262AAVI30200C-E3/4W1.464W50/tubeT ubeFigure 1. Forward Derating Curve Figure 2. Forward Power Loss Characteristics Per Diode元器件交易网New ProductV30200C, VB30200C & VI30200CVishay General Semiconductor Document Number: 89014For technical questions within your region, please contact one of the following: Figure3. Typical Instantaneous Forward Characteristics Per DiodeFigure4. Typical Reverse Characteristics Per DiodeFigure5. Typical Junction Capacitance Per DiodeFigure6. Typical Transient Thermal Impedance Per Diode元器件交易网New ProductV30200C, VB30200C & VI30200CVishay General Semiconductor For technical questions within your region, please contact one of the following:Document Number: 89014PACKAGE OUTLINE DIMENSIONS in inches (millimeters)元器件交易网Disclaimer Legal Disclaimer NoticeVishayAll product specifications and data are subject to change without notice.Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product.Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products.No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay.The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.Product names and markings noted herein may be trademarks of their respective owners.元器件交易网Document Number: 。

1C10C0G101J050B(vishay)中文数据手册「EasyDatasheet」

J K M
TOLERANCE
± 5% ± 10% ± 20%
AVAILABLE IN EIA CHARACTERISTIC
C0G X7R Z5U
B = Bulk
R = Tape and Reel
* 1.0 [25.4] minimum lead length.
文件编号：42012 修订25九月00
31
050 DC VOLTAGE RATING
Thisisexpressed in volts. To complete the three-digit block, zeros precede the voltage rating.
B LEAD LENGTH*
See Dimensional Configurations.
文件编号：42012 修订25九月00
芯片中文手册,看全文,戳
标准零件编号
1C20C0G222J050R 1C20C0G222J100B 1C20C0G222J100R 1C20C0G330J050B 1C20C0G330J050R 1C20C0G330J100B 1C20C0G330J100R 1C20C0G331J050B 1C20C0G331J050R 1C20C0G331J100B 1C20C0G331J100R 1C20C0G332J050B 1C20C0G332J050R 1C20C0G332J100B 1C20C0G332J100R
1C20X7R333K100B 1C20X7R333K100R 1C20X7R472K050B 1C20X7R472K050R 1C20X7R472K100B 1C20X7R472K100R 1C20X7R473K050B 1C20X7R473K050R 1C20X7R473K100B 1C20X7R473K100R 1C20Z5U103M050B 1C20Z5U103M050R 1C20Z5U103M100B 1C20Z5U103M100R 1C20Z5U104M050B 1C20Z5U104M050R 1C20Z5U104M100B 1C20Z5U104M100R 1C20Z5U223M050B 1C20Z5U223M050R

VB40100C

New ProductV40100C, VF40100C, VB40100C & VI40100CVishay General SemiconductorDocument Number: 89042For technical questions within your region, please contact one of the following:Dual High-Voltage Trench MOS Barrier Schottky RectifierUltra Low V F = 0.38 V at I F = 5 AFEATURES•Trench MOS Schottky technology•Low forward voltage drop, low powerlosses•High efficiency operation•Low thermal resistance•Meets MSL level 1, per J-STD-020, LF maximumpeak of 245 °C (for TO-263AB package)•Solder dip 260 °C, 40 s (for TO-220AB, ITO-220ABand TO-262AA package)•Component in accordance to RoHS 2002/95/ECand WEEE 2002/96/ECTYPICAL APPLICATIONSFor use in high frequency inverters, switching powersupplies, freewheeling diodes, OR-ing diode, dc-to-dcconverters and reverse battery protection.MECHANICAL DATACase: TO-220AB, ITO-220AB, TO-263AB andTO-262AAEpoxy meets UL 94V-0 flammability ratingTerminals: Matte tin plated leads, solderable perJ-STD-002 and JESD22-B102E3 suffix for consumer grade, meets JESD 201 class1A whisker testPolarity: As markedMounting Torque:10 in-lbs maximumPRIMARY CHARACTERISTICSI F(AV) 2 x 20 AV RRM100 VI FSM250 AV F at I F = 20 A0.61 VT J max.150 °C12312KMAXIMUM RATINGS (T A = 25°C unless otherwise noted)PA AMETE SYMBOLV40100C VF40100C VB40100C VI40100C UNIT Maximum repetitive peak reverse voltage V RRM 100VMaximum average forward rectified current(Fig. 1)per deviceper diodeI F(AV)4020APeak forward surge current 8.3 ms single half sine-wavesuperimposed on rated load per diodeI FSM 250 AIsolation voltage (ITO-220AB only)From terminal to heatsink t = 1 minV AC1500VOperating junction and storage temperature range T J, T STG- 40 to + 150 °CNew ProductV40100C, VF40100C, VB40100C & VI40100CVishay General Semiconductor For technical questions within your region, please contact one of the following:Document Number: 89042Notes:(1) Pulse test: 300 µs pulse width, 1 % duty cycle (2) Pulse test: Pulse width ≤ 40 msRATINGS AND CHARACTERISTICS CURVES (T A = 25 °C unless otherwise noted)ELECTRICAL CHARACTERISTICS (T A = 25°C unless otherwise noted)PA AMETE TEST CONDITIONS SYMBOL TYP.MAX.UNITBreakdown voltage(2)I R = 1.0 mAT A = 25 °CV BR100 (minimum)-VI R = 10 mA 105 (minimum)-Instantaneous forward voltage per diode (1)I F = 5 AI F = 10 A I F = 20 A T A = 25 °CV F0.470.540.67--0.73VI F = 5 A I F = 10 A I F = 20 A T A = 125 °C 0.380.450.61--0.67Reverse current at rated V R per diode (2)V R = 70 V T A = 25 °C T A = 125 °C I R910--µA mA V R = 100 VT A = 25 °C T A = 125 °C-21100045µA mATHERMAL CHARACTERISTICS (T A = 25°C unless otherwise noted)PA AMETE SYMBOL V40100C VF40100C VB40100CVI40100CUNITTypical thermal resistance per diodeR θJC2.04.02.02.0°C/WORDERING INFORMATION (Example)PACKAGE PREFERRED P/N UNIT WEIGHT (g)PACKAGE CODEBASE QUANTITYDELIVERY MODETO-220AB V40100C-E3/4W 1.854W 50/tube T ube ITO-220AB VF40100C-E3/4W 1.754W 50/tube T ube TO-263AB VB40100C-E3/4W 1.394W 50/tube T ube TO-263AB VB40100C-E3/8W 1.398W 800/reel T ape and reelTO-262AAVI40100C-E3/4W1.464W50/tubeTubeFigure 1. Forward Current Derating Curve Figure 2. Forward Power Loss Characteristics Per DiodeNew ProductV40100C, VF40100C, VB40100C & VI40100CVishay General Semiconductor Document Number: 89042For technical questions within your region, please contact one of the following: Figure3. Typical Instantaneous Forward Characteristics Per DiodeFigure4. Typical Reverse Characteristics Per DiodeFigure5. Typical Junction Capacitance Per DiodeFigure6. Typical Transient Thermal Impedance Per DiodeFigure7. Typical Transient Thermal Impedance Per DiodeNew ProductV40100C, VF40100C, VB40100C & VI40100CVishay General Semiconductor For technical questions within your region, please contact one of the following:Document Number: 89042PACKAGE OUTLINE DIMENSIONS in inches (millimeters)Disclaimer Legal Disclaimer NoticeVishayAll product specifications and data are subject to change without notice.Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product.Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products.No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay.The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.Product names and markings noted herein may be trademarks of their respective owners.Document Number: 。

VB60100C中文资料

New ProductV60100C & VB60100CVishay General SemiconductorDocument Number: 88942For technical questions within your region, please contact one of the following: Dual High-Voltage Trench MOS Barrier Schottky RectifierUltra Low V F = 0.36 V at I F = 5 AFEATURES•Trench MOS Schottky technology•Low forward voltage drop, low power losses•High efficiency operation•Low thermal resistance•Meets MSL level 1, per J-STD-020, LF maximumpeak of 245 °C (for TO-263AB package)•Solder dip 260 °C, 40 s (for TO-220AB)•Component in accordance to RoHS 2002/95/ECand WEEE 2002/96/ECTYPICAL APPLICATIONSFor use in high frequency inverters, switching powersupplies, freewheeling diodes, OR-ing diode, dc-to-dcconverters and reverse battery protection.MECHANICAL DATACase: TO-220AB and TO-263ABEpoxy meets UL 94V-0 flammability ratingTerminals: Matte tin plated leads, solderable perJ-STD-002 and JESD22-B102E3 suffix for commercial grade, meets JESD 201 class1A whisker testPolarity: As markedMounting Torque:10 in-lbs MaximumPRIMARY CHARACTERISTICSI F(AV) 2 x 30 AV RRM100 VI FSM320 AV F at I F = 30 A0.66 VT J max.150 °C12312KMAXIMUM RATINGS (T A = 25°C unless otherwise noted)PARAME ER SYMBOLV60100C VB60100C UNIMaximum repetitive peak reverse voltage V RRM 100V Maximum average forward rectified current (Fig. 1)per deviceper diodeI F(AV)6030APeak forward surge current 8.3 ms single halfsine-wave superimposed on rated loadper diode I FSM 320Operating junction and storage temperature range T J, T STG- 40 to + 150 °CNew ProductV60100C & VB60100CVishay General Semiconductor For technical questions within your region, please contact one of the following:Document Number: 88942Notes:(1) Pulse test: 300 µs pulse width, 1 % duty cycle (2) Pulse test: 10 ms pulse widthRATINGS AND CHARACTERISTICS CURVES (T A = 25 °C unless otherwise noted)ELECTRICAL CHARACTERISTICS (T A = 25°C unless otherwise noted)PARAME ER T ES T CONDI T IONS SYMBOL TYP.MAX.UNI TBreakdown voltageI R = 1.0 mA T A = 25 °CV BR100 (minimum)-VInstantaneous forward voltage per diode (1)I F = 5 AI F = 10 A I F = 15 A I F = 20 A I F = 30 A T A = 25 °CV F0.450.520.580.630.73--0.63-0.79I F = 5 A I F = 10 A I F = 15 A I F = 20 A I F = 30 A T A = 125 °C0.360.450.530.580.66--0.58-0.70Reverse current at rated V RM per diode (2)V R = 80 VT A = 25 °C T A = 125 °CI R241350020µA mA V R = 100 VT A = 25 °C T A = 125 °C 65301000-µA mATHERMAL CHARACTERISTICS (T A = 25°C unless otherwise noted)PARAME ER SYMBOL V60100C VB60100C UNI TTypical thermal resistance per diodeR θJC 2.52.5°C/WORDERING INFORMATIONPACKAGE PREFERRED P/N UNIT WEIGHT (g)PACKAGE CODEBASE QUANTITY DELIVERY MODETO-220AB V60100C-E3/4W 1.894W 50/tube Tube TO-263AB VB60100C-E3/4W 1.384W 50/tube Tube TO-263ABVB60100C-E3/8W1.388W800/reelTape and reelFigure 1. Forward Current Derating CurveFigure 2. Forward Power Loss Characteristics Per DiodeNew ProductV60100C & VB60100CVishay General Semiconductor Document Number: 88942For technical questions within your region, please contact one of the following: Figure3. Typical Instantaneous Forward Characteristics Per DiodeFigure4. Typical Reverse Characteristics Per DiodeFigure5. Typical Junction Capacitance Per DiodeFigure6. Typical Transient Thermal Impedance Per DiodeNew ProductV60100C & VB60100CVishay General Semiconductor For technical questions within your region, please contact one of the following:Document Number: 88942PACKAGE OUTLINE DIMENSIONS in inches (millimeters)Legal Disclaimer NoticeVishay Document Number: NoticeSpecifications of the products displayed herein are subject to change without notice. Vishay Intertechnology, Inc., or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies.Information contained herein is intended to provide a product description only. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Vishay's terms and conditions of sale for such products, Vishay assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Vishay products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Vishay for any damages resulting from such improper use or sale.。

B2200VB-077 产品数据表说明书

B2200VB-077Product featuresCarbon Steel Body, Hardened Chrome Plated, Stainless Steel Ball and StemType overviewTypeDN B2200VB-07750Technical dataFunctional dataValve size [mm]2" [50]Fluidchilled or hot water, up to 60% glycol, steam Fluid Temp Range (water)-22...380°F [-30...193°C]Fluid Temp Range (steam)-22...380°F [-30...193°C]Body Pressure Rating ANSI Class 300Close-off pressure ∆ps 250 psiFlow characteristic equal percentage Rangeability Sv300:1Maximum differential pressure (water)150 psi Max Differential Pressure (Steam)100 psi Close-Off Pressure (Steam)150 psi Flow Pattern 2-way Leakage rateANSI Class IV Controllable flow range 75°Cv77 Maximum Inlet Pressure (Steam)150 psiMaterialsValve body WCC grade carbon steel Body finish matt black body finish Spindle stainless steel Spindle seal PTFE V-ring SeatPTFEPipe connection NPT female ends Ballstainless steel Suitable actuatorsNon-SpringSY1AMB(X)PRB(X)SpringAF Electrical fail-safePKRB(X)Product featuresFast quarter turn open or closed operation, stainless-steel ball and stem, positive isolation, two-piece body constructionB2200VB-077 Application Water-side control of air handling apparatus in ventilation and air-conditioning system.Water/Steam control in heating system.300:1 rangeability.The dimensions and drilling of end flanges conform to the American cast iron flange standard,Class 150 (ANSI B16.1).Flow/Mounting detailsDimensionsType DNB2200VB-07750B2VB-AMA B C D E F12.8" [325]7.0" [178]13.5" [342]10.5" [267] 1.8" [46] 1.8" [46]B2200VB-077B2VB-NFA B C D E F11.4" [289]7.0" [178]14.5" [368]11.1" [283] 1.9" [48] 1.9" [48]B2VB-PRA B C D E F11.4" [289]7.0" [178]15.0" [380]12.6" [321] 3.9" [100] 3.9" [100]AFX24-MFT-X1Modulating, Spring Return, 24 V, Multi-Function Technology®Technical dataElectrical dataNominal voltageAC/DC 24 V Nominal voltage frequency 50/60 HzNominal voltage rangeAC 19.2...28.8 V / DC 21.6...28.8 V Power consumption in operation 7.5 W Power consumption in rest position 3 W Transformer sizing 10 VAElectrical Connection18 GA appliance cable, 1 m, 3 m or 5 m, with 1/2" conduit connector, degree of protection NEMA 2 / IP54Overload Protectionelectronic throughout 0...95° rotation Functional dataOperating range Y 2...10 VOperating range Y note 4...20 mA w/ ZG-R01 (500 Ω, 1/4 W resistor)Operating range Y variable Start point 0.5...30 V End point 2.5...32 VOperating modes optional variable (VDC, PWM, on/off, floating point)Position feedback U 2...10 V Position feedback U note Max. 0.5 mA Position feedback U variable VDC variableDirection of motion motor selectable with switch 0/1Direction of motion fail-safe reversible with cw/ccw mounting Manual override 5 mm hex crank (3/16" Allen), supplied Angle of rotation 95°Angle of rotation note adjustable with mechanical end stop, 35...95°Running Time (Motor)150 s / 90°Running time motor variable 70...220 s Running time fail-safe <20 sOverride controlMIN (minimum position) = 0%MID (intermediate position) = 50%MAX (maximum position) = 100%Noise level, motor 40 dB(A)Noise level, fail-safe 62 dB(A)Position indicationMechanical Safety dataPower source ULClass 2 Supply Degree of protection IEC/EN IP54Degree of protection NEMA/UL NEMA 2Enclosure UL Enclosure Type 2Agency Listing cULus acc. to UL60730-1A/-2-14, CAN/CSA E60730-1:02, CE acc. to 2014/30/EU Quality StandardISO 9001AFX24-MFT-X1FootnotesSafety dataUL 2043 CompliantSuitable for use in air plenums per Section 300.22(C) of the NEC and Section 602 of the IMCAmbient humidity Max. 95% RH, non-condensing Ambient temperature -22...122°F [-30...50°C]Storage temperature -40...176°F [-40...80°C]Servicingmaintenance-free Weight Weight4.6 lb [2.1 kg]MaterialsHousing material Galvanized steel and plastic housing*Variable when configured with MFT options.AccessoriesElectrical accessoriesDescriptionType Service Tool, with ZIP-USB function, for programmable andcommunicative Belimo actuators, VAV controller and HVAC performance devicesZTH USElectrical installationWarning! Live electrical components!During installation, testing, servicing and troubleshooting of this product, it may be necessary to work with live electrical components. Have a qualified licensed electrician or other individual who has been properly trained in handling live electrical components perform these tasks. Failure to follow all electrical safety precautions when exposed to live electrical componentscould result in death or serious injury.Meets cULus requirements without the need of an electrical ground connection.Actuators with appliance cables are numbered.Provide overload protection and disconnect as required.Actuators may also be powered by DC 24 V.Only connect common to negative (-) leg of control circuits.A 500 Ω resistor (ZG-R01) converts the 4...20 mA control signal to 2...10 V.Control signal may be pulsed from either the Hot (Source) or Common (Sink) 24 V line.For triac sink the Common connection from the actuator must be connected to the Hotconnection of the controller. Position feedback cannot be used with a triac sink controller; theactuator internal common reference is not compatible.IN4004 or IN4007 diode. (IN4007 supplied, Belimo part number 40155).Actuators may be controlled in parallel. Current draw and input impedance must be observed.Master-Slave wiring required for piggy-back applications. Feedback from Master to control input(s) of Slave(s).Wiring diagrams On/OffFloating PointAFX24-MFT-X1 VDC/mA Control PWM ControlOverride Control Primary - Secondary。

MBR40100PT中文资料

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元器件交易网
MBR40100PT
High Tjm (+175oC) Schottky Barrier Diodes
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VB10150C中文资料

V10150C, VF10150C, VB10150C & VI10150CVishay General SemiconductorDocument Number: 89068For technical questions within your region, please contact one of the following:High-Voltage Trench MOS Barrier Schottky RectifierUltra Low V F = 0.63 V at I F = 3 AFEATURES•Trench MOS Schottky technology •Low forward voltage drop, low power losses •High efficiency operation•Meets MSL level 1, per J -STD-020, LFmaximum peak of 245 °C (for TO-263AB package) •Solder dip 260 °C, 40 s (for TO-220AB, ITO-220AB and TO-262AA package) •Component in accordance to RoHS 2002/95/EC and WEEE 2002/96/ECTYPICAL APPLICATIONSFor use in high frequency inverters, switching power supplies, freewheeling diodes, OR-ing diode, dc-to-dc converters and reverse battery protection.MECHANICAL DATACase: TO-220AB, ITO-220AB, TO-263AB and TO-262AAEpoxy meets UL 94V-0 flammability ratingTerminals: Matte tin plated leads, solderable per J-STD-002 and JESD22-B102E3 suffix for consumer grade, meets JESD 201 class 1A whisker testPolarity: As markedMounting Torque:10 in-lbs maximumPRIMARY CHARACTERISTICSI F(AV) 2 x 5 A V RRM 150 V I FSM 60 A V F at I F = 5 A 0.69 V T J max.150 °C12312KMAXIMUM RATINGS (T A = 25°C unless otherwise noted)PA AMETESYMBOL V10150CVF10150CVB10150CVI10150CUNITMaximum repetitive peak reverse voltage V RRM 150V Maximum average forward rectified current (Fig. 1)per device per diodeI F(AV)105APeak forward surge current 8.3 ms single half sine-wave superimposed on rated load per diode I FSM 60 A Isolation voltage (ITO-220AB only)from terminal to heatsink t = 1 minV AC 1500V Operating junction and storage temperature rangeT J , T STG- 55 to + 150°CV10150C, VF10150C, VB10150C & VI10150CVishay General Semiconductor For technical questions within your region, please contact one of the following:Document Number: 89068Notes:(1) Pulse test: 300 µs pulse width, 1 % duty cycle (2) Pulse test: Pulse width ≤ 40 msRATINGS AND CHARACTERISTICS CURVES (T A = 25 °C unless otherwise noted)ELECTRICAL CHARACTERISTICS (T A = 25°C unless otherwise noted)PA AMETE TEST CONDITIONS SYMBOL TYP.MAX.UNITBreakdown voltageI R = 1.0 mA T A = 25 °C V BR150 (minimum)-VInstantaneous forward voltage per diode (1)I F = 3 AI F = 5 A T A = 25 °CV F0.820.99-1.41VI F = 3 A I F = 5 A T A = 125 °C 0.630.69-0.75Reverse current per diode (2)V R = 100 VT A = 25 °C T A = 125 °C I R0.50.5--µA mA V R = 150 VT A = 25 °C T A = 125 °C-1.010010µA mATHERMAL CHARACTERISTICS (T A = 25°C unless otherwise noted)PA AMETE SYMBOL V10150C VF10150C VB10150CVI10150CUNITTypical thermal resistance per diodeR θJC4.06.54.04.0°C/WORDERING INFORMATION (Example)PACKAGE PREFERRED P/N UNIT WEIGHT (g)PACKAGE CODEBASE QUANTITYDELIVERY MODETO-220AB V10150C-E3/4W 1.874W 50/tube T ube ITO-220AB VF10150C-E3/4W 1.744W 50/tube T ube TO-263AB VB10150C-E3/4W 1.394W 50/tube T ube TO-263AB VB10150C-E3/8W 1.388W 800/reel T ape and reelTO-262AAVI10150C-E3/4W1.454W50/tubeT ubeFigure 1. Maximum Forward Current Derating CurveFigure 2. Forward Power Loss Characteristics Per DiodeV10150C, VF10150C, VB10150C & VI10150CVishay General SemiconductorDocument Number: 89068For technical questions within your region, please contact one of the following:Figure 3. Typical Instantaneous Forward Characteristics Per Diode Figure 4. Typical Reverse Characteristics Per Diode Figure 5. Typical Junction Capacitance Per DiodeFigure 6. Typical Transient Thermal Impedance Per DiodeFigure 7. Typical Transient Thermal Impedance Per DiodeV10150C, VF10150C, VB10150C & VI10150CVishay General Semiconductor For technical questions within your region, please contact one of the following:Document Number: 89068PACKAGE OUTLINE DIMENSIONS in inches (millimeters)Disclaimer Legal Disclaimer NoticeVishayAll product specifications and data are subject to change without notice.Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product.Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products.No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay.The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.Product names and markings noted herein may be trademarks of their respective owners.元器件交易网Document Number: 。

V40100C中文资料

V40100C, VF40100C, VB40100C & VI40100CVishay General SemiconductorDocument Number: 89042For technical questions within your region, please contact one of the following:Dual High-Voltage Trench MOS Barrier Schottky RectifierUltra Low V F = 0.38 V at I F = 5 AFEATURES•Trench MOS Schottky technology •Low forward voltage drop, low power losses •High efficiency operation •Low thermal resistance•Meets MSL level 1, per J-STD-020, LF maximum peak of 245 °C (for TO-263AB package) •Solder dip 260 °C, 40 s (for TO-220AB, ITO-220AB and TO-262AA package) •Component in accordance to RoHS 2002/95/EC and WEEE 2002/96/EC TYPICAL APPLICATIONSFor use in high frequency inverters, switching power supplies, freewheeling diodes, OR-ing diode, dc-to-dc converters and reverse battery protection.MECHANICAL DATACase: TO-220AB, ITO-220AB, TO-263AB and TO-262AAEpoxy meets UL 94V-0 flammability ratingTerminals: Matte tin plated leads, solderable per J-STD-002 and JESD22-B102E3 suffix for consumer grade, meets JESD 201 class 1A whisker testPolarity: As markedMounting Torque:10 in-lbs maximumPRIMARY CHARACTERISTICSI F(AV) 2 x 20 A V RRM 100 V I FSM 250 A V F at I F = 20 A 0.61 V T J max.150 °C12312KMAXIMUM RATINGS (T A = 25°C unless otherwise noted)PA AMETE SYMBOL V40100C VF40100C VB40100C VI40100C UNITMaximum repetitive peak reverse voltage V RRM 100V Maximum average forward rectified current (Fig. 1)per device per diodeI F(AV)4020APeak forward surge current 8.3 ms single half sine-wave superimposed on rated load per diode I FSM 250 A Isolation voltage (ITO-220AB only)From terminal to heatsink t = 1 minV AC 1500V Operating junction and storage temperature rangeT J , T STG- 40 to + 150°CV40100C, VF40100C, VB40100C & VI40100CVishay General Semiconductor For technical questions within your region, please contact one of the following:Document Number: 89042Notes:(1) Pulse test: 300 µs pulse width, 1 % duty cycle (2) Pulse test: Pulse width ≤ 40 msRATINGS AND CHARACTERISTICS CURVES (T A = 25 °C unless otherwise noted)ELECTRICAL CHARACTERISTICS (T A = 25°C unless otherwise noted)PA AMETE TEST CONDITIONS SYMBOL TYP.MAX.UNITBreakdown voltage(2)I R = 1.0 mAT A = 25 °CV BR100 (minimum)-VI R = 10 mA 105 (minimum)-Instantaneous forward voltage per diode (1)I F = 5 AI F = 10 A I F = 20 A T A = 25 °CV F0.470.540.67--0.73VI F = 5 A I F = 10 A I F = 20 A T A = 125 °C 0.380.450.61--0.67Reverse current at rated V R per diode (2)V R = 70 V T A = 25 °C T A = 125 °C I R910--µA mA V R = 100 VT A = 25 °C T A = 125 °C-21100045µA mATHERMAL CHARACTERISTICS (T A = 25°C unless otherwise noted)PA AMETE SYMBOL V40100C VF40100C VB40100CVI40100CUNITTypical thermal resistance per diodeR θJC2.04.02.02.0°C/WORDERING INFORMATION (Example)PACKAGE PREFERRED P/N UNIT WEIGHT (g)PACKAGE CODEBASE QUANTITYDELIVERY MODETO-220AB V40100C-E3/4W 1.854W 50/tube T ube ITO-220AB VF40100C-E3/4W 1.754W 50/tube T ube TO-263AB VB40100C-E3/4W 1.394W 50/tube T ube TO-263AB VB40100C-E3/8W 1.398W 800/reel T ape and reelTO-262AAVI40100C-E3/4W1.464W50/tubeTubeFigure 1. Forward Current Derating Curve Figure 2. Forward Power Loss Characteristics Per DiodeV40100C, VF40100C, VB40100C & VI40100CVishay General SemiconductorDocument Number: 89042For technical questions within your region, please contact one of the following:Figure 3. Typical Instantaneous Forward Characteristics Per Diode Figure 4. Typical Reverse Characteristics Per Diode Figure 5. Typical Junction Capacitance Per DiodeFigure 6. Typical Transient Thermal Impedance Per DiodeFigure7. Typical Transient Thermal Impedance Per DiodeV40100C, VF40100C, VB40100C & VI40100CVishay General Semiconductor For technical questions within your region, please contact one of the following:Document Number: 89042PACKAGE OUTLINE DIMENSIONS in inches (millimeters)Disclaimer Legal Disclaimer NoticeVishayAll product specifications and data are subject to change without notice.Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product.Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products.No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay.The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.Product names and markings noted herein may be trademarks of their respective owners.元器件交易网Document Number: 。

VCNL4010-GS08;中文规格书,Datasheet资料

Fully Integrated Proximity and Ambient Light Sensor with Infrared Emitter, I 2C Interface, and Interrupt FunctionDESCRIPTIONThe VCNL4010 is a fully integrated proximity and ambient light sensor. Fully integrated means that the infrared emitter is included in the package. It has 16 bit resolution. It includes a signal processing IC and features standard I 2C communication interface. It features an interrupt function.APPLICATIONS•Proximity sensor for mobile devices (e.g. smart phones,touch phones, PDA, GPS) for touch screen locking, power saving, etc.•Integrated ambient light function for display/keypad contrast control and dimming of mobile devices•Proximity/optical switch for consumer, computing and industrial devices and displays•Dimming control for consumer, computing and industrial displaysFEATURES•Package type: surface mount•Dimensions (L x W x H in mm): 3.95 x 3.95 x 0.75•Integrated infrared emitter, ambient light sensor,proximity sensor, and signal conditioning IC •Interrupt function•Supply voltage range V DD : 2.5 V to 3.6 V •Supply voltage range IR anode: 2.5 V to 5 V •Communication via I 2C interface •I 2C Bus H-level range: 1.7 V to 5 V •Floor life: 168 h, MSL 3, acc. J-STD-020•Low stand by current consumption: 1.5 μA•ompliant to RoHS Directive 2011/65/EU and in accordance to WEEE 2002/96/ECNote**Please see document “Vishay Material Category Policy”:/doc?99902PROXIMITY FUNCTION•Built-in infrared emitter and photo-pin-diode for proximity function•16 bit effective resolution for proximity detection range ensures excellent cross talk immunity•Programmable LED drive current from 10 mA to 200 mA in 10 mA steps•Excellent ambient light suppression by modulating the infrared signal•Proximity distance up to 200 mmAMBIENT LIGHT FUNCTION•Built-in ambient light photo-pin-diode with close-to-human-eye sensitivity•16 bit dynamic range from 0.25 lx to 16 klx •100 Hz and 120 Hz flicker noise rejectionNote(1)Adjustable through I 2C interfacePRODUCT SUMMARYPART NUMBER OPERATING RANGE (mm)OPERATING VOLTAGE RANGE (V)I 2C BUS VOLTAGE RANGE (V)LED PULSE CURRENT (1)(mA)AMBIENT LIGHT RANGE (lx)AMBIENT LIGHT RESOLUTION(lx)OUTPUT CODE VCNL40101 to 2002.5 to3.61.7 to 510 to 2000.25 to 16 3830.2516 bit, I 2CNotes(1)MOQ: minimum order quantity(2)VCNL4000 Demokit provides USB dongle, basic software including Vishay licence. The VCNL4010 sensor board could be ordered free of charge by contacting sensorstechsupport@ . Software updates for VC NL4010 can be downloaded from our web site:/???/ORDERING INFORMATIONORDERING CODE PACKAGING VOLUME (1)REMARKSVCNL4010-GS08Tape and reelMOQ: 1800 pcs 3.95 mm x 3.95 mm x 0.75 mmVCNL4010-GS18MOQ: 7000 pcsVCNL4000Demokit (2)-MOQ: 1 pc-ABSOLUTE MAXIMUM RATINGS (T amb = 25 °C, unless otherwise specified)PARAMETER TEST CONDITIONSYMBOL MIN.MAX.UNIT Supply voltageV DD - 0.3 5.5V Operation temperature range T amb - 25+ 85°C Storage temperature range T stg - 40+ 85°C Total power dissipation T amb ≤ 25 °C P tot 50mW Junction temperatureT j100°CBASIC CHARACTERISTICS (T amb = 25 °C, unless otherwise specified)PARAMETER TEST CONDITIONSYMBOLMIN.TYP.MAX.UNIT Supply voltage V DD 2.5 3.6V Supply voltage IR anode 2.55V I 2C Bus H-level range 1.75V INT H-level range 1.75V INT low voltage 3 mA sink current 0.4V Current consumptionStandby current,no IRED-operation 1.52μA Current consumptionproximity mode incl. IRED (averaged)2 measurements per second,IRED current 20 mA5μA 250 measurements per second,IRED current 20 mA 520μA 2 measurements per second,IRED current 200 mA 35μA 250 measurements per second,IRED current 200 mA 4.0mA Current consumption ambient light mode2 measurements per secondaveraging = 12.5μA 8 measurements per secondaveraging = 110μA 2 measurements per secondaveraging = 64160μA 8 measurements per secondaveraging = 64640μA Ambient light resolution Digital resolution (LSB count )0.25lx Ambient light output E V = 100 lx averaging = 64400counts I 2C clock rate rangef SCL3400kHzCIRCUIT BLOCK DIAGRAMNote•nc must not be electrically connectedPads 8 to 11 are only considered as solder padsTEST CIRCUIT BASIC CHARACTERISTICS (T amb = 25 °C, unless otherwise specified)Fig. 1 - Idle Current vs. Ambient Temperature Fig. 2 - Idle Current vs. V DDFig. 3 - Proximity Value vs. Distance Fig. 4 - Forward Current vs. TemperatureFig. 5 - Relative Radiant Intensity vs. WavelengthFig. 6 - Relative Radiant Intensity vs. Angular Displacement Fig. 7 - Relative Spectral Sensitivity vs. Wavelength(Proximity Sensor) Fig. 8 - Relative Radiant Sensitivity vs. Angular Displacement(Proximity Sensor)Fig. 9 - Ambient Light Value vs. Illuminance Fig. 10 - Relative Spectral Sensitivity vs. Wavelength(Ambient Light Sensor)Fig. 11 - Relative Radiant Sensitivity vs. Angular Displacement(Ambient Light Sensor)APPLICATION INFORMATIONVCNL4010 is a cost effective solution of proximity and ambient light sensor with I2C bus interface. The standard serial digital interface is easy to access “Proximity Signal” and “Light Intensity” without complex calculation and programming by external controller. Beside the digital output also a flexible programmable interrupt pin is available.1. Application CircuitFig. 12 - Application Circuit(x) = Pin NumberNote•The interrupt pin is an open drain output. The needed pull-up resistor may be connected to the same supply voltage as the application controller and the pull-up resistors at SDA/SCL. Proposed value R2 should be >1 kΩ , e.g. 10 kΩ to 100 kΩ.Proposed value for R3 and R4, e.g. 2.2 kΩ to 4.7 kΩ, depend also on the I2C bus speed.For detailed description about set-up and use of the interrupt as well as more application related information see AN: “Designing VCNL4010 into an Application”.2. I 2C InterfaceThe VCNL4010 contains seventeen 8 bit registers for operation control, parameter setup and result buffering. All registers are accessible via I 2C communication. Figure 13 shows the basic I 2C communication with VCNL4010.The built in I 2C interface is compatible with all I 2C modes (standard, fast and high speed).I 2C H-level range = 1.7 V to 5 V.Please refer to the I 2C specification from NXP for details.Device AddressThe VC NL4010 has a fix slave address for the host programming and accessing selection. The predefined 7 bit I 2C bus address is set to 0010 011 = 13h. The least significant bit (LSB) defines read or write mode. Accordingly the bus address is set to 0010 011x = 26h for write, 27h for read.Register AddressesVC NL4010 has seventeen user accessible 8 bit registers.The register addresses are 80h (register #0) to 90h (register #16).REGISTER FUNCTIONSRegister #0 Command RegisterRegister address = 80hThe register #0 is for starting ambient light or proximity measurements. This register contains 2 flag bits for data ready indication.Note•With setting bit 3 and bit 4 at the same write command, a simultaneously measurement of ambient light and proximity is done. Beside als_en and/or prox_en first selftimed_en needs to be set. On-demand measurement modes are disabled if selftimed_en bit is set. For the selftimed_en mode changes in reading rates (reg #4 and reg #2) can be made only when b0 (selftimed_en bit) = 0. For the als_od mode changes to the reg #4 can be made only when b4 (als_od bit) = 0; this is to avoid synchronization problems and undefined states between the clock domains. In effect this means that it is only reasonable to change rates while no selftimed conversion is ongoing.TABLE 1 - COMMAND REGISTER #0Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0config_lockals_data_rdyprox_data_rdyals_odprox_odals_enprox_enselftimed_enDescriptionconfig_lock Read only bit. Value = 1als_data_rdy Read only bit. Value = 1 when ambient light measurement data is available in the result registers. This bitwill be reset when one of the corresponding result registers (reg #5, reg #6) is read.prox_data_rdyRead only bit. Value = 1 when proximity measurement data is available in the result registers. This bit will be reset when one of the corresponding result registers (reg #7, reg #8) is read.als_od R/W bit. Starts a single on-demand measurement for ambient light. If averaging is enabled, starts a sequence of readings and stores the averaged result. Result is available at the end of conversion for reading in the registers #5(HB) and #6(LB).prox_od R/W bit. Starts a single on-demand measurement for proximity.Result is available at the end of conversion for reading in the registers #7(HB) and #8(LB).als_en R/W bit. Enables periodic als measurement prox_en R/W bit. Enables periodic proximity measurementselftimed_enR/W bit. Enables state machine and LP oscillator for self timed measurements; no measurement is performed until the corresponding bit is setRegister #1 Product ID Revision RegisterRegister address = 81h. This register contains information about product ID and product revision.Register data value of current revision = 21h.Register #2 Rate of Proximity Measurement Register address = 82h.Note•If self_timed measurement is running, any new value written in this register will not be taken over until the mode is actualy cycled.Register #3 LED Current Setting for Proximity ModeRegister address = 83h. This register is to set the LED current value for proximity measurement.The value is adjustable in steps of 10 mA from 0 mA to 200 mA.This register also contains information about the used device fuse program ID.TABLE 2 - PRODUCT ID REVISION REGISTER #1Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Product IDRevision IDDescriptionProduct ID Read only bits. Value = 2Revision IDRead only bits. Value = 1TABLE 3 - PROXIMITY RATE REGISTER #2Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0n/aRate of Proximity Measurement (no. ofmeasurements per second)DescriptionProximity rateR/W bits.000 - 1.95 measurements/s (DEFAULT)001 - 3.90625 measurements/s 010 - 7.8125 measurements/s 011 - 16.625 measurements/s 100 - 31.25 measurements/s 101 - 62.5 measurements/s 110 - 125 measurements/s 111 - 250 measurements/sTABLE 4 - IR LED CURRENT REGISTER #3Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Fuse prog IDIR LED current valueDescriptionFuse prog ID Read only bits.Information about fuse program revision used for initial setup/calibration of the device.IR LED current valueR/W bits. IR LED current = Value (dec.) x 10 mA.Valid Range = 0 to 20d. e.g. 0 = 0 mA , 1 = 10 mA, …., 20 = 200 mA (2 = 20 mA = DEFAULT) LED Current is limited to 200 mA for values higher as 20d.Register #4 Ambient Light Parameter Register Register address = 84h.Note•If self_timed measurement is running, any new value written in this register will not be taken over until the mode is actualy cycled.Register #5 and #6 Ambient Light Result RegisterRegister address = 85h and 86h. These registers are the result registers for ambient light measurement readings.The result is a 16 bit value. The high byte is stored in register #5 and the low byte in register #6.TABLE 5 - AMBIENT LIGHT PARAMETER REGISTER #4Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Cont. conv.modeals_rateAuto offset compensationAveraging function(number of measurements per run)DescriptionCont. conversion modeR/W bit. Continuous conversion mode.Enable = 1; Disable = 0 = DEFAULTThis function can be used for performing faster ambient light measurements. Please refer to the application information chapter 3.3 for details about this function. Ambient light measurement rateR/W bits. Ambient light measurement rate 000 - 1 samples/s001 - 2 samples/s = DEFAULT 010 - 3 samples/s 011 - 4 samples/s 100 - 5 samples/s 101 - 6 samples/s 110 - 8 samples/s 111 - 10 samples/sAuto offset compensationR/W bit. Automatic offset compensation.Enable = 1 = DEFAULT; Disable = 0In order to compensate a technology, package or temperature related drift of the ambient light values there is a built in automatic offset compensation function.With active auto offset compensation the offset value is measured before each ambient light measurement and subtracted automatically from actual reading.Averaging functionR/W bits. Averaging function.Bit values sets the number of single conversions done during one measurement cycle. Result is the average value of all conversions.Number of conversions = 2decimal_value e.g. 0 = 1 conv., 1 = 2 conv, 2 = 4 conv., ….7 = 128 conv.DEFAULT = 32 conv. (bit 2 to bit 0: 101)TABLE 6 - AMBIENT LIGHT RESULT REGISTER #5Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0DescriptionRead only bits. High byte (15:8) of ambient light measurement resultTABLE 7 - AMBIENT LIGHT RESULT REGISTER #6Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0DescriptionRead only bits. Low byte (7:0) of ambient light measurement resultRegister #7 and #8 Proximity Measurement Result RegisterRegister address = 87h and 88h. These registers are the result registers for proximity measurement readings.The result is a 16 bit value. The high byte is stored in register #7 and the low byte in register #8.Register #9 Interrupt Control Register Register address = 89h.TABLE 8 - PROXIMITY RESULT REGISTER #7Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0DescriptionRead only bits. High byte (15:8) of proximity measurement resultTABLE 9 - PROXIMITY RESULT REGISTER #8Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0DescriptionRead only bits. Low byte (7:0) of proximity measurement resultTABLE 10 - INTERRUPT CONTROL REGISTER #9Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Int count exceedn/aINT_PROX_ready_ENINT_ALS_ready_ENINT_THRES_ENINT_THRES_SELDescriptionInt count exceedR/W bits. These bits contain the number of consecutive measurements needed above/below the threshold000 - 1 count = DEFAULT 001 - 2 count 010 - 4 count 011 - 8 count 100 -16 count 101 - 32 count 110 - 64 count 111 - 128 countINT_PROX_ready_EN R/W bit. Enables interrupt generation at proximity data ready INT_ALS_ ready_EN R/W bit. Enables interrupt generation at ambient data readyINT_THRES_EN R/W bit. Enables interrupt generation when high or low threshold is exceeded INT_THRES_SELR/W bit. If 0: thresholds are applied to proximity measurements If 1: thresholds are applied to als measurementsRegister #10 and #11 Low ThresholdRegister address = 8Ah and 8Bh. These registers contain the low threshold value. The value is a 16 bit word. The high byte is stored in register #10 and the low byte in register #11.TABLE 11 - LOW THRESHOLD REGISTER #10Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0DescriptionR/W bits. High byte (15:8) of low threshold valueTABLE 12 - LOW THRESHOLD REGISTER #11Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0DescriptionR/W bits. Low byte (7:0) of low threshold valueRegister #12 and #13 High ThresholdRegister address = 8Ch and 8Dh. These registers contain the high threshold value. The value is a 16 bit word. The high byte is stored in register #12 and the low byte in register #13.TABLE 13 - HIGH THRESHOLD REGISTER #12Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0DescriptionR/W bits. High byte (15:8) of high threshold valueTABLE 14 - HIGH THRESHOLD REGISTER #13Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0DescriptionR/W bits. Low byte (7:0) of high threshold valueRegister #14 Interrupt Status RegisterRegister address = 8Eh. This register contains information about the interrupt status for either proximity or ALS function and indicates if high or low going threshold exceeded.TABLE 15 - INTERRUPT STATUS REGISTER #14Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0n/a int_prox_ready int_als_ready int_th_low int_th_hiDescriptionint_prox_ready R/W bit. Indicates a generated interrupt for proximityint_als_ready R/W bit. Indicates a generated interrupt for alsint_th_low R/W bit. Indicates a low threshold exceedint_th_hi R/W bit. Indicates a high threshold exceedNote•Once an interrupt is generated the corresponding status bit goes to 1 and stays there unless it is cleared by writing a 1 in the corresponding bit. The int pad will be pulled down while at least one of the status bit is 1.分销商库存信息: VISHAYVCNL4010-GS08。

MBR20100C中文资料

UTC assum es no responsibility for equipm ent failures that result from using products at v alues that exceed, ev en m om entarily, rated v alues (such as m axim um ratings, operating condition ranges, or other param eters) listed in products specifications of any and all UTC products described or contained herein. UTC products are not designed for use in life support appliances, devices or system s where m alfunction of these products can be reasonably expected to result in personal injury. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The inform ation presented in this docum ent does not form part of any quotation or contract, is believ ed to be accurate and reliable and m ay be changed without notice.
DIODE

550C中文资料

550C中文资料关键信息项：1、资料名称：550C 中文资料2、资料用途：＿___________________________3、资料提供方：＿___________________________4、资料接收方：＿___________________________5、资料使用期限：＿___________________________6、资料保密要求：＿___________________________7、违约责任：＿___________________________8、争议解决方式：＿___________________________11 协议背景本协议旨在规范550C 中文资料的相关事宜，确保资料的合理使用、保护和传播。

111 资料的定义和范围本协议中所提及的550C 中文资料包括但不限于文字、图表、图像、音频、视频等与 550C 相关的各类中文形式的信息。

112 资料的用途资料接收方应仅将 550C 中文资料用于具体合法且明确的用途，不得用于其他任何未经授权的目的。

12 资料提供方的权利和义务121 提供方应确保所提供的 550C 中文资料的真实性、准确性和完整性。

122 提供方有权对资料接收方的使用情况进行监督和检查。

13 资料接收方的权利和义务131 接收方应按照协议约定的用途使用 550C 中文资料。

132 接收方有义务对资料进行妥善保管，采取合理的安全措施防止资料泄露、丢失或损坏。

133 未经提供方书面同意，接收方不得将资料转让、出售、出租或提供给任何第三方。

14 资料使用期限141 双方约定 550C 中文资料的使用期限为具体时间段。

142 在使用期限届满后，接收方应立即停止使用并按照提供方的要求归还或销毁资料。

15 资料保密要求151 接收方应对 550C 中文资料予以保密，不得向任何无关人员透露资料的内容。

152 接收方应采取必要的保密措施，如限制访问、加密存储等，以确保资料的保密性。

MCP41050中文

ppm/°C 编码 80h
， RS 和 SHDN 引脚的工作方式请参见图 2-12 数字输入 / 输出（CS、 SCK、 SI 和 SO）
VAB = VDD，抽头上无连接。变阻器位置非线性度 R-INL 是指抽头在最大电阻和最小电阻范围内测量的实际位置偏离理想位置的程度。 R-DNL 测量连续抽头位置间的步长相对理想值的变化。对于 10 kΩ 的电位器， VDD = 3V 时 IW = 50 µA， VDD = 5V 时 IW = 400 µA。测试电路请参见图 2-26。在器件配置为分压器或电位器模式时，在 VW 上测量 INL 和 DNL。 VA = VDD 且 VB = 0V。 DNL 规范极限值 ±1 LSB （最大值）是在规定的单调操作条件下的值。测试电路请参见图 2-25。电阻端子 A、 B 和 W 相互间无极性限制。满量程误差和零刻度误差使用图 2-25 进行测量。在 VW 引脚上测得，此时该引脚附近的另一个 VW 引脚上的电压满幅摆动。供电电流与流经电位器的电流无关。
2006 Microchip Technology Inc.
DS11195C_CN 第 1 页
MCP41XXX/42XXX
1.0 电气特性直流特性：10 kΩ 器件
电气特性：除非另外声明，否则 VDD = +2.7V 至 5.5V 且 TA = -40°C 至 +85°C （TSSOP 器件只能在 +25°C 和 +85°C 条件下工作）。典型规范值：VDD = 5V、 VSS = 0V、 VB = 0V 且 TA = +25°C。参数变阻器模式标称电阻变阻器差分非线性度变阻器积分非线性度变阻器温度系数抽头电阻抽头电流标称电阻匹配电位器分压器分辨率单调性差分非线性度积分非线性度分压器温度系数满量程误差零刻度误差电阻端子电压范围电容（CA 或 CB）电容带宽 -3dB 稳定时间电阻噪声电压串扰施密特触发器高电平输入电压施密特触发器低电平输入电压施密特触发器输入迟滞低输出电压高输出电压输入泄漏电流引脚电容（所有输入 / 输出）电源要求工作电压范围输入电流，有源输入电流，静态电源灵敏度注 1： 2： 3： 4： 5： 6： VDD IDDA IDDS PSS PSS 2.7 －－－－－ 340 0.01 0.0015 0.0015 5.5 500 1 0.0035 0.0035 V µA µA %/% %/% VDD = 5.5V， CS = VSS， fSCK = 10 MHz， SO = 开路，编码 FFh （注 6） CS， SHDN， RS = VDD = 5.5V， SO = 开路（注 6） VDD = 4.5V - 5.5V， VA = 4.5V，编码 80h VDD = 2.7V -3.3V， VA = 2.7V，编码 80h CW BW tS eNWB CT VIH VIL VHYS VOL VOH ILI CIN 和 COUT 动态特性（测试所有动态特性时 VDD = 5V）－－－－ 0.7VDD －－－ VDD - 0.5 -1 － 1 2 9 -95 －－ .05VDD －－－ 10 －－－－－ .3VDD － 0.40 － +1 － V V µA pF IOL = 2.1 mA， VDD = 5V IOH = -400 µA， VDD = 5V CS = VDD， VIN = VSS 或 VDD，包括 VA SHDN=0 VDD = 5.0V， TA = +25°C， fc = 1 MHz MHz µS nV/√Hz dB V V VB = 0V，在编码为 80h，输出负载 = 30 PF 时测得 VA = VDD， VB = 0V，误差范围为 ±1%，编码从 00h 过渡到 80h，输出负载 = 30 pF VA = 开路，编码 80h， f = 1 kHz VA = VDD， VB = 0V （注 5） VA,B,W 0 －－－ 15 5.6 VDD －－ pF pF 注4 f = 1 MHz，编码 80h，请参见图 2-30 f = 1 MHz，编码 80h，请参见图 2-30 N N DNL INL ∆VW/∆T VWFSE VWFSE VWZSE VWZSE 8 8 -1 -1 － -2 -2 0 0 －－ ±1/4 ±1/4 1 -0.7 -0.7 +0.7 +0.7 －－ +1 +1 － 0 0 +2 +2 位位 LSB LSB LSB LSB LSB LSB 注3 注3 编码 FFh， VDD = 5V，请参见图 2-25 编码 FFh， VDD = 3V，请参见图 2-25 编码 00h， VDD = 5V，请参见图 2-25 编码 00h， VDD = 3V，请参见图 2-25 R R-DNL R-INL ∆RAB/∆T RW RW IW ∆R/R 8 -1 -1 －－－ -1 － 10 ±1/4 ±1/4 800 52 73 － 0.2 12 +1 +1 － 100 125 +1 1 kΩ LSB LSB ppm/°C Ω Ω mA % 仅 MCP42010， P0 到 P1 ； TA = +25°C VDD = 5.5V、 IW = 1 mA、编码 00h VDD = 2.7V、 IW = 1 mA、编码 00h TA = +25°C （注 1）注2 注2 符号最小值典型值最大值单位条件

SI4010中文手册

SI4010-C2数据手册-中文特点⏹ 可配置不使用外部晶振➢ 晶振源可配置 ⏹ 高速8051UC 内核 ➢管道指令架构 ➢ 70%的指令执行需要1个或2个时钟周期 ➢ 高达24 MIPs(使用24M 时钟时) ➢ 4k RAM/8k NVM(一次性非易失性存储器) ➢128 bit EEPROM ➢256字节的内部数据RAM ➢ 12 kB API 函数（嵌入在ROM 中） ⏹ 大量的数字外设 ➢ 128位AES 加速器 ➢5/9个具有唤醒功能GPIO ➢LED 驱动器 ➢数据串行器 ➢高速频率计数器 ➢在线调试接口：C2 ➢唯一的4字节序列号 ➢ 超低功耗睡眠定时器 ⏹ 一枚纽扣电池➢ 供给电压：1.8到3.6V ➢ 待机电流 < 10nA ⏹ 高性能射频发射机 ➢ 频率范围:27-960 MHz ➢ +10 dBm 输出功率（可调的） ➢ 天线自动调整 ➢ 符号速率高达100kbps ➢ FSK/OOK 调制方式 ➢ Manchester, NRZ, 4/5编码 ⏹ 模拟外设 ➢带POR 电路的LDO 调节器 ➢ 电池电压监测 ⏹ 温度范围-40至+85℃ ⏹ 可选汽车质量标准AEC-Q100（等待最后的资格测试） ⏹ 10-pin MSOP / 14-pinSOIC说明Si4010是一个全集成无晶体CMOS SoC射频发射机，内置CIP-518051单片机。

该设备可以在-40至85°C的温度范围内运行，而无需外部晶体参考源，从而减少板面积和BOM成本。

该设备包括用于编程用户应用程序的8kb非易失性存储器块以及可以被用户应用程序调用API函数的12k内嵌ROM（存放API函数代码）。

Si4010包括Silicon Laboratories的2线C2调试和编程接口，允许客户在开发阶段将其代码下载到芯片RAM中，以便在对NVM编程之前进行测试和调试。

NVM为一次性烧录，程序开发完毕之后使用NVM烧录最后的应用程序。

Microchip Technology DS30010074C_CN 第1 页 PIC24FJ10

2016 Microchip Technology Inc.DS30010074C_CN 第1页PIC24FJ1024GA610/GB610系列高性能CPU•改进的哈佛架构•对于PIC24，提供最大程序存储器（1024KB ），适用于最复杂应用•32 KB SRAM ，适合于所有器件类型•32 MHz 时，最高运行速度达到16 MIPS •8MHz 快速RC 内部振荡器： -96MHz PLL 选项-多个时钟分频选项-运行时自校准功能，能保持精度小于±0.20%-快速启动•17位X 17位单周期硬件小数/整数乘法器•32位/16位硬件除法器•16位X 16位工作寄存器阵列•优化的C 编译器指令集架构•2个地址发生单元，分别用于数据存储器的读和写寻址通用串行总线功能•符合USB v2.0 On-The-Go （On-The-Go ，OTG ）规范•双角色能力——可充当主机或外设•主机模式下的低速（1.5 Mb/s ）和全速（12 Mb/s ）USB 操作•设备模式下的全速USB 操作•用于USB 的高精度PLL•使用FRC 振荡器执行USB 设备模式操作——无需晶振•支持最多32个端点（两个方向各为16个）：-USB 模块可以将器件上的任意RAM 存储单元用作USB 端点缓冲区•片上USB 收发器，以及用于片外USB 收发器的接口•支持控制、中断、等时和批量传输•片内上拉和下拉电阻模拟特性•最多24路通道的10/12位模数（Analog-to-Digital ，A/D ）转换器：-转换速率为200 ksps （12位）-自动扫描和阈值比较功能-可在休眠模式下进行转换•3个带可编程输入/输出配置的轨到轨增强型模拟比较器•充电时间测量单元（Charge Time Measurement Unit ，CTMU ）：-用于电容触摸传感，最多24路通道-时间测量分辨率可达100 ps低功耗特性•休眠和空闲模式可有选择地关闭外设和/或内核，可显著降低功耗和实现快速唤醒•打盹模式允许CPU 以低于外设的时钟速度运行•备用时钟模式支持即时切换到较低的时钟速度，可选择性地降低功耗•宽范围数字控制振荡器（Digitally Controlled Oscillator ，DCO ），用于快速启动和低功耗操作单片机特性•大的双分区闪存程序阵列：-能够容纳两个独立的软件应用程序，包括自举程序-允许在一个分区中执行应用程序代码的同时对另一个分区进行编程-允许在活动分区之间进行运行时切换•可承受10,000次擦/写（典型值）•数据保持时间：最少20年•可在软件控制下自编程•供电电压范围为2.0V 至3.6V•工作环境温度范围：-40°C 至+85°C •片上稳压器（1.8V ），用于低功耗操作•可编程参考时钟输出•通过2个引脚进行在线串行编程（In-Circuit Serial Programming ™，ICSP ™）和在线仿真（In-Circuit Emulation ，ICE ）•支持JTAG 边界扫描•故障保护时钟监视器操作：-检测时钟故障并切换至片内低功耗RC 振荡器•上电复位（Power-on Reset ，POR)、欠压复位（Brown-out Reset ，BOR ）、上电延时定时器（Power-up Timer ，PWRT ）和振荡器起振定时器（Oscillator Start-up Timer ，OST ）•可编程高/低电压检测（High/Low-Voltage Detect ，HLVD ）•灵活的看门狗定时器（Watchdog Timer ，WDT ）自身带有RC 振荡器，能可靠工作具有大的双分区闪存程序存储器和 USB On-The-Go （OTG ）的16位单片机PIC24FJ1024GA610/GB610系列DS30010074C_CN 第2页 2016 Microchip Technology Inc.外设特性•外设引脚选择（Peripheral Pin Select ， PPS ）——允许对许多外设进行独立的I/O 映射•最多5个外部中断源•所有I/O 引脚上的可配置电平变化中断：-每个引脚可独立配置为进行上升沿或下降沿电平变化检测•8通道DMA 支持所有外设模块：-最大程度降低CPU 开销并提高数据吞吐量•5个带预分频器的16位定时器/计数器：-可以配对成32位定时器/计数器•6个输入捕捉模块，每个带有专用的16位定时器•6个输出比较/PWM 模块，每个都具有专用的16位定时器•4个单输出CCP （SCCP ）和3个多输出CCP （MCCP ）模块：-每个模块使用独立的16/32位时基-内部时基和周期寄存器-传统PIC24F 捕捉和比较模式（16位和32位）-特殊的变频脉冲和无刷直流电机输出模式•增强型并行主/从端口（Enhanced Parallel Master/Slave Port ，EPMP/EPSP ）•带时间戳功能的硬件实时时钟/日历（Real-Time Clock/Calendar ，RTCC ）•3个3线/4线SPI 模块：-支持4帧模式-8级深FIFO 缓冲区-支持I 2S 操作•3个I 2C 模块支持多主器件/从模式和7位/10位寻址•6个UART 模块：-支持RS-485、RS-232和LIN/J2602-用于IrDA ®的片上硬件编码器/解码器-自动波特率检测（Auto-Baud Detect ，ABD ）时自动唤醒-4级深FIFO 缓冲区•32位可编程循环冗余校验（Cyclic Redundancy Check ，CRC ）发生器•4个可配置逻辑单元（Configurable Logic Cell ，CLC ）：-2个输入和1个输出，全部可映射到外设或I/O 引脚-与/或/异或逻辑和D/JK 触发器功能•所有I/O 引脚上的高灌/拉电流（18mA/18mA ）•数字I/O 引脚上的可配置漏极开路输出•多个I/O 引脚上可承受5.5V 输入2016 Microchip Technology Inc.DS30010074C_CN 第3页PIC24FJ1024GA610/GB610系列PIC24FJ1024GA610/GB610系列产品表1列出了每个器件的器件名称、引脚数、存储器大小和外设可用性。

W89C940资料

ELANC-PCI (TWISTED-PAIR ETHER-LAN CONTROLLER WITHPCI INTERFACE) GENERAL DESCRIPTIONhe ELANC-PCI (Twisted-pair Ether-LAN Controller with PCI Interface) integrates a W89C902 Serial(ELANC-PCI) LAN Coprocessor for Twisted-Pair (SLCT) and PC/AT PCI bus interface logic into a single chip. The ELANC-PCI provides an easy way of implementing the interface between an IEEE 802.3-compatible Ethernet and a personal computer, ELANC-PCI also provide fast DMA operation to improve the packet transmit and receive performance.The PCI bus is a high performance local bus architecture with low latency random access time. It is a synchronous bus with operation up to 33MHz. The PCI bus interface is designed to provide the registers with the device information required for configuration, recording the status of the lines , control registers, interrupt line and I/O base address registers. It is capable of functioning in a half-duplex environment.The W89C940Fis designed to fully comply with the standard of PCI 2.0 specification. Taking advantage of PCI's nature, W89C940F supports auto-configuration function to free users' depression and confusion on tunning system resources conflict. With extremely high throughput on PCI bus, W89C940F offers a 32 bits data path to highly boost its performance without extra cost. Comparing with LAN card with ISA bus, its improvement is excellent. Besides, it also supports up to 256KB flash memory reserved for various applications, for instance anti-virus, popular drivers, Boot ROM, viewing your PC assets...etc., and what is more, these software are able to be updated on line. This can increase more niche feature on your LAN card, help you get more and bright your company profile. W89C940F is a single chip - build-in PCI bus interface and all necessary circuits - which will let design and board assembly become easy.FEATURES• Fully compatible with IEEE 802.3 standard• Software compatible with Novell NE2000• Complies with PCI Local Bus Specification Revision 2.0•Slave Mode for PCI bus•Fast DMA operation enhancing network access performance•AUI, UTP interface available•Supports one chip 32Kx8 and 16Kx8 SRAM•Supports up to 64KB boot ROM• EEPROM auto-load function after power on reset•EEPROM on-board programming function available•UTP interface polarity auto detection correction function available• UTP/BNC auto media-switching function provided•LED displaying for network segment Link/activity status•Signature register available for device identification•Single 5V power supply with low power consumption•100 Pin PQFPPIN CONFIGURATION505152535455565758596061626364656667686970717273748175767778798082838485868788894948474645444342414039383736353490919293949596979899100123456101178912131415161718192021222324252627282930333231V C C A D 22A D 21A D 20A D 19A D 18A D 17A D 16A D 15CB E #2/F R A M #E I R D Y #T R D Y #D E V S E L #S T O P #G N D V C CP A RC #B E #1A D 14A D 13A D 12A D 11A D 10A D 9A D 8C /B E #0B U S CL KG N D V C CDN G PX T N X T NX R P D C P X R ND C ACT EECSB PC S BR C S B M S A 14\L M S A 13M S A 12MS A 11M S A M M 10S A M S A M S A M S A M S A M S A M S A M S A M S A S A 9876543210V C C X 1X 2G N DTPDP TPDM XRDP XRDM DGND RST#INTA AD31AD30AD29AD28AD27AD26AD25AD24AD23C/BE3#IDSEL DGNDMSWRB MSRDB MSD7MSD6MSD5MSD4MSD3MSD2MSD1MSD0AD0AD1AD2AD3AD4AD5AD6AD7DGND DVCCW89C940(100 PINS)#AVCC D D D D D D D ABLOCK DIAGRAMPIN DESCRIPTIONPCI INTERFACENAME NUMBERTYPE DESCRIPTIONCLK29inClock:Bus clock from PCI bus. All of the PCI signals, except RST#, are synchronized by rising edge of clock.The allowable operating frequency of CLK for W89C940 is from 25MHz to 33MHz.RST#87in Reset:Asynchronous reset signal from PCI bus.AD[31:00]AD31-AD24AD23AD22-AD16AD15-AD8AD7-AD089 - 96992 - 819 - 2633 - 40t/sAddress and Data:Bidirection bus for PCI address and data signals transaction. AD[31:00] is a time division bus. Two phases are used to carry the address and data messages of PCI bus. The address phase is the clock cycle in which FRAME# is aeerted.AD[31:24] contains the most significant byte(MSB) and the AD[7:0] contain the least significant byte(LSB) during the data phase.The data written from host should be stable and valid when IRDY# is asserted. The data driven by W89C940 will be stable and valid when TRDY# is asserted.C/BE[3:0]#C/BE3#C/BE2#C/BE1#C/BE0#9791827t/s inBus Command and Byte Enables:C/BE[3:0]# define the type of bus command during the address phase and the byte enables during the data phase of a transaction. There are 16 types of bus command defined in PCI bus. Four bits of C/BE[3:0]# are used to decode the 16types of bus command. The byte enable determine which byte lanes carry meaningful data.C/BE0# indicate the byte 0(AD[7:0]) is valid. C/BE1# indicate the byte 1(AD[15:8]) is valid. C/BE2# indicate the byte 2(AD[23:16]) is valid. C/BE3# indicate the byte 3(AD[32:24]) is valid.PAR17t/s Parity:Even parity across AD[31:0] and C_BE[3:0]B.W89C940 will drive the PAR in read data phase. The host drives the PAR for address phase and writes data phase. PAR is stable and valid one clock after the address phase. PAR is stable and valid one clock after either IRDY# is asserted on a write transaction or TRDY# is asserted on a read transaction. Once PAR is valid, it remains valid until one clock after the completion of the current data phase.FRAME#10s/t/s inCycle Frame:FRAME# is asserted by host to indicate the beginning of a bus transaction. When FRAME# is deasserted, the transaction is in the final data phase.PCI INTERFACENAME NUMBER TYPE DESCRIPTIONIRDY#11s/t/sin Initiator Ready:Initiator Ready indicates the host's ability to complete the current data phase of transaction. During a write cycle, IRDY# indicates that valid data is presented on AD[31:00]. During a read cycle, it indicates the master is ready to accept the data. The wait cycles are inserted till IRDY# and TRDY# are asserted at the same cycle.TRDY#12s/t/s Target Ready:Target Ready indicates the W89C940's ability to complete the current data phaseof transaction. During a read cycle, TRDY# indicates that valid data is presentedon AD[31:00]. During a write cycle, it indicates the W89C940 is ready to acceptthe data. The wait cycles are inserted till both IRDY# and TRDY# are asserted atthe same cycle.STOP#14s/t/s STOP:Stop indicates W89C940 is requesting the master to stop the current transaction. IDSEL98in Initialization Device Select:IDSEL is used as a chip select during PCI configuration read and writetransaction.DEVSEL#13s/t/s Device Select:DEVSEL# will be asserted when W89C940 decode the correct address.INTA#88o/d Interrupt Request:INTA# is used to request an interrupt service. The interrupt signal can bemasked by the register of IMR( Interrupt Mask Register). INTA# status is kept atISR( Interrupt Status Register).NETWORK INTERFACENAME NUMBER TYPE DESCRIPTIONX1 X25352I/TTLO/TTLCrystal or Oscillator Input.Crystal or oscillator input (X1) and output (X2) pin. If a crystal is used, it shouldbe connected directly to X1 and X2. If an oscillator is selected, X1 is the 20 MHzinput and X2 should be left floating.TXP TXN 7574O/AUIAUI Transmit Output:AUI differential output pair. The data transmitted by DTE will be sent through TXPand TXN in a differential signal with manchest code format. A 270 ohm pull-downresistor is required for each of TXP and TXN. TXP and TXN should be isolatedby a pulse transformer from directly connecting outside loop.NETWORK INTERFACENAME NUMBER TYPE DESCRIPTIONRXP RXN7978I/AUIAUI Receive Input:AUI differential input pair. The data received by network transceiver will be sent back through RXP and RXN in a differential signal format. The RXP and RXN are also should be isolated by a pulse transformer.CDP CDN7776I/AUIAUI Collision Input:AUI differential input pair. The network transceiver will drive a 10MHz differential signal onto CDP and CDN when a collision event is occurred. The CDP and CDN should be isolated by a pulse transformer.XRDP XRDM 8485I/TPITPI Receive Input:10BASE-T receive differential input pair. RXP and RXN should be shunted by a 100 ohms resistor for twisted-pair line impedance matching.TPDP TPDM 8283O/TPITPI Transmit Output:10BASE-T transmit differential output pair. A 1.21K ohm shunt resistor is required across the TXP and TXN for signal pre-equalization.ACT73O/LED Activity Displaying:Network activity displaying. ACT will indicate the network activity status by three types of signals(DC 0 , DC1 and AC 10Hz).DC 0 : indicating "Link Good", if UTP is selected.DC 1 : indicating 1) "Link fail", if UTP is selected.2) "idle", if AUI is selected.AC 10HZ : indicating the DTE is transmitting a packet or the carrier on the network is detected by the transceiver and the carrier sense signal is received by W89C940.The ACT will keep DC 1 if there is an abnormal network collision occurred, f.g.the transceiver collision signal always active.MEMORY INTERFACENAME NUMBER TYPE DESCRIPTIONMSD[7:0]48 - 41B/MOSLocal Memory Data Bus:A bidirection bus for data transfer between the local memory and the W89C940.MSD0 is used as a serial data input pin during the auto configuration duration for hardware reset. The data drove by the DO of EEPROM will clocked into the MSD0 when the EEPROM load operation is active. The Ethernet node ID and optional configuration content will be loaded into chip s registers at this moment.MSD1 is used as a serial data output pin during the auto configuration duration for hardware reset.The command drove by the MSD1 will be clocked into the DI of EEPROM for accessing the content of EEPROM.MSD2 supplies the clock with a period of 1.2 µS for EEPROM during auto configuration duration.MEMORY INTERFACENAME NUMBER TYPE DESCRIPTIONMSRDB 49O/MOS Local Memory Read Enable.An active low signal to enable the local SRAM read.MSWRB 50O/MOS Local Memory Write Enable.An active low signal to enable the local SRAM write.MSA[14:0]69 - 55O/MOSLocal Memory Address B us.Address bus for local memory addressing.The MSA14 will be used as the address strobe signal when the size is larger than 32Kx8. If the ROM size is larger than 32Kx8, B oot ROM address !13-A10 is connected to MSA13-MSA10 and A17-A14 is connected to the latched MSA13-MSA10. The valid address for the higher significant bits(A14,A15,....) will be stable before the BPCSB is active low and should be latched by an external data latch which is triggered by MSA14. The A0 ~ A13 of the B OOT ROM device are connected to MSA0 ~ MSA13 directly no matter the B OOT ROM size is larger than 32Kx8 or not.RCSB 70O/MOS Memory Chip Select:The RCSB is active low.RCSB enables the local memory read/write cycle in conjunction with the MSRDB,MSWRB pins.BPCSB71O/MOS BOOT ROM Chip Select:BPCSB is active low.BPCSB enables the BOOT ROM read cycle during the system booting up.EECS72O/MOS EEPROM Chip Select.The EEPROM read/write operation will be enabled when EECS is active high.POWER PINSNAME NUMBER TYPE DESCRIPTIONDVCC 1, 16, 30,31, 54I Digital Power Supply:5V DC power supply for internal digital logic circuitry.DGND 15, 28, 32,51, 86, 100I Digital Ground:Ground pins for internal digital logic circuitry.AVCC81IAnalog Power Supply:5V DC power supply for internal analog circuitry.POWER PINSNAME NUMBER TYPE DESCRIPTIONAGND80I Analog Ground:Ground pin for internal analog circuitry.It is recommended that there is a decoupling capacitor connected between thepower supply pins and ground pins. A RC low pass filter is also recommended tobe used for analog power supply.Note: Signal Type Definitionin Input is a standard input-only signalout Totem Pole output is a standard active driver.t/s Tri-State is a bi-directional, tri-state input/output pin.s/t/s Sustained Tri-State is an active low tri-state signal owned and driven by one and only one agent at a time. The agent that drives an s/t/s pin low must drive it high for at least one clock beforeletting it float. A new agent cannot start driving a s/t/s signal any sooner than one clock after theprevious owner tri-states it. A pull-up is required to sustain the inactive state until another agentdrives it, and must be provided by the central resource.o/d Open Drain allows multiple devices to share as a wire-OR.FUNCTIONAL DESCRIPTIONIEEE 802.3 MAC FUNCTIONCore Coprocessor (SLCT) OperationThe SLCT core coprocessor has five major logic blocks that control Ethernet operations: the register files,transmit logic, receive logic, FIFO logic, and DMA logic. The relationship between these blocks is depicted in the following block diagram.Register FilesThe register files of the SLCT can be accessed in the same way as the configuration registers. The ELANC-PCI should be in slave mode when the system accesses the register files. The command register (CR) determines the page number of the register file, while the system address SA<0:3> selects one register address from 01H to 0fH. The PCI IO read/write commands are used to activate the I/O operations. Refer to the W89C90 data sheet for more detailed information on the registers.DMA Interface LogicThe SLCT has two types of DMA operations, local DMA and remote DMA.FIFO LogicThe SLCT has a 16-byte FIFO, which acts as an internal buffer to adjust transmission/reception speed differences between DMAs. The FIFO has FIFO threshold pointers to determine the level at which it should initiate a local DMA. The threshold levels are different for reception and transmission. The FIFO threshold levels are defined in the DCR register.The FIFO logic also provides a FIFO overrun and underrun signal for network management purposes. In a case where the receive packets are flooding into the FIFO but the SLCT still does not have the bus authority, the FIFO may be overrun. On the other hand, if a transmission begins before data are fed into the FIFO, it may be underrun. Both cases result in a network error. These types of cases can be prevented by changing the values of the FIFO thresholds.Normally, the data in the FIFO cannot be read; reading FIFO data during normal operation may cause the system to hang. In loopback mode, however, the SLCT allows FIFO data to be read by byte in order to check the correctness of the loopback operation.Receive LogicThe receive logic is responsible for receiving the serial network data and packing the data in byte/word sequence. The receive logic thus has serial to parallel logic in addition to network detection capability.The ELANC-PCI accepts both physical addresses and group addresses (multicast and broadcast addresses).The SLCT extracts the address field from the serial input data. It then determines if the address is acceptable,according to the configurations defined in the receive configuration register (RCR). If the address is not acceptable, the packet reception is aborted. If the address is acceptable, the data packet is sent to the serial to parallel logic before being fed into the FIFO. Data packets can thus be processed either byte or word-wide.After receiving a data packet, the SLCT automatically adds four bytes of data receive status, next packet pointer, and two bytes of receive byte count into the FIFO for network management purposes. The receive status contains the status of the incoming packet, so that the system can determine if the packet is desired. The next packet pointer points to the starting address of the next packet in the local receive ring. The receive byte count is the length of the packet received by the SLCT. Note that the receive byte count may be different from the "length" field specified in the Ethernet packet format. These four bytes of data will be transferred to the local buffer with the last batch of the local DMA. However, these four bytes are stored at the first four addresses before the packet.Transmit LogicThe SLCT must be filled before transmission begins. That is, the local DMA read must begin before the SLCT begins transmission. The SLCT first transmits 62 bits of preamble, then two bits of SFD, and then the data packet. The parallel to serial logic serializes the data from the FIFO into a data packet. After the data packet,the SLCT optionally adds four bytes of cyclic redundancy code (CRC) to the tail of the packet.A protocol PLA determines the network operations of the ELANC-PCI. Collision detection, random backoff, and auto retransmit are implemented in the transmit logic. The protocol PLA ensures that the ELANC-PCI follows IEEE 802.3 protocol.10BASE2 AND 10BASE5 PLS (PHYSICAL LAYER SIGNAL) FUNCTIONSNA OperationFile 1The ELANC-PCI also contains a Serial Network Adapter (SNA), which adapts the Non-Return-to-Zero (NRZ) used in the core processor and host system to Manchester coded network symbols.The SNA contains three blocks: a Phase Locked Loop (PLL), a Manchester encoder/decoder, and a collision decoder, as well as crystal/oscillator logic.The Manchester encoder/decoder handles code interpretation between NRZ signals and Manchester coded signals. The PLL locks the receiving signals with an internal voltage control oscillator (VCO) so that network noise(jitter) can be eliminated before the signals enter the core coprocessor. The collision decoder detects whether the network is in a collision status.10BASE-T MAU FUNCTIONTP Transceiver OperationTransmit DriverThere are two signals for data transmission, TXP and TXN, which connect to the twisted-pair cable via a transmitter filter and an optional common mode choke.Smart SquelchThe main function of this block is to determine when valid data are present on the differential receiving inputs (RXP/RXN). To ensure that impulse noise on the medium will not be taken as a valid datum, this circuit adopts a combination of amplitude and timing measurements to determine the validity of the input signals. To qualify incoming data, the smart squelch circuitry monitors the signals for three peaks of alternating polarity that occur within a 400 nS window. Once this condition has been satisfied, the squelch level is reduced to minimize the noise effect and the chances of causing premature Start Of Idle (SOI) pulse detection. If the receiver detects activity on the receive line while packets are being transmitted, incoming data is qualified on five peaks of alternating polarity so as to prevent false collisions caused by impulse noise. The squelch function returns to its squelch state under any of the following conditions:−A normal Start Of Idle (SOI) signal−An inverted SOI signal−A missing SOI signalA missing SOI signal is assumed when no transitions have occurred on the receiver for 175nS after a packet has arrived. In this case, a normal SOI signal is generated and appended to the data.Collision DetectionA collision occurs when transmit and receive signals occur simultaneously on the twisted pair cable. Collisions will not be reported when the device is in link-fail state. The collision signal is also generated when the transceiver has detected a jabber condition or when the SQE test is being performed.SQE testThe Signal Quality Error (SQE) test is used to test the collision signaling circuitry in the Twisted Pair Transceiver module. After each packet transmission, an SQE signal is sent to the SLCT. The SLCT expects this signal and will flag an error if it does not exist.JabberThe jabber timer monitors the transmitter and disables the transmission if the transmitter is active for greater than 26.2 mS.The jabber will re-enable the transmitter after the SLCT has been idle for at least 420 mS.Link IntegrityDuring periods of inactivity, link pulses are generated and received by both MAUs at either end of the twisted pair to ensure that the cable has not been broken or shorted. A positive, 100 nS Link Integrity signal is generated by the Twisted Pair Transceiver and transmitted on the twisted pair cable every 13 ms during periods of no transmission activity. The ELANC-PCI assumes a link-good state if it senses valid link pulse activity on the Twisted Pair Transceiver receive circuit. If neither receive data nor a link pulse (positive or negative) is detected within 105 mS, the ELANC-PCI enters link-fail state. When a link-fail condition occurs, four consecutive positive link pulses (or eight negative link pulses) must be received before a link-good condition is assumed.LCE CORE ACCESS FUNCTIONLCE core access function (LCE: Lan Controller of Ethernet)The LCE core of the ELANC-PCI can be accessed by programming the register of the LCE core. The ELANC-PCI's register files are mapped into the lower 16 I/O spaces: iobase to iobase+0FH. Any read/write to the ELANC-PCI's registers is an "IN"/"OUT" command to these addresses.Addresses iobase+10H to iobase+17H are mapped to the I/O port for the system to access the contents of the buffer memory. Remote DMA reads and writes correspond to "IN"/"OUT" commands to these addresses.When addresses iobase+18H to +1FH are read a software reset will be issued to the core coprocessor and released about 780nsec later, automatically.The following table summarizes the I/O address mapping:ADDRESS REGISTER OPERATIONiobase+00H - iobase+0FH LCE core's registers Slave register read/writeiobase+10H - iobase+17H I/O Ports Remote DMA read/writeiobase+18H - iobase+1FH Reset Software resetThe buffer memory map for LCE core memory address space is summarized in the following table:NE2000 COMPATIBLE0000H - 001FH ID Registers0020H - 00FFH0100H - 3FFFH Unused4000H - 7FFFH16K X 8 local memory8000H - FFFFH UnusedNODE IDEach node in an Ethernet network has a unique six-byte ID. The node ID is mapped into the memory space of the ELANC-PCI. The ELANC-PCI will load the node ID from the EEPROM after power on reset. The node I.D. should be allocated in the first 3 words(with the address of 00H ~ 02H) of the EEPROM.Bus ArbitrationThe ELANC-PCI handles bus arbitration automatically. The LAN card can operate in four modes: idle state, slave read/write mode, DMA mode, and PCI mode. The ELANC-PCI controls the on-board devices by decoding these modes.At power on, the ELANC-PCI is in idle mode. If a register read/write command is issued, the ELANC-PCI enters the slave read/write mode. If a local DMA or remote DMA is initiated by the ELANC-PCI core coprocessor, the ELANC-PCI enters DMA mode. A PCI command will put the ELANC-PCI into PCI mode. At any given time, the ELANC-PCI can be in only one state. The ELANC-PCI handles state changes automatically. However, two events, such as a DMA command and an PCI command, may be requested at the same time; in this case, the ELANC-PCI allocates the bus on a first-come, first-served basis. No predefined priority is set within the ELANC-PCI.NE2000 MODE DMA FUNCTIONThe ELANC-PCI provides two DMA channels for system access. The remote DMA mode moves data between system memory space and local memory space. The local DMA moves data between the FIFO of the SLCT and local memory space. However, since the SLCT can handle local DMA operations without system intervention (refer to the data sheet for the SLCT), the system has to perform only remote DMA reads/writes.In a transmit operation, the data should be moved to local memory before the system orders the SLCT to start transmission. The remote DMA write moves the data from the PCI bus to the local SRAM. This is simply an "OUT" command on the PC. For a receive operation, the network may feed data constantly and the local memory may become full if the data are not moved out to system memory through a remote DMA read operation. This operation is the "IN" command on the PC.Remote DMAA remote DMA can be performed only in I/O mode. The remote DMA moves data between the host and the local buffers. Unlike a local DMA, the remote DMA is byte or word-wide. Each remote DMA operation transfers four bytes, double-word, depending on the PCI cycle.Since the remote DMA is simply an PCI I/O operation, PCI is sometimes affected by a remote DMA. If the remote DMA is interleaved with other devices, TRDY# is deasserted to force the system to insert wait states. The ELANC-PCI will automatically handle any arbitration necessary.A Double word access on W89C940 from PCI bus is allowed. The buffer memory access will stop when the Remote Byte Counter is decreased to zero. A double word read command will read only three bytes of valid data if remote byte counter is set 3 or two bytes of valid data if the remote byte counter is set 2 respectively. Local DMAThe local DMA transfers data from/to the on-board buffers. To perform data reception or transmission from/to remote nodes in the network, data must be moved from/to the FIFO. To enhance the efficiency of the transmission, the local DMA transfers data in batches: Data are first collected and then moved in a batch. Each transfer can move up to 12 bytes of data at once. This scheme reduces time wasted in requesting the bus.A local DMA begins by requesting the local bus. If the bus is available to the ELANC-PCI, it responds at once by asserting the bus acknowledge; if, on the other hand, the bus is currently authorized to another device, the ELANC-PCI will not assert the bus acknowledge and the SLCT must wait. Note that this sequence will not affect the host system or the PCI bus signals. After each batch is transferred, the SLCT checks the FIFO threshold levels to determine if another batch transfer should be requested.BOOT PROM ACCESS FUNCTIONBoot PROM OperationFor diskless applications, the system requires an on-board boot device. The ELANC-PCI allows the system to use an on-board BOOT PROM as the boot device.The BOOT PROM is essentially a byte-read device. ELANC-PCI will fetch a byte from the BOOT PROM and drive the AD bus of the PCI Interface. If the system do a word read command, the ELANC-PCI will invoke two byte read operation with consecutive address and drove the second byte on another byte of the PCI interface.For double word command, the ELANC-PCI will deassert the TRDY# until four read operation with consecutive address to the BOOT PROM is completed and then the four bytes of data will be drove onto the 32 bits data bus of PCI.W89C940 can support the EPROM and Flash memory with 220nsec access time with the size up to 256KB. In order to support 64KB,128KB and 256KB size with 15-bit address bus, W89C940 use MSA14 to latch the high address bits MSA[17:14] from MSA[13:10]. The structure for address latch is shown as following.74LS373CONFIGURATION PROGRAMMING FUNCTIONELANC-PCI Mode Configuration RegistersMCRA mode configuration register(MCR) is used to program the operation mode of the ELANC-PCI. The address is page 0, 0AH. MCR can be updated by software. Reading this register is the same as reading a register in the SLCT core coprocessor. Writing to these registers is done by first reading the register to be written to and then using a slave write operation to update the configurations.The content of MCR is as following table: BIT SYMBOL DESCRIPTION01PHY0PHY1Physical Layer Interface:These two bits select the type of physical interface which the ELANC-PCI attached on. Both the thin Ehternet and thick Ethernet type use the AUI of ELANC-PCI as the input/output interface. The other two UTP types,then, use the TPI of ELANC-PCI as the input/output interface. The output and input pins of AUI or TPI are idle, when the corresponding type is not selected.PHY1 PHY0 Physical Interface Type0 0 UTP (with 10BASE-T compatible receive squelch level) 0 1 Thin Ethernet1 0 Thick Ethernet (AUI port)1 1 UTP (with reduced receive squelch level)2GDLNKGood Link Status:A read operation on this bit will get the link test status. A "1" indicate that it is link good and a "0" is link fail.The GDLNK do not imply any information if the PHY0 and PHY1 is programmed as Thin or Thick Ethernet.3LNKENLink Test Pulse enable:The network media auto switching function, link integrity test function and the link test pulse generation function will be enabled when LNKEN = "0".Otherwise, all of these functions will be disabled when LNKEN = "1".4SHLSSRAM High/Low Speed Select:High speed SRAM with 20nsec access time is selected if SHLS =1. Low speed SRAM with 70nsec access time is selected if SHLS =0.567BPS0BPS1BPS2BOOT PROM Size:The size of the BOOT PROM is selected by BPS0, BPS1, and BPS2.BPS2 BPS1 BPS0 SIZE 0 0 X No boot PROM 0 1 0 8K 0 1 1 16K 1 0 0 32K 1 0 1 64K 1 1 0 128K 1 1 1 256K。