Jitter in ring oscillators
A 5.9-GHz Voltage-Controlled Ring Oscillator in 0.18-m CMOS
A 5.9-GHz V oltage-Controlled Ring Oscillator in 0.18- m CMOSYalcin Alper Eken ,Student Member,IEEE,and John P.Uyemura ,Senior Member,IEEEAbstract—This paper presents the design of three-and nine-stage voltage-controlled ring oscillators that were fabricated in TSMC0.18-m CMOS technology with oscillation frequencies up to 5.9GHz.The circuits use a multiple-pass loop architecture and delay stages with cross-coupled FETs to aid in the switching speed and to improve the noise parameters.Measurements show that the oscillators have linear frequency-voltage characteristics over a wide tuning range,with the three-and nine-stage rings resulting in frequency ranges of 5.16–5.93GHz and 1.1–1.86GHz,respectively.The measured phase noise of the nine-stage ring oscillator was 105.5dBc/Hz at a 1-MHz offset from a 1.81-GHz center frequency,whereas the value for the three-stage ring oscillator was simulated to be 99.5dBc/Hz at a 1-MHz offset from a 5.79-GHz center frequency.Index Terms—CMOS,LC oscillators,multiple-pass architec-ture,phase-locked loop (PLL),phase noise,ring oscillators,VLSI,voltage-controlled oscillators (VCOs).I.I NTRODUCTIONTHE phase-locked loop (PLL)is a critical component in many high-speed systems as it provides the timing basis for functions such as clock control,data recovery,and synchro-nization.The voltage-controlled-oscillator (VCO)is perhaps the most crucial element of the PLL because it directly provides the output signal of the PLL.A CMOS VCO can be built using ring structures,relaxation circuits,or an LC resonant circuit.The LC design has the best noise and frequency performance owing to the large quality factor Q achievable with resonant networks [1].However,adding high-quality inductors to a CMOS process flow increases the cost and complexity of the chip,and also in-troduces problems such as the control of eddy currents.Ring oscillators,on the other hand,can be built in any standard CMOS process and may require less die area than LC designs.The design is straightforward,and ring architectures can be used to provide multiple output phases and wide tuning ranges.In this brief,we present a design that improves the overall characteristics of CMOS ring oscillators to be com-parable to those of LC designs.The prototype circuits were implemented in a standard TSMC0.18-m non-epi CMOS process,and achieved maximum oscillation frequencies up to 5.9GHz with linear frequency–voltage characteristics.The architecture of multiple-pass ring oscillators and the use of saturated gain stages to increase the frequency and voltage swing at the output are examined in Section II.Details of the design and measurement of the prototype circuits are presentedManuscript received November 21,2002;revised July 24,2003.This work was supported by Integrated Device Technology,Inc.The authors are with the School of Electrical and Computer Engineering,Georgia Institute of Technology,Atlanta,GA 30332-0250USA (e-mail:eken@).Digital Object Identifier10.1109/JSSC.2003.820869Fig.1.N -stage multiple-pass ring oscillator.in Section III,along with a comparison of the results with other published circuits.II.M ULTIPLE -P ASS R ING O SCILLATORSW ITH S ATURATED S TAGESBecause of the frequency limitations of a single-loop ring oscillator,other architectural techniques are necessary to ex-plore the maximum frequency levels of ring oscillators.Some of these techniques include the use of subfeedback loops [2],output-interpolation methods [3],multiple-feedback loops [4],and dual-delay paths [5],[6].The multiple-pass loop architecture,which is shown in Fig.1foran -stage ring,is the basic architecture chosen in this work.This technique adds auxiliary feedforward loops that work in conjunction with the main loop.The main idea is to reduce the delay of the stages below the smallest delay that is pos-sible inside a simple ring oscillator loop.This is achieved byadding a set of secondaryinputs,and ,to every stage and switching these earlier than the primary inputs during the operation.Although the illustration is for an oscillator with an odd number of stages with the feedforward loops passing over a single stage,other configurations are possible to obtain a dif-ferent frequency increase or decrease.It is important to note that the majority of the frequency-in-crease techniques discussed above [2],[4]–[6]depends on the use of intercoupled feedback loops to increase the maximum frequency,similar to the multiple-pass loop architecture used in this work.Basically,all of these methods are fundamentally same and they are based on a one-dimensional variation of the coupled-oscillator structure introduced in [7]and discussed as the look-ahead ring oscillator in [8].Changing the architecture increases the oscillation frequency,but phase noise and jitter are also important considerations.Many ring oscillators use analog gain stages,but biasing the transistors into continuous conduction increases their contribution to the total noise.To overcome this problem,the gain transistors can be periodically switched in and out of0018-9200/04$20.00©2004IEEEFig.2.Saturated gain stage with cross-coupled PMOS transistors.conduction,which reduces the noise.The reduction of the noise by switching is shown by [5]as(1)where is the output noise power of the oscil-lator that incorporatesswitching,is the output noise power if there was no switching,andis the conducting time of the transistors in aperiod .Another problem with using standard gain stages is the output signal amplitudes that are much smaller than rail-to-rail rger signal levels correspond to better noise performance because the noise per-formance of a system is expressed by using signal-to-noise-ratio (SNR)values instead of the absolute noise power values.These imply that the best characteristics are obtained with a full-rail output signal.A design that provides both of these characteristics is the sat-urated gain stage with regenerative cross-coupled PMOS tran-sistors as shown in Fig.2[5].This provides for rail-to-rail output signals and full switching of the FETs in the stage.From a qual-itative viewpoint,it can be seen that the feedback properties of the latching transistors M1and M2speed up the signal transi-tions at the output.This improves both the oscillation frequency and the noise performance of the VCO.The stage also avoids the use of cascode connections and a tail current-source tran-sistor that would limit the signal swing and add more noise to the output.III.P ROTOTYPE O SCILLATOR D ESIGNSA primary goal of the research was to explore the maximum frequency limitations and noise performance levels of ring VCOs built in a standard CMOS process.To this end,three-and nine-stage multiple-pass ring oscillators were designed and fabricated using a non-epi TSMC0.18-m CMOS processwith a power supply valueofV .The circuits were designed with MOSIS SCMOS rules that required a minimum drawn channel length of0.20m.The test chip also included other circuits such as an integrated LC oscillator,charge pump prototypes,and phase-frequency detector networks,but these are not discussed in this brief.The prototype oscillators employ the saturated stage design given in Fig.2with the transistor ratios provided on the figure.The delay of the stage,and thus,the VCO frequency,iscon-Fig.3.Frequency –voltage characteristics of (a)the three-and (b)the nine-stage ring oscillator.trolled by altering the strength of the latch using the control ter-minalthat is connected to the NMOS switches M3and M4.Higher control voltages result in a stronger coupling be-tween M1and M2,making it more difficult to switch the output voltage,and hence decreasing the frequency.Hwang [9]uses a similar method to control the VCO frequency.Two pairs of in-puts are used to adapt the stage to a multiple-pass architecture.To ease the requirements on the needed testing equipment,high-speed current-mode-logic (CML)buffers and frequency dividers were used to divide the frequency of the oscillators from 1/2to 1/64of their actual value.The output of the divider circuits is then fed to a high-speed driver chain to the output pads for measurement.The performance of the three-stage multiple-pass design was simulated and measured with the results given in Fig.3(a).Spectre simulations of the oscillator predicted an operation range of 5.18–6.11GHz for control voltages of 0.3–1.8V .The measured silicon output was from 5.16GHz up to 5.93GHz,indicating a maximum difference of 3.7%with the simulations.The peaking of the simulated characteristics is attributed to the limitations of the simulator tool in the subthreshold region.Removing test circuitry and reducing the drawn channel length to0.18m predicts a maximum oscillation frequency of 7.7GHz as shown in the plot.The nine-stage multiple-pass ring oscillator employed the same gain stage as that used in the three-stage design.The fre-quency –voltage curves shown in Fig.3(b)were extracted fromFig.4.(a)Phase noise of the three-and nine-stage ring oscillators extracted from Spectre RF simulations.(b)Power spectrum at the divide-by-two output of the nine-stage oscillator.simulations and measurements and show good agreement with a maximum difference of4%.When the control voltages were varied between0.3and1.8V,the measured and the simulated frequency ranges were1.1–1.86GHz and1.16–1.93GHz, respectively.It should be noted that the frequency range of a multiple-pass architecture does not scale linearly with the number of stages.The phase noise values were estimated using SpectreRF simulations and the published techniques that apply to this type of stage design.As illustrated in Fig.4(a),simulations predicted the phasenoiseofthethree-stagedesignas99.5dBc/Hzata1-MHz offset from a5.79-GHz center frequency,whereas the value for the nine-stage design was112.84dBc/Hz at a1-MHz offset from a1.82-GHz center frequency.Simulations also showed that the dividers and buffers have negligible contribution to the output phase noise.Dai’s equation[10]gives the single-sideband phase noise for oscillators with clipped signalsaswhere(2)where is the single-sideband phasenoise,is the excessnoisefactor,is the maximum output slewrate,is theangular frequency offset from the centerfrequencyisFig.5.Maximum frequencies versus minimum channellength.Fig.6.Phase noise versus minimum channel length.the thermalenergy,is the power supply voltage,and is theequivalent output resistance of a delay ing this equation,the phase noise of the three-and nine-stage multiple-pass ringoscillators was calculated to be95.05dBc/Hz and120.99dBc/Hz,respectively,at the same offset and center frequenciesas given in the simulation results.The large difference for thenine-stage design is accounted to the additional noise sourcesbecause of the increase in the number of stages.This couldbe compensated by using a larger excess noisefactor in theequations.Fig.4(b)shows the measured power spectrum at the di-vide-by-two output of the nine-stage design.The phase noiseof the nine-stage design was extracted as105.5dBc/Hz ata1-MHz offset from a1.81-GHz center frequency;this valueaccounts for the bandwidth of the input low-pass filter ofthe spectrum analyzer and the division factor.Supply/grounddisturbances and flicker noise sources,which were ignored inthe calculations and simulations,are considered to be the mainsources of the difference between the measurements and theestimations.In an effort to compare the oscillators’performance,twoscatter plots were created using designs published in the openliterature.Fig.5shows the maximum oscillator frequency asa function of the minimum CMOS feature size,and Fig.6provides information on the phase noise.The points weremeasured,calculated/simulated,or taken from the referencedpapers.To provide consistency in the comparison,phase noisedata from the papers were scaled to a1-MHz offset from thecenter frequencies with an assumed 20-dB/decade drop.The maximum frequency values for circuits with the present design were obtained from Spectre/HSPICE simulations,with the exception of the measured values cited for the0.18-m points.The simulation results showed that the three-stage circuit is capable of oscillation frequencies up to 4.5and 12GHz in0.25-m and0.13-m processes,respectively.IV .C ONCLUSIONWe have demonstrated the use of a multiple-pass loop ring oscillator architecture with latching saturated gain stages as a technique for achieving high-frequency CMOS VCO circuits.The performance curves show that the design can be extrapo-lated to other processes with good results.The attractive fea-tures of this approach are the simplicity of the design and the fact that rings can be implemented in any CMOS process.The results of this study suggest that it is not always necessary to resort to integrated LC networks for high-frequency VCO/CCO modules,but that simpler ring designs may suffice.A CKNOWLEDGMENTThe authors would like to thank B.Butka,D.McDonagh,P.Murtagh,and P.Platt of the IDT Atlanta Design Center for their help in the design and testing,and B.Terlemez of Georgia Tech for his contributions to the chip project.R EFERENCES[1] B.Razavi,“A study of phase noise in CMOS oscillators,”IEEE J.Solid-State Circuits ,vol.31,pp.331–343,Mar.1996.[2]L.Sun,T.Kwasniewski,and K.Iniewski,“A quadrature output voltagecontrolled ring oscillator based on three-stage subfeedback loops,”in Proc.Int.Symp.Circuits and Systems ,vol.2,Orlando,FL,1999,pp.176–179.[3]Y .Sugimoto and T.Ueno,“The design of a 1V ,1GHz CMOS VCOcircuit with in-phase and quadrature-phase outputs,”in Proc.Int.Symp.Circuits and Systems ,vol.1,Hong Kong,1997,pp.269–272.[4] D.-Y .Jeong,S.-H.Chai,W.-C.Song,and G.-H.Cho,“CMOS cur-rent-controlled oscillators using multiple-feedback loop architectures,”in IEEE Int.Solid-State Circuits Conf.Dig.Tech.Papers ,1997,pp.386–387.[5] C.H.Park and B.Kim,“A low-noise,900-MHz VCO in 0.6- mCMOS,”IEEE J.Solid-State Circuits ,vol.34,pp.586–591,May 1999.[6]S.-J.Lee, B.Kim,and K.Lee,“A novel high-speed ring oscil-lator for multiphase clock generation using negative skewed-delay scheme,”IEEE J.Solid-State Circuits ,vol.32,pp.289–291,Feb.1997.[7]J.Maneatis and M.Horowitz,“Precise delay generation using coupledtransistors,”IEEE J.Solid-State Circuits ,vol.28,pp.1273–1282,Dec.1993.[8],“Multiple interconnected ring oscillator circuit,”U.S.Patent 5,475,344,Dec.12,1995.[9]I.-C.Hwang and S.-M.Kang,“A self regulating VCO with supply sen-sitivity of <0.15%-delay/1%-supply,”in IEEE Int.Solid-State Circuits Conf.Dig.Tech.Papers ,2002,pp.140–141.[10]L.Dai and R.Harjani,“Design of low-phase-noise CMOS ring-oscilla-tors,”IEEE Trans.Circuits Syst.II ,vol.49,pp.328–338,May 2002.。
整理翻译
channel-length modulation 沟道效应
phase-locked loop 锁相环 phase/frequency detector 鉴相鉴频器
guard ring 保护环 switched-capacitor开关电容
negative 负的 positive 正的 frequency characteristics频率特性
sub-harmonic 分频谐波，次谐波 in series with串联
equivalent resistor value等价电阻值 biased偏压
phase margin 相位裕度 pinch-off behavior夹断特性 pole 极点 node结点
dominant poles 主极点 inant poles 非主极点 power spectral density
功率谱密度 power supply rejection 电源抑制
current mode control 电流模式控制
slope compensation斜率补偿 signal flow graph信号流图
fixed frequency固定频率
trailing edge modulation 后延调变（下降边）
feedforwards term 前馈控制（正反馈控制）
back-end processing 后端工艺 ringing 减幅震荡 ripple波纹
second-order effects 二级效应 shadowing 阴影 sheet resistance 薄层电阻 silicide 硅化物 skew偏移 slew rate 转换速率 spacers 隔离墙
环型振荡器(ring oscillator)的抖动(jitter)分析
Jitter and Phase Noise in Ring Oscillators Ali Hajimiri,Sotirios Limotyrakis,and Thomas H.Lee,Member,IEEEAbstract—A companion analysis of clock jitter and phase noise of single-ended and differential ring oscillators is presented.The impulse sensitivity functions are used to derive expressions for the jitter and phase noise of ring oscillators.The effect of the number of stages,power dissipation,frequency of oscillation,and short-channel effects on the jitter and phase noise of ring oscillators is analyzed.Jitter and phase noise due to substrate and supply noise is discussed,and the effect of symmetry on the upconversion of 1/f noise is demonstrated.Several new design insights are given for low jitter/phase-noise design.Good agreement between theory and measurements is observed.Index Terms—Design methodology,jitter,noise measurement, oscillator noise,oscillator stability,phase jitter,phase-locked loops,phase noise,ring oscillators,voltage-controlled oscillators.I.I NTRODUCTIOND UE to their integrated nature,ring oscillators have be-come an essential building block in many digital and communication systems.They are used as voltage-controlled oscillators(VCO’s)in applications such as clock recovery circuits for serial data communications[1]–[4],disk-drive read channels[5],[6],on-chip clock distribution[7]–[10],and integrated frequency synthesizers[10],[11].Although they have not found many applications in radio frequency(RF), they can be used for some low-tier RF systems. Recently,there has been some work on modeling jitter and phase noise in ring oscillators.References[12]and[13] develop models for the clock jitter based on time-domain treatments for MOS and bipolar differential ring oscillators, respectively.Reference[14]proposes a frequency-domain approach tofind the phase noise based on an linear time-invariant model for differential ring oscillators with a small number of stages.In this paper,we develop a parallel treatment of frequency-domain phase noise[15]and time-domain clock jitter for ring oscillators.We apply the phase-noise model presented in[16] to obtain general expressions for jitter and phase noise of the ring oscillators.The next section briefly reviews the phase-noise model presented in[16].In Section III,we apply the model to timing jitter and develop an expression for the timing jitter of oscilla-tors,while Section IV provides the derivation of a closed-form expression to calculate the rms value of the impulse sensitivity function(ISF).Section V introduces expressions for jitter and phase noise in single-ended and differential ring oscillators Manuscript received April8,1998;revised November2,1998.A.Hajimiri is with the California Institute of Technology,Pasadena,CA 91125USA.S.Limotyrakis and T.H.Lee are with the Center for Integrated Systems, Stanford University,Stanford,CA94305USA.Publisher Item Identifier S0018-9200(99)04200-6.in long-and short-channel regimes of operation.Section VI describes the effect of substrate and supply noise as well as the noise due to the tail-current source in differential struc-tures.Section VII explains the design insights obtained from this treatment for low jitter/phase-noise design.Section VIII summarizes the measurement results.II.P HASE N OISEThe output of a practical oscillator can be writtenasis periodic in2modelfluctuations in amplitude and phase due to internal and external noise sources.The amplitudefluctuations are significantly attenuated by the amplitude limiting mechanism, which is present in any practical stable oscillator and is particularly strong in ring oscillators.Therefore,we will focus on phase variations,which are not quenched by such a restoring mechanism.As an example,consider the single-ended ring oscillator with a single current source on one of the nodes shown in Fig.1.Suppose that the current source consists of an impulse of current withareais proportional to the injectedcharge(3)where is the voltage swing across the capacitorandthus represents the sensitivity of every point of the waveform to aperturbation,Fig.1.Five-stage inverter-chain ring oscillator.Being interested in its phase(4)where is a unit step.Knowing the response to an impulse,we can calculatewhere represents the noise current injected into the node of interest.Note that the integration arises from the closed-loop nature of the oscillator.The single-sideband phase-noise spectrum due to a white-noise current source is given by[16]1(6)where is the single-sideband power spectral density of the noise current source,and is the frequency offset from the carrier.In the caseof multiple noise sources injecting into the samenode,noise sourcesistimes for a differential ringoscillator).From(5),it follows that the upconversion of low-frequencynoise,such as1(7)where is the dc value of the ISF.Since the height of thepositive and negative lobes of the ISF is determined by theslope of the rising and falling edges of the output waveform,respectively,symmetry of the rising and falling edges canreduce and hence the upconversion of1whereis the variance of the uncertainty introduced by one stageduring one transition.Notingthatis a proportionality constant determined by circuitparameters.Another instructive special case that is not usually consid-ered is when the noise sources are totally correlated with oneanother.Substrate and supply noise are examples of such noisesources.Low-frequency noise sources,such as1is another proportionality constant.Noise sourcessuch as thermal noise of devices are usually modeled asuncorrelated,while substrate and supply-noise sources,aswell as low-frequency noise,are approximated as partiallyor fully correlated sources.In practice,both correlated anduncorrelated sources exist in a circuit,and hence a log–logplot of the timingjitterIn most digital applications,it is desirable foror wherecalculated to bebecomeslarger,since each transition occupies a smaller fraction of theperiod.Based on these observations,we approximate the ISFas triangular in shape and with symmetric rising and fallingedges,as shown in Fig.6.The case of nonsymmetric risingand falling edges is considered in Appendix B.The ISF has a maximum of1where is themaximum slope of the normalized waveform,and hence theslopes of the sides of the triangles areFig.8.RMS values of the ISF’s for various single-ended ring oscillators versus number of stages.On the other hand,stage delay is proportional to the risetime(14)whereis a proportion-ality constant,which is typically close to one,as can be seen in Fig.7.The period is2(16)Note that the1dependenceofbecause the effect of variations in other parameters,suchas,and thus the ISF is a unitless,frequency-andamplitude-independent function.Equation (16)is valid for differential ring oscillators as well,since in its derivation no assumption specific to single-ended oscillators was made.Fig.9showsthechanges.Members of thesecond set of oscillators have a fixed total power dissipation and fixed load resistors,which result in variable swings and for whom data are shown with circles.The third case is that of a fixed tail current for each stage and constant load resistors,whose data are illustrated using crosses.Again,in spite of the diverse variations of the frequency and othercircuit parameters,the1dependencyof This is shown with the solid line in Fig.9.A similar resultcan be obtained for bipolar differential ring oscillators.AlthoughFig.9.RMS values of the ISF’s for various differential ring oscillators versus number of stages.V.E XPRESSIONS FOR J ITTER AND P HASE N OISE IN R ING O SCILLATORSIn this section,we derive expressions for the phase noise and jitter of different types of ring oscillators.Throughout this section,we assume that the symmetry criteria required tominimize(and hence the upconversion of1(17)whereis the zero-bias drain sourceconductance,is the gate-oxide capacitance per unitarea,is 2/3for long-channel devices in the saturationregion and typically two to three times greater for short-channel devices [18].Equation (17)is valid in both short-and long-channel regimes as long as an appropriate valueforis givenby(18)where-stage single-ended ringoscillator,the power dissipation associated with this processis(22)whereis the delay of each stage and and are the rise and fall time,respectively,associated with the maximum slope during a transition.Assuming that the thermal noise sources of the different devices are uncorrelated,and assuming that the waveforms (and hence the ISF)of all the nodes are the same except for a phase shift,the total phase noise due toall(23)is the characteristic voltage of the device.Forlong-channel mode of operation,it is definedas(25)increases,leading to no net dependence of phase noiseon,since there is not a strongdependence on the number of stages for single-ended CMOSring oscillators.Note that(25)and(26)establish the lowerbound and therefore should not be used to calculate the phasenoise and jitter of an arbitrary oscillator,for which(6)and(12)should be used,respectively.We may carry out a similar calculation for the short-channelcase.For such devices,the drain current may be expressedasis the number ofstages,is the tail bias currentof the differential pair,and(32)Surprisingly,tail-current source noise in the vicinityofnoise sources is2degrading as the number of stages increases for a given fre-quency and power dissipation.This result may be understoodas a consequence of the necessary reduction in the chargeswing that is required to accommodate a constant frequencyof oscillation at afixed power level asi.e.,th Fourier coefficient of the ISF.Equation(38)means that for identical sources,only noise in the vicinity ofinteger multiples of affects the phase.To verify this effect,sinusoidal currents with an amplitudeof1020dB/dec slope.The effect of injection in the vicinityof harmonics that are not integer multiples of;however,as can be seenin Fig.11,there is some sideband power due to the amplituderesponse.Low-frequency noise can also result in correlation betweenuncertainties introduced during different cycles,as its valuedoes not change significantly over a small number of periods.Therefore,the uncertainties add up in amplitude rather than power,resulting in a region with a slope of one in the log–log plot of jitter even in the absence of external noise sources such as substrate and supply noise.VII.D ESIGN I MPLICATIONSOne can use (23)and (34)to compare the phase-noise performance of single-ended and differential MOS ring os-cillators.As can be seenforfor a regular ring oscillator is three,even a properly designed differential CMOS ring oscillator underperforms its single-ended counterpart,especially for a larger number of stages.This difference is even more pronounced if proper precautions to reduce the noise of the tail current are not taken.However,the differential ring oscillator may still be preferred in IC’s because of the lower sensitivity to substrate and supply noise,as well as lower noise injection into other circuits on the same chip.The decision to use differential versus single-ended ring oscillators should be based on both of these considerations.The common-mode sensitivity problem in a single-ended ring oscillator can be mitigated to some extent by using two identical ring oscillators laid out close to each other that oscillate out of phase because of small coupling inverters [19].Single-ended configurations may be used in a less noisy environment to achieve better phase-noise performance for a given power dissipation.As shown in Appendix B,asymmetry of the rising and falling edges degrades phase noise and jitter by increasingthe1corner frequency.Thus,every effort should be taken to make the rising and falling edges symmetric.By properly adjusting the symmetry properties,one can suppress or even eliminate low-frequency-noise upconversion [16].As shown in [16],differential symmetry is insufficient,and the symmetry of each half circuit is important.One practical method to achieve this symmetry is to use more linear loads,such as resistors or linearized MOS devices.This method reduces the1increases.Hence for aprocess with large1will reduce the jitter.In general,the choice of the number of stages must be made on the basis of several design criteria,such as1Second,in a ringoscillator,the device noise is maximum during the transitions,which is the time where the sensitivity,and hence the ISF,is the largest [16].VIII.E XPERIMENTAL R ESULTSThe phase-noise measurements in this section were per-formed using three different systems:an HP 8563E spectrum analyzer with phase-noise measurement capability,an RDL NTS-1000A phase-noise measurement system,and an HP E5500phase-noise measurement system.The jitter measure-ments were performed using a Tektronix CSA 803A commu-nication signal analyzer.Tables I–III summarize the phase-noise measurements.All the reported phase-noise values are at a 1-MHz offset from the carrier,chosen to achieve the largest dynamic range in the measurement.Table I shows the measurement results for three different inverter-chain ring oscillators.These oscillators are made of the CMOS inverters shown in Fig.12(a),with no frequency tuning mechanism.The output is taken from one node of the ring through a few stages of tapered inverters.Oscillators number 1and 2are fabricated in a2-mTABLE II NVERTER -C HAIN R ING OSCILLATORSTABLE IIC URRENT -S TARVED I NVERTER -C HAIN R ING OSCILLATORSAs an illustrative example,we will show the details of phase-noise calculations for oscillator number ing (16)tocalculatethe phase noise can be obtained from (6).We calculate the noise power when the stage is halfway through a transition.At this point,the drain current is simulated to be3.47mA.An10of 2.5is used in (28)to obtain a noise poweroffC.There is one such noise source oneach node;therefore,the phase noiseisdBc/Hz.Table II summarizes the data obtained for current-starved ring oscillators with the cell structure shown in Fig.12(b),all implemented in the same0.25-).Table III summarizes the results obtained for differential ring oscillators of various sizes and lengths with the inverter topology shown in Fig.12(c),covering a large span of frequen-cies up to 5.5GHz.All these ring oscillators are implemented in the same0.25-TABLE IIID IFFERENTIAL R ING OSCILLATORS(a)(b)(c)Fig.12.Inverter stages for (a)inverter-chain ring oscillators,(b)current-starved inverter-chain ring oscillators,and (c)differential ring oscillators.calculations for oscillator number 12.The noise current due to one of differential pair NMOS devices is given by (28).The total capacitance on each node in the balanced caseisfF,and the simulated voltage swing is 1.208V;therefore,mA,and thereforethe noise current of the NMOS device has a single-sideband spectral densityofstages,there is one such noise source on each node;therefore,the phase noise is2of 0.9,(34)predicts a phase noiseofMHzdBc/HzFig.13.Die photograph of the current-starved single-endedoscillators.Fig.14.Die photograph of the 12-stage differential ringoscillator.Fig.15.Timing jitter measurement setup using CSA803A.distinguished from the device under test (DUT)’s jitter.This extra jitter can be directly measured by looking at the jitter on the triggering edge.This edge can be readily identified since it has lower rms jitter than the transitions before and after it.The effect of this excess jitter should be subtracted from the jitter due to the DUT.Assuming no correlation between the jitter of the DUT and the sampling head,the equivalent jitter due to the DUT can be estimatedby(39)whereis the measured rms jitter at adelayis the jitter on the triggering edge.Fig.16shows the rms jitter versus the measurement delay for oscillator number 12on a log–log plot.The bestfitFig.16.RMS jitter versus measurement interval for the four-stage,2.8-GHz differential ring oscillator(oscillator number12).Fig.17.Phase noise versus symmetry voltage for oscillator number7.(41)ThereforeAnalog and digital designers prefer using phase noise and timing jitter,respectively.The relationship between these two parameters can be obtained by noting that timing jitter is the standard deviation of the timinguncertainty(45)where represents the expected value.Since the autocor-relation functionof(46)the timing jitter in(45)can be writtenas(47)The relation between the autocorrelation and the power spec-trum is given by the Khinchin theorem[21],i.e.,can be expressed in terms of phase noise in the1regionas(50)where(52)whereandrepresents the asymmetryof the waveform and is definedas(54)Combining(52)and(54)results in thefollowing:can be calculated from Fig.18in a similar manner andis givenby,and the1corner approaches zero.A CKNOWLEDGMENTThe authors would like to thank M.A.Horowitz,G.Nasser-bakht,A.Ong,C.K.Yang,B.A.Wooley,and M.Zargari for helpful discussions and support.They would further like to thank Texas Instruments,Inc.,and Stanford Nano-Fabrication facilities for fabrication of the oscillators.R EFERENCES[1]L.DeVito,J.Newton,R.Croughwell,J.Bulzacchelli,and F.Benkley,“A52and155MHz clock-recovery PLL,”in ISSCC Dig.Tech.Papers, Feb.1991,pp.142–143.[2] A.W.Buchwald,K.W.Martin,A.K.Oki,and K.W.Kobayashi,“A6-GHz integrated phase-locked loop using AlCaAs/Ga/As heterojunction bipolar transistors,”IEEE J.Solid-State Circuits,vol.27,pp.1752–1762, Dec.1992.[3] i and R.C.Walker,“A monolithic622Mb/s clock extraction dataretiming circuit,”in ISSCC Dig.Tech.Papers,Feb.1993,pp.144–144.[4]R.Farjad-Rad,C.K.Yang,M.Horowitz,and T.H.Lee,“A0.4mmCMOS10Gb/s4-PAM pre-emphasis serial link transmitter,”in Symp.VLSI Circuits Dig.Tech Papers,June1998,pp.198–199.[5]W.D.Llewellyn,M.M.H.Wong,G.W.Tietz,and P.A.Tucci,“A33Mbi/s data synchronizing phase-locked loop circuit,”in ISSCC Dig.Tech.Papers,Feb.1988,pp.12–13.[6]M.Negahban,R.Behrasi,G.Tsang,H.Abouhossein,and G.Bouchaya,“A two-chip CMOS read channel for hard-disk drives,”in ISSCC Dig.Tech.Papers,Feb.1993,pp.216–217.[7]M.G.Johnson and E.L.Hudson,“A variable delay line PLL for CPU-coprocessor synchronization,”IEEE J.Solid-State Circuits,vol.23,pp.1218–1223,Oct.1988.[8]I.A.Young,J.K.Greason,and K.L.Wong,“A PLL clock generatorwith5–110MHz of lock range for microprocessors,”IEEE J.Solid-State Circuits,vol.27,pp.1599–1607,Nov.1992.[9]J.Alvarez,H.Sanchez,G.Gerosa,and R.Countryman,“A wide-bandwidth low-voltage PLL for PowerPC TM microprocessors,”IEEE J.Solid-State Circuits,vol.30,pp.383–391,Apr.1995.[10]I.A.Young,J.K.Greason,J.E.Smith,and K.L.Wong,“A PLL clockgenerator with5–110MHz lock range for microprocessors,”in ISSCC Dig.Tech.Papers,Feb.1992,pp.50–51.[11]M.Horowitz,A.Chen,J.Cobrunson,J.Gasbarro,T.Lee,W.Leung,W.Richardson,T.Thrush,and Y.Fujii,“PLL design for a500Mb/s interface,”in ISSCC Dig.Tech.Papers,Feb.1993,pp.160–161. [12]T.C.Weigandt,B.Kim,and P.R.Gray,“Analysis of timing jitter inCMOS ring oscillators,”in Proc.ISCAS,June1994.[13]J.McNeill,“Jitter in ring oscillators,”IEEE J.Solid-State Circuits,vol.32,pp.870–879,June1997.[14] B.Razavi,“A study of phase noise in CMOS oscillators,”IEEE J.Solid-State Circuits,vol.31,pp.331–343,Mar.1996.[15] A.Hajimiri,S.Limotyrakis,and T.H.Lee,“Phase noise in multi-gigahertz CMOS ring oscillators,”in Proc.Custom Integrated Circuits Conf.,May1998,pp.49–52.[16] A.Hajimiri and T.H.Lee,“A general theory of phase noise in electricaloscillators,”IEEE J.Solid-State Circuits,vol.33,pp.179–194,Feb.1998.[17],The Design of Low Noise Oscillators.Boston,MA:KluwerAcademic,1999.[18] A.A.Abidi,“High-frequency noise measurements of FET’s with smalldimensions,”IEEE Trans.Electron Devices,vol.ED-33,pp.1801–1805, Nov.1986.[19]T.Kwasniewski,M.Abou-Seido,A.Bouchet,F.Gaussorgues,and J.Zimmerman,“Inductorless oscillator design for personal communica-tions devices—A1.2 m CMOS process case study,”in Proc.CICC, May1995,pp.327–330.[20]J.G.Maneatis and M.A.Horowitz,“Precise delay generation using cou-pled oscillators,”IEEE J.Solid-State Circuits,vol.28,pp.1273–1282, Dec.1993.[21]W. A.Gardner,Introduction to Random Processes.New York:McGraw-Hill,1990.[22]W.F.Egan,Frequency Synthesis by Phase Lock.New York:Wiley,1981.Ali Hajimiri received the B.S.degree in electronicsengineering from Sharif University of Technology,Tehran,Iran,in1994and the M.S.and Ph.D.degrees in electrical engineering from Stanford Uni-versity,Stanford,CA,in1996and1998,respec-tively.He was a Design Engineer with Philips,wherehe worked on a BiCMOS chipset for GSM cellularunits from1993to1994.During the summer of1995,he was with Sun Microsystems,where heworked on the UltraSparc microprocessor’s cache RAM design methodology.During the summer of1997,he was with Lucent Technologies(Bell Labs),where he investigated low-phase-noise integrated oscillators.In1998,he joined the Faculty of the California Institute of Technology,Pasadena,as an Assistant Professor.His research interests are high-speed and RF integrated circuits.He is coauthor of The Design of Low Noise Oscillators(Boston,MA:Kluwer Academic,1999).Dr.Hajimiri was the Bronze Medal Winner of the21st International Physics Olympiad,Groningen,the Netherlands.He was a corecipient of the International Solid-State Circuits Conference1998Jack Kilby Outstanding PaperAward.Sotirios Limotyrakis was born in Athens,Greece,in1971.He received the B.S.degree in electricalengineering from the National Technical Universityof Athens in1995and the M.S.degree in electri-cal engineering from Stanford University,Stanford,CA,in1997,where he currently is pursuing thePh.D.degree.In the summer of1993,he was with K.D.D.Corp.,Saitama R&D Labs,Japan,where he workedon the design of communication protocols.Duringthe summers of1996and1997,he was with the Texas Instruments Inc.R&D Center,Dallas,TX,where he focused on LNA,low-phase-noise oscillator design,and GSM mobile unit transmit path architectures.His current research interests include the design of mixed-signal circuits for high-speed data conversion and broad-band communications. Mr.Limotyrakis received the W.Burgess Dempster Memorial Fellowship from the School of Engineering,Stanford University,in1995.Thomas H.Lee(S’87–M’87),for a photograph and biography,see p.585of the May1999issue of this J OURNAL.。
VCO Oscillator Design
General amplitude control
•One thought is to detect oscillator amplitude, and then adjust Gm so that it equals a desired value •By using feedback, we can precisely achieve GmRp = 1 •Issues •Complex, requires power, and adds noise
• As input amplitude is increased
– Effective gain from input to fundamental of output drops – Amplitude feedback occurs! (GmRp = 1 in steady-state)
5
Negative-Resistance Model
Z βVout
At resonance:
LCs = − 1
2
G m G m R P Ls = = Gm RP Y Ls 1 s≈− ± 2 RP C 1 LC 10
One zero at s=0
Two poles at:
Closed loop root locus as Gm changes
•
•
Root locus plot allows us to view closed loop pole locations as a function of open loop poles/zero and open loop gain (GmRp) As gain (GmRp) increases, closed loop poles move into 11 right half S-plane
Oscillator
Locking area
V inj V0
0.1 0.12 0.14 0.16 0.18 0.2
If NOT locked Large amplitude variations (periodic beat notes)
December 10, 2004 Slide 5
Amplitude Variations (unlocked driven oscillator)
Proof: linear models (LTI/LTV) cannot capture injection locking
December 10, 2004 Slide 9
Nonlinear phase macromodel (PPV)
Nonlinear scalar differential equation
0
-0.005
-0.01 -1
-0.5
0
0.5
1
Voltage >
December 10, 2004 Slide 16
LC osc: Max locking range vs injection strength Nonlinear
0.15
宽调谐范围CMOS压控振荡器(IJEM-V7-N5-3)
I.J. Engineering and Manufacturing, 2017, 5, 31-38Published Online September 2017 in MECS ()DOI: 10.5815/ijem.2017.05.03Available online at /ijemWide Tuning Range CMOS VCOAbhishek Kumar a*and Kriti Tiwari ba Assistant Professor, Lovely Professional University, Punjab, Indiab Student, Lovely Professional University, Punjab, IndiaReceived: 14 January 2017; Accepted: 13 May 2017; Published: 08 September 2017AbstractA communication system requires a highly stabilized frequency; LC and RC oscillator are two wide option for frequency generation. Performance of an LC oscillator suffers from leakage, area, noise etc compare RC oscillator. Voltage controlled oscillator (VCO) is preferred category if RC oscillator to generate high oscillator frequency. VCO contains odd number of delay stage cascaded together; output frequency strongly depends on switching threshold of individual stages. A 3 stage current starved VCO can generate upto 0.6 Ghz; this work is focused around body bias technique to increase frequency without increasing number of delay stage. Oscillation frequency has been controlled by bulk terminal of PMOS and NMOS individually and by means of adaptive body bias network. Cadence spectre based simulation result at CMOS 90nm shows that by reverse biasing of PMOS obtained frequency is 1.2GHz-10.01GHz with tuning range of 95% while biasing of NMOS generate frequency of 500MHz- 12.5GHz with tuning range capability of 96%. This design presents high frequency with wider tuning range and optimum reduced power by which this oscillator design can be used in different band of communication.Index Terms: Ring oscillators, Voltage-controlled oscillators, Frequency, Phase noise, Tuning, Bandwidth.© 2017 Published by MECS Publisher. Selection and/or peer review under responsibility of the Research Association of Modern Education and Computer Science.1.IntroductionVoltage controlled oscillator is commonly investigated as it is a crucial circuit of phase locked loop (PLL), clock and data recovery circuits (CDR), Radio Frequency application. Ring oscillator is the primary component of VCO; a cascade combination of delay stages connected as closed loop. In satellite / microwave communication clock data recovery unit at receiver restore the clock from received data with the help of PLL [1, 2]. Ring oscillator is the heart of VCO it generates oscillating frequency in specific band (up to 30 GHz). In * Corresponding author. Tel.: 9888431215E-mail address: abhishek.15393@lpu.co.inthis work current starved topology has been consider as basic element for delay calculation [14]; it limits the current to the inverter for charging and discharging of load there by controlling the stage delay and oscillation frequency. Current starved ring oscillator can generate frequency 4 GHz applicable for L, S and C-band. In this work frequency range tried improve up to 12.5 GHz for K-band application using body biasing technique. Body biasing of MOS effectively alter the threshold voltage it significantly improves the delay stage result in high frequency.A current starved topology shown in Fig1, it is observed that MOSFETs M2 and M3 operate as an inverter, while MOSFETs M1 and M4 operate as current sources. The main control on the inverter chain is of V inVCO to modify the current that flow from the N1 and P1. The current from these transistors due to direct connection of M5 with M1 along with following transistor and M6 with M4 followed by transistor in series mirror the current in each. Change in the control voltage induces by change in inverter current. V inVCO modulates the turn on resistance of pull down transistor M1 and through the current mirror, the pull-up transistor M6 [3-7]. Large value of V inVCO allows a large current to flow, producing a small resistance and a small delay. Cadence Spetre based simulation justify that a current starved ring oscillator can produce frequency 626 MHz at Vdd 1V.Fig.1. Current Starved Ring Oscillator [8, 9]Oscillator’s frequency primarily depends in threshold voltage of MOS; body biasing is one of technique through which threshold voltage of particular MOS can be varied; usually PMOS body terminal should connect to maximum supply and NMOS body to minimum ground; but additional voltage at body terminal vary the threshold voltage by eqn (1). Threshold voltage of MOS increases by reverse biasing and decrease with forward biasing [1, 2, 11]. Effect of body voltage over represented by , γ is body bias factor, Vth decrease for higher V SB and decreases for lower V SB .0Th T V V γ=+1.1. Organization of paperThe second section of the paper elaborate current starve ring oscillator with PMOS and NMOS body bias individually and their effect over frequency and other parameter explored. Section-3 of the paper incorporates conclusion and possible future work.2. Current Starve VCO with Body BiasA ring oscillator frequency can enhance by an additional supply at body terminal, reverse biasing bodyreduces Vth in case of PMOS and increase in case of Vth. Variation in Vth configure delay of MOS, in this section effect of reverse bias over frequency has been explored.2.1.Current Starve Ring Oscillator with PMOS Body BiasingFig2 shows a 3 Stage current starved topology of ring oscillator. In the presented VCO, substrates of PMOS have been connected to dc supply which is kept at optimum value 0.5V, Vctrl is varied in the range of 0 to1V, and Simulations have been carried out using cadence spectre based on CMOS 90nm technology at supply 1V. PMOS reverse body bias increase threshold voltage and leads to high oscillation frequency. Positive bulk terminal input reduced sub threshold leakage current and minimizes the power dissipation [8, 9, 10].Fig.2. Current Starved Ring Oscillator with PMOS Body BiasingOn current increases with increasing body voltage increases upto V SB=0.5 V. Further increase in the body voltage decrease the value of drain current (I DS). Fig3 shows variation of frequency w.r.t Vctrl keeping body voltage at optimum value 0.5V. Current starve VCO with PMOS Body Biasing voltage can achieve maximum frequency oscillation frequency 1.2 to 11GHz while Vctrl ranges from 0-1V at body voltage V SB 0.5V. Power consumption of the above circuit is 30uw.Fig.3. Frequency Variation with Vctrl at Body Voltage 0.5V2.2.Current Starve Ring Oscillator with NMOS Body BiasingFig4 present a 3 Stage current starved topology of ring oscillator with substrates of NMOS have been connected to dc supply which is kept at optimum value 0.5V, Vctrl is varied in the range of 0-1V. NMOS substrate bias technique with VCO enhance the oscillation frequency [12, 13]. A positive voltage at the body of NMOS, results on reduction in threshold voltage which leads to high power consumption of the circuit. So it is desirable to choose the optimum value of Vctrl.Fig.4. Current Starved ring oscillator with PMOS body biasingIncreasing the body voltage there is increase in the On current up to V SB=0.5 V; further increase in the body voltage decrease the value of I DS. Fig5 shows variation of frequency w.r.t Vctrl keeping body voltage at optimum value 0.5V. Current starve VCO with PMOS Body bias increases frequency proportionally 0.5 to 12.5GHz with control voltage ranges from 0 to 1V. Power consumption of NMOS body biased current starve VCO is drastically increases with increases in oscillation frequency. For frequency 12.5GHz power consumption increases up to 250uW.Fig.5. Frequency Variation with Vctrl at body voltage 0.5V2.3.Adaptive Body Bias Ring OscillatorsAdaptive Body Biasing Ring oscillator is the technique of utilizing the transistor body effect to change transistor threshold voltage during operation by applying adaptive body bias either in forward bias or reverse bias. In this design different body voltages at different Instant of time can be applied which targets to overall wider tuning range of circuit with high frequency along with optimum power saving and phase noise. A fine orwider tuning range of frequency is major achievement of this work. The bulk terminal of the oscillator is controlled appropriately depending on the required specifications of the circuit. Objective of adaptive body biasing is to maintain the transistor threshold voltage to retain the device performance by applying either forward body biasing or reverse body biasing. Fig6 presents a current starve ring oscillator with adaptive body bias (ABB) network, ABB can be implemented using multiplexer, select lines S0 and S1; it generates a dc output voltage which bias the body of MOS devices in oscillator circuit. Output obtained from ABB circuit is mentioned in table1. The output voltage level obtained from this circuit maintains bulk of MOS more positive or more negative. The performance of the oscillator is maintained in terms of current driving capability by applying either forward adaptive body biasing or reverse adaptive body biasing. Table1 presents 4 different voltage levels generated by ABB circuit; Oscillation frequency (12.54 to 12.62GHz) is unaffected from ABB network. Power consumption greatly decreased from 749uw to 197uw while bulk supply ranges from 0.745V to 66.4uV attainable amplitude of the designed ring oscillator’s frequency is 0. 935V for 1V supply voltage.Fig.6. Ring Oscillator with PMOS and NMOS Bulk Connected to Adaptive Body BiasTable.1. ABB Ring Oscillator at Different Input LevelS0 S1 VoltageLevel (v)Frequency (GHz) Power (uW) Phase Noise (dB/Hz) 0 0 0.74512.62 74.9 -58.1 0 1 0.512.56 132 -58.11 1 0 0.2412.59 112 -58.11 1166.4u 12.54 197 -58.11 Oscillation frequency can further enhance by varying width of transistor, dimensions of transistor depend upon the design speciation of the oscillator, the width of inverter transistors (M4, M10, M14 at 30um) (M1, M7, M11 at 10um) (M2, M8, M12 at 120nm) (M3, M9, M13 at 240nm) the highest possible frequency achievable from this circuit is 13.7 GHz. Fig7 shows the variation in the frequency of the oscillator with width of transistor.This range of frequency lies to Ku band (Kurtz-Under band) primary used for satellite communication focuses on editing and broadcasting the frequency range of this band lies in 12GHz to18 GHz. Variation in the Channel length results in drastic reduction in frequency by increasing the value of length, so it is advisable to avoid variations with length of MOS. Adaptive body bias circuit with 3 stage current starved ring oscillator present phase noise -58.11db/Hz. Further improvement in phase noise is possible by varying width of MOS. Phase noise varies exponentially with respect to W ratio shown in fig8 with increase in W ratio of transistor, phase noise effect is better which is always desirable.Fig7. Variation of Frequency with respect to W/L Ratio of ABB Ring OscillatorFig.8. Phase Noise of ABB CS oscillator vs W/L ratioTable.2. Comparative study of Ring Oscillator with Body BiasWithout Bias PMOSReverse Bias NMOS Reverse Bias Adaptive Bias Without BiasPMOS Reverse Bias NMOS Reverse Bias Adaptive Bias [7]CMOS180nm Ring 0.958 G - 4.46G 0.226 u-94.51[13]CMOS45nm Ring 5.33 G3.8 G4.76 G 2.68 u5.68 u 12.03 n [15]CMOS45nm Ring 5.63 G10.15 u -6400This Work CMOS90nm Current Starve 0.626 G 0.5 G - 10.1 G 0.5 G - 12.5 G 10.063G - 10.066 G 490 u 30u 250 u 2.21 m -60Reference Process Type Operating Frequency with body boas 0.5vPower Phase Noise (dB/Hz)3.ConclusionA Body biasing is alternative method to increase the oscillation frequency of ring oscillator. A 3 stage current starve VCO without body bias can have oscillation frequency only 626MHz suitable for L-band application; reverse biasing the PMOS bulk terminal can achieve the oscillation frequency is 500MHz-10.01GHz for control voltage 0-1V while NMOS biasing the achieved results are 500MHz-12.5GHz suitable for Ku band application. Table2 summarized the performance of ring oscillator with either PMOS or NMOS bulk terminal are reverse biased. Adaptive body bias network provides bias voltage for body terminal allow the user to switch reverse bias. PMOS body bias result in less power dissipation compare to NMOS, adaptive bias network yield sustains high oscillation frequency.References[1]Behazd Razavi, "Design of analog cmos integrated ciruit", July 2000.[2]Eitenne sicard, Sonia Delmas “Advanced CMOS cell Design “Tata McGraw Hill Professional, 2007[3]P. M. Farahabadi, H. Miar-Naimi, A. Ebrahimzadeh, "A New Solution to Analysis of CMOS RingOscillators", Iranian Journal of Electrical & Electronic Engineering, vol. 5, no. 1, March 2009.[4]J.K.Panigrahi, D.P.A charya, “Performance Analysis and Design of Wideband CMOS Voltage ControlledRing Oscillator”, IEEE 5th International Conference on Industrial and Information Systems Proceedings, pp 234-238, Jul29-Aug 01, 2010.[5]M K Mandal, B C Sarkar,” Ring oscillators: Characteristics and applications” Indian Journal of pure andapplied physics Vol.48,pp136-145,2010.[6]M K Mandal, B C Sarkar, "Ring oscillator: Characteristics and application", Indian journal of pure &applied physics, vol. 48, pp. 136-145, February 2010.[7]As hish Raman and R.K sarin “1P6M 0.18-μn Low Power CMOS Ring Oscillator For Radio FrequencyApplication “International journal of computer Theory and Engineering ,Vol 3,No.6 pp770-774,2011. [8]Sushil Kumar, Gurjt Kumar, "Design and performance of nine stage cmos based ring oscillator",International Journal of VLSI design & Communication Systems (VLSICS), vol. 3, no. 3, June 2012 [9]Sushil Kumar and Dr. Gurjit Kaur, “Design and performance analysis of nine stages CMOS based ringoscillator,” International Journal Of VLSI Design & Communication Systems Vol.3, No.3, 2012.[10]X. Gui, M. M. Green, "Design of CML Ring Oscillators With Low Supply Sensitivity", IEEETransactions on Circuits and Systems I: Regular Papers, vol. 60, no. 7, pp. 1753-1763, July 2013. [11]Abhishek Kuma r. “Effect of Body Biasing Over CMOS Inverter” International Journal of electronics &communication technology, Vol 4, issue 1, pp 369-371, Jan-march 2013.[12]Vandna Sikarwar, Neha Yadav, Shyam Akashe,” Design and analysis of CMOS ring oscillator using 45nm technology” IEEE 3rd International conference on Advance computing, pp1491-1495, 2013[13]Akansha SHRIVASTAVA, Anshul SAXENA, Shyam AKASHE “High performance of low voltagecontrolled ring oscillator with reverse body biasing” Frontier of optoelectronics,Vol.6,Issue3 pp-338-345, 2013[14]Abbas Ramazani, Sadegh Biabani, Gholamreza Hadidi, "CMOS ring oscillator with combined delaystages", International ournal ofelectronics and Communication. (AEU), vol. 68, pp. 515-519, 2014. [15]Kriti Tiwari, Abhishek Kumar. “11 GHz CMOS Ring oscillator” International Conference on Computing,Communication, and Automation”, pp 1280-1283, 2015Authors’ ProfilesAbhishek Kumar pursuing PhD in Electronics and Electrical Engineering from LovelyProfessional University, Punjab, India His area of interest is secured hardware design forrandom number and secret key, additional silicon IC based feature included in cryptographicmodule. He is focused on CMOS circuit design for low power, data converter, memory unitand computational circuit at CMOS 90nm technology.Kriti Tiwari Have completed B.Tech & M.Tech(Electronics & Communication Engg) fromLovely Professional University, Punjab, India. Her research interest includes high frequencyoscillator design with CMOS technology.How to cite this paper: Abhishek Kumar, Kriti Tiwari,"Wide Tuning Range CMOS VCO", International Journal of Engineering and Manufacturing(IJEM), Vol.7, No.5, pp.31-38, 2017.DOI: 10.5815/ijem.2017.05.03。
A general theory of phase noise in electrical oscillators
A General Theory of Phase Noisein Electrical OscillatorsAli Hajimiri,Student Member,IEEE,and Thomas H.Lee,Member,IEEE Abstract—A general model is introduced which is capableof making accurate,quantitative predictions about the phasenoise of different types of electrical oscillators by acknowledgingthe true periodically time-varying nature of all oscillators.Thisnew approach also elucidates several previously unknown designcriteria for reducing close-in phase noise by identifying the mech-anisms by which intrinsic device noise and external noise sourcescontribute to the total phase noise.In particular,it explains thedetails of how1=f noise in a device upconverts into close-inphase noise and identifies methods to suppress this upconversion.The theory also naturally accommodates cyclostationary noisesources,leading to additional important design insights.Themodel reduces to previously available phase noise models asspecial cases.Excellent agreement among theory,simulations,andmeasurements is observed.Index Terms—Jitter,oscillator noise,oscillators,oscillator sta-bility,phase jitter,phase locked loops,phase noise,voltagecontrolled oscillators.I.I NTRODUCTIONT HE recent exponential growth in wireless communicationhas increased the demand for more available channels inmobile communication applications.In turn,this demand hasimposed more stringent requirements on the phase noise oflocal oscillators.Even in the digital world,phase noise in theguise of jitter is important.Clock jitter directly affects timingmargins and hence limits system performance.Phase and frequencyfluctuations have therefore been thesubject of numerous studies[1]–[9].Although many modelshave been developed for different types of oscillators,eachof these models makes restrictive assumptions applicable onlyto a limited class of oscillators.Most of these models arebased on a linear time invariant(LTI)system assumptionand suffer from not considering the complete mechanism bywhich electrical noise sources,such as device noise,becomephase noise.In particular,they take an empirical approach indescribing the upconversion of low frequency noise sources,suchascorner in the phase noise spectrum is smallerthanis the amplitude,0018–9200/98$10.00©1998IEEEFig.1.Typical plot of the phase noise of an oscillator versus offset fromcarrier.is an arbitrary,fixed phase refer-ence.Therefore,the spectrum of an ideal oscillator with norandom fluctuations is a pair of impulsesat.In a practical oscillator,however,the output is more generally givenbyandis aperiodic function with period2andrepresents the single side-band power at a frequency offsetofandis dominated by its phaseportion,,known as phase noise,which we will simplydenoteas.Fig.2.A typical RLC oscillator.The semi-empirical model proposed in [1]–[3],known also as the Leeson–Cutler phase noise model,is based on an LTI assumption for tuned tank oscillators.It predicts the followingbehaviorfor:is an empirical parameter (often called the “deviceexcess noisenumber”),is the absolutetemperature,),andregion can beobtained by applying a transfer function approach as follows.The impedance of a parallel RLC,for,is easily calculated tobeHAJIMIRI AND LEE:GENERAL THEORY OF PHASE NOISE IN ELECTRICAL OSCILLATORS181Fig.3.Phase and amplitude impulse response model.a multiplicativefactor,a priori.One importantreason is that much of the noise in a practical oscillatorarises from periodically varying processes and is thereforecyclostationary.Hence,as mentioned in[3],region of the spectrum can be calculatedasregion is thus easily obtained,the expressionforthecorner of thephase noise is the same asthe(7)whereis the effective series resistance,givenbyare shown in Fig.2.Note that itis still not clear how tocalculateinputs(each associated with one noise source)and two outputsthat are the instantaneous amplitude and excess phase of theoscillator,,as defined by(1).Noise inputs to thissystem are in the form of current sources injecting into circuitnodes and voltage sources in series with circuit branches.Foreach input source,both systems can be viewed as single-input,single-output systems.The time and frequency-domainfluctuationsof can be studied by characterizingthe behavior of two equivalent systems shown in Fig.3.Note that both systems shown in Fig.3are time variant.Consider the specific example of an ideal parallel LC oscillatorshown in Fig.4.If we inject a current impulse as shown,the amplitude and phase of the oscillator will have responsessimilar to that shown in Fig.4(a)and(b).The instantaneousvoltagechange182IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL.33,NO.2,FEBRUARY1998(a)(b)Fig.5.(a)A typical Colpitts oscillator and (b)a five-stage minimum size ring oscillator.capacitor and will not affect the current through the inductor.It can be seen from Fig.4that the resultant changeinis time dependent.In particular,if the impulse is applied at the peak of the voltage across the capacitor,there will be no phase shift and only an amplitude change will result,as shown in Fig.4(a).On the other hand,if this impulse is applied at the zero crossing,it has the maximum effect on the excessphase,which results in no phase change and changes only the amplitude,while applying an impulse atpointm CMOS inverter chain ring oscillatorshown in Fig.5(b).The results are shown in Fig.6(a)and (b),respectively.The impulse is applied close to a zerocrossing,(a)(b)Fig.6.Phase shift versus injected charge for oscillators of Fig.5(a)and (b).where it has the maximum effect on phase.As can be seen,the current-phase relation is linear for values of charge up to 10%of the total charge on the effective capacitance of the node of interest.Also note that the effective injected charges due to actual noise and interference sources in practical circuits are several orders of magnitude smaller than the amounts of charge injected in Fig.6.Thus,the assumption of linearity is well satisfied in all practical oscillators.It is critical to note that the current-to-phase transfer func-tion is practically linear even though the active elements may have strongly nonlinear voltage-current behavior.However,the nonlinearity of the circuit elements defines the shape of the limit cycle and has an important influence on phase noise that will be accounted for shortly.We have thus far demonstrated linearity,with the amount of excess phase proportional to the ratio of the injected charge to the maximum charge swing across the capacitor on the node,i.e.,when the impulseis injected.Therefore,the unit impulse response for excess phase can be expressedas(10)whereis the unit step.Wecallwhich describes how much phase shift results fromapplying a unit impulse attimeis a function of the waveformor,equivalently,the shape of the limit cycle which,in turn,is governed by the nonlinearity and the topology of the oscillator.Given the ISF,the output excessphaseHAJIMIRI AND LEE:GENERAL THEORY OF PHASE NOISE IN ELECTRICAL OSCILLATORS183(a)(b)Fig.7.Waveforms and ISF’s for(a)a typical LC oscillator and(b)a typical ring oscillator.where represents the input noise current injected into the node of interest.Since the ISF is periodic,it can be expanded in a Fourierseriesth harmonic.As will be seenlater,for an arbitrary inputcurrent injected into any circuit node,once the variousFourier coefficients of the ISF have been found.As an illustrative special case,suppose that we inject a lowfrequency sinusoidal perturbation current into the node ofinterest at a frequencyof(14)where.The argumentsof all the integrals in(13)are at frequencies higherthanand are significantly attenuated by the averaging nature ofthe integration,except the term arising from thefirst integral,whichinvolves.Therefore,the only significant termin,denotedas.As an important second special case,consider a current at afrequency close to the carrier injected into the node of interest,givenby.A process similar to thatof the previous case occurs except that the spectrumofFig.8.Conversion of the noise around integer multiples of the oscillationfrequency into phase noise.consists of two impulsesat as shown in Fig.8.This time the only integral in(13)which will have a lowfrequency argument isfor is givenby.More generally,(13)suggests that applying acurrentclose to any integer multiple of theoscillation frequency will result in two equal sidebandsat.Hence,in the generalcaseusing(13).Computing the power spectral density(PSD)of the oscillatoroutputvoltage requires knowledge of how the outputvoltage relates to the excess phase variations.As shown inFig.8,the conversion of device noise current to output voltagemay be treated as the result of a cascade of two processes.Thefirst corresponds to a linear time variant(LTV)current-to-phase converter discussed above,while the second is anonlinear system that represents a phase modulation(PM),which transforms phase to voltage.To obtain the sidebandpower around the fundamental frequency,the fundamentalharmonic of the oscillatoroutputas the input.Substitutinggiven by(17).Therefore,an injected currentat(18)184IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL.33,NO.2,FEBRUARY1998(a)(b)Fig.9.Simulated power spectrum of the output with current injection at(a) f m=50MHz and(b)f0+f m=1:06GHz.This process is shown in Fig.8.Appearance of the frequencydeviation.This type of nonlinearity does not directlyappear in the phase transfer characteristic and shows itself onlyindirectly in the ISF.It is instructive to compare the predictions of(18)withsimulation results.A sinusoidal current of10MHz.This power spectrum is obtained usingthe fast Fourier transform(FFT)analysis in HSPICE96.1.Itis noteworthy that in this version of HSPICE the simulationartifacts observed in[9]have been properly eliminated bycalculation of the values used in the analysis at the exactpoints of interest.Note that the injected noise is upconvertedinto two equal sidebandsat,where is the average capacitance on each node of thecircuitand is the maximum swing across it.For thisoscillator,–whose power spectral density has both aflat region anda,which in turn becomeclose-in phase noise in the spectrumof,as illustrated inFig.11.It can be seen that thetotal is given by the sumof phase noise contributions from device noise in the vicinityof the integer multiplesof,weighted by thecoefficients.This is shown in Fig.12(a)(logarithmic frequency scale).The resulting single sideband spectral noisedensity isplotted on a logarithmic scale in Fig.12(b).The sidebands inthe spectrumof,in turn,result in phase noise sidebandsin the spectrumof through the PM mechanism discussin the previous subsection.This process is shown in Figs.11and12.The theory predicts the existenceof,andflatregions for the phase noise spectrum.The low-frequency noisesources,such asflicker noise,are weighted by thecoefficientand showaHAJIMIRI AND LEE:GENERAL THEORY OF PHASE NOISE IN ELECTRICAL OSCILLATORS185Fig.11.Conversion of noise to phase fluctuations and phase-noise side-bands.the white noise terms are weighted byother coefficients and give rise tothecontainsregions.Finally,the flat noise floor in Fig.12(b)arises from the white noise floor of the noise sources in the oscillator.The total sideband noise power is the sum of these two as shown by the bold line in the same figure.To carry out a quantitative analysis of the phase noise sideband power,now consider an input noise current with a white power spectraldensityHz.Based on the foregoing development and (18),the total single sideband phase noise spectral density in dB below the carrier per unit bandwidth due to the source on one node at an offset frequencyof(20)where.As aresultregion of the phase noise spectrum.For a voltage noise source in series with aninductor,,wherecorner of thephase noise.It is important to note that it is by nomeans(a)(b)Fig.12.(a)PSD of (t )and (b)single sideband phase noise power spectrum,L f 1!g .obvious from the foregoing development thatthecanbe describedby(22)whereportion of the phasenoisespectrum:corner,corner in the phase noisespectrum:phase noise corner due to internal noisesources is not equal tothe186IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL.33,NO.2,FEBRUARY1998Fig.13.Collector voltage and collector current of the Colpitts oscillator of Fig.5(a).D.Cyclostationary Noise SourcesIn addition to the periodically time-varying nature of the system itself,another complication is that the statistical prop-erties of some of the random noise sources in the oscillator may change with time in a periodic manner.These sources are referred to as cyclostationary.For instance,the channel noise of a MOS device in an oscillator is cyclostationary because the noise power is modulated by the gate source overdrive which varies with time periodically.There are other noise sources in the circuit whose statistical properties do not depend on time and the operation point of the circuit,and are therefore called stationary.Thermal noise of a resistor is an example of a stationary noise source.A white cyclostationary noise current can be decom-posed as[13]:is a white cyclostationaryprocess,is awhite stationary processandis a deterministic periodic function describing the noise amplitude modulation.Wedefineto be a normalized function with a maximum value of1.Thisway,is equal to the maximum mean square noisepower,,which changes periodically with time.Applying the above expression forto(11),(27)wherecan be derived easily from device noise character-istics and operating point.Hence,this effective ISF shouldbeFig.14.0(x ),0e (x ),and (x )for the Colpitts oscillator of Fig.5(a).used in all subsequent calculations,in particular,calculation of thecoefficients .Note that there is a strong correlation between the cyclosta-tionary noise source and the waveform of the oscillator.The maximum of the noise power always appears at a certain point of the oscillatory waveform,thus the average of the noise may not be a good representation of the noise power.Consider as one example the Colpitts oscillator of Fig.5(a).The collector voltage and the collector current of the transistor are shown in Fig.13.Note that the collector current consists of a short period of large current followed by a quiet interval.The surge of current occurs at the minimum of the voltageacross the tank where the ISF is small.Functions,andfor this oscillator are shown in Fig.14.Note that,in thiscase,is quite differentfrom is at a maximum,i.e.,thesensitivity is large)at the same time the noise power is large.Functions,and for the ring oscillator of Fig.5(b)are shown in Fig.15.Note that in the case of theringoscillatorare almost identical.This indicates that the cyclostationary properties of the noise are less important in the treatment of the phase noise of ring oscillators.This unfortunate coincidence is one of the reasons why ring oscillators in general have inferior phase noise performance compared to a Colpitts LC oscillator.The other important reason is that ring oscillators dissipate all the stored energy during one cycle.E.Predicting Output Phase Noise with Multiple Noise Sources The method of analysis outlined so far has been used to predict how much phase noise is contributed by a single noise source.However,this method may be extended to multiple noise sources and multiple nodes,as individual contributions by the various noise sources may be combined by exploiting superposition.Superposition holds because the first system of Fig.8is linear.HAJIMIRI AND LEE:GENERAL THEORY OF PHASE NOISE IN ELECTRICAL OSCILLATORS187Fig.15.0(x ),0e (x ),and (x )for the ring oscillator of Fig.5(b).The actual method of combining the individual contributions requires attention to any possible correlations that may exist among the noise sources.The complete method for doing so may be appreciated by noting that an oscillator has a current noise source in parallel with each capacitor and a voltage noise source in series with each inductor.The phase noise in the output of such an oscillator is calculated using the following method.1)Find the equivalent current noise source in parallel with each capacitor and an equivalent voltage source in series with each inductor,keeping track of correlated and noncorrelated portions of the noise sources for use in later steps.2)Find the transfer characteristic from each source to the output excess phase.This can be done as follows.a)Find the ISF for each source,using any of the methods proposed in the Appendix,depending on the required accuracy and simplicity.b)Find,the amount of charge swing across the effec-tive capacitor it is injectingintois the tank capacitor,andis the maximum voltage swing across the tank.Equation (19)reducesto,the result obtained in [8]istwo times larger than the result of (29).Assuming that the total noise contribution in a parallel tank oscillator can be modeled using an excess noisefactorandfor valuesofregionare suggested by (24),which shows thatthe188IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL.33,NO.2,FEBRUARY1998(a)(b)(c)(d)Fig.16.(a)Waveform and (b)ISF for the asymmetrical node.(c)Waveform and (d)ISF for one of the symmetrical nodes.waveform.One such property concerns the rise and fall times;the ISF will have a large dc value if the rise and fall times of the waveform are significantly different.A limited case of this for odd-symmetric waveforms has been observed [14].Although odd-symmetric waveforms havesmall coefficients,the class of waveforms withsmall is not limited to odd-symmetric waveforms.To illustrate the effect of a rise and fall time asymmetry,consider a purposeful imbalance of pull-up and pull-down rates in one of the inverters in the ring oscillator of Fig.5(b).This is obtained by halving the channelwidthAatMHz is applied to one of the symmetric nodes ofthe(a)(b)Fig.17.Simulated power spectrum with current injection at f m =50MHz for (a)asymmetrical node and (b)symmetrical node.oscillator.In the second experiment,the same source is applied to the asymmetric node.As can be seen from the power spectra of the figure,noise injected into the asymmetric node results in sidebands that are 12dB larger than at the symmetric node.Note that (30)suggests that upconversion of low frequency noise can be significantly reduced,perhaps even eliminated,byminimizing ,at least in principle.Sincedepends on the waveform,this observation implies that a proper choice of waveform may yield significant improvements in close-in phase noise.The following experiment explores this concept by changing the ratioofA of sinusoidal current at 100MHz intoone node.The sideband power below carrier as a function oftheA at 50MHz injected at the drain node of one of the buffer stages results in two equal sidebands,Fig.18.Simulated and predicted sideband power for low frequency injection versus PMOS to NMOS W=Lratio.Fig.19.Four-stage differential ring oscillator.upconversion of noise to close-in phase noise,even though differential signaling is used.Since the asymmetry is due to the voltage dependent con-ductance of the load,reduction of the upconversion might be achieved through the use of a perfectly linear resistive load,because the rising and falling behavior is governed by an RC time constant and makes the individual waveforms more symmetrical.It was first observed in the context of supply noise rejection [15],[16]that using more linear loads can reduce the effect of supply noise on timing jitter.Our treatment shows that it also improves low-frequency noise upconversion into phase noise.Another symmetry-related property is duty cycle.Since the ISF is waveform-dependent,the duty cycle of a waveform is linked to the duty cycle of the ISF.Non-50%duty cyclesgenerally result inlargerforeven tank of an LC oscillator is helpful in this context,since ahighMHz,MHz,and MHz,and the sideband powersatis proportionalto,and hence the sideband power is proportionaltoA (rms)at20dB/decade,again in complete accordance with (18).The third experiment aims at verifying the effect of thecoefficientson the sideband power.One of the predictions of the theory isthatis responsible for the upconver-sion of low frequency noise.As mentionedbefore,is a strong function of waveform symmetry at the node into which the current is injected.Noise injected into a node with an asymmetric waveform (created by making one inverter asymmetric in a ring oscillator)would result in a greater increase in sideband power than injection into nodes with more symmetric waveforms.Fig.22shows the results of an experiment performed on a five-stage ring oscillator in which one of the stages is modified to have an extra pulldownFig.21.Measured sideband power versus f m ,for injections in vicinity of multiples of f 0.Fig.22.Power of the sidebands caused by low frequency injection into symmetric and asymmetric nodes of the ring oscillator.NMOS device.A current of20m,5-V CMOS process runningatandregion.For thisprocess we have a gate oxide thicknessofnm and threshold voltagesofVand mandm m,and a lateral diffusionof fF.Therefore,Fig.23.Phase noise measurements for a five-stage single-ended CMOS ring oscillator.f 0=232MHz,2- m processtechnology.identical noise sources thenpredictskHz,this equationpredictskHz dBc/Hz,in good agreement with a measurementofregion,it is enough to calculatetheratio iscalculated to be 0.3,which predictsamandmm,whichresults in a total capacitance of 43.5fFand,or122.5d B c /H z ,a g a i n i na g r e e m e n t w i t h p r e d i c t i o n s .T h e r a t i o i s c a l c u l a t e t ob e 0.17w h ic h p r ed i c t sar e g i o n b e h a v i o r .I t i n v o l v e s a s e v es t a r v e d ,s i n g l e -e n d e d r i n g o s c i l l a t o r i s t a g e c o n s i s t s o f a n a d d i t i o n a l N M O S a i n s e r i e s .T h e g a t e d r i v e s o f t h e a d d e d i n d e p e n d e n t c o n t r o l o f t h e r i s e a n d f a l l t h e p h a s e n o i s e w h e n t h e c o n t r o l v o l t a g a c h i e v e s y m m e t r y v e r s u s w h e n t h e y a r e n c o n t r o l v o l t a g e s a r e a d j u s t e d t o k e e p t h eFig.24.Phase noise measurements for an 11-stage single-ended CMOS ring oscillator.f 0=115MHz,2- m processtechnology.Fig.25.Effect of symmetry in a seven-stage current-starved single-ended CMOS VCO.f 0=60MHz,2- m process technology.constant at 60MHz.As can be seen,making the waveform more symmetric has a large effect on the phase noise intheregion.Another experiment on the same circuit is shown in Fig.26,which shows the phase noise power spectrum at a 10kHz offset versus the symmetry-controlling voltage.For all the data points,the control voltages are adjusted to keep the oscillation frequency at 50MHz.As can be seen,the phase noise reaches a minimum by adjusting the symmetry properties of the waveform.This reduction is limited by the phase noiseinm CMOS process.Each stage istapped with an equal-sized buffer.The tail current source has a quiescent current of108fFand the voltage swingisV,which resultsin fF.The total channel noise current on eachnodeFig.26.Sideband power versus the voltage controlling the symmetry of the waveform.Seven-stage current-starved single-ended CMOS VCO.f 0=50MHz,2- m processtechnology.Fig.27.Phase noise measurements for a four-stage differential CMOS ring oscillator.f 0=200MHz,0.5- m process technology.is,the phase noise inthe,or103.9d B c /H z ,a g a i n i n a g r e e m e n t w i tA l s o n o t e t h a t d e s p i t e d i f f e r e n t i a l s y m m e trw h i l e k e e p i n g t h e e f f e c t i v ec a p a c i t a n ce c o n s t a n t t o m a i n t a iand e c r e a s e s t h e c o n d u c t i o n a n g l e ,a n d t h e r e f f e c t i ve.T h e p h a s e n o i s e u l t i m a t e l y i n c r e a s e s(h e r e ,a b o u t0.2)t h a t m i n i m i z e s t h e p h a s e n o i s e .T h i s r t h e o r e t i c a l b a s i s f o r t h e c o m m o n r u l e -o f -t hFig.28.Sideband power versus capacitive division ratio.Bipolar LC Colpitts oscillator f 0=100MHz.use)inColpitts oscillators [17].VI.C ONCLUSIONThis paper has presented a model for phase noise which explains quantitatively the mechanism by which noise sources of all types convert to phase noise.The power of the model derives from its explicit recognition of practical oscillators as time-varying systems.Characterizing an oscillator with the ISF allows a complete description of the noise sensitivity of an oscillator and also allows a natural accommodation of cyclostationary noise sources.This approach shows that noise located near integer mul-tiples of the oscillation frequency contributes to the total phase noise.The model specifies the contribution of those noise components in terms of waveform properties and circuit parameters,and therefore provides important design insight by identifying and quantifying the major sources of phase noise degradation.In particular,it shows that symmetry properties of the oscillator waveform have a significant effect on the upconversion of low frequency noise and,hence,thefromit.The second method is based on an analytical state-space approach to find the excess phase change caused by an impulse of current from the oscillation waveforms.The third method is an easy-to-use approximate method.A.Direct Measurement of Impulse ResponseIn this method,an impulse is injected at different relative phases of the oscillation waveform and the oscillatorsimulatedFig.29.State-space trajectory of an n th-order oscillator.for a few cycles afterwards.By sweeping the impulse injec-tion time across one cycle of the waveform and measuring the resulting timeshiftis the period of oscillation.Fortunately,many implementations of SPICE have an internal feature to perform the sweep automatically.Since for each impulse one needs to simulate the oscillator for only a few cycles,the simulation executes rapidly.Onceth-order system can be represented by its trajectory inanwhich suddenly changes the state of the systemto.As discussed earlier,amplitude variations eventually die away,but phase variations do not.Application of the perturbation impulse causes a certain change in phase in either a negative or positive direction,depending on the state-vector and the direction of the perturbation.To calculate the equivalent time shift,we first find the projection of the perturbation vector on a unity vector in the direction of motion,i.e.,the normalized velocityvectoris the equivalent displacement along the trajectory,and,which arises from the projection operation.Theequivalent time shift is given by the displacement divided by。
OSCILLATOR PHASE NOISE AND SAMPLING CLOCK JITTER
Date: 2007 June 12. Key words and phrases. Phase noise, Oscillator phase noise, clock jitter. ST Microelectronics, (Genesis Microchip) Bangalore, India ().
1
NOISE
(1)
v (t) = v0 (1 + α(t)) cos ω0 t + φ(t) +
β 2 t 2
The long term drift effect of the oscillator due to ageing is reflected in β . a(t) is the amplitude noise and φ(t) represents phase noise. The phase noise φ(t) will have deterministic component as well as random components. The deterministic component is attributed by physical phenomena like supply voltage, temperature change, output impedance of the oscillator etc. The random nature of the phase noise is usually represented with a power spectral density expressed in power law. Instantaneous frequency2 of v (t) is 1 d (2) f (t) = [2πf0 + φ(t)] 2π dt
SMSL D3 数字音频解码器说明书
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目录安全注意事项 (1)特点 (2)目录 (3)技术参数 (5)关于遥控器 (6)部件介绍......................................................................................7~8主机前面. (7)主机背面 (8)显示界面和操作介绍................................................................9-12恢复出厂设置/保修条款. (13)Table of contentSafety notes (14)Features (15)Specification (16)Remote Control (17)Functions..................................................................................................................................18~19 Main unit front (18)Main unit back (19)Operation Instructions.................................................................................................20-23 Factory Reset/Warranty Terms. (24)技术参数输入方式 B /光纤/同轴/I2S/ AES(EBU) 输出方式 ......................................................................................................单端线路/平衡线路 THD+N ............................................................................................................................0.001% 动态范围 ...........................................................................................................................112dB 信噪比 ..............................................................................................................................112dB USB传输方式 ............................................................................................................... 异步传输 USB兼容性 ...............................................................Windows 7 / 8 / 8.1 / 10, Mac OSX, Linux 位深 B / I2S 1bit，16~32bit 光纤/同轴/AES(EBU) 1bit，16~24bit 采样率 B / I2S PCM 44.1~768kHzDSD 2.8224~22.5792MHz 光纤/同轴/AES(EBU) PCM 44.1~192kHz 消耗功率 ..............................................................................................................................10W 待机功耗 ...........................................................................................................................<0.8W 体积 ...................................................................................................280X240X51mm(WxHxD)重量 ..................................................................................................................................3.96kg如果遥控器距离本机很近时操作仍无效，请用新电池更换。
相位噪声&抖动仿真方法VCO Design Using SpectreRF
VCO Design Using SpectreRF
________________________________________________________________________
Contents
Voltage Controlled Oscillator Design Measurements ........................................................ 3 Purpose............................................................................................................................ 3 Audience ......................................................................................................................... 3 Overview......................................................................................................................... 3 Introduction to VCOs.......................................................................................................... 3 The Design Example: oscHartley ....................................................................................... 4 Example Measurements Using SpectreRF.......................................................................... 5 Lab1: Output Frequency, Output Power, Phase Noise and Jitter ................................... 6 Measurement (Pnoise with shooting or Flexible Balance engine).................................. 6 Lab2: Frequency Pushing (Swept PSS) ........................................................................ 31 Lab3: Tuning Sensitivity and Linearity (Swept PSS)................................................... 36 Lab4: Power Dissipation (PSS) ................................................................................... 43 Lab5: Frequency Pulling (Swept PSS) ........................................................................ 48 Conclusion ........................................................................................................................ 62 Reference .......................................................................................................................... 62
Ring oscillators
专利名称：Ring oscillators发明人：Shuxian Chen,Jeffrey T. Watt申请号：US11960343申请日：20071219公开号：US07859354B1公开日：20101228专利内容由知识产权出版社提供专利附图：摘要：Ring oscillator circuitry is provided. The ring oscillator circuitry may include a loop of inverters. A control gate may be interposed in the loop to control operation of the loop. The control gate may be activated using a ring oscillator trigger signal. During application of the trigger signal, the trigger signal may become degraded due to circuitparasitics. Trigger signal conditioning circuitry may be used to remove noise from the degraded trigger signal. A version of the trigger signal that has been conditioned by the trigger signal conditioning circuitry may be applied to a control input of the control gate. The trigger signal conditioning circuitry may include a low pass filter, a hysteresis circuit, and a two-stage buffer. The two-stage buffer may be formed from transistors with the same characteristics as the transistors in the inverters of the ring oscillator loop.申请人：Shuxian Chen,Jeffrey T. Watt地址：Fremont CA US,Palo Alto CA US国籍：US,US代理机构：Treyz Law Group代理人：G. Victor Treyz更多信息请下载全文后查看。
相位抖动的英文单词
相位抖动的英文单词英文回答：Phase jitter is a measure of the short-term variations in the phase of an oscillator signal. It is caused by both internal and external noise sources and can degrade the performance of systems that rely on precise timing.Phase jitter is typically measured in degrees or radians and can be characterized by its frequency spectrum. The low-frequency components of phase jitter are often due to environmental factors, such as temperature fluctuations and mechanical vibrations. The high-frequency components are typically due to electronic noise sources, such as flicker noise and shot noise.Phase jitter can have a number of negative effects on system performance. For example, it can increase the bit error rate in digital communication systems and reduce the accuracy of analog-to-digital converters.There are a number of techniques that can be used to reduce phase jitter. These include using low-noise oscillators, filtering the oscillator signal, and using phase-locked loops.中文回答：相位抖动是衡量振荡器信号相位短期变化的度量。
正弦波振荡器的基本原理英语
正弦波振荡器的基本原理英语Basic Principles of Sine Wave Oscillators.A sine wave oscillator is an electronic circuit that generates a sinusoidal waveform. Sinusoidal waveforms are commonly used in electronics and signal processing, and are found in applications such as audio synthesis, telecommunications, and control systems.There are many different types of sine wave oscillators, but they all share some common basic principles. The first principle is that of feedback. In a sine wave oscillator, a portion of the output signal is fed back to the input. This feedback signal is used to control the frequency and amplitude of the oscillation.The second principle is that of resonance. In a sine wave oscillator, the feedback loop forms a resonant circuit. This resonant circuit amplifies the feedback signal at a specific frequency, which is the frequency of theoscillation.The third principle is that of negative resistance. In a sine wave oscillator, the feedback loop provides negative resistance. This negative resistance cancels out the positive resistance of the other components in the circuit, resulting in an overall negative resistance. Negative resistance is necessary for oscillation to occur.The basic operation of a sine wave oscillator can be understood by considering a simple example. The circuit shown in Figure 1 is a basic sine wave oscillator. The circuit consists of an amplifier, a feedback resistor (Rf), and a resonant circuit (LC).Figure 1: Basic sine wave oscillator.The amplifier provides the gain necessary foroscillation to occur. The feedback resistor controls the amount of feedback, and the resonant circuit determines the frequency of the oscillation.When the circuit is powered up, the amplifier begins to amplify the noise in the circuit. This amplified noise is fed back to the input of the amplifier through the feedback resistor. The feedback signal is in phase with the input signal, which causes the amplifier to amplify the signal even more. This positive feedback loop results in oscillation.The frequency of the oscillation is determined by the resonant circuit. The resonant circuit consists of an inductor (L) and a capacitor (C). The inductance of the inductor and the capacitance of the capacitor determine the resonant frequency of the circuit.The amplitude of the oscillation is determined by the gain of the amplifier and the amount of feedback. The gain of the amplifier is set by the value of the feedback resistor. The amount of feedback is set by the value of the feedback capacitor (Cf).Sine wave oscillators are used in a wide variety of applications. Some common applications include:Audio synthesis: Sine wave oscillators are used to generate the basic waveforms used in synthesizers and other electronic musical instruments.Telecommunications: Sine wave oscillators are used to generate the carrier waves used in radio and television broadcasting.Control systems: Sine wave oscillators are used to generate the reference signals used in control systems.Sine wave oscillators are a versatile and important electronic circuit. They are used in a wide variety of applications, and they play an essential role in many modern electronic systems.Additional Details.The following are some additional details about the basic principles of sine wave oscillators:Feedback: The feedback loop in a sine wave oscillator is essential for oscillation to occur. The feedback signal provides the energy necessary to sustain the oscillation.Resonance: The resonant circuit in a sine wave oscillator determines the frequency of the oscillation. The resonant frequency of the circuit is the frequency at which the feedback signal is amplified the most.Negative resistance: The negative resistance in a sine wave oscillator cancels out the positive resistance of the other components in the circuit. This negative resistance results in an overall negative resistance, which is necessary for oscillation to occur.Amplitude control: The amplitude of the oscillation in a sine wave oscillator is determined by the gain of the amplifier and the amount of feedback. The gain of the amplifier is set by the value of the feedback resistor. The amount of feedback is set by the value of the feedback capacitor.Sine wave oscillators are a complex topic, but the basic principles are relatively simple. By understanding the basic principles, you can design and build your own sine wave oscillators.。
RingOscillatorWP@全新芯片测试实验室
Ring Oscillator Frequency Measurements Usingan Automated Parametric Test SystemYang PanApplications EngineerSemiconductor Business GroupKeithley Instruments, Inc.AbstractUsing an Automated Parametric Test (APT) System, such as the Keithley S680 tester, to measure ring oscillator test structures provides test engineers withan inline tool to monitor semiconductor manufacturing quality and diagnose production problems in real time. Ring oscillator test structures have beenin use for decades and continue to play a critical role in process monitoringof advanced technologies. At the 90nm technology node, a single-stage ring oscillator’s frequency can be as high as 100GHz. Fortunately, a multi-stage ring oscillator coupled with a frequency divider can be designed to down-convert the output frequency to less than 100MHz, making frequency measurements less expensive and more feasible. This white paper demonstrates a practical, low cost, and high throughput method for measuring ring oscillator frequency. IntroductionShort gate-delay times allow transistors to process data faster and improve overall circuit performance. A number of parameters have an impact on gate-delay time, including gate capacitance, channel mobility, etc. Therefore, design, process integration, and production process engineers evaluate and monitor gate-delay measurements in order to optimize and control the gate-delay time throughout the technology lifecycle. At the 90nm technology node, gate-delay times can be as short as a few picoseconds, which corresponds to an oscillation frequency of 100GHz or higher. Measuring gate delays in the picosecondrange directly is very complex and expensive, as well as infeasible in an inline production regime. On the other hand, the ring oscillator circuit can provide an indirect, yet accurate, measurement of the gate delay when measured with conventional lower-cost instruments.A ring oscillator is a device consisting of an odd number of NOT gates (inverters) in which the output voltage oscillates between binary levels. Each inverter delays the input signal for a certain period of time (the gate-delay time); at the output of the final stage, the total delay time is equal to the product of single gate-delay time multiplied by the number of stages. By measuring a ring oscillator’s fundamental frequency, the average gate-delay time can be calculated, as shown in Figure 1.n × 2TFrequency =1Figure 1. A 9-stage ring oscillatorIn addition to a ring of inverters (inverter ring), the test structure often includes afrequency divider for down-converting the oscillator’s fundamental frequency [1] [2] [3] [4].A multi-stage frequency divider is typically used to lower the output frequency of the inverter ring from the gigahertz range to the megahertz range, which makes the circuit’s fundamental output frequency (<100MHz) compatible with the types of probes, cables, and instruments typically used in production parametric testers.This white paper demonstrates a practical, low cost, high throughput method for measuring a ring oscillator’s frequency in a manufacturing environment. It includes an example of a typical ring oscillator test program and measurement results, along with tips on how to avoid picking up higher harmonic frequencies. Finally, a simple parallel technique for high throughput measurements is presented.The ring oscillator test structures used in the development of this technique were fabricated with a typical 90nm technology on 300mm wafers. A Keithley S680 automated parametric tester was used to implement fully automated ring oscillator testing. The tester was equipped with either an Advantest Model R3131 (3GHz) spectrum analyzer or an Advantest ModelU3751 (8GHz) spectrum analyzer to measure frequency and amplitude. The ring oscillator’s fundamental frequency was confirmed with a Tektronix TDS3032 (300MHz) oscilloscope.General ConsiderationsAs part of the chip design process, IC designers, as well as technology development engineers and process integration engineers, need to consider ring oscillator design as part of their overall test strategy. The following considerations should be included in this strategy:Test structure (ring oscillator) output frequency• Frequency bandwidth range of the probe card• Frequency bandwidth range of the cables• Frequency bandwidth of the switch matrix (internal to the test system)• Frequency range of spectrum analyzer• The higher the test frequency requirements are, the higher the cost of test will be. Three frequency-bandwidth options are available in Keithley S680 Automated Parametric Testers: 60MHz, 1GHz, and 40GHz.To control the cost of test, the ring oscillator test structure design can be adjusted to reduce the output frequency. A ring oscillator’s total gate delay time is linearly proportional to the number of stages, according to the equation in Figure 1. The more stages there are, the lower the frequency will be. The influence of local process variations may result in slightly different gate-delay times for each inverter or stage in the ring oscillator. The effects of local process variation can be minimized by calculating the average gate-delay time; therefore, the more stages there are, the more accurate the test will be. However, the number of stages is limited by the available size of test-area (the allocated area on the chip for frequency test). In addition to increasing the number of inverter stages, a frequency divider further reduces the teststructure’s output signal frequency. The reduction in frequency is exponentially proportional to the number of dividers in the chain (by 1/2m , with m equal to the number of stages in the divider). However, a digital frequency divider is made by a pair of flip-flops, and its area is approximately 10 times that of a ring oscillator’s. Therefore, a compromise should be made by balancing the number of stages of the ring oscillator and the number of stages of the frequency divider in order to minimize test-area. In the end, the ring oscillator test structure’s output frequency is given by:1 f test = _____________ n × 2T × 2mwhere f test is test frequency, T is the average gate-delay time, n and m are the number of stages in the ring oscillator and the number of frequency dividers respectively. For example, if n = 100, m = 5, T = 4 picoseconds, then f test = 39.1MHz.Automated Parametric Test System DescriptionA 300mm wafer prober (in this case, a TSK [Tokyo Seimitsu Kogu Co., Ltd.] AccretechUF3000) was paired with the Keithley S680 Automated Parametric Test System configuration as illustrated in Figure 2. The DC bias needed to power the ring oscillator test structure was sourced from the system’s Source-Measure Units (SMUs). The ring oscillator test structure’s output signal was picked up by probe card and fed to the spectrum analyzer or otherinstruments via the test head and cables. The system was operated under the control of theKeithley Test Environment (KTE) software.Keithley Test Environment at Sun workstationInstrument cabinetWafer prober, test head,and microscopeOscilloscopeSpectrum AnalyzerSMUFigure 2. Keithley S680 Automated parametric test system configured for ring oscillator measurements Test ProgramThe following code snippet example was developed for testing a ring oscillator structure using Keithley Test Environment software./* Include Header Files */#include <stdio.h>#include <lptdef.h>#include <lptdef _lowercase.h>#include <math.h>#include <ksox _def.h>#include <AVTST3131_proto.h> /* Advantest R3131 prototype driver */#include “freqstruct.h”./* Connect instruments to probe pins via matrix */conpin(SMU1,P1,0);conpin(SMU2,P2,0);conpin(SMU3,P2,0);conpin(FOHM1,P4,0);conpin(SMU1L,SMU2L,SMU3L,Pgrnd1,Pgrnd2,GND,0);/* Configure SMUs for Ring Oscillator Test */setmode(SMU1, KI_LIM_MODE, KI_VALUE);setmode(SMU2, KI_LIM_MODE, KI_VALUE);setmode(SMU3, KI_LIM_MODE, KI_VALUE);setmode(SMU1, KI_INTGPLC, 1.0);setmode(SMU2, KI_INTGPLC, 1.0);lorangei(SMU1,100.0e-9);lorangei(SMU2,100.0e-9);limiti(SMU1,I1);limiti(SMU2,I2);limiti(SMU3,I3);setauto(SMU1);setauto(SMU2);/* Sequence power up of ring oscillator to ensure single mode oscillation */ forcev(SMU3,V3);forcev(SMU1,V1);forcev(SMU2,V2);/* Delay to ensure stable oscillation */rdelay(Delay);/* Power up ring oscillator and measure current */measi(SMU1,Im1);measi(SMU2,Im2);/* Setup spectrum analyser for measurement */Spastat = freq_init();Spastat = freq_setup(low,high,rbw);/* Make frequency and magnitude measurement using spectrum analyzer */Spastat = freq_measure(&Freq,Vpeak);/* Reset SMUs and clear matrix relays */devint();return;Test ResultsFigure 3 shows the results of measuring a ring oscillator’s frequency and peak amplitude with a spectrum analyzer. The X-axis is set to 9MHz per division. The frequency sweep (along the x-axis) starts at 1MHz and stops at 91MHz with a bandwidth resolution of 0.1MHz. The amplitude is on a linear scale of 10mV per division. The spectral peak of the ring oscillator output occurs at 32.68MHz with an amplitude of 62.56mV. Note the very quiet noise floor. This is an indication of both good ring oscillator test structure design and a good test system architecture.Figure 3. A ring oscillator’s frequency and peak amplitude as measured with a spectrum analyzer.The fundamental frequency of a ring oscillator increases as the voltage increases, which causes the ring oscillator to act as a voltage-controlled oscillator (VCO). The VCO effectis not difficult to explain. When the voltage applied to the drain of the transistors VisDD increased, both input signal rise time and output signal fall-time are reduced; therefore, gate-delay time is reduced and oscillation frequency increases. The actual test results reflect this relationship clearly:V0.8V 1.0V 1.2VDDFrequency17.2MHz26.3MHz33.4MHzThe measurements in this table were made using a spectrum analyzer. To validate these results, the same ring oscillator was measured with an oscilloscope. Figure 4 shows the waveform of the ring oscillator as viewed with an oscilloscope. The period of the waveform is 30.44 nanoseconds and the corresponding frequency is 32.85MHz. These results are consistent with the spectrum analyzer measurement and confirm that the measurement was made on fundamental frequency rather than a harmonic.Figure 4. Ring oscillator output as viewed with an oscilloscope. The time base is set to 20ns per division and the voltage scale is set to 500mV per division. The measured wave period is 30.44ns and themeasured amplitude is 1.08V when the supply voltage is 1.2V.Ring oscillator measurements often must be made across the length and width of the entire wafer to understand the process’s impact on the gate-delay time. To demonstrate the production capability of the ring oscillator measurement, the S680 tester was instructed to perform the measurement on all wafer sites. Figure 5 shows a wafer map of the ring oscillator frequency measurements spanning a full 300mm wafer. The average oscillation frequency throughout the wafer was 33.45MHz with a standard deviation of 0.88MHz. This result demonstrates the uniformity of the production wafer.Unit: MHz33.0833.4733.2732.8832.2832.2832.0931.8932.4832.6833.0833.0833.0832.4832.0932.2832.6833.2732.8833.2733.6733.4733.2732.8832.4832.8834.0734.2634.2634.8633.4733.8732.8832.2832.4834.0734.6633.6734.4634.4634.2633.2732.2832.6834.2634.8635.0635.4534.8634.4633.6732.0931.8933.2734.4635.0634.6634.2633.6733.6732.0933.2734.0734.2633.8934.0733.4732.4833.0833.6733.6733.6734.0733.4734.07Figure 5. Wafer map of ring oscillator frequency measurements made with a spectrum analyzer using full automation capabilities of the test system. The average frequency is 33.45MHz. Standarddeviation is 0.88MHz. Supply voltage is 1.2V.Harmonic AnalysisDue to the bistable multivibrator behavior of the ring oscillator, harmonic frequencies are always present to some degree. The following example examines a ring oscillator that has a lower fundamental frequency than that in the first example. This ring oscillator was chosen because it is rich in harmonics less than 100MHz. Figure 6 shows the frequency spectrum of the ring oscillator’s output. The frequency axis is set to 9.9MHz per division and the frequency sweep starts at 1MHz and stops at 100MHz, with a bandwidth resolution of 0.1MHz. The amplitude is on the logarithmic scale and set to 10dB per division. The fundamental peak occurs at 10.90MHz at an amplitude of 259mV, or –5.72dB. It is important to note thatthe amplitude (Y-axis) is displayed in logarithmic scale, which makes it easier to observe harmonic peaks than if they were shown in linear scale.Figure 6. Spectrum of the ring oscillator’s fundamental and harmonics.The –3dB bandwidth of high frequency matrix of S680 tester is 60MHz. If the oscillation frequency is higher than 60MHz, the signal still can be seen via the spectrum analyzer,but the attenuation caused by the matrix is greater. The table below shows the amplitude of the fundamental and harmonics of the ring oscillator test structure. Note the relatively high magnitude of the first harmonic.Harmonics 1 23456789Freq (MHz)10.9021.9932.8843.9754.8665.7576.6487.5398.42Amp (mV)259.09.73620.7720.2523.4613.84 3.820 1.881 1.447Amp (dB)–5.72–34.2–27.6–27.9–26.6–31.2–42.3–48.5–50.8Notes:1) Y-axis full scale is 500.6mV or 0dB.2) The formula to calculate amplitude in logarithm scale is: 20 × Log10(Amp(mV)/500.6) dB.Occasionally, a spectrum analyzer can pick up higher-order harmonic signals, which can cause a false fundamental frequency reading. The best way to avoid detecting and measuring higher harmonics is to set the sweep-stop frequency less than the second harmonic frequency. For example, if the estimated second harmonic frequency is 50MHz, then set the sweep-stop frequency to 40MHz. If it is difficult to estimate the second harmonic frequency, an alternative technique is to set a low limit for peak amplitude. For example, if the estimated fundamental amplitude is 100mV, then set the lower amplitude limit to 30mV. This technique works because the amplitude of the fundamental frequency is always the highest among all the harmonics, as seen in the preceding table. A third method for avoiding higher harmonic frequencies is to force supply voltage and subsequently enable (trig) voltage [5]. It is importantto add a delay time after supply-voltage is forced and before enable-voltage is forced. This ensures that the ring is initialized in a known state; otherwise, more than one oscillation cycle could be traveling around the ring. This approach should be considered during the chip design stage [5].Throughput Improvement Through Parallel TestingMany techniques are available to enhance throughput of an automated parametric tester, including parallel testing. To demonstrate parallel testing of ring oscillators, the Keithley Test Environment (KTE) software controlled two spectrum analyzers installed in the S680 tester to measure two ring oscillators simultaneously. Using this simple parallel test technique can reduce total test time by ~25–30%. The isolation of high frequency signals within the S680 tester’s switch matrix is sufficient to test ring oscillators in parallel.SummaryThis paper demonstrates the capability to implement precision ring oscillator measurements in a production setting using a Keithley S680 tester. Careful selection of test structures and appropriate test system design tradeoffs can allow low cost, precise, and high throughput production testing. These tradeoffs start with the basis of frequency down-conversion within the test structure, which impacts tester configuration, test code, and the wafer sampling plan. High throughput low cost ring oscillator test can increase visibility into process performance, as demonstrated by the wafer map of ring oscillator frequency shown earlier in this document. References[1] M. B. Ketchen and M. Bhushan, “Product-representative ‘at speed’ test structures forCMOS characterization,” IBM Journal of Research and Development, vol. 50, no. 4/5, July/September 2006.[2] J. Bock, et al, “3.3 ps SiGe Bipolar Technology,” in Proc. IEDM, 2004, pp. 255–258.[3] M. Kondo, et al, “Sub-10fJ ECL/68µA 4.7-GHz Divider Ultra-Low-Power SiGe BaseBipolar Transistors with a Wedge-Shaped CVD-SiO2 Isolation Structure and a BPSG-Refilled Trench,” in Proc. IEDM, 1996, pp. 245–248.[4] “Circuit for Harmonic-free Startup of a Ring Oscillator Using Arbitrarily Low FrequencyInputs,” /IPCOM/000141619/.[5] Nobuo Sasaki. “Higher harmonic generation in CMOS/SOS ring oscillators,” IEEE Trans.Electron Devices, vol. ED-29, no. 2, pp. 280–283, February 1962.11Specifications are subject to change without notice.All Keithley trademarks and trade names are the property of Keithley Instruments, Inc.All other trademarks and trade names are the property of their respective companies.A G R E A T E R M E A S U R E O F C O N F I D E N C EKeithley instruments, inc.■ 28775 AURORA ROAD ■ ClEvElAND, OhIO 44139-1891 ■440-248-0400 ■Fax: 440-248-6168 ■1-888-KEIThlEY ■BelgiumSint-Pieters-leeuw Ph: 02-3630040 Fax: 02-3630064 **************** www.keithley.nl chinaBeijingPh: 8610-82255010Fax: 8610-82255018******************finlandEspooPh: 09-88171661Fax: 09-88171662********************franceSaint-AubinPh: 01-64532020Fax: 01-60117726****************www.keithley.frgermanyGermeringPh: 089-84930740Fax: 089-84930734****************www.keithley.deindiaBangalorePh: 080-26771071,-72,-73Fax: 080-26771076**************************italyPeschiera Borromeo (Mi) Ph: 02-5538421Fax: 02-55384228****************www.keithley.it japanTokyoPh: 81-3-5733-7555Fax: 81-3-5733-7556********************www.keithley.jpkoreaSeoulPh: 82-2-574-7778Fax: 82-2-574-7838********************.krwww.keithley.co.krmalaysiaPenangPh: 60-4-656-2592Fax: 60-4-656-3794*************************netherlandsGorinchemPh: 0183-635333Fax: 0183-630821****************www.keithley.nlsingaporeSingaporePh: 65-6747-9077Fax: 65-6747-2991************************.sgswedenSolnaPh: 08-50904600Fax: 08-6552610*******************switzerlandZürichPh: 044-8219444Fax: 044-8203081****************www.keithley.chtaiwanhsinchuPh: 886-3-572-9077Fax: 886-3-572-9031*********************.twunited kingdomThealePh: 0118-9297500Fax: 0118-9297519****************.uk© Copyright 2008 Keithley Instruments, Inc.Printed in the U.S.A.No. 29170408.1K.DCI。
最新文档-Chapter 4 Oscillator - UniMAP Portal4章子-德艺门-PPT精品文档
Square wave
Sawtooth wave
Types of oscillators
1. RC oscillators
Wien Bridge Phase-Shift
2. LC oscillators
Hartley Colpitts Crystal
3. Unijunction / relaxation oscillators
The types of RC oscillators that we will discuss are the Wien-bridge and the phase-shift
Wien-bridge Oscillator
It is a low frequency oscillator which ranges from a few kHz to 1 MHz.
The feedback oscillator relies on a positive feedback of the output to maintain the oscillations.
The relaxation oscillator makes use of an RC timing circuit to generate a nonsinusoidal signal such as square wave
(including computers), and test equipment make use of oscillators
Introduction
An oscillator is a circuit that produces a repetitive signal from a dc voltage.
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Jitter in Ring OscillatorsJohn A.McNeillAbstract—Jitter in ring oscillators is theoretically described, and predictions are experimentally verified.A design procedure is developed in the context of time domain measures of oscillator jitter in a phase-locked loop(PLL).A major contribution is the identification of a designfigure of merit ,which is independent of the number of stages in the ring.Thisfigure of merit is used to relate fundamental circuit-level noise sources(such as thermal and shot noise)to system-level jitter performance.The procedure is applied to a ring oscillator composed of bipolar differential pair delay stages.The theoretical predictions are tested on155 and622MHz clock-recovery PLL’s which have been fabricated in a dielectrically isolated,complementary bipolar process.The measured closed-loop jitter is within10%of the design procedure prediction.Index Terms—Design methodology,jitter,noise measurement, oscillator noise,oscillator stability,phase jitter,phase-locked loops,phase noise,voltage controlled oscillators.I.I NTRODUCTIOND UE to their speed and ease of integration,ring oscillatorsare increasingly being used as voltage controlled oscil-lators(VCO’s)in jitter sensitive applications.One example is in clock recovery phase-locked loops(PLL’s)for serial data communication[1]–[3].Other applications that would benefit from the cost and size advantages of a fully integrated low jitter VCO include disk drive clock recovery[4],[5],clock frequency multiplication[6],[7],and oversampling analog-to-digital converters(ADC’s)[8],[9].This paper presents a framework for a theoretical un-derstanding of fundamental limits on jitter performance in ring oscillator VCO’s and a design methodology for con-necting system-level,closed-loop PLL jitter performance to circuit-level VCO design.Section II begins development of this approach by comparing the ring oscillator to harmonic and relaxation oscillators in the context of noise analysis. Sections III and IV continue development in terms of time domain measures of jitter performance.Section V presents the key equations of the design methodology as applied to a bipolar differential pair delay stage.Section VI gives experimental results.II.C OMPARISON OF O SCILLATOR T YPESA.Harmonic OscillatorA harmonic oscillator is characterized by an equivalence to two energy storage elements,operating in resonance,to give a Manuscript received July9,1996;revised December10,1996.This work was supported by Analog Devices Semiconductor,Inc.The author is with Worcester Polytechnic Institute,Worcester,MA01609 USA.Publisher Item Identifier S0018-9200(97)03830-4.Fig.1.Typical ring oscillator schematic.periodic output signal.The actual resonant element might be an LC tank or a quartz crystal.Resonant circuit-based VCO’s are known to have excellent jitter performance[10],[11]. Unfortunately,the requirement of an off-chip tank or crystal defeats the purpose of integrating the PLL function.Although integrated inductors have been reported in the GHz frequency range[12],these generally havelowsome of the empirical results show promise of excellent jitter performance [3].However,investigation into a theoretical analysis of jitter has only recently begun for bipolar [30],[31]and CMOS [32],[33]ring oscillators.Perhaps one reason that analysis of jitter in ring oscillators has lagged is that the ring does not fit well into either of the harmonic or multivibrator oscillator models.The number of energy storage elements is not as explicit;in fact there are many “energy storage elements”since the ring is composed of multiple stages.III.M ETHODSOFQ UANTIFYING J ITTERThe design technique developed in this paper follows from different methods of measuring jitter in the time domain.Following is a brief description of three relevant time domain measures of jitter.Note that in the closed-loop cases,it is assumed that the VCO is the dominant jitter source.A.Closed-Loop,Transmit Clock ReferencedFor a clock recovery PLL,jitter is usually specified as the standarddeviation of the phase difference between the transmitted clock and the recovered clock.This measurement can be made as shown in Fig.2(a),using an instrument such as a communications signal analyzer (CSA)[34].The transmitclockis observed as the CSA input.In the presence of jitter,a distribution of threshold crossing times is observed as shown in Fig.2(b).The CSA records a histogram of this distribution;the standard deviation of the distributionis .Although this test is a simple indicator of PLL performance,the test provides little information on improving jitter from circuit-level noise sourcesif is not satisfactory.This test also requires the PLL to be operating closed-loop.VCO design and simulation would be simplified if we could consider the VCO by itself (open loop),while being able to predict theclosed-loop .B.Open Loop,Self ReferencedWe can also measure the jitter of the VCO on a stand-alone basis as shown in Fig.2(c).With the VCO free-running at its centerfrequency,(1)The proportionalityconstantis that of a second-order system [35].In clock recovery PLL’s,however,it is common to overdamp the loop to avoid peaking in the jitter transfer function [30],and the loop transfer function can be approximatedas.Analysis [30]shows that the two asymptotes intersect at the loop bandwidth timeconstant(3)If.IV.J ITTER I NDEPENDENCE OFR ING L ENGTHTheparameterfor a single delay stage.To complete the design path from circuit level to system level,it is necessary to determine how thecircuit-level(a)(b)(c)(d)(e)(f)Fig.2.(a)Measurement technique:time domain,closed loop,and transmit clock referenced.(b)Measurement result:standard deviation of T CLK=RCLK phase.(c)Measurement technique:time domain and open loop.(d)Measurement result:standard deviation versus delay time 1T .(e)Measurement technique:time domain and closed loop.(f)Measurement result:standard deviation versus delay time 1T .An experiment was performed in which ring oscillators of lengths three,four,five,seven,and nine stages were fabricated in a3-GHz,as well as the free-running VCO centerfrequencies.Fig.4shows that the jitter increases roughly as the square root of delay time,consistent with the model of (1).More importantly,the jitter over a given measurement interval is the same regardless of how many stages there are in the ring.Table I shows thattheFig.3.Differential pair delaygate.Fig.4.Jitter versus delay for three-,four-,five-,seven-,and nine-stage rings.TABLE IR ING E XPERIMENT RESULTSregardless of the length of the ring:even as center frequency varies by a 3:1ratio over a range of 56–170MHz,the valueof8%.We conclude that the ability of a ringto accurately measure an interval of time depends primarily on the accuracy of its basic delay element as characterizedby,we can predict the jitter for a ring of anylength using that stage.This may seem counterintuitive at first:when more delay stages (and,seemingly,more noise sources)are added,why is the jitter unchanged?The reason can be seen by considering the jitter accumulation process from the “point of view”of the signal transition or “edge”that propagates around the ring.The only delay stage that affects jitter accumulation at a given instant is the stage that is processing the transition.All other gates in the ring are inactive and do not contribute to jitter.Thus,from the standpoint of jitter accumulation,the key measure is the number of gate transitions,not the number of oscillator periods.This is why measures that normalize to the oscillator period are not independent of the number of stages [32].V.DETERMININGat the gate level requires a detailed analysisof each circuit-level noise source and depends on the partic-ular gate used as the delay element in the ring.For design illustration,the simple delay stage shown in Fig.3will be analyzed.The inputvoltageto one of the collectorloads,.Capacitorsand represent wiring stray,junction,and any explicit capacitances that may be present at the collector node.We begin the analysis by noting that the delay through the gate has two components:the delay through the differential pair(from ),and the delay through the emitter follower buffers(from.iv)The amplitude of the noise is much smaller than thedifferential signal.v)All noise sources are white and uncorrelated.As has been shown in the literature [37],the switching time of a differential pair depends on many factors,so some tradeoff of accuracy is necessary to obtain a simple analytical expression.Generally,as long as assumption iii)holds,the differential pair switches the tail current much faster than the RC time constant of the collector load,and assumption ii)introduces an error less than 20%of delay time.The error due to assumption i)is usually less than 10%.Although the error in delay time due to these assumptions is not insignificant,the assumptions are nevertheless justified since the resulting theory predicts jitter quite well and provides insights for guiding design.The following subsections derive theeffective(a)(b)(c)(d)Fig.5.(a)Noise model,(b)voltage waveforms,R C 1=R C 2thermal noise (noise effect exaggerated),(c)tail current source noise waveforms,and (d)differential input switching noisewaveforms..These sources appear directlyat,but are bandlimited bytheand poles.If the differential pair is represented by an ideal switch that is switched attimecrosses zero.For the noise-freewaveform,solving (4)for(6)The solid lines in the figure represent the actual collector waveforms,including the exaggerated effect of typical thermalnoisewaveformsand .By superposition,the noise waveforms simply “ride”on the ideal exponential.The result is that,at the time of the ideal differential waveformzero crossing,there is a voltageerror(7)The standard deviation of the differential voltage error issimply the square root of the sum of the squared(RSS)individual standarddeviations.Applying theJohnson noise equation gives the well-knownresult(8)Using(7)and(8)gives for the standard deviation of thetime error(thejitter)for the individual gate is determined by dividing thestandard deviation ofdelay by the square root of the averagedelay in(5)has dimensionsofcharacterizes the gate’s ability to resolve time(jitter)by anenergy uncertainty()as a fraction of the energyflow overtime(corresponds to improved jitter,(10)indicatesthat jitter improves when biascurrent is increased.This issimilar to results that have been reported for differential delaystages in CMOS ring oscillators[32],[33].Equation(10)alsoindicates that jitter is improved when the dc powerdissipationis large enough to fully switch thedifferential pair,the current noise is passed to the output,but isbandlimited by the eithertheor pole.Whenis reduced.The analysis can be simplified by using assumption iii)to idealize the differential pair as switching instantaneously.Fig.5(c)shows theresulting waveforms,aswell as the superimposed noisewaveforms.Priorto switching,the noise currentthroughwith standard deviation givenby,this voltage is sampledon.For decays exponentially with a timeconstantof,analysis shows[30]that the standard deviation“builds up”asinto(16)gives).Thermal Noise:If the tail current source is degenerated,the output noise will be dominated by the thermal noise ofthe degeneration resistor[38].Using the thermal noisedensityfraction of the energy flow over time(resultsinlowerof the preceding stage of the ring.Calculatingthe jitter effects of these sources is complicated by the fact that the gain from input to output depends on the signal amplitude.Fig.5(d)shows the input waveforms,the time-dependent transconductance,and the collectorvoltages.The input–output characteristic of a bipolar differential pairis(19)where tanh is the hyperbolic tangent function [39].The incre-mental gainis(20)where sech is the hyperbolic secant.For input signals that are large comparedtoand)into (23)gives).In this case,the relative magnitude of the total equivalent baseresistancemodel.For a white noise densityof is givenby(25)where rad/Vandfrom Different SourcesSinceeachof all sourcestogether is just the RSS combination of theindividual.Then (10),(16),(24),and (25)can be used in a noise budgeting process to assign contributions of each source to thetotal)and circuit-leveldesign considerations.For example,in the case of low power design,(10)and (18)set a limit on the best possible jitter that can be achieved for a given dc power dissipation.As another example,(24)shows that for a given equivalent baseresistance)temperature dependent as well.TABLE IIS UMMARY OF D ESIGNP ARAMETERS ,P REDICTED P ERFORMANCE ,ANDM EASURED RESULTSThe relationship between open-loop(,we can predict what the closed-loop performance should be if limited only by the VCO jitter.Then we can compare this prediction with actual closed-loop measurements to determine if performance is being degraded by jitter coupled from other on-chip circuitry.VII.E XPERIMENTAL R ESULTSA.SimulationTo test the results of the mathematical techniques developed in Section V,the effects of the individual noise sources in the circuit of Fig.5(a)were simulated using transient noise sources and a differential pair behavioral model following (19).The simulation environment allowed control over the circuit conditions so that it was possible to isolate the effects of individual noise sources,something that would be difficult if not impossible in a physical circuit.For each of the noise sources,circuit parameters were varied over an order of magnitude range around design center values.The simulated results [30]showed agreement to within 10%of thepredictedis given bysubstituting the circuit parameter values into (10),(16),(24),and (25).Combining these in RSS fashiongives s.The dashed line in Fig.4shows thepredicted.Good agreement is seenbetween this plot and the measured results.For the four-stage ring,the circuit implementation allowed variation inthe tail current.Table III gives the measured results and thepredicted.Usingthisand is quite good.Fig.7shows the measured closed-loopTABLE IIIMEASUREDR ESULTS AND P REDICTED V ERSUSIEEFig.6. versus tail current IEE.of 13.07ps rms for the 622MHz clock recovery PLL with a pseudorandom data input.VIII.C ONCLUSIONThis paper has developed a methodology to guide design of low-jitter,voltage controlled ring oscillators.The key design parameter is the time domain figure-of-merit,depends primarily on the individualgate and not on the number of gatesin the ring or the ring operating frequency.Explicit expressions were developed to provide a simple,direct means of relating jitter performance to fundamental design parameters.Experimental results at 155and 622MHz show that system-level jitter can be predicted to an accuracy of order 10%.A CKNOWLEDGMENTThe efforts of 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