微处理器80C86及其外围芯片协合效应实验研究
TEC-XP16实验指导书
计算机组成原理实验指导书王潇编写仲恺农业工程学院计算机科学与工程学院二00八年十月目录第一章TEC-XP16实验计算机系统原理 (1)§1.1TEC-XP16计算机组成原理实验系统概述 (1)§1.2TEC-XP16机指令系统 (8)§1.3TEC-XP16机运算器部件 (12)§1.4TEC-XP16机内存储器部件 (15)§1.5TEC-XP16机的控制器部件 (18)§1.6TEC-XP16机的输入输出及中断 (22)第二章TEC-XP16实验计算机系统实验内容 (24)实验一基础汇编语言程序设计 (24)实验二脱机运算器实验 (29)实验三存储器部件教学实验 (32)实验四组合逻辑控制器部件教学实验 (37)实验五微程序控制器部件教学实验 (51)实验六输入/输出接口扩展实验 (59)实验七中断实验 (63)实验八8位模型机的设计与实现(综合实验) (71)附录 (74)附录1 联机通讯指南 (74)附录2TEC-XP16计算机组成原理实验系统简明操作卡 (77)附录3微程序入口地址映射表 (78)附录4指令流程框图 (80)附录5指令流程表 (82)附录6书写实验报告的一般格式 (86)参考文献 (87)第一章TEC-XP16实验计算机系统原理§1.1 TEC-XP16计算机组成原理实验系统概述一、教学计算机系统的实现方案和硬软件资源概述TEC-XP是由清华大学计算机系和清华大学科教仪器厂联合研制的适用于计算机组成原理课程的实验系统，主要用于计算机组成原理和数字电路等的硬件教学实验，同时还支持监控程序、汇编语言程序设计、BASIC高级语言程序设计等软件方面的教学实验。
它的功能设计和实现技术，都紧紧地围绕着对课程教学内容的覆盖程度和所能完成的教学实验项目的质量与水平来进行安排。
其突出特点是硬、软件基本配置比较完整，能覆盖相关课程主要教学内容，支持的教学实验项目多且水平高。
80C196KC单片机电磁脉冲效应模拟实验研究
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摘要： 用电流注入模拟电磁脉冲耦合电流的方法对 Ｉ ｅ ８Ｃ ９Ｋ ｎ ｌ ０ １６ Ｃ单片机的电磁脉冲效应进行 了 ｔ 研究， 介绍了试验系统和方法， 给出了单片机输入端口、 输出端 口、 电源端Ｖ等端 １的工作状态电磁脉冲 Ｉ ２ Ｉ
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在每个电压点对指定端 口进行 ２ 次试验 ， Ｏ 记录 每次试验后单片机失效 （ 干扰或损 坏） 与否。采 用步进方式 逐步增 大 电压 的方法增加 注入 电
Intel80x86微处理器第06次课v2016pdf
• 段寄存器（4个）
– CS(代码段寄存器)、DS(数据段寄存器)、 – SS(堆栈段寄存器)、ES(附加段寄存器)
• 指令指针寄存器（1个）
– IP(指令指针)：指向当前指令代码段中的位置；
8086/8088 CPU内部寄存器及标志位中英名称对照表：
通用数据寄存器: AX 累加器 Accumulator register BX 基地址 Base address register CX 计数 Count register DX 数据 Data register
• • • • • • 8086/8088 CPU的功能结构 8086/8088 CPU的寄存器结构 8086/8088 CPU的引脚功能 8086/8088 CPU的工作模式 8086 微处理器的总线时序 8086/8088 CPU的存储器管理
•
微型计算机的工作过程
– 微机的工作过程就是执行程序的过程，也就是执行指令序列的过程，即周而复 始地取指令、分析指令和执行指令。 – 计算机的工作过程可以描述为：(P50 图2-22 2002版)
8086 EU BIU BUS 取指1 忙 执行1 取指2 忙 执行2 取指3 忙 执行3 取指4 忙 执行4 取指5 忙 执行5 取指6 忙 执行6
BUS
8086/8088 CPU内部结构
• BIU的组成：
– 四个16位的段寄存器(CS、DS、SS、ES)
– – – – –
16位指令指针IP 指令队列(6个/4个字节) 16位内部寄存器(与EU部件通信) 20位地址加法器() 输入/输出总线控制电路
CPU总线周期的基本概念；规则字的概念及其传送特点 √ 8086 微机系统的存储器组织；逻辑地址、物理地址的表示方法及其转换计算 √ 8086 微机系统（最小方式）的组成及特点 √
80x86汇编语言程序设计课后答案
80x86汇编语言程序设计课后答案【篇一：《80x86汇编语言程序设计》教案及答案(第二版)】汇编语言程序设计》(第2版)沈美明、温冬婵编著教案编写时间：2007年8月18日前言1. 汇编语言是计算机能提供给用户的最快而又最有效的语言，也是能够利用计算机所有硬件特性并能直接控制硬件的唯一语言。
2. 汇编语言程序设计是高等院校电子计算机硬、软件及应用专业学生必修的核心课程之一。
它不仅是计算机原理、操作系统等其它核心课程的必要先修课，而且对于训练学生掌握程序设计技术、熟悉上机操作和程序调试技术都有重要作用。
3. 本教材共有十一章，其内容安排如下：(1). 第一、二章为汇编语言所用的基础知识。
(2). 第三章详细介绍80x86系列cpu的指令系统和寻址方式。
(3). 第四章介绍伪操作、汇编语言程序格式及汇编语言的上机过程。
(4). 第五、六章说明循环、分支、子程序结构和程序设计的基本方法。
(5). 第七章说明宏汇编、重复汇编及条件汇编的设计方法。
(6). 第八章叙述输入/输出程序设计方法，重点说明中断原理、中断过程及中断程序设计方式。
(7). 第九章说明bios和dos系统功能调用的使用方法。
(8). 第十～十一章分别说明图形显示、发声及磁盘文件存储的程序设计方法，同时提供各种程序设计方法和程序实例。
附：教学参考书1. 沈美明、温冬婵编著，ibm–pc汇编语言程序设计(第2版)，清华大学出版社，2001年(教材)2. 沈美明、温冬婵编著，ibm–pc汇编语言程序设计，清华大学出版社，1991年3. 沈美明、温冬婵编著，ibm–pc汇编语言程序设计—例题习题集，清华大学出版社，1991年6月4. 沈美明、温冬婵、张赤红编著，ibm–pc汇编语言程序设计—实验教程，清华大学出版社，1992年5. 周明德，微型计算机ibm pc/xt(0520系列)系统原理及应用(修订版)，清华大学出版社，19916. 郑学坚、周斌，微型计算机原理及应用(第二版)，清华大学出版社，19957. 王士元、吴芝芳，ibm pc/xt[长城0520] 接口技术及其应用，南开大学出版社，19908. 杨素行，微型计算机系统原理及应用，清华大学出版社，19959. 戴梅萼、史嘉权，微型计算机技术及应用—从16位到32位(第二版)，清华大学出版社，199610. 张昆藏，ibm pc/xt微型计算机接口技术，清华大学出版社，199111. 孟绍光，李维星，高档微机组成原理及接口技术(80386/80486/pentium)，学苑出版社，199312. 吴秀清，周荷琴，微型计算机原理与接口技术，中国科学技术大学出版社目录第 1 章基础知识 ....................................................................................................... .. (1)1.1 进位计数制与不同基数的数之间的转换 (1)1.2 二进制数和十六进制数的运算 ....................................................................................................... .. (2)1.3 计算机中数和字符的表示 ....................................................................................................... . (3)1.4 几种基本的逻辑运算 ....................................................................................................... (3)第 2 章 80x86计算机组织 ....................................................................................................... . (4)2.1 80x86微处理器 ....................................................................................................... . (4)2.2 基于微处理器的计算机系统构成 ....................................................................................................... . (4)2.3 中央处理机 ....................................................................................................... . (5)2.4 存储器 ....................................................................................................... (6)2.5 外部设备 ....................................................................................................... .. (7)第 3 章 80x86的指令系统和寻址方式 ....................................................................................................... .. (8)3.1 80x86的寻址方式 ....................................................................................................... (8)3.2 程序占有的空间和执行时间 ....................................................................................................... . (10)3.3 80x86的指令系统 ....................................................................................................... . (10)第 4 章汇编语言程序格式 ....................................................................................................... .. (26)4.1 汇编程序功能 ....................................................................................................... . (26)4.2 伪操作 ....................................................................................................... . (26)4.3 汇编语言程序格式 ....................................................................................................... .. (30)4.4 汇编语言程序的上机过程 ....................................................................................................... .. (33)第 5 章循环与分支程序设计 ....................................................................................................... . (35)5.1 循环程序设计 ....................................................................................................... . (35)5.2 分支程序设计 ....................................................................................................... . (36)5.3 如何在实模式下发挥80386及其后继机型的优势 (36)第 6 章子程序结构 ....................................................................................................... .. (37)6.1 子程序的设计方法 ....................................................................................................... .. (37)6.2 子程序的嵌套 ....................................................................................................... . (38)6.3 子程序举例 ....................................................................................................... .. (38)第 7 章高级汇编语言技术 ....................................................................................................... .. (39)7.1 宏汇编 ....................................................................................................... . (39)7.2 重复汇编 ....................................................................................................... . (40)7.3 条件汇编 ....................................................................................................... . (41)第 8 章输入/输出程序设计 ....................................................................................................... . (42)8.1 i/o设备的数据传送方式 ....................................................................................................... .. (42)8.2 程序直接控制i/o方式 ....................................................................................................... . (43)8.3 中断传送方式 ....................................................................................................... . (43)第 9 章 bios和dos中断 ....................................................................................................... . (46)9.1 键盘i/o ....................................................................................................... .. (46)9.2 显示器i/o ....................................................................................................... . (48)9.3 打印机i/o ....................................................................................................... . (49)9.4 串行通信口i/o ....................................................................................................... .. (50)第 10 章图形与发声系统的程序设计 ....................................................................................................... ........... 51 10.1 显示方 (51)10.2 视频显示存储器 ....................................................................................................... .................................. 51 10.3 ega/vga图形程序设计 ....................................................................................................... .................... 52 10.4 通用发声程序 ....................................................................................................... ...................................... 53 10.5 乐曲程序 ....................................................................................................... . (54)第 11 章磁盘文件存取技术 ....................................................................................................... ........................... 55 11.1 磁盘的记录方式 ....................................................................................................... .................................. 55 11.2 文件代号式磁盘存取 ....................................................................................................... .......................... 56 11.3 字符设备的文件代号式i/o ....................................................................................................... ................ 57 11.4 bios磁盘存取功能 ....................................................................................................... .. (58)附录：《ibm—pc汇编语言程序设计》习题参考答案 ............................................................................... 59 第一章.第二章.第三章.第四章.第五章.第六章.第七章.第八章.第九章.第十章.第十一章. 习题 ....................................................................................................... ................. 59 习................. 60 习题 ....................................................................................................... ................. 61 习题 ....................................................................................................... ................. 74 习题 ....................................................................................................... ................. 79 习题 ....................................................................................................... ................. 97 习题 ....................................................................................................... ............... 110 习题 ....................................................................................................... ............... 117 习题 ....................................................................................................... ............... 122 习题 ....................................................................................................... ............... 125 习题 ....................................................................................................... (136)错误！未指定书签。
26616-微机原理与接口技术——基于8086和Proteus仿真(第2版)-习题参考答案
封面作者：PanHongliang仅供个人学习1.答：为了区别所使用的数制，一般用以下两种书写格式表示：①用括号将数字括起，后面加数制区分，数制用下标的形式给出；②用后缀区分，二进制数、十进制数、八进制数、十六进制数的后缀分别为字母B（或b）、D（或d）、O（或o）或Q（或q）、H（或h）。
例如：十六进制数56.78可以表示成(56.78)16或56.78H；十进制数56.78可以表示成(56.78)10或56.78D。
2.答：123D采用十进制，0AFH采用十六进制，77Q采用八进制，1001110B采用二进制。
3.答：字长为8位的二进制数原码表示的最大值：127，最小值：-127；补码表示的最大值：127，最小值：-128。
字长为16位的二进制数原码表示的最大值：32767，最小值：-32767；补码表示的最大值：32767，最小值：-32768。
4.答：(1)125D=0111 1101B=7DH(2) 255D=1111 1111B=FFH(3)72D=0100 1000B=48H(4)5090D=0001 0011 1110 0010B=13E2H5.答：(1)1111 0000B=240D=F0H(2) 1000 0000 B =128D =80H(3)1111 1111 B =255 D =FFH(4)0101 0101B=85D=55H6.答：(1)FFH=255D=1111 1111B(2) ABCDH=43947D=1010 1011 1100 1101B(3)123H=291D=0000 0001 0010 0011B(4)FFFFH=65535D=1111 1111 1111 1111B7.答：(1)8位时(16)原=0001 0000 ；(16)补=0001 0000；16位时(16)原=0000 0000 0001 0000 ；(16)补=0000 0000 0001 0000；(2) 8位时(-16)原=1001 0000 ；(-16)补=1111 0000；16位时(-16)原=1000 0000 0001 0000 ；(-16)补=1111 1111 1111 0000；(3)8位时(+0)原=0000 0000；(+0)补=0000 0000；16位时(+0)原=0000 0000 0000 0000；(+0)补=0000 0000 0000 0000；(4)8位时(-0)原=1000 0000 ；(-0)补=0000 0000；16位时(-0)原=1000 0000 0000 0000；(-0)补=0000 0000 0000 0000；(5)8位时(127)原=0111 1111；(127)补=0111 1111；16位时(127)原=0000 0000 0111 1111；(127)补=0000 0000 0111 1111；(6)8位时-128超过原码表示的范围；(-128)补=1000 0000；16位时(-128)原=1000 0000 1000 0000；(-128)补=1111 1111 1000 0000；(7)8位时(121)原=0111 1001 ；(121)补=0111 1001；16位时(121)原=0000 0000 0111 1001；(121)补=0000 0000 0111 1001；(8)8位时(-9)原=1000 1001 ；(-9)补=1111 0111；16位时(-9)原=1000 0000 0000 1001；(-9)补=1111 1111 1111 0111；8.答：（1）[x]补=1100 0010；（2）[-x]补=0000 1101；（3）[x]原=1100 0010；（4）[x]反=1011 1101。
第02章 Intel 80x86 系列微处理器(4)
同济大学电信学院2.3 Intel 80386/486 CPU2.3.1 80386/80486的主要特点2.3.2 80386/80486的内部结构2.3.3 80386/80486的三种工作方式2.3.1 80386/80486的主要特点●采用全32位结构，其内部寄存器、ALU和操作是32位，数据线和地址线均为32位●提供32位外部总线接口，最大数据传输率为32MB/s，具有自动切换数据总线宽度的功能●具有片内集成的存储器管理部件MMU，可支持虚拟存储和特权保护，虚拟存储器空间可达64太字节（TB）●具有实地址方式、保护方式和虚拟8086方式3种工作方式●采用了比8086更先进的流水线结构，使其能高效、并行地完成取指、译码、执行和存储管理功能(指令队列16字节长）同济大学电信学院2.3.2 80386/80486内部结构同济大学电信学院同济大学电信学院80386内部结构●总线接口部件（BIU ）●指令预取部件（IPU ）●指令译码部件（IDU ）●指令执行部件（EU ）●分段部件（SU ）●分页部件（PU ）80386内部结构●总线接口部件（BIU）◆微处理器与系统的接口，其功能是：在取指令、取数据、分段部件请求和分页部件请求时，有效地满足微处理器对外部总线的传输要求。
◆BIU能接收多个内部总线请求，并且能按优先权加以选择，最大限度地利用所提供的总线宽度，为这些请求服务。
●指令预取部件（IPU）◆职责是从存储器预先取出指令◆有一个能容纳16条指令的队列同济大学电信学院同济大学电信学院80386内部结构●指令译码部件（IDU ）◆职责是从预取部件的指令队列中取出指令字节，对它们进行译码后存入自身的已译码指令队列中，并且作好供执行部件处理的准备工作。
◆如果在预译码时发现是转移指令，可提前通知总线接口部件BIU去取目标地址中的指令，取代原预取队列中的顺序指令。
80386内部结构●指令执行部件（EU）◆由控制部件、数据处理部件和保护测试部件组成。
新型的L80C86 CPU电路电磁脉冲试验方法
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Ｋｅ ｒ ｓ： ｙ ｗｏ ｄ ＣＰＵ ； ＥＭＰ； ｇ ｓｅ Ｒｅ ｉｔｒ
１ 引 言
随着各国对 电磁脉冲效应 的广泛关 注， 如何更
好的测试 电磁脉 冲效应也越显重要。经过几年对 电
以利用 ８ Ｃ ６的 Ｎ Ｉ ０８ Ｍ 中断 ， 获得其内部寄存器的内 容。②实验过程中， 系统先将 当前 ８ Ｃ ６内部寄存 ０８ 器值传送到 Ｐ ｃ端 ， 然后进行一次效应实验 ， 接着系
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统再将 ８ Ｃ ６当前 寄存器值 传送给 Ｐ ０８ ｃ机 。Ｐ ｃ机
磁脉冲效应的试验 ， 我们初步探索 出了对 Ｃ Ｕ类 电 Ｐ 路进行电磁脉冲效应 的试验方法。通过一次电磁脉
冲效应试验介绍 了这种新型的试验方法。
第二章80x86微处理器解析
第二章 80x86微处理器
合肥工业大学计算机与信息学院 2012-02
第二章 80x86微处理器
2.1 微处理器的基本结构 2.2 Intel8086微处理器 2.3 8086中的程序状态字和堆栈 2.4 8086系统的组成 2.5 8086系统时钟和总线周期 2.6 80386微处理器* 2.7 80486微处理器* 2.8 Pentium处理器*
时钟启停逻辑用作控制启停主脉冲信号的开关，按指令和 控制台的要求，可准确地开启或关闭时钟脉冲序列。
➢ 脉冲分配器
产生计算机各部分所需的能按一定顺序逐个出现的节拍 电位，以控制和协调计算机各部分有节奏地动作。
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2.1.2 控制器
微操作控制——产生各部件所需的控制信号
☆什么是微操作？
微型计算机执行一条指令，通常是把一条指令分成若干 个基本动作（微操作），并在节拍和脉冲信号指挥下完 成一个微操作。
➢ 所以，在不考虑数据信息表示方式的情况下，计算机 只要具备加法、“与”、“或”、“非”等运算和移 位操作功能，就能实现各种算术运算和逻辑运算。
算术逻辑单元(Arithmetic Logic Unit，ALU)
➢ 是一个对二进制数进行算术和逻辑运算的部件。
4
2.1.1 算术逻辑单元ALU
ALU的主要功能
➢ 实现方式3：可编程序逻辑阵列控制
通过程序设计来执行特定逻辑功能的组合逻辑结构。 优点：具有上述两种控制的优点。
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2.1 微处理器的基本结构
1. 算术逻辑单元ALU 2. 控制器 3. 总线与总线缓冲器 4. 寄存器阵列
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2.1.3 总线与总线缓冲器
片内总线
➢ 在微处理器内部各单元之间传送信息的总线。
80C86
S E M I C O N D U C T O R80C86CMOS 16-Bit MicroprocessorFeatures•Compatible with NMOS 8086•Completely Static CMOS Design-DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5MHz (80C86) -DC . . . . . . . . . . . . . . . . . . . . . . . . . . . .8MHz (80C86-2)•Low Power Operation-lCCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500µA Max -ICCOP . . . . . . . . . . . . . . . . . . . . . . . . .10mA/MHz Typ•1MByte of Direct Memory Addressing Capability•24 Operand Addressing Modes•Bit, Byte, Word and Block Move Operations•8-Bit and 16-Bit Signed/Unsigned Arithmetic-Binary, or Decimal-Multiply and Divide•Wide Operating Temperature Range-C80C86 . . . . . . . . . . . . . . . . . . . . . . . . . .0o C to +70o C -l80C86 . . . . . . . . . . . . . . . . . . . . . . . . .-40o C to +85o C -M80C86 . . . . . . . . . . . . . . . . . . . . . . .-55o C to +125o C DescriptionThe Harris 80C86 high performance 16-bit CMOS CPU is manufactured using a self-aligned silicon gate CMOS pro-cess (Scaled SAJI IV). T wo modes of operation, minimum for small systems and maximum for larger applications such as multiprocessing, allow user configuration to achieve the highest performance level. Full TTL compatibility (with the exception of CLOCK) and industry standard operation allow use of existing NMOS 8086 hardware and software designs. Ordering InformationPACKAGE TEMP. RANGE5MHz8MHzPKG.NO. PDIP0o C to +70o C CP80C86CP80C86-2E40.6-40o C to +85o C lP80C86IP80C86-2E40.6 PLCC0o C to +70o C CS80C86CS80C86-2N44.65 -40o C to +85o C lS80C86IS80C86-2N44.65 CERDIP 0o C to +70o C CD80C86CD80C86-2F40.6-40o C to +85o C ID80C86ID80C86-2F40.6-55o C to +125o C MD80C86/B MD80C86-2/BF40.6 SMD#-55o C to +125o C8405201QA8405202QA F40.6 CLCC-55o C to +125o C MR80C86/B MR80C86-2/BJ44.A SMD#-55o C to +125o C8405201XA8405202XA J44.AMarch 1997File Number2957.1 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.Pinouts80C86 (DIP)TOP VIEW80C86 (PLCC, CLCC)TOP VIEW1312345678910111214151617181920GND AD14AD13AD12AD11AD10AD9AD8AD7AD6AD5AD4AD3AD2AD1AD0NMI INTR CLK GND2840393837363534333231302927262524232221V CC AD15A16/S3A17/S4A18/S5A19/S6BHE/S7MN/MX RD RQ/GT0RQ/GT1LOCK S2S1S0QS0QS1TEST READY RESET(INTA)(ALE)(DEN)(DT/R))(M/IO)(WR)(HLDA)(HOLD)MAX (MIN)1413121110987171615253035393837363334323129463140414243442827262524232221201918A19/S6BHE/S7MN/MX RD HOLD HLDA WR M/IO DT/R DENNC NC A19/S6BHE/S7MN/MX RD RQ/GT0RQ/GT1LOCK S2S1S0AD9AD8AD7AD6AD5AD4AD3AD2AD1AD0AD10AD10AD9AD8AD7AD6AD5AD4AD3AD2AD1AD0A D 12A D 13A D 14G N DN CV C CA D 15A 16/S 3A 17/S 4A 18/S 5A D 11A D 11A D 12A D 13A D 14G N DN CV C CA D 15A 16/S 3A 17/S 4A 18/S 5N M II N T RC L KG N DN CR E S E TR E A D YT E S TQ S 1Q S 0N CN CN M II N T RC L KG N DN CR E S E TR E A D YT E S TI N T AA L EMAX MODE 80C86MIN MODE 80C86MAX MODE 80C86MIN MODE 80C86Functional DiagramREGISTER FILE EXECUTION UNIT CONTROL AND TIMINGINSTRUCTION QUEUE6-BYTE FLAGS16-BIT ALU BUS INTERFACE UNIT164QS0, QS1S2,S1,S0243GNDV CCCLKRESET READY BUS INTERFACE UNITRELOCATION REGISTER FILE 3A19/S6A16/S3INTA,RD,WR DT/R,DEN, ALE, M/IOBHE/S72SEGMENT REGISTERSANDINSTRUCTION POINTER(5 WORDS)DATA POINTERANDINDEX REGS (8 WORDS)TEST INTR NMI HLDAHOLD RQ/GT0,1LOCKMN/MX 3ESCS SS DS IPAH BH CHDHAL BL CL DLSP BP SI DIARITHMETIC/LOGIC UNITB-BUS C-BUSEXECUTIONUNITINTERFACEUNITBUSQUEUEINSTRUCTION STREAM BYTEEXECUTION UNIT CONTROL SYSTEMFLAGSMEMORY INTERFACEA-BUSAD15-AD0Pin DescriptionThe following pin function descriptions are for 80C86 systems in either minimum or maximum mode. The “Local Bus” in these description is the direct multiplexed bus interface connection to the 80C86 (without regard to additional bus buffers).SYMBOL PIN NUMBER TYPE DESCRIPTIONAD15-AD02-16, 39I/OADDRESS DATA BUS: These lines constitute the time multiplexed memory/lO address (T1) and data (T2, T3, TW, T4) bus. A0 is analogous to BHE for the lower byte of the data bus, pins D7-D0. It is LOW during Ti when a byte is to be transferred on the lower portion of the bus in memory or I/O operations. Eight-bit oriented devices tied to the lower half would normally use A0 to con-dition chip select functions (See BHE). These lines are active HIGH and are held at high imped-ance to the last valid logic level during interrupt acknowledge and local bus “hold acknowledge”or “grant sequence”.A19/S6A18/S5A17/S4A16/S335-38OADDRESS/STATUS: During T1, these are the four most significant address lines for memory op-erations. During I/O operations these lines are LOW. During memory and I/O operations, status information is available on these lines during T2, T3, TW, T4. S6 is always LOW. The status of the interrupt enable FLAG bit (S5) is updated at the beginning of each clock cycle. S4 and S3are encoded as shown.This information indicates which segment register is presently being used for data accessing.These lines are held at high impedance to the last valid logic level during local bus “hold ac-knowledge” or “grant sequence”.BHE/S734OBUS HIGH ENABLE/STATUS: During T1 the bus high enable signal (BHE) should be used to enable data onto the most significant half of the data bus, pins D15-D8. Eight bit oriented devices tied to the upper half of the bus would normally use BHE to condition chip select functions.BHE is LOW during T1 for read, write, and interrupt acknowledge cycles when a byte is to be trans-ferred on the high portion of the bus. The S7 status information is available during T2, T3 and T4. The signal is active LOW, and is held at high impedance to the last valid logic level during interrupt acknowledge and local bus “hold acknowledge” or “grant sequence”, it is LOW during T1 for the first interrupt acknowledge cycle.RD 32OREAD: Read strobe indicates that the processor is performing a memory or I/O read cycle, de-pending on the state of the M/IO or S2 pin. This signal is used to read devices which reside on the 80C86 local bus.RD is active LOW during T2, T3 and TW of any read cycle, and is guaran-teed to remain HIGH in T2 until the 80C86 local bus has floated.This line is held at a high impedance logic one state during “hold acknowledge” or “grand se-quence”.READY 22IREADY: is the acknowledgment from the addressed memory or I/O device that will complete the data transfer. The RDY signal from memory or I/O is synchronized by the 82C84A Clock Gener-ator to form READY . This signal is active HIGH. The 80C86 READY input is not synchronized.Correct operation is not guaranteed if the Setup and Hold Times are not met.S4S3CHARACTERISTICS 00Alternate Data 01Stack 10Code or None 11DataBHE A0CHARACTERISTICS00Whole Word01Upper Byte From/to Odd Address 10Lower Byte From/to Even address 11NoneINTR18IINTERRUPT REQUEST: is a level triggered input which is sampled during the last clock cycle of each instruction to determine if the processor should enter into an interrupt acknowledge op-eration. A subroutine is vectored to via an interrupt vector lookup table located in system mem-ory. It can be internally masked by software resetting the interrupt enable bit.lNTR is internally synchronized. This signal is active HIGH.TEST 23ITEST: input is examined by the “Wait” instruction. If the TEST input is LOW execution continues,otherwise the processor waits in an “Idle”state. This input is synchronized internally during each clock cycle on the leading edge of CLK.NMI 17INON-MASKABLE INTERRUPT: is an edge triggered input which causes a type 2 interrupt. A subroutine is vectored to via an interrupt vector lookup table located in system memory. NMI is not maskable internally by software. A transition from LOW to HIGH initiates the interrupt at the end of the current instruction. This input is internally synchronized.RESET 21IRESET: causes the processor to immediately terminate its present activity. The signal must tran-sition LOW to HIGH and remain active HIGH for at least four clock cycles. It restarts execution,as described in the Instruction Set description, when RESET returns LOW. RESET is internally synchronized.CLK 19ICLOCK: provides the basic timing for the processor and bus controller. It is asymmetric with a 33% duty cycle to provide optimized internal timing.VCC 40VCC: +5V power supply pin. A 0.1µF capacitor between pins 20 and 40 is recommended for de-coupling.GND 1, 20GND: Ground. Note: both must be connected. A 0.1µF capacitor between pins 1 and 20 is rec-ommended for decoupling.MN/MX 33IMINIMUM/MAXIMUM: Indicates what mode the processor is to operate in. The two modes are discussed in the following sections.Minimum Mode SystemThe following pin function descriptions are for the 80C86 in minimum mode (i.e., MN/MX = V CC ). Only the pin functions which are unique to minimum mode are described; all other pin functions are as described below.SYMBOL PIN NUMBERTYPE DESCRIPTIONM/IO28OSTATUS LINE: logically equivalent to S2 in the maximum mode. It is used to distinguish a mem-ory access from an I/O access. M/lO becomes valid in the T4 preceding a bus cycle and remains valid until the final T4 of the cycle (M = HIGH, I/O = LOW). M/lO is held to a high impedance logic one during local bus “hold acknowledge”.WR 29OWRITE: indicates that the processor is performing a write memory or write I/O cycle, depending on the state of the M/IO signal.WR is active for T2, T3 and TW of any write cycle. It is active LOW, and is held to high impedance logic one during local bus “hold acknowledge”.INTA 24OINTERRUPT ACKNOWLEDGE: is used as a read strobe for interrupt acknowledge cycles. It is active LOW during T2, T3 and TW of each interrupt acknowledge cycle. Note that INTA is never floated.ALE 25OADDRESS LATCH ENABLE: is provided by the processor to latch the address into the 82C82/82C83 address latch. It is a HIGH pulse active during clock LOW of T1 of any bus cycle.Note that ALE is never floated.Pin Description (Continued)The following pin function descriptions are for 80C86 systems in either minimum or maximum mode. The “Local Bus” in these description is the direct multiplexed bus interface connection to the 80C86 (without regard to additional bus buffers).SYMBOL PIN NUMBERTYPE DESCRIPTIONDT/R27O DATA TRANSMIT/RECEIVE: is needed in a minimum system that desires to use a data bustransceiver. It is used to control the direction of data flow through the transceiver. Logically,DT/R is equivalent to S1 in maximum mode, and its timing is the same as for M/IO (T = HIGH,R = LOW). DT/R is held to a high impedance logic one during local bus “hold acknowledge”. DEN26O DATA ENABLE: provided as an output enable for a bus transceiver in a minimum system whichuses the transceiver.DEN is active LOW during each memory and I/O access and for INTA cy-cles. For a read or INTA cycle it is active from the middle of T2 until the middle of T4, while for awrite cycle it is active from the beginning of T2 until the middle of T4.DEN is held to a high im-pedance logic one during local bus “hold acknowledge”.HOLD HLDA 31, 30IOHOLD: indicates that another master is requesting a local bus “hold”. To be an acknowledged,HOLD must be active HIGH. The processor receiving the “hold” will issue a “hold acknowledge”(HLDA) in the middle of a T4 or TI clock cycle. Simultaneously with the issuance of HLDA, theprocessor will float the local bus and control lines. After HOLD is detected as being LOW, theprocessor will lower HLDA, and when the processor needs to run another cycle, it will again drivethe local bus and control lines.HOLD is not an asynchronous input. External synchronization should be provided if the systemcannot otherwise guarantee the setup time.Maximum Mode SystemThe following pin function descriptions are for the 80C86 system in maximum mode (i.e., MN/MX - GND). Only the pin functions which are unique to maximum mode are described below.SYMBOLPINNUMBER TYPE DESCRIPTIONS0 S1 S2262728OOOSTATUS: is active during T4, T1 and T2 and is returned to the passive state (1, 1, 1) during T3or during TW when READY is HIGH. This status is used by the 82C88 Bus Controller to generateall memory and I/O access control signals. Any change by S2,S1 or S0 during T4 is used toindicate the beginning of a bus cycle, and the return to the passive state in T3 or TW is used toindicate the end of a bus cycle.These signals are held at a high impedance logic one state during “grant sequence”.minimum mode are described; all other pin functions are as described below.SYMBOLPINNUMBER TYPE DESCRIPTIONS2S1S0CHARACTERISTICS000Interrupt Acknowledge001Read I/O Port010Write I/O Port011Halt100Code Access101Read Memory110Write Memory111PassiveRQ/GT0RQ/GT131, 30I/OREQUEST/GRANT: pins are used by other local bus masters to force the processor to release the local bus at the end of the processor’s current bus cycle. Each pin is bidirectional withRQ/GTO having higher priority than RQ/GT1.RQ/GT has an internal pull-up bus hold device so it may be left unconnected. The request/grant sequence is as follows (see RQ/GT Sequence Timing)1. A pulse of 1 CLK wide from another local bus master indicates a local bus request (“hold”)to the 80C86 (pulse 1).2.During a T4 or TI clock cycle, a pulse 1 CLK wide from the 80C86 to the requesting master (pulse 2) indicates that the 80C86 has allowed the local bus to float and that it will enter the “grant sequence” state at the next CLK. The CPU’s bus interface unit is disconnected logi-cally from the local bus during “grant sequence”.3. A pulse 1 CLK wide from the requesting master indicates to the 80C86 (pulse 3) that the “hold” request is about to end and that the 80C86 can reclaim the local bus at the next CLK.The CPU then enters T4 (or TI if no bus cycles pending).Each Master-Master exchange of the local bus is a sequence of 3 pulses. There must be one idle CLK cycle after each bus exchange. Pulses are active low.If the request is made while the CPU is performing a memory cycle, it will release the local bus during T4 of the cycle when all the following conditions are met:1.Request occurs on or before T2.2.Current cycle is not the low byte of a word (on an odd address).3.Current cycle is not the first acknowledge of an interrupt acknowledge sequence.4.A locked instruction is not currently executing.If the local bus is idle when the request is made the two possible events will follow:1.Local bus will be released during the next cycle.2. A memory cycle will start within three clocks. Now the four rules for a currently active memory cycle apply with condition number 1 already satisfied.LOCK 29OLOCK: output indicates that other system bus masters are not to gain control of the system bus while LOCK is active LOW. The LOCK signal is activated by the “LOCK” prefix instruction and remains active until the completion of the next instruction. This signal is active LOW, and is held at a high impedance logic one state during “grant sequence”. In MAX mode,LOCK is automat-ically generated during T2 of the first INT A cycle and removed during T2 of the second INT A cycle.QS1, QSO 24, 25OQUEUE STATUS: The queue status is valid during the CLK cycle after which the queue opera-tion is performed.QS1 and QS0 provide status to allow external tracking of the internal 80C86 instruction queue.Note that QS1, QS0 never become high impedance.unique to maximum mode are described below.SYMBOL PIN NUMBER TYPE DESCRIPTIONQSI QSO 00No Operation01First byte of op code from queue 10Empty the queue11Subsequent byte from queueFunctional DescriptionStatic OperationAll 80C86 circuitry is of static design. Internal registers, counters and latches are static and require no refresh as with dynamic circuit design. This eliminates the minimum operating frequency restriction placed on other microproces-sors. The CMOS 80C86 can operate from DC to the speci-fied upper frequency limit. The processor clock may be stopped in either state (HIGH/LOW) and held there indefi-nitely. This type of operation is especially useful for system debug or power critical applications.The 80C86 can be single stepped using only the CPU clock. This state can be maintained as long as is necessary. Single step clock operation allows simple interface circuitry to pro-vide critical information for bringing up your system.Static design also allows very low frequency operation (down to DC). In a power critical situation, this can provide extremely low power operation since 80C86 power dissipa-tion is directly related to operating frequency. As the system frequency is reduced, so is the operating power until, ulti-mately, at a DC input frequency, the 80C86 power require-ment is the standby current, (500µA maximum).Internal ArchitectureThe internal functions of the 80C86 processor are parti-tioned logically into two processing units. The first is the Bus Interface Unit (BlU) and the second is the Execution Unit (EU) as shown in the CPU functional diagram.These units can interact directly, but for the most part perform as separate asynchronous operational processors. The bus interface unit provides the functions related to instruction fetching and queuing, operand fetch and store, and address relocation. This unit also provides the basic bus control. The overlap of instruction pre-fetching provided by this unit serves to increase processor performance through improved bus bandwidth utilization. Up to 6 bytes of the instruction stream can be queued while waiting for decoding and execution.The instruction stream queuing mechanism allows the BIU to keep the memory utilized very efficiently. Whenever there is space for at least 2 bytes in the queue, the BlU will attempt a word fetch memory cycle. This greatly reduces “dead-time”on the memory bus. The queue acts as a First-In-First-Out (FIFO) buffer, from which the EU extracts instruction bytes as required. If the queue is empty (following a branch instruction, for example), the first byte into the queue imme-diately becomes available to the EU.The execution unit receives pre-fetched instructions from the BlU queue and provides un-relocated operand addresses to the BlU. Memory operands are passed through the BIU for pro-cessing by the EU, which passes results to the BIU for storage. Memory OrganizationThe processor provides a 20-bit address to memory, which locates the byte being referenced. The memory is organized as a linear array of up to 1 million bytes, addressed as 00000(H) to FFFFF(H). The memory is logically divided into code, data, extra and stack segments of up to 64K bytes each, with each segment falling on 16-byte boundaries. (See Figure 1).All memory references are made relative to base addresses contained in high speed segment registers. The segment types were chosen based on the addressing needs of pro-grams. The segment register to be selected is automatically chosen according to the specific rules of Table 1. All informa-tion in one segment type share the same logical attributes (e.g. code or data). By structuring memory into re-locatable areas of similar characteristics and by automatically select-ing segment registers, programs are shorter, faster and more structured. (See Table 1).Word (16-bit) operands can be located on even or odd address boundaries and are thus, not constrained to even boundaries as is the case in many 16-bit computers. For address and data operands, the least significant byte of the word is stored in the lower valued address location and the most significant byte in the next higher address location. The BIU automatically performs the proper number of memoryTABLE 1.TYPE OFMEMORYREFERENCEDEFAULTSEGMENTBASEALTERNATESEGMENTBASE OFFSET Instruction Fetch CS None IPStack Operation SS None SP Variable (exceptfollowing)DS CS, ES, SS EffectiveAddress String Source DS CS, ES, SS SIString Destination ES None DIBP Used As BaseRegisterSS CS, DS, ES EffectiveAddress SEGMENTREGISTER FILECSSSDSES64K-BIT+ OFFSETFFFFFHCODE SEGMENTXXXXOHSTACK SEGMENTDATA SEGMENTEXTRA SEGMENT00000HFIGURE 1.80C86 MEMORY ORGANIZATIONaccesses; one, if the word operand is on an even byte boundary and two, if it is on an odd byte boundary. Except for the performance penalty,this double access is transpar-ent to the software. The performance penalty does not occur for instruction fetches; only word operands.Physically, the memory is organized as a high bank (D15-D8) and a low bank (D7-D0) of 512K bytes addressed in par-allel by the processor’s address lines.Byte data with even addresses is transferred on the D7-D0 bus lines, while odd addressed byte data (A0 HIGH) is trans-ferred on the D15-D8 bus lines. The processor provides two enable signals, BHE and A0, to selectively allow reading from or writing into either an odd byte location, even byte location, or both. The instruction stream is fetched from memory as words and is addressed internally by the proces-sor at the byte level as necessary.In referencing word data, the BlU requires one or two memory cycles depending on whether the starting byte of the word is on an even or odd address, respectively. Consequently, in ref-erencing word operands performance can be optimized by locating data on even address boundaries. This is an espe-cially useful technique for using the stack, since odd address references to the stack may adversely affect the context switching time for interrupt processing or task multiplexing. Certain locations in memory are reserved for specific CPU operations (See Figure 2). Locations from address FFFF0H through FFFFFH are reserved for operations including a jump to the initial program loading routine. Following RESET, the CPU will always begin execution at location FFFF0H where the jump must be located. Locations 00000H through 003FFH are reserved for interrupt operations. Each of the 256 possible interrupt service routines is accessed thru its own pair of 16-bit pointers (segment address pointer and offset address pointer). The first pointer, used as the offset address, is loaded into the lP and the second pointer, which designates the base address is loaded into the CS. At this point program control is transferred to the interrupt routine. The pointer ele-ments are assumed to have been stored at the respective places in reserved memory prior to occurrence of interrupts. Minimum and Maximum Operation ModesThe requirements for supporting minimum and maximum 80C86 systems are sufficiently different that they cannot be met efficiently using 40 uniquely defined pins. Consequently, the 80C86 is equipped with a strap pin (MN/MX) which defines the system configuration. The definition of a certain subset of the pins changes, dependent on the condition of the strap pin. When the MN/MX pin is strapped to GND, the 80C86 defines pins 24 through 31 and 34 in maximum mode. When the MN/MX pin is strapped to V CC, the 80C86 gener-ates bus control signals itself on pins 24 through 31 and 34. The minimum mode 80C86 can be used with either a multi-plexed or demultiplexed bus. This architecture provides the 80C86 processing power in a highly integrated form.The demultiplexed mode requires two 82C82 latches (for 64K addressability) or three 82C82 latches (for a full megabyte of addressing). An 82C86 or 82C87 transceiver can also be used if data bus buffering is required. (See Figure 6A.) The 80C86 provides DEN and DT/R to control the transceiver, and ALE to latch the addresses. This configuration of the minimum mode provides the standard demultiplexed bus structure with heavy bus buffering and relaxed bus timing requirements.The maximum mode employs the 82C88 bus controller (See Figure 6B). The 82C88 decodes status lines S0,S1 and S2, and provides the system with all bus control signals.Moving the bus control to the 82C88 provides better source and sink current capability to the control lines, and frees the 80C86 pins for extended large system features. Hardware lock, queue status, and two request/grant interfaces are pro-vided by the 80C86 in maximum mode. These features allow coprocessors in local bus and remote bus configurations. Bus OperationThe 80C86 has a combined address and data bus com-monly referred to as a time multiplexed bus. This technique provides the most efficient use of pins on the processor while permitting the use of a standard 40 lead package. This “local bus” can be buffered directly and used throughout the system with address latching provided on memory and I/O modules. In addition, the bus can also be demultiplexed at the processor with a single set of 82C82 address latches if a standard non-multiplexed bus is desired for the system. Each processor bus cycle consists of at least four CLK cycles. These are referred to as T1, T2, T3and T4(see Fig-ure 3). The address is emitted from the processor during T1 and data transfer occurs on the bus during T3 and T4. T2is used primarily for changing the direction of the bus during read operations. In the event that a “NOT READY” indication is given by the addressed device, “Wait” states (TW) are inserted between T3and T4.Each inserted wait state is the same duration as a CLK cycle. Periods can occur between 80C86 driven bus cycles. These are referred to as idle”states (T I) or inactive CLK cycles. The processor uses these cycles for internal housekeeping and processing.During T1of any bus cycle, the ALE (Address Latch Enable) signal is emitted (by either the processor or the 82C88 bus controller, depending on the MN/MX strap). At the trailing edge of this pulse, a valid address and certain status infor-mation for the cycle may be latched.Status bits S0,S1 and S2 are used by the bus controller, in maximum mode, to identify the type of bus transaction according to Table 2.TABLE 2.S2S1S0CHARACTERISTICS000Interrupt001Read I/O010Write I/O011Halt100Instruction Fetch101Read Data from Memory110Write Data to Memory111Passive (No Bus Cycle)Status bits S3 through S7 are time multiplexed with high order address bits and the BHE signal, and are therefore valid during T2 through T4. S3 and S4 indicate which seg-ment register (see Instruction Set Description) was used for this bus cycle in forming the address, according to Table 3.S5 is a reflection of the PSW interrupt enable bit. S3 is always zero and S7 is a spare status bit.I/O AddressingIn the 80C86, I/O operations can address up to a maximum of 64K I/O byte registers or 32K I/O word registers. The I/O address appears in the same format as the memory address on bus lines A15-A0. The address lines A19-A16 are zero in I/O operations. The variable I/O instructions which use regis-ter DX as a pointer have full address capability while the direct I/O instructions directly address one or two of the 256I/O byte locations in page 0 of the I/O address space.I/O ports are addressed in the same manner as memory loca-tions. Even addressed bytes are transferred on the D7-D0 bus lines and odd addressed bytes on D15-D8. Care must be taken to ensure that each register within an 8-bit peripheral located on the lower portion of the bus be addressed as even.TABLE 3.S4S3CHARACTERISTICS00Alternate Data (Extra Segment)01Stack 10Code or None 11DataTYPE 225 POINTER(AVAILABLE)RESET BOOTSTRAP PROGRAM JUMPTYPE 33 POINTER (AVAILABLE)TYPE 32 POINTER (AVAILABLE)TYPE 31 POINTER (AVAILABLE)TYPE 5 POINTER (RESERVED)TYPE 4 POINTER OVERFLOW TYPE 3 POINTER1 BYTE INT INSTRUCTIONTYPE 2 POINTER NON MASKABLE TYPE 1 POINTER SINGLE STEP TYPE 0 POINTER DIVIDE ERROR16 BITSCS BASE ADDRESSIP OFFSET014H 010H 00CH008H 004H 000H07FH080H 084H FFFF0HFFFFFH 3FFH 3FCHAVAILABLE INTERRUPT POINTERS(224)DEDICATED INTERRUPT POINTERS(5)RESERVED INTERRUPT POINTERS(27)FIGURE 2.RESERVED MEMORY LOCATIONS。
2)80x86微处理器
二、8086中的寄存器 １、通用寄存器 4个16位寄存器: AX,BX,CX,DX。 其中AX是累加器。 8个8位寄存器： AH,AL,BH,BL,CH,CL,DH,DL。 ２、专用寄存器 SP：堆栈指针寄存器, 用于确定堆栈在内存中位置 BP：基数指针寄存器, 用于寄存器间接寻址中 SI：源变址寄存器, 用于寄存器间接寻址中 DI：目的变址寄存器, 用于寄存器间接寻址
第二章
§１
80x86微处理器
8086/8088的结构
8086/8088CPU是Intel公司于1978年推出的一种16位 微处理器，是最早投入市场的16位CPU产品之一。其 中8086CPU外部数据总线是16位的，而8088CPU外部 数据总线是8位的。
Hale Waihona Puke 主要特点如下：数据总线16位,能处理16位数据,也能处理8位数据。 地址总线20位,可寻址的地址空间为1m字节。 在汇编语言上与8080/8085兼容 时钟频率为5mhz 具有一整套以之相配的外围接口芯片 采用单－５V电源
６、WR：写信号、输出、低电平有效 ７、HOLD：总线保持请求信号、输入、高电平有效。 此信号是CPU之外的其他主部件要求占用总线，向CPU 发出的请求信号。 ８、HLDA：总线保持响应信号、输出、高电平有效。 此信号表示CPU对其他主部件的总线请求作出响应， 与此同时，所有与三态门相接的CPU的引脚呈现高 阻，从而让出了总线。
实际上，1m字节存贮器分成两个体，偶数地址单元 形成一个体，其数据线连数据总线低8位,而奇数地 址形成一个体,其数据线连数据总线高8位。 ３、I/O编址
第2章80x86微处理器
主讲 曹红波
第2章:80x86微处理器
2.1 微处理器的发展 2.2 8086微处理器 2.3 80286微处理器
2.4 80386微处理器
2.5 80486微处理器
2.6 Pentium系列微处理器
第二章:80x86微处理器
2.1 微处理器的发展
第一代(1971～1973) 第二代(1974～1977) 第三代(1978～1984) 第四代(1985～1999) 第五代(2000年至今) 4位和低档8位微处理器时代 8位微处理器时代 16位微处理器时代 32位微处理器时代 64位高档微处理器时代
例如： 3AH + 7CH＝B6H AAH + 7CH＝26H
（1）
产生溢出：OF=1
没有溢出：OF=0
问题：
什么是溢出？ 溢出和进位有什么区别？ 处理器怎么处理，程序员如何运用？ 如何判断是否溢出？
下午4时33分 25
什么是溢出
―溢出”针对有符号数
处理器内部以补码表示有符号数 8位表示范围是： -128 ~ +127 16位表示范围是： -32768 ~+32767 如果运算结果超出了这个范围，就是产生了溢出，
7
8086的编程结构
1． 总线接口部件
功能：负责与CPU外部传送数据 （ROM RAM，IO）
下午4时33分
8
1． 总线接口部件
BIU组成部分： (1) 4个段寄存器 CS—码段寄存器。用于存放代码段的段基址。 DS—数据段寄存器。用于存放数据段的段基址。 SS—堆栈段寄存器。用于存放堆栈段的段基址。 ES—附加段寄存器。用于存放附加段的段基址。
下午4时33分
80x86微处理器
1.1 80x86微处理器的发展历程及性能
1.80286微处理器 2.80386微处理器 3.80486微处理器 4.Pentium微处理器 5.Pentium MMX 6.Pentium Pro 7.Pentium Ⅱ 8.Pentium Ⅲ 9.Pentium 4 10.Intel Core 2 Duo
2021年1月30日星期六
1.2 80386的内部结构
1.80386的主要特性 （1）灵活的32位微处理器，提供32位指令，可采用8位、16位或
32位的数据宽度。 （2）提供32位外部总线接口，最大数据传输速率为32 Mb/s。 （3）具有片内集成的存储器管理部件MMU，可支持虚拟存储和特
权保护。 （4）具有实地址模式、保护模式和虚拟8086模式3种工作方式。 （5）具有4 GB（232）的物理寻址空间和64 TB（246）的虚拟存
2021年1月30日星期六
2021年1月30日星期六
图1-17 段寄存器组成
பைடு நூலகம்
2）6个段描述符 每个段对应一个段描述符（8个字节），6个段描述符存放在CPU内的段 描述符高速缓存器中，它们均由内存的描述符表拷贝而成，CPU访问某一段 时，均按存放在CPU内该段的段描述符所描述的信息进行操作。
每个段描述符 共8个字节，包 括32位段基址， 20位段限值， 12位段属性信 息，如图1-18 所示。
位线性地址乘4，找到某一存储容量为4字节的页描述符。在页目录基址寄存 器的低12位中，有PCD和PWT两位控制位，其余10位保留。 CR2、CR3寄存器如图1-22所示。
2021年1月30日星期六
图1-22 控制寄存器CR2、CR3
6.调试寄存器 80386 CPU 芯片内有8个调试寄存器DR0~DR7，为调试提供了硬件支持。
L80C86 16位微处理器
L80C8616位微处理器
朱秉晨;宁书林;等
【期刊名称】《微处理机》
【年(卷),期】1995(000)001
【摘要】本文报道了1994年研制成功的我国L80C86 16位微处理器，论述了标志我国μPLSI新水平的该电路结构特征、系统逻辑、电路设计、芯片形成及测验技术等。
【总页数】8页(P23-30)
【作者】朱秉晨;宁书林;等
【作者单位】电子工业部东北微电子研究所，沈阳110032;电子工业部东北微电子研究所，沈阳110032
【正文语种】中文
【中图分类】TP332
【相关文献】
1.16位嵌入式RISC微处理器设计 [J], 雷少波;黄民
2.使用最广泛的16位微处理器8086／8088：微处理器技术系列讲座4 [J], 郑清明
3.增强型16位微处理器（一）：微处理器技术系列讲座5 [J], 郑清明
4.微处理器技术系列讲座.
5.：增强型16位微处理器（二） [J], 郑清明
5.微处理器技术系列讲座.8.：增强型16位微处理器（五） [J], 郑清明
因版权原因，仅展示原文概要，查看原文内容请购买。
微型计算机原理第3章资料
第3章 80x86微处理器
3．20位地址加法器 8086/8088CPU在对存储单元进行访问以读取指令或读/写 操作数时，必须在地址总线上提供20位的地址信息，以便选中 对应的存储单元。那么，CPU是如何产生20位地址的呢？ CPU提供的用来对存储单元进行访问的20位地址是由BIU 中的地址加法器产生的。
第3章 80x86微处理器
3.2.1 8086/8088内部结构 一．总线接口单元BIU 总线接口单元BIU的功能是负责完成CPU与存储器或I/O设
备之间的数据传送。具体任务是：
① 指令队列出现空字节(8088CPU 1个空字节，8086CPU 2 个空字节)时，从内存取出后续指令。BIU取指令时，并不影响 EU的执行，两者并行工作，大大提高了CPU的执行速度。
表3.1给出了80x86系列微处理器概况。下面通过对表中有关 技术数据的分析来说明Intel 80x86系列微处理器的发展情况。
第3章 80x86微处理器
表中“集成度”是指CPU芯片中所包含的晶体管数。 “主频”是指芯片所使用的主时钟频率，它直接影响计算 机的运行速度。 “数据总线”是计算机中各个组成部件间进行数据传送时 的公共通道，“内数据总线宽度”是指CPU芯片内部数据传送 的宽度（位数），“外数据总线宽度”是指CPU与外部交换数 据时的数据宽度，显然，数据总线位数越多，数据交换的速度 就越快。
8086有16条数据总线，可以处理8位或16位数据。有20条地址 总线，可以直接寻址1M（220）字节的存储单元和64K个I/O端口。 在8086推出后不久，为方便原8位机用户，Intel公司很快推出了 8088微处理器，其指令系统与8086完全兼容，CPU内部结构仍为16 位，但外部数据总线是8位的，这样设计的目的主要是为了与原有 的8位外围接口芯片兼容。并以8088为CPU组成了IBM PC、PC/XT 等准16位微型计算机，由于其性能价格比高，很快占领了市场。
Intel 80386微处理器的内部自测试
Intel 80386微处理器的内部自测试
Patrick P.Gelsinger;■晓云
【期刊名称】《微电子学与计算机》
【年(卷),期】1987(0)6
【摘要】80(?)86是一种新型的微处理器,采用单片集成,达几十万个晶体管。
它可以完成整个计算机能担负的大量的工作。
这种规模的集成大大地增加了测试的复杂性。
在有的部位,传统的基于功能的测试方法已完全不适用。
80386将内部自测试法与别的测试工具相结合,能够直接测试芯片上晶体管部位的大约50%。
这些增加的测试功能用于三个大的PLA、控制ROM(CROM)。
【总页数】2页(P47-48)
【关键词】特征值;自测试;开销;本征值;内部自测;微处理器;Intel 80386
【作者】Patrick P.Gelsinge r;■晓云
【作者单位】
【正文语种】中文
【中图分类】G6
【相关文献】
1.Intel80386在线仿真器的实现 [J], 朱勤;夏华龙
2.Motorola 68020与Intel80386的性能比较 [J], 孙昱东
3.Intel 80386调试工具DB386的开发 [J], 李敏;明宗桂
4.Windows3．1操作系统下对Intel80386、80486、PentiumCPU平面内存模
式的实现 [J], 汪辰
5.嵌入式微处理器INTEL80386EX在航电设备中的应用 [J], 许平
因版权原因，仅展示原文概要，查看原文内容请购买。
新型的L80C86 CPU电路电磁脉冲试验方法
新型的L80C86 CPU电路电磁脉冲试验方法
郑虹;刘丽娜;高松;丰洋;许仲德
【期刊名称】《微处理机》
【年(卷),期】2006(27)6
【摘要】介绍了一种新型的CPU类器件的EMP效应模拟试验方法,通过比较脉冲前后测量波形及CPU寄存器存数的变化,能够更科学地反映电磁脉冲对CPU类电路的影响,得到的结果客观、准确.
【总页数】3页(P22-23,27)
【作者】郑虹;刘丽娜;高松;丰洋;许仲德
【作者单位】辽宁大连亿达集团公司,大连,116021;中国电子科技集团公司第四十七研究所,沈阳,110032;中国电子科技集团公司第四十七研究所,沈阳,110032;中国电子科技集团公司第四十七研究所,沈阳,110032;中国电子科技集团公司第四十七研究所,沈阳,110032
【正文语种】中文
【中图分类】TN3
【相关文献】
1.8086CPU电磁脉冲效应测试系统的研制 [J], 吴伟;程引会;陈明;李宝忠
2.电磁脉冲与连续波对数字电路的辐照效应比较数字电路故障诊断 [J], 刘保声;王新阳;崔劢
3.新型航空瞬变电磁法脉冲电流发射电路研究 [J], 于生宝;姜健;孙长玉;陈旭
4.高功率微波电磁脉冲敏感阈值试验方法研究 [J], 张荣荣;吴小松;李金蓉
5.精确制导武器的电磁脉冲仿真试验方法研究 [J], 张江南;吴皓;谯梁;王鑫;陈飞因版权原因，仅展示原文概要，查看原文内容请购买。
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文章编号:1007-4627(2001)01-0070-03微处理器80C86及其外围芯片协合效应实验研究张庆祥,杨兆铭(兰州物理研究所真空低温技术与物理国家实验室,甘肃兰州730000)摘 要:研究了总剂量辐照对微处理器80C86及其外围芯片82C85单粒子效应敏感度的影响.252Cf 轰击80C86获得的单粒子效应截面在0-120Gy(Si)剂量范围内没有明显的变化;外围芯片82C85中发生的单粒子脉冲可能引起系统故障.关键词:单粒子效应;总剂量效应;微处理器;外围芯片中图分类号:P354.2 文献标识码:A1 引言空间辐射环境能够以不同的作用机制引起星载电子系统发生多种辐射效应,例如总剂量效应、单粒子效应(SEE)以及充放电效应等.两种或两种以上的作用叠加产生的效应不同于这些作用分别产生的效应.本文所研究的总剂量辐照和单粒子辐照产生的协合效应,特指总剂量辐照对SEE的影响,这对评估卫星寿命末期SEE敏感度具有重要意义.协合效应的评估实验设备复杂,实验技术难度大,国际上一直在探讨协合效应与单一效应之间的关系,以求得以单一效应实验替代协合效应实验.为了节省经费,空间电子学系统越来越多地使用商用器件,而商用器件对总剂量辐照的响应具有很大的离散性,因此总剂量效应再度成为国际上研究的热点,商用器件的协合效应也值得特别关注.16位微处理器80C86在空间电子学系统中得到了广泛的应用,其SEE在国内外进行了深入的研究[1-3].本文研究了80C86及其外围芯片82C85的协合效应,尝试在两种偏置下对80C86进行总剂量辐照,并考虑外围芯片的SEE对微处理器的影响.2 实验条件样品型号及功能如表1,82C85是80C86的外围芯片.测试样品由陶瓷封装芯片去盖得到.测试系统硬件是与微机相连的80C86单板机.单板机接通交流电即可工作,其输入输出由微机控制.80C86的SEE的检测采用单机自检测法,检测程序占用了AX16位、DX8位和FL16位,检测其余11个寄存器,共152位.每次将寄存器的正确值和取出值都显示在屏幕上,可以直观的观察寄存器的出错情况,对于程序执行过程中出现的死机情表1 样品型号及功能器件标号器件功能厂家CD80C86/+ 84111598微处理器HarrisCD82C85H9437时钟发生器和控制器Harris况,也可以根据其具体表现进行一些初步的分析.系统有错误注入措施以验证系统的可靠性,经过长时间的开机,没发现由系统本身产生的错误记录.用标称强度为1 Ci(1 Ci= 3.7 104Bq)的252Cf源轰击待测器件,252Cf裂变碎片在Si中的平均线性能量传输(LE T)值为43MeV/(mg c m-2),远大于只有27MeV/(mg cm-2)的56Fe离子,而后者代表了空间辐射环境中最重的离子.总剂量辐照采用兰州辐射研究中心的60Co源,采用静态辐照和准动态辐照两种方法.静态辐照法是指在总剂量辐照时对80C86加固定偏置和时钟,准动态辐照是指在样品处于与SE E实验相同的电路环境下进行辐照.对82C85的辐照采用了准动态辐照.3块80C86样品中,1#和3#采用准动态辐照,2#采用静态辐照,剂量率约为0.01Gy(Si)/s.60C o源辐照后立即进行SEE测试,然后继续总剂量辐照,再进行SEE检测,第19卷 第1期原子核物理评论Vol 19,No.1 2002年3月Nuclear Physics Review M ar.,2002收稿日期:2001 03 27;修改日期:2001 05 11作者简介:张庆祥(1971-),男(汉族),甘肃通渭人,在读博士,从事宇航器件单粒子效应研究直到器件不能正常工作为止.80C86最高照到100 Gy(Si)左右,功能就不正常,但经过退火,又能恢复正常功能.所有实验均在室温下进行.3 实验结果和讨论截面用检测到的事件数除以离子注量得到,其中单粒子翻转(SE U)截面是寄存器位翻转的截面, SEE截面指发生的所有错误的截面.离子注量根据252Cf源的半衰期及源与芯片表面的距离计算.每个检测的寄存器均发生了SE U,除了寄存器的位翻转,还有相当一部分其它错误,例如内部数据传输不同步、寄存器中出现乱码以及死机等现象.80C86中的算术逻辑单元、控制和时钟电路以及输入输出电路属于组合逻辑电路.研究表明组合逻辑电路中的SEE表现为单粒子瞬时脉冲(SE T), 80C86中的SE T可能干扰指令控制时序,从而引起系统工作不正常,甚至SE T也能引起寄存器的翻转.80C86内部地址寄存器或指令寄存器发生翻转,导致程序被!打飞∀,也出现乱码和死机现象,但这种死机可以通过复位来恢复.实验中还发现一种危害很大的死机现象,复位和重新上电都不能使之恢复.由于系统没有电流监测手段,所以不能断定该故障发生时偏置电流的变化.关机让其自行恢复需要较长时间,如果将芯片从管座拔下,再装上则立即恢复正常.实验获得的3个80C86样品的SE U及SEE截面(!)与总剂量(D)的关系如图1所示.从图中可以看出,在0-120Gy(Si)范围内,考虑到SE U实验数据的统计误差,翻转截面没有明显的变化.由于准动态法在辐照的同时系统没有工作,仅处于加电状态,所以与静态辐照没有太大区别.以上结果与Sanderson等[4]报道的HM1 6504 9的结果一致.该文作者认为,要观察到总剂量辐照引起的明显的SEE截面的变化需要满足以下两个条件:一是用于SEE测试的离子的LE T值在阈值附近;二是器件能够在失效前承受足够高的剂量.在总剂量辐照下,带电离子在器件氧化层(SiO2)中通过电离辐射产生电子 空穴对,大部分电子很快迁移出SiO2,而大部分的空穴被俘获,一部分空穴积累在Si/SiO2界面上,会造成金属 氧化物 半导体(MOS)电容平带电压的漂移,使MOS晶体管的阈值电压漂移、图180C86SEE及SEU载面与总剂量的关系跨导降低、亚阈电流增大和1/f噪声增大等.总之,改变产生SEE的临界电荷,即改变了引起SEE的LE T阈值,相当于将表征器件SEE敏感度的截面(!) LET曲线沿LET轴平移,平移的方向取决于器件单元的工艺以及单元中写入的内容[5,6].所以总剂量辐照对LE T阈值附近的离子截面的影响更大,而LE T值较大时,截面已经接近饱和,因此影响较小.80C86的LE T阈值小于等于3MeV/(mg c m-2))[3],而252Cf裂变碎片的平均LET值为43 MeV/(mg cm-2).因此不难理解以上的实验结果.80C86SE U中!0#1∀所占的比例(R0 1)与总剂量(D)的关系见图2,没有看出明显的变化.总的来说,!0#1∀的比例除个别点外均超过0.5,与文献[2]中的结果一致.图280C86SE U中!0#1∀的比例与总剂量的关系82C85SEE测试中发现了位翻转、乱码以及系统死机现象.82C85检测时,其时钟信号送入可编程间隔计时器82C54,然后由系统读出,而252Cf只轰击82C85,保证了检测到的位翻转是由82C85中产生的单粒子脉冲(SE T)引起的,因为82C85同时提供系统的时钟和复位信号,SET通过这些输出信号作用于微处理器,使系统出现乱码和死机现象.国外也有时钟处理电路的SE T导致微处理器工作不71第1期张庆祥等:微处理器80C86及其外围芯片协合效应实验研究正常的报道[7].由此看来外围芯片的SET也能造成微处理器故障,从而影响系统的正常工作.4个剂量点82C85的SEE截面没有明显变化,该样品在150Gy(Si)的总剂量下仍可正常工作,因此82C85具有比80C86更强的抗总剂量能力.4 结论在0-120Gy(Si)范围内,总剂量辐照没有对80C86的单粒子敏感度产生明显的影响.包括剂量率和偏置条件在内的总剂量辐照条件以及退火条件对实验结果的影响很大,因此协合效应的研究需要制定一个规范的实验条件,才能使实验数据之间具有可比性.另外,无论是在复杂器件(例如微处理器)内部发生的SET,还是器件之间SE T的传递都会对系统造成影响,尤其是微处理器外围芯片的SE T 可能对系统的正常工作造成危害.致谢 衷心感谢中科院近代物理研究所王树金副研究员及其研究组对本工作的大力协助.参 考 文 献:[1]Harboe Sorensen R,Adams L,Daly E J,e t al.The SEU Risk Assess ment of Z80,8086and80C86Microprocessors Intended for Use ina Lo w Al ti tude Polar Orbi t[J].IEEE Tran Nucl Sci,1986,33(6):1626 1631.[2]Harboe Sorensen R,Adams L.A Summary of SEU Resul ts Usi ng Californium 252[J].IEEE Tran Nucl Sci,1988,35(6):1622-1628.[3]Nichols D K,Smi th L S,Soli G tes t Trends in Parts SEP Susceptibili ty fro m Heavy Ions[J].IEEE Tran Nucl Sci,1989,36(6):2 388-2395.[4]Sanderson T K,Mapper D,Stephen J H,et al.SEU Meas ure mentsusing252Cf Fissi on Particles,on CMOS Static RAMs,Subjected to aContinuous Period of Lo w Dose Rate60Co Irradiation[J].IEEE Tran Nucl Sci,1987,34(6):1287-1291.[5]Stas sinopoulos E G,Brucker G J,G unten O Van,et al.Variation inSEU Sensi tivity of Dose imprinted CMOS SRA M[J].IEEE Tran Nucl Sci,1989,36(6):2330-2338.[6]A xnes s C L,Schwank J R,Winokur P S,et al.Single Event Upset inIrradiated16k CMO S SRAMs[J].IEEE Tran Nucl Sci,1988,35(6):1602-1607.[7]Leavy J F,Hoffmann L F,Shovan R W,e t al.Upset Due to SingleParticle Caus ed Propagated Trans ient i n a Bulk CMOS Microprocessor [J].IEEE Tran Nucl Sci,1991,38(6):1493-1499.Total Dose Dependence of SEE Sensitivities for Microprocessor80C86and Its Peripheral Chip82C85Z HANG Qing xiang,YANG Zhao ming(National Laboratory o f Vacuum and Cryogenics Technology and Physics,Lanzhou Institute o f Physics,Lanzhou730000,China)Abstract:Total dose dependence of the single event effct(SEE)sensitivity for microprocessor80C86and its peripheral chip82C85are reported.In this study,1 Ci252Cf was used as a heavy ion simulator and the samples were tested by a patent8086test syste m following exposure to60Co rays.It is found that SEE c ross section of80C86does not show sig nificant change with inc reasing total dose from0-120Gy(Si).SEE test also shows that single event transient(SE T)in 82C85could cause system failure.Key words:single event effect;total dose effect;microprocessor;peripheral chip72原子核物理评论第19卷。