基于ADF4360-1的本振源设计

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ADF4360使用

ADF4360-x是ADI公司推出的一系列的锁相环（Complete Phase Locked Loop）。

和其他锁相环芯片如ADF4106相比，ADF4360-x在片内集成了VCO（V oltage Controlled Oscillator）。

这一点非常重要，因为一般情况下我们要使用一个外置的VCO，这些模块有可能是自己使用三极管、调谐二极管、电感等器件自己搭建的。

但更多情况下，为了降低设计难度，提高各种性能，我们则是购买集成VCO 模块。

这些模块非常昂贵，小批量的情况下单颗价格往往在300元以上，而且体积已经有指甲片般大了。

那些对成本、空间要求很高的通信电子产品往往无法接受这样的VCO。

近几年，随着MMIC技术的发展，基于MMIC的VCO技术已经变得非常成熟。

其中Maxim很早就推出了相关的产品，比如MAX2753和MAX2624。

而Analog Devices并没有单独推出VCO MMIC的产品，而是将VCO 和锁相环的其他部分（除了环路滤波器以外）集成在了一起，针对不同的频段推出了一系列的锁相环，从ADF4360-0 ~ ADF4360-8。

这些芯片几乎相同的引脚定义，同时内部控制寄存器每一位的定义也完全相同。

由于将VCO集成到了芯片内部，使得整个PLL系统的面积大大减小（至少50%以上），而且成本也得到了有效控制。

ADF4360系列锁相环中，ADF4360-7和-8需要在片外设置两个电感来确定VCO所处的频段，相当于将VCO的电感部分移出至片外。

两个0603的电感并没有占据太大体积，但有两点必须注意：一个是电感到ADF4360芯片之间以及到接地平面之间的连线必须尽可能的短，而且电感必须使用线绕试的（比如使用Coilcraft 0603CS系列的RF电感。

如果使用普通叠层电感的话，VCO基本上不能起振）。

另一个问题就是ADF4360的每一个电源引脚一定要分别使用102和104的瓷片电容去偶。

ADF4360-7压控振荡器

通信原理课程设计课程名称：基于ADF4360-7的集成整形N合成器的压控振荡器指导老师：专业：班级：姓名：学号：摘要:ADF4360-7是一款整合了整形N合成器的压控振荡发生器(VCO)。

ADF4360-7的中心频率是由外部传感器进行设定的。

其允许频率范围从350MHz到1800MHz。

另外可以选择使用2分频，则用户接受的射频输出信号频率范围在175MHz到900MHz。

全部片内寄存器都是由一个简单的3线接口来控制的。

设备操作电压范围从3.0V到3.6V并且在不使用时可以随时关闭。

Abstract:The ADF4360-7 is an integrated integer-N synthesizer and voltage controlled oscillator (VCO). The ADF4360-7 center frequency is set by external inductors. This allows a frequency range of between 350 MHz to 1800 MHz. In addition, a divide-by-2 option is available, whereby the user receives an RF output of between 175 MHz and 900 MHz. Control of all the on-chip registers is through a simple 3-wire interface. The device operates with a power supply ranging from 3.0 V to 3.6 V and can be powered down when not in use.关键词：压控振荡器、合成器、频率、结构、功能Key words: VCO、synthesizer 、frequency、configuration、function目录集成整形N合成器的压控振荡器 (5)芯片特性 (5)应用范围 (5)技术规范 (6)时序特性 (7)极限工作范围 (8)管脚结构和功能描述 (9)典型工作特性 (11)电路说明 (17)参考输入部分 (17)比例器 (17)A,B计数器 (17)R 计数器 (18)PFD和CHARGE PUMP (18)MUXOUT和LOCK DETECT (19)输入转换寄存器 (20)压控振荡器VCO (20)锁存器结构 (23)开机 (26)控制写入 (28)N计数器写入 (30)R计数器写入 (30)ADF4360-7的应用 (32)外观尺寸 (39)集成整形N合成器的压控振荡器芯片特性：输出频率范围：350MHz 到 1800MHz2分频输出电源 3.0V 到 3.6V逻辑兼容 1.8V*整形N合成器可编程双模比例器 8/9，16/17可编程输出电平三线接口逻辑锁与数字锁检测硬件及软件关闭模式应用范围:手持无线通信(DECT, GSM, PCS, DCS, WCDMA)测试设备；无线局域网；有线电视设备技术规范：AV DD = DV DD = V VCO= 3.3 V ± 10%； AGND = DGND = 0 V；TA = T MIN to T MAX表11.工作温度范围 -40°C to +85°C2.设计保证符合样值3.ICP内部参数使整个频率范围保持环路增益不变4.T A= 25°C； AV DD= DV DD= V VCO= 3.3 V；P = 325.这些特征是为了保证VCO核心电流=15mA6.变频范围1.45G—1.75G,PFD频率200kHZ,环路带宽10kHz7.V VCO用50Ω负载电阻8.VCO的噪声在开环下测量9.合成器固有噪声通过测量VCO带内的相位噪声输出功率减去20logN(N为对频率的分频值)10.相位噪声符合EVAL-adf4360-xEB1和HP8562E频谱分析仪, 频谱分析仪用来测量合成器输出, 偏移频率=1kHz11.f REFIN=10 MHz；f PFD=200kHz；N=8000；环B/W=10kHz12.f REFIN=10 MHz；f PFD=1MHz；N=1600；环B/W=25kHz13.寄生信号符合EVAL-adf4360-xEB1和HP8562E频谱分析仪, 频谱分析仪用来测量合成器输出, f REFOUT = 10 MHz时序特性AV DD = DV DD = V VCO= 3.3 V ± 10%；AGND = DGND = 0 V；1.8 V and 3 V logic levels used；T A = T MIN to T MAX表2图2 时序特性表极限工作范围T A= 25°C，其它另做说明表3GND = AGND = DGND = 0 V.当芯片工作在高于以上所列的最大工作范围时将可能造成设备的损坏。

基于ADF4360-1的2.4G频率合成器设计

基于ADF4360-1的2.4G频率合成器设计作者：杨婧来源：《科技创新导报》 2013年第1期杨婧（中北大学信息探测与处理技术研究所山西太原 030051）摘?要：该文通过高性能、低功耗的8位ATmega8微处理器产生控制信号，利用美国ADI公司生产的锁相环芯片ADF4360-1，设计了一个稳定的2.4?GHz本振信号源电路模块，可广泛应用于电视，仪器，通信等领域。

文中详细介绍了系统中核心芯片的性能、结构以及应用方法，设计出了完整的硬件电路并对电路的各个参数进行了评估，结果基本上符合要求。

关键词：ATmega8 ADF4360-1?锁相环频率合成?本振信号源中图分类号：TN742 文献标识码：A 文章编号：1674-098X（2013）01（a）-00-01在现代无线电通信及相关领域中，为确保通信的稳定和可靠，对通信设备的频率准确度和稳定度提出了越来越高的要求。

与LC振荡电路“跑频”严重相比，晶体振荡电路具有可微调的稳定频率，但变化范围小，频率值不高。

频率合成技术是指将一个或少量的高稳定度、高准确度的标准频率作为参考频率，经过相应的信号处理过程，从而获得大量离散的具有同一稳定度和准确度的信号频率。

主要有三种合成方法：直接模拟合成、锁相环合成以及直接数字合成。

1 锁相式频率合成器的基本原理锁相环路（PLL）具有较为突出的优点：频率在一定范围内可调；数字化接口；能实现快速准确的跳频通信；抗干扰能力强。

锁相环频率合成器通过锁相环完成频率的加减乘除运算，是一种建立在相位负反馈基础上的闭环控制系统，对相位噪声和杂散具有很好的抑制作用。

原理图如图1所示，主要由鉴相器、环路滤波器和压控振荡器组成。

外部晶振提供的参考频率信号与压控振荡器的输出频率经程序N分频后在鉴相器内进行相位比较，产生误差控制电压，再经环路滤波器滤除误差信号中的噪声和高频分量，最后输出的直流脉冲电压控制压控振荡器产生所需的振荡频率。

通过锁相式频率合成实现的频率源应用广泛于通信、电视等电子设计领域，重点用于以下三方面：接收机本地振荡；发射机载波信号；信号发生器。

基于ADF4360

本电路设计中，ADF4360-2 的 PFD 输入频率为 1MHz，因此参考时钟分频 R=40。由公式 fVCO=(B&TImes;P+A)乘以 fREFIN/R，可计算出 N 为 11250，双模预频器设置为 P/(P+1)=32/33，计数器 A 设置为 8，计数器 B 设置为 32。根据 ADF4360-2 芯片资料，3 个控制寄存器初始化设置为 R 寄存器 00000A1H，C 寄存器 8FF12CH，N 寄存器 803E42H，配置值如表 1 所列。单片机通过提供时钟信号 CLK、数据信号 DATA 和使能信号 LE，对 ADF4360-2 内部寄存器进行配置，使得 VCO 输出所需频率的信号，同时负责对 ADF4360-2 的锁定标志进行检测，如果检测已经锁定，则配置数据工作完成。单片机程序流程如图 3 所示。
结语本文介绍了利用锁相频率合成芯片 ADF4360-2 设计 1GHz 信号的输出方法，给出了电路系统结构框图以及单片机程序流程。由于 ADF4360-2 内部集成 VCO，外部通过单片机 I/O 口写入控制字，因此该系统具有外围电路简单、调试方便、功耗和成本低等特点，可广泛应用于各种电路系统中。
◆能够进行模拟与数字锁定检测; ◆支持软件和硬件掉电功能。 ADF4360-2 的功能模块图如图 1 所示。它主要由一个 14 位可编程参考 R 计数器、一个 24 位数据寄存器、一个 24 位功能锁存器、压控振荡器、相位比较器、锁定检测器、多路外部频率源信号和单片机控制信号，14 位可编程参考 R 分频器对外部频率源信号分频后，得到参考频率送至鉴相器。控制信号由时钟信号 CLK、数据信号 DATA 和使能信号 LE 组成。在 CLK 的控制下，串行输入

相频率合成器ADF4360

相频率合成器ADF4360-4及其在WLAN混频电路中的应用赵浩平，刘乃安(西安电子科技大学通信工程学院，陕西西安710071)1 引言在无线通信领域，高性能频率源是通信设备的核心。

锁相(Phase Lock)技术是一种相位负反馈控制，锁相环电路具有优异特性：具有锁定时无剩余频差；良好的窄带载波跟踪和带宽调制跟踪；对相位噪声和杂散具有很好的抑制性；易于集成。

通过锁相频率合成技术，频率源可广泛应用于通信、电视等领域。

本文介绍的ADI公司的ADF4360系列器件是高性价比、应用广泛的锁相频率合成器，可用于无线通信射频系统(GSM、DECT、PCS、WCDMA以及DCS)基站和WLAN电路中。

2 锁相环频率合成器ADF4360-42.1 工作原理锁相环路(PLL)通常由鉴相器(PD)、环路滤波器(LP)、压控振荡器(VCO)和可编程分频器组成，外部晶体振荡器经R分频产生的参考频率与VCO的输出频率经N分频后，在鉴相器中相位比较，产生误差控制电压，经环路滤波器滤除高频分量和噪声后，控制VCO产生所需振荡频率。

AD4360-4是一款双模前置分频型单环频率合成器，双模前置分频器是一种在不改变频率分辨率的同时提高合成器输出频率的有效方法。

双模前置型锁相频率合成器方框图如图1。

图1中,(P+1)/P为高速双模前置分频器，分频模数为P+1和P；A为吞脉冲可编程计数器；B为主可编程计数器；MC为模控制逻辑电路。

其分频比为N=(P+1)A+P(B-A)=PB+A (1)合成器输出频率为：fo=N=(PB+A)fr (2)由式2可知，输出频率的分辨率△fo=fr。

因此，双模前置分频型单环合成器采用吞脉冲分频技术，保持合成器输出频率的分辨率不变。

双模前置分频器有两种计数工作模式，只要一个模控制信号控制就可实现简单的换模计数工作，而不需要采用类似可编程分频器的预置操作，因而其工作频率可以做得像固定分频器那样高，双模前置分频器很好地解决了固定前置分频器提高输出频率fo而降低频率分辨率△fo的矛盾。

ADF4360-7压控振荡器要点

ADF4360-7的中心频率是由外部传感器进行设定的。

其允许频率范围从350MHz到1800MHz。

另外可以选择使用2分频，则用户接受的射频输出信号频率范围在175MHz到900MHz。

全部片内寄存器都是由一个简单的3线接口来控制的。

设备操作电压范围从3.0V到3.6V并且在不使用时可以随时关闭。

基于ADF4360-7的频率合成系统

压来控制ＶＯ的频率，到使其与Ｃ达输入信号频率相等的目的。其中，鉴相器比较两输入信号的相位，将
差值转换成电压输出。通滤波器低滤除鉴相器输出电压中的高频成分
和噪声，出平均分量去控制ＶＯ取Ｃ
的频率。Ｃ是频率受电压控制的ＶＯ振荡器，想的频率受控特性应为理
线性的。的输出分频后送到鉴相它
器已输入端，供负反馈。提传统的锁相电路的缺点在于使用器件多，电路复杂度高，组成部分
是分离的，占用空间大，调试费时费
力，以产生所需的频率。相环路难锁
图２
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表１
控制锁存器
频率范围从３０ｚ１０ＭＨ。５ＭＨ到８０ｚ另外还有一个二分频可选择，样使这用者可以得到１５ｚ９０ｚ的７ＭＨ￣０ＭＨＲＦ输出。ＡＦ３０７对所有芯片上Ｄ４６－的寄存器的控制使用一个简单的３线控制。工作电压在３Ｏ它．Ｖ到３６．Ｖ
Ｎ计数锁存器
，
二集电曩１丹瞢３
粒
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Ｂ计ｌ蕾－来自之间，不使用的时候也能关断。在该芯片适用于无线手持设备（ＥＴＤＣ，

基于ADF4360-0的2.4 GHz射频信号源设计

基于ADF4360-0的2.4 GHz射频信号源设计作者：陈肇南来源：《机电信息》2020年第03期摘要：在现代无线通信系统中，对数据的高速无线传输需求日益增加，而且无线路由器、蓝牙等技术也在生活中有着广泛的应用，故而对于2.4 GHz频段的信号源的需求越来越多。

但是，除了一些在2.4 GHz频带产生信号的高端信号发生器外，平常使用的信号源很少会涉及2.4 GHz这一频段，因此，为满足科学和教育的需要，设计和研发了一款便宜可靠的2.4 GHz 射频信号发生器，并对其实现与仿真进行了介绍。

关键词：2.4 GHz;射频信号源;压控振荡器0 引言在电子通信系统中，如果想实现更大的带宽，我们只能通过使用更高的载波频率来满足要求。

在无线通信中，需要使用天线来发送和接收信号，工作频率越高，天线的尺寸就越小，满足了小型化的通信要求。

由于整体趋势是朝着宽频率覆盖、高精度、多功能以及自动化和智能化的方向发展，当今电子领域更多的电子通信系统使用更高频率的射频，这促进了丰富的射频应用，并带动了射频技术的进一步发展[1]。

1 相关原理概述压控振荡器（VCO）的定义为输出频率对应于输入控制电压的振荡电路，其在无线测量仪器和通信系统电路中使用广泛。

VCO作为锁相环电路和时钟恢复电路的主要组成部分，其性能可以直接影响到频率源的性能，这又决定了整个系统输出信号的稳定性、噪声特性和谐波抑制特性。

正是由于这些因素，VCO在电子通信技术领域发挥着重要作用。

因其具有电子调谐、紧凑、低功耗和高可靠性等优点，关于VCO的研究很多。

近年来，随着集成电路的快速发展，VCO的设计和实现逐渐融入其中，集成式VCO使用方便、性能稳定[2]。

2 关于ADF4360-0的介绍在ADF4360系列锁相环中，我們需要在芯片ADF4360-7和ADF4360-8的外部去设置两个电感，作用是方便确定VCO所处频段，这个操作步骤就相当于从芯片中将VCO的电感移除。

基于ADF4360-7的混频器本振源电路设计

基于ADF4360-7的混频器本振源电路设计韩进;王多伟【摘要】In the field of wireless communication,the local oscillator signal plays an important role in the communication system's stability.The working principle and characteristics of ADF4360-7 chip are introduced in this paper.By ADF436-7 chip,the local oscillator signal of 934MHz and -5 dbm output power is generated and up-conversed with the middle frequency modulation signal of 44MHz and 10dbm output power by the mixer to generate the frequency source of 978MHz and 8dbm output power.The ADI sim PLL Ver3 .1 software simulation and experiment results show that the frequency is stable and the specifications meet the technical requirements,and it has lower phase noise output and better spurious suppression.%在无线通信领域，本振信号对于通信系统的稳定性具有至关重要的作用。

采用锁相式频率合成技术，基于锁相环芯片ADF4360-7设计了一种本振源电路。

基于ADF4360-1的本振源设计

基于ADF4360-1的本振源设计时间：2009-12-16来源：现代电子技术作者：邹玲，石小磊湖北工业大学关键字：4360ADF0 引言在无线通信领域，本振信号性能的优劣是影响混频器输出频谱纯度的主要因素。

频率合成技术是指由一个稳定、准确的标准参考频率，经过一系列的处理过程，产生大量离散的具有同一稳定度和准确度的信号频率。

锁相式频率合成器是一种建立在相位负反馈基础上的闭环控制系统，主要由鉴相器、环路滤波器和压控振荡器组成。

通过锁相频率合成实现的频率源在通信、CATV等领域得到了广泛应用，很多现代电子设备和系统的功能实现都直接依赖于频率源的性能。

ADI公司生产的ADF4360-1是电流型电荷泵数字锁相式频率综合器芯片，具有很高的性价比。

1 ADF4360-1的工作原理及主要性能ADF4360-1主要由数字鉴相器、电荷泵、分频器、计数器及双模前置P／(P+1)分频器等组成。

如图1所示。

1．1 工作原理从ADF4360-1外部输入的信号有标准频率源信号和控制信号，14位可编程参考R分频器对外部频率源信号分频后得到参考频率送至鉴相器。

控制信号由时钟信号CLK、数据信号DATA和使能信号LE组成。

在CLK的控制下，串行输入24位数据信号，暂时存放在24位数据寄存器中。

在接收到使能信号LE后，先前输入的24位数据根据地址位到达对应的锁存器。

ADF4360-1的主分频比N由双模预分频器(P／P+1)、可编程5位A计数器及13位B分频器实现，算法为N=B×P+A，输出频率为:fout=(B×P+A)×fref／R，通过设置A，B，R三个控制字寄存器的控制字来实现对锁相环的控制。

该芯片外围只需添加环路滤波器，根据输出频率大小选择合适的参数，即可输出较稳定的频率。

1．2 主要性能ADF4360-1是美国ADI公司生产的一款高性能锁相频率合成芯片，主要可应用于无线射频通信系统基站(GSM，WCDMA)、手机以及通信检测设备中，为上下变频提供本振信号。

基于ADF4360-7的宽频带频率合成器设计

在空闲时还可工作于低功耗模式。由于本设计只对ＳＲＩ较关心，而对相噪、杂散、二次谐波等要ＮｚＥ求都不高，所以ＡＦ３０７Ｄ４６ — 的宽频带、片上分频器和内置的ＶＯＣ等使它成为本设计的理想选择。
ＡＦ３０７的功能原理图如图２Ｄ４６— 所示口】。在本文介绍的设计中，单片机Ａｍｇｌ通过三线接口Ｔｅａ６
集终端中５０ＭｚＨ的本振信号，并使之与中频信号混频，进行基带转换０Ｈ～１ｚＧ。
迄今为止，在频率合成中应用最为广泛的是锁相环（Ｌ技术。目前上海天文台的２射电ＰＬ）５ｍ望远镜观测基地ＶＢ数据采集终端中所用的锁相环电路由计数分频器、压控振荡器（Ｃ和缓冲ＬＩＶＯ）
维普资讯
总第３卷１
第１期
时间频率学报
ＪｕｎｌｏｉｎｒｑｅｃｏｒａｆｍｅａｄＦｅｕｎｙＴ
Ｖｏ．１Ｎｏ１１．３
２０年６月０８
Ｊｎ．０８ｕｅ２０
基于ＡＦ３０７的宽频带频率合成器设计Ｄ４６－
刘晗超
（．中国科学院上海天文台，上海２０３；１０００２．中国科学院研究生院，北京１０３００９）
摘要：介绍了一种采用锁相环技术（Ｌ）ＰＬ产生高稳定度正弦信号的宽频带频率合成器方案，在
该系统中采用锁相环频率合成器芯片ＡＦ３０７Ｄ４６—设计锁相环电路。简要分析了该芯片的工作原理，并给出了频率合成器的电路参数。通过该系统实现的宽频带本振信号的输出频率范围达到

一种基于ADF4360-9和FPGA的合成时钟源设计

在电子系统相关领域，时钟系统至关重要，是电子系统的脉搏，诸如电路系统、雷达系统、通讯系统等电子信息系统对时钟有严格的低相位噪声要求'1(，但直接制造低相位噪声的晶振难以实现。针对这一问题，设计了一种合成时钟源，即利用FPGA技术，结合外围硬件电路,控制时钟芯片的输出2 ,产生稳定的时钟源。在该时钟源合成技术中，锁相环是基础, 它是一种典型的反馈控制电路,可以抑制噪声和大大降低杂散干扰，而电荷泵锁相环是它的一种结构，易于集成和追踪，且捕获范围广。该合成时钟源制作相对简单，稳定度高，电路功耗低，成本和性能均远优于直接制造晶振。
1 ADF4360-9时钟芯片及工作原理介绍
1.1芯片内部结构
ADF43609时钟芯片集成了压控振荡器和整数 N分频器,VCO的输出频率范围为65〜400 MHz, 其中DIVOUT引脚输出VCO被分频后的COMS 时钟，分频系数范围为2〜31,VCO分频后的频率还可以再分频,MCU经由简单3线SPI接口控制全部片上寄存器。该时钟芯片内部包括24位的R寄存器、N寄存器、控制寄存器、鉴频鉴相器、压控振荡器和电荷泵,其内部功能框图如图1所示。
摘要:为了获得稳定可靠的时钟源，设计了一种合成时钟源。通过FPGA产生控制信号，结合硬件电路和软件设计，控制 ADF3360-9时钟芯片输出，得到稳定的时钟模块。ModelSim软件测试结果表明了程序时序的正确性，且实际测试的相位
噪声与仿真的相位噪声基本一致，本时钟源相位噪声理想，稳定可靠。
关键词：时钟源;锁相环%电荷泵%相位噪声% FPGA
写testbench程序进行仿真，验证程序是否正确。系统框图如图3所示电源电路如图4所示, ADF4360-9时钟芯片电路图如图5所示。
图4中电源电路的作用是给ADF4360-9芯片供电，电源电路是以精密的低压差电压稳压器 ADP3300-3为中心，通过搭建外围电路来实现。因

ADF4360-1[1]

Integrated Synthesizer and VCOADF4360-1 Rev.BInformation furnished by Analog Devices is believed to be accurate and reliable.However, no responsibility is assumed by Analog Devices for its use, nor for anyinfringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: Fax: 781.326.8703© 2004 Analog Devices, Inc. All rights reserved.FEATURESOutput frequency range: 2050 MHz to 2450 MHzDivide-by-2 output3.0 V to 3.6 V power supply1.8 V logic compatibilityInteger-N synthesizerProgrammable dual-modulus prescaler 8/9, 16/17, 32/33 Programmable output power level3-wire serial interfaceAnalog and digital lock detectHardware and software power-down mode APPLICATIONSWireless handsets (DECT, GSM, PCS, DCS, WCDMA)Test equipmentWireless LANsCATV equipment GENERAL DESCRIPTIONThe ADF4360-1 is a fully integrated integer-N synthesizer and voltage-controlled oscillator (VCO). The ADF4360-1 is designed for a center frequency of 2250 MHz. In addition, there is a divide-by-2 option available, whereby the user gets an RF output of between 1025 MHz and 1225 MHz.Control of all the on-chip registers is through a simple 3-wire interface. The device operates with a power supply ranging from 3.0 V to 3.6 V and can be powered down when not in use.FUNCTIONAL BLOCK DIAGRAMCPVCO REFTUNEC CC NOUT AOUT BFigure 1.ADF4360-1Rev. B | Page 2 of 24TABLE OF CONTENTSSpecifications.....................................................................................3 Timing Characteristics.....................................................................5 Absolute Maximum Ratings............................................................6 Transistor Count...........................................................................6 ESD Caution..................................................................................6 Pin Configuration and Function Descriptions.............................7 Typical Performance Characteristics.............................................8 Circuit Description...........................................................................9 Reference Input Section...............................................................9 Prescaler (P/P + 1)........................................................................9 A and B Counters.........................................................................9 R Counter......................................................................................9 PFD and Charge Pump................................................................9 MUXOUT and Lock Detect......................................................10 Input Shift Register.....................................................................10 VCO.............................................................................................10 Output Stage................................................................................11 Latch Structure...........................................................................12 Power-Up.....................................................................................16 Control Latch..............................................................................18 N Counter Latch.........................................................................19 R Counter Latch.........................................................................19 Applications.....................................................................................20 Direct Conversion Modulator..................................................20 Fixed Frequency LO...................................................................21 Interfacing...................................................................................21 PCB Design Guidelines for Chip-Scale Package..........................22 Output Matching........................................................................22 Outline Dimensions.......................................................................23 Ordering Guide.. (23)REVISION HISTORY12/04—Rev. A to Rev. BUpdated Format..................................................................Universal Changes to Specifications................................................................3 Changes to the Timing Characteristics.........................................5 Changes to the Power-Up Section................................................16 Added Table 10...............................................................................16 Added Figure 16..............................................................................16 Changes to Ordering Guide..........................................................23 Updated Outline Dimensions. (23)6/04—Data Sheet Changed from Rev. 0 to Rev. AChanges to Specifications................................................................3 Changes to Table 6..........................................................................12 Changes to Table 7..........................................................................13 Changes to Table 9.. (15)8/03—Revision 0: Initial VersionADF4360-1Rev. B | Page 3 of 24SPECIFICATIONS 1AV DD = DV DD = V VCO = 3.3 V ± 10%; AGND = DGND = 0 V; T A = T MIN to T MAX , unless otherwise noted. Table 1.Parameter B Version Unit Conditions/Comments REF IN CHARACTERISTICS REF IN Input Frequency 10/250 MHz min/max For f < 10 MHz, use a dc-coupled CMOS compatiblesquare wave, slew rate > 21 V/µs.REF IN Input Sensitivity 0.7/AV DD p-p min/max AC-coupled. 0 to AV DD V max CMOS compatible. REF IN Input Capacitance 5.0 pF max REF IN Input Current ±100 µA max PHASE DETECTORPhase Detector Frequency 28 MHz max CHARGE PUMPI CP Sink/Source 3With R SET = 4.7 kΩ. High Value 2.5 mA typ Low Value 0.312 mA typ R SET Range 2.7/10 kΩ I CP 3-State Leakage Current 0.2 nA typ Sink and Source Current Matching 2 % typ 1.25 V ≤ V CP ≤ 2.5 V. I CP vs. V CP 1.5 % typ 1.25 V ≤ V CP ≤ 2.5 V. I CP vs. Temperature 2 % typ V CP = 2.0 V. LOGIC INPUTS V INH , Input High Voltage 1.5 V min V INL , Input Low Voltage 0.6 V max I INH /I INL , Input Current ±1 µA max C IN , Input Capacitance 3.0 pF max LOGIC OUTPUTS V OH , Output High Voltage DV DD – 0.4 V min CMOS output chosen. I OH , Output High Current 500 µA max V OL , Output Low Voltage 0.4 V max I OL = 500 µA. POWER SUPPLIES AV DD 3.0/3.6 V min/V max DV DD AV DD V VCO AV DD AI DD 410 mA typDI DD 4 2.5 mA typ I VCO 4, 524.0 mA typ I CORE = 15 mA.I RFOUT 43.5 – 11.0 mA typ RF output stage is programmable.Low Power Sleep Mode 47 µA typ RF OUTPUT CHARACTERISTICS 5 VCO Output Frequency 2050/2450 MHz min/max I CORE = 15 mA. VCO Sensitivity 57 MHz/V typ Lock Time 6400 µs typ To within 10 Hz of final frequency. Frequency Pushing (Open Loop) 6 MHz/V typ Frequency Pulling (Open Loop) 15 kHz typ Into 2.00 VSWR load. Harmonic Content (Second) −20 dBc typ Harmonic Content (Third) −35 dBc typOutput Power 5, 7−13/−6 dBm typ Programmable in 3 dB steps. See Table 7. Output Power Variation ±3 dB typ For tuned loads, see the Output Matching section. VCO Tuning Range 1.25/2.5 V min/maxADF4360-1Rev. B | Page 4 of 24Parameter B Version Unit Conditions/CommentsNOISE CHARACTERISTICS 1, 5VCO Phase-Noise Performance 8 −110 dBc/Hz typ @ 100 kHz offset from carrier. −130 dBc/Hz typ @ 1 MHz offset from carrier. −141 dBc/Hz typ @ 3 MHz offset from carrier. −148 dBc/Hz typ @ 10 MHz offset from carrier.Synthesizer Phase-Noise Floor 9−172 dBc/Hz typ @ 25 kHz PFD frequency. −163 dBc/Hz typ @ 200 kHz PFD frequency. −147 dBc/Hz typ @ 8 MHz PFD frequency. In-Band Phase Noise 10, 11−81 dBc/Hz typ @ 1 kHz offset from carrier.RMS Integrated Phase Error 120.72 Degrees typ 100 Hz to 100 kHz.Spurious Signals due to PFD Frequency 11, 13−70 dBc typ Level of Unlocked Signal with MTLD Enabled −38 dBm typ1 Operating temperature range is –40°C to +85°C.2Guaranteed by design. Sample tested to ensure compliance. 3I CP is internally modified to maintain constant-loop gain over the frequency range. 4T A = 25°C; AV DD = DV DD = V VCO = 3.3 V; P = 32. 5These characteristics are guaranteed for VCO Core Power = 15 mA. 6Jumping from 2.05 GHz to 2.45 GHz. PFD frequency = 200 kHz; loop bandwidth = 10 kHz. 7Using 50 Ω resistors to V VCO into a 50 Ω load. For tuned loads, see the section. Output Matching 8The noise of the VCO is measured in open-loop conditions. 9The synthesizer phase-noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value). 10The phase noise is measured with the EVAL-ADF4360-xEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REF IN for the synthesizer; offset frequency = 1 kHz. 11f REFIN = 10 MHz; f PFD = 200 kHz; N = 12500; Loop B/W = 10 kHz. 12f REFIN = 10 MHz; f PFD = 1 MHz; N = 2400; Loop B/W = 25 kHz. 13The spurious signals are measured with the EVAL-ADF4360-xEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REF IN for the synthesizer; f REFOUT = 10 MHz @ 0 dBm.ADF4360-1Rev. B | Page 5 of 24TIMING CHARACTERISTICS 1AV DD = DV DD = V VCO = 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; T A = T MIN to T MAX , unless otherwise noted. Table 2.Parameter Limit at T MIN to T MAX (B Version) Unit Test Conditions/Comments t 1 20 ns min LE Setup Timet 2 10 ns min DATA to CLOCK Setup Time t 3 10 ns min DATA to CLOCK Hold Time t 4 25 ns min CLOCK High Duration t 5 25 ns min CLOCK Low Duration t 6 10 ns min CLOCK to LE Setup Time t 720ns minLE Pulse Width1See the section for the recommended power-up procedure for this device.Power-UpCLOCKDATALELEFigure 2. Timing DiagramADF4360-1Rev. B | Page 6 of 24ABSOLUTE MAXIMUM RATINGST A = 25°C, unless otherwise noted. Table 3.Parameter Rating AV DD to GND 1−0.3 V to +3.9 V AV DD to DV DD −0.3 V to +0.3 V V VCO to GND −0.3 V to +3.9 V V VCO to AV DD −0.3 V to +0.3 V Digital I/O Voltage to GND −0.3 V to V DD + 0.3 V Analog I/O Voltage to GND −0.3 V to V DD + 0.3 VREF IN to GND −0.3 V to V DD + 0.3 VOperating Temperature RangeMaximum Junction Temperature 150°CCSP θJA Thermal Impedance(Paddle Soldered) 50°C/W (Paddle Not Soldered) 88°C/W Lead Temperature, SolderingVapor Phase (60 sec) 215°C Infrared (15 sec) 220°C1GND = AGND = DGND = 0 V.Stresses above those listed under Absolute Maximum Ratingsmay cause permanent damage to the device. This is a stress rat-ing only; functional operation of the device at these or any other conditions above those indicated in the operational sec-tions of this specification is not implied. Exposure to absolutemaximum rating conditions for extended periods may affect device reliability. This device is a high performance RF integrated circuit with an ESD rating of <1 kV and it is ESD sensitive. Proper precautions should be taken for handling and assembly.TRANSISTOR COUNT 12543 (CMOS) and 700 (Bipolar)ESD CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulateon the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy elec-trostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.ADF4360-1Rev. B | Page 7 of 24PIN CONFIGURATION AND FUNCTION DESCRIPTIONSCPGND AV DD AGND RF OUT A RF OUT B V VCO DATA CLK REF IN DGND C N R SETV T U N E A G N D A G N D A G N D A G N D C C C PC EA G N DD V D DM U X O U TL E04414-003Figure 3. Pin ConfigurationADF4360-1Rev. B | Page 8 of 24TYPICAL PERFORMANCE CHARACTERISTICSFREQUENCY OFFSET (Hz)O U T P U T P O W E R (d B )Figure 4. Open Loop VCO Phase Noise04414-005–145–150–155–140–135–130–125–120–115–110–105–90–95–100–85–80–75–7010010M1M 100k10k 1000FREQUENCY OFFSET (Hz)O U T P U T P O W E R (d B )Figure 5. VCO Phase Noise, 2250 MHz, 200 kHz PFD, 10 kHz Loop Bandwidth04414-006–145–150–155–140–135–130–125–120–115–110–105–90–95–100–85–80–75–7010010M1M 100k10k 1000FREQUENCY OFFSET (Hz)O U T P U T P O W E R (d B )Figure 6. VCO Phase Noise, 1125 MHz,Divide-by-2 Enabled, 200 kHz PFD, 10 kHz Loop BandwidthO U T P U T P O W E R (d B )–2kHz –1kHz 2250MHz 1kHz 2kHzFigure 7. Close-In Phase Noise at 2250 MHz (200 kHz Channel Spacing)O U T P U T P O W E R (d B )–200kHz–100kHz2250MHz100kHz200kHzFigure 8. Reference Spurs at 2250 MHz(200 kHz Channel Spacing, 10 kHz Loop Bandwidth)O U T P U T P O W E R (d B )–90–80–70–60–50–40–30–20–100–1MHz–0.5MHz2250MHz0.5MHz1MHzFigure 9. Reference Spurs at 2250 MHz(1 MHz Channel Spacing, 25 kHz Loop Bandwidth)ADF4360-1Rev. B | Page 9 of 24CIRCUIT DESCRIPTIONREFERENCE INPUT SECTIONThe reference input stage is shown in Figure 10. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed, and SW1 and SW2 are opened. This ensures that there is no loading of the REF IN pin on power-down.04414-010POWER-DOWNFigure 10. Reference Input StagePRESCALER (P/P + 1)The dual-modulus prescaler (P/P + 1), along with the A and B counters, enables the large division ratio, N , to be realized (N = BP + A). The dual-modulus prescaler, operating at CML levels, takes the clock from the VCO and divides it down to a manage-able frequency for the CMOS A and B counters. The prescaler is programmable. It can be set in software to 8/9, 16/17, or 32/33 and is based on a synchronous 4/5 core. There is a minimum divide ratio possible for fully contiguous output frequencies; this minimum is determined by P , the prescaler value, and is given by (P 2−P).A ANDB COUNTERSThe A and B CMOS counters combine with the dual-modulus prescaler to allow a wide range division ratio in the PLL feed-back counter. The counters are specified to work when the prescaler output is 300 MHz or less. Thus, with a VCOfrequency of 2.5 GHz, a prescaler value of 16/17 is valid, but a value of 8/9 is not valid.Pulse Swallow FunctionThe A and B counters, in conjunction with the dual-modulus prescaler, make it possible to generate output frequencies that are spaced only by the reference frequency divided by R. The VCO frequency equation is()R f A B P f REFIN VCO /×]+×[=where:f VCO is the output frequency of the VCO.P is the preset modulus of the dual-modulus prescaler (8/9, 16/17, and so on).B is the preset divide ratio of the binary 13-bit counter (3 to 8191). A is the preset divide ratio of the binary 5-bit swallow counter (0 to 31). f REFIN is the external reference frequency oscillator.Figure 11. A and B CountersR COUNTERThe 14-bit R counter allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector (PFD). Division ratios from 1 to 16,383 are allowed.PFD AND CHARGE PUMPThe PFD takes inputs from the R counter and N counter(N = BP + A) and produces an output proportional to the phase and frequency difference between them. Figure 12 is a simpli-fied schematic. The PFD includes a programmable delay ele-ment that controls the width of the antibacklash pulse. This pulse ensures that there is no dead zone in the PFD transfer function and minimizes phase noise and reference spurs. Two bits in the R counter latch, ABP2 and ABP1, control the width of the pulse (see Table 9).04414-012Figure 12. PFD Simplified Schematic and Timing (In Lock)ADF4360-1Rev. B | Page 10 of 24MUXOUT AND LOCK DETECTThe output multiplexer on the ADF4360 family allows the user to access various internal points on the chip. The state of MUXOUT is controlled by M3, M2, and M1 in the function latch. The full truth table is shown in Table 7. Figure 13 shows the MUXOUT section in block diagram form.Lock DetectMUXOUT can be programmed for two types of lock detect: digital and analog. Digital lock detect is active high. When LDP in the R counter latch is set to 0, digital lock detect is set high when the phase error on three consecutive phase detector cycles is less than 15 ns.With LDP set to 1, five consecutive cycles of less than 15 ns phase error are required to set the lock detect. It stays set high until a phase error greater than 25 ns is detected on any subse-quent PD cycle.The N-channel open-drain analog lock detect should be oper-ated with an external pull-up resistor of 10 kΩ nominal. When lock has been detected, the output will be high with narrow low-going pulses.DGNDMUXOUTDV ANALOG LOCK DETECT SDOUT04414-013Figure 13. MUXOUT CircuitINPUT SHIFT REGISTERThe ADF4360 family’s digital section includes a 24-bit input shift register, a 14-bit R counter, and an 18-bit N counter, com-prising of a 5-bit A counter and a 13-bit B counter. Data isclocked into the 24-bit shift register on each rising edge of CLK. The data is clocked in MSB first. Data is transferred from the shift register to one of four latches on the rising edge of LE. The destination latch is determined by the state of the two control bits (C2, C1) in the shift register. The two LSBs are DB1 and DB0, as shown in Figure 2.The truth table for these bits is shown in Table 5. Table 6 shows a summary of how the latches are programmed. Note that the test mode latch is used for factory testing and should not be programmed by the user.Table 5. C2 and C1 Truth TableControl BitsC2 C1 Data Latch 0 0 Control Latch 0 1 R Counter1 0 N Counter (A and B) 11Test Mode LatchVCOThe VCO core in the ADF4360 family uses eight overlapping bands, as shown in Figure 14, to allow a wide frequency range to be covered without a large VCO sensitivity (K V ) and resultant poor phase noise and spurious performance.The correct band is chosen automatically by the band select logic at power-up or whenever the N counter latch is updated. It is important that the correct write sequence be followed at power-up. This sequence is 1. R counter latch 2. Control latch 3. N counter latchDuring band select, which takes five PFD cycles, the VCO V TUNE is disconnected from the output of the loop filter and connected to an internal reference voltage.04414-0140.40.20.60.81.01.21.41.61.82.42.22.02.62.83.01850190019502000205021002150220022502300235024002450250025502600FREQUENCY (MHz)V O L T A G E (V )Figure 14. Frequency vs. V TUNE , ADF4360-1The R counter output is used as the clock for the band select logic and should not exceed 1 MHz. A programmable divider is provided at the R counter input to allow division by 1, 2, 4, or 8 and is controlled by Bits BSC1 and BSC2 in the R counter latch. Where the required PFD frequency exceeds 1 MHz, the divide ratio should be set to allow enough time for correct band selection.After band select, normal PLL action resumes. The nominal value of K V is 57 MHz/V or 28 MHZ/V if divide-by-2 operation has been selected (by programming DIV2 [DB22], high in the N counter latch). The ADF4360 family contains linearization circuitry to minimize any variation of the product of I CP and K V.The operating current in the VCO core is programmable in four steps: 5 mA, 10 mA, 15 mA, and 20 mA. This is controlled by Bits PC1 and PC2 in the control latch.OUTPUT STAGEThe RF OUT A and RF OUT B pins of the ADF4360 family are con-nected to the collectors of an NPN differential pair driven by buffered outputs of the VCO, as shown in Figure 15. To allow the user to optimize the power dissipation versus the output power requirements, the tail current of the differential pair is programmable via Bits PL1 and PL2 in the control latch. Four current levels may be set: 3.5 mA, 5 mA, 7.5 mA, and 11 mA. These levels give output power levels of −13 dBm, −10.5 dBm, −8 dBm, and −6 dBm, respectively, using a 50 Ω resistor to V DD and ac coupling into a 50 Ω load. Alternatively, both outputs can be combined in a 1 + 1:1 transformer or a 180° microstrip coupler (see the Output Matching section). If the outputs are used individually, the optimum output stage consists of a shunt inductor to V DD.Another feature of the ADF4360 family is that the supply current to the RF output stage is shut down until the part achieves lock as measured by the digital lock detect circuitry. This is enabled by the mute-till-lock detect (MTLD) bit in the control latch.RF A RF BFigure 15. Output Stage ADF4360-1LATCH STRUCTURETable 6 shows the three on-chip latches for the ADF4360 family. The two LSBs determine which latch is programmed. Table 6. Latch StructureCONTROL LATCHN COUNTER LATCHR COUNTER LATCHTable 7. Control LatchTable 9. R Counter LatchPOWER-UPPower-Up SequenceThe correct programming sequence for the ADF4360-1 after power-up is: 1. R counter latch 2. Control latch 3. N counter latchInitial Power-UpInitial power-up refers to programming the part after theapplication of voltage to the AV DD , DV DD , V VCO , and CE pins. On initial power-up, an interval is required between programming the control latch and programming the N counter latch. This interval is necessary to allow the transient behavior of the ADF4360-1 during initial power-up to have settled.During initial power-up, a write to the control latch powers up the part and the bias currents of the VCO begin to settle. If these currents have not settled to within 10% of their steady-state value, and if the N counter latch is then programmed, the VCO may not oscillate at the desired frequency, which does not allow the band select logic to choose the correct frequency band and the ADF4360-1 may not achieve lock. If the recommended interval is inserted, and the N counter latch is programmed, the band select logic can choose the correct frequency band, and the part locks to the correct frequency.The duration of this interval is affected by the value of the capacitor on the C N pin (Pin 14). This capacitor is used to reduce the close-in noise of the ADF4360-1 VCO. The recom-mended value of this capacitor is 10 µF. Using this value requires an interval of ≥ 5 ms between the latching in of the control latch bits and latching in of the N counter latch bits. If a shorter delay is required, this capacitor can be reduced. A slight phase noise penalty is incurred by this change, which is explained in the Table 10.Table 10. C N Capacitance vs. Interval and Phase NoiseC N Value Recommended Interval between Control Latch and N Counter Latch Open-Loop Phase Noise @ 10 kHz Offset 10 µF ≥ 5 ms −85 dBc 440 nF≥ 600 µs−84 dBcCLOCKPOWER-UPDATALECONTROL LATCH WRITE TO N COUNTER LATCH WRITE04414-02Figure 16. ADF4360-1 Power-Up TimingHardware Power-Up/Power-DownIf the ADF4360-1 is powered down via the hardware (using the CE pin) and powered up again without any change to the N counter register during power-down, it locks at the correct fre-quency because the part is already in the correct frequency band. The lock time depends on the value of capacitance on the C N pin, which is <5 ms for 10 µF capacitance. The smaller ca-pacitance of 440 nF on this pin enables lock times of <600 µs. The N counter value cannot be changed while the part is in power-down because it may not lock to the correct frequency on power-up. If it is updated, the correct programming se-quence for the part after power-up is to the R counter latch, followed by the control latch, and finally the N counter latch, with the required interval between the control latch and N counter latch, as described in the Initial Power-Up section. Software Power-Up/Power-DownIf the ADF4360-1 is powered down via the software (using the control latch) and powered up again without any change to the N counter latch during power-down, it locks at the correct fre-quency because it is already in the correct frequency band. The lock time depends on the value of capacitance on the C N pin, which is <5 ms for 10 µF capacitance. The smaller capacitance of 440 nF on this pin enables lock times of <600 µs.The N counter value cannot be changed while the part is in power-down because it may not lock to the correct frequency on power-up. If it is updated, the correct programming se-quence for the part after power-up is to the R counter latch, followed by the control latch, and finally the N counter latch, with the required interval between the control latch and N counter latch, as described in the Initial Power-Up section.CONTROL LATCHWith (C2, C1) = (0, 0), the control latch is programmed. Table 7 shows the input data format for programming the control latch. Prescaler ValueIn the ADF4360 family, P2 and P1 in the control latch set the prescaler values.Power-DownDB21 (PD2) and DB20 (PD1) provide programmable power-down modes.In the programmed asynchronous power-down, the device powers down immediately after latching a 1 into Bit PD1, with the condition that PD2 has been loaded with a 0. In the pro-grammed synchronous power-down, the device power-down is gated by the charge pump to prevent unwanted frequency jumps. Once the power-down is enabled by writing a 1 intoBit PD1 (on the condition that a 1 has also been loaded to PD2), the device will go into power-down on the second rising edge of the R counter output, after LE goes high. When the CE pin is low, the device is immediately disabled regardless of the state of PD1 or PD2.When a power-down is activated (either in synchronous or asynchronous mode), the following events occur:•All active dc current paths are removed.•The R, N, and timeout counters are forced to their load state conditions.•The charge pump is forced into three-state mode.•The digital lock detect circuitry is reset.•The RF outputs are debiased to a high impedance state. •The reference input buffer circuitry is disabled.•The input register remains active and capable of loading and latching data. Charge Pump CurrentsCPI3, CPI2, and CPI1 in the ADF4360 family determine Current Setting 1.CPI6, CPI5, and CPI4 determine Current Setting 2. See the truth table in Table 7.Output Power LevelBits PL1 and PL2 set the output power level of the VCO. See the truth table in Table 7.Mute-Till-Lock DetectDB11 of the control latch in the ADF4360 family is the mute-till-lock detect bit. This function, when enabled, ensures that the RF outputs are not switched on until the PLL is locked.CP GainDB10 of the control latch in the ADF4360 family is the charge pump gain bit. When it is programmed to a 1, Current Setting 2 is used. When it is programmed to a 0, Current Setting 1 is used. Charge Pump Three-StateThis bit puts the charge pump into three-state mode when programmed to a 1. It should be set to 0 for normal operation. Phase Detector PolarityThe PDP bit in the ADF4360 family sets the phase detector polarity. The positive setting enabled by programming a 1 is used when using the on-chip VCO with a passive loop filter or with an active noninverting filter. It can also be set to 0. This is required if an active inverting loop filter is used.MUXOUT ControlThe on-chip multiplexer is controlled by M3, M2, and M1.See the truth table in Table 7.Counter ResetDB4 is the counter reset bit for the ADF4360 family. When this is 1, the R counter and the A, B counters are reset. For normal operation, this bit should be 0.Core Power LevelPC1 and PC2 set the power level in the VCO core. The recom-mended setting is 15 mA. See the truth table in Table 7.。

基于ADF4156与ADF5001的微波本振源设计

基于ADF4156与ADF5001的微波本振源设计单菡【摘要】现代射频与微波电子系统中要求频率源具有高频低相噪,且具有可靠性好,体积小、功耗低等特点.本文介绍一种基于ADF4156和ADF5001的微波本振源设计.本电路是低噪声微波小数N分频锁相环(PLL)的完整实现方案,以ADF4156作为小数N分频PLL核心器件,使用ADF5001外预分频器将PLL频率范围扩展至18GHZ.采用具有适当偏置和滤波的超低噪声运算放大器驱动微波VCO,在12GHZ 下可实现完全低噪声PLL.【期刊名称】《制造业自动化》【年(卷),期】2012(034)011【总页数】4页(P138-141)【关键词】锁相环;ADF4156;ADF5001;微波本振源【作者】单菡【作者单位】江苏科技大学,镇江212003【正文语种】中文【中图分类】F406.20 引言锁相(Phase Lock)技术是一种相位反馈频率控制技术，该技术在锁定时无剩余频差，并具有良好的窄带载波跟踪性能和带宽调制跟踪性能，而且对相位噪声和杂散也具有很好的抑制作用。

因此，通过锁相频率合成技术实现的频率源已在通信、电视等领域得了广泛应用。

本文介绍的基于ADF4156与ADF5001的微波本振源设计就是应用锁相技术结合RF预分频器实现微波本振源。

1 工作原理本文所述微波本振源是由通过PLL频率合成器（包含低噪声数字鉴频鉴相器(PFD)、精密电荷泵和可编程参考分频器组成）、环路滤波器，压控振荡器、RF外部预分频器和高稳定度参考时钟五部分形成锁相环电路来实现的，其原理框图如图1所示。

图1 锁相环原理框图频率合成器在锁相环（PLL）中工作，鉴频鉴相器（PFD）将反馈频率与参考时钟基准频率的某一分频形式相比较。

PFD的输出电流脉冲经过滤波和积分，产生一个电压。

此电压驱动一个外部电压控制振荡器（VCO）提高或降低频率，从而驱动PFD的平均输出接近零。

频率分频器分频，参考时钟分频器将基准参考输入时钟频率降至PFD频率（FPFD=FREF/R）,反馈小数分频器（N）计数器和RF外部预分频器（P）降低输出频率，在PFD处与经过分频的基准参考时钟频率相比较，达到均衡时，这两个频率相等，则有(FOUT/P)/N= FREF/R，因此输出频率FOUT= (FREF/R)×P×N，小数N分频器内置一个Σ-Δ型小数插值器，能够实现可编程小数N分频。

基于ADF4360-1的本振源设计

基于ADF4360-1的本振源设计
邹玲;石小磊
【期刊名称】《现代电子技术》
【年(卷),期】2009(32)21
【摘要】结合锁相频率合成基本原理以及高集成锁相频率合成芯片ADF4360-1工作特性,设计一个稳定的2.33 GHz本振源电路模块,应用于中频射频发信机中.详细介绍了核心芯片的结构、原理及应用,并给出完整的硬件电路.经仿真测试,该电路的性能指标基本符合要求.
【总页数】3页(P71-73)
【作者】邹玲;石小磊
【作者单位】湖北工业大学,电气与电子工程学院,湖北,武汉,430068;湖北工业大学,电气与电子工程学院,湖北,武汉,430068
【正文语种】中文
【中图分类】TN742
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基于ADF4360-1的本振源设计作者：邹玲石小磊来源：《现代电子技术》2009年第21期摘要:结合锁相频率合成基本原理以及高集成锁相频率合成芯片ADF4360-1工作特性,设计一个稳定的2.33 GHz本振源电路模块,应用于中频射频发信机中。

详细介绍了核心芯片的结构、原理及应用,并给出完整的硬件电路。

经仿真测试,该电路的性能指标基本符合要求。

关键词:锁相环频率合成;ADF4360-1;本振;环路滤波器中图分类号:TN742 文献标识码:A文章编号:1004-373X(2009)21-071-03Design of Clock Signal Generator Based on ADF4360-1ZOU Ling,SHI Xiaolei(School of Electrical and Electronic Engineering,Hubei University ofTechnology,Wuhan,430068,China)Abstract:The principle of phase locked loop and the performance characteristics of fully integrated voltage-controlled oscillator ADF4360-1 are analyzed.A design of a stedy 2.33 GHz local oscillator signal generator circuit module is applied to the system of Intermediate Frequency(IF).The paper elaborates on the structure,performance and application of the core chip,designs the hardware circuit.The simulation and measure of the system show that the result is correct basically.Keywords:PLL frequency synthesis;ADF4360-1;local oscillation;loop filter0 引言在无线通信领域,本振信号性能的优劣是影响混频器输出频谱纯度的主要因素。

频率合成技术是指由一个稳定、准确的标准参考频率,经过一系列的处理过程,产生大量离散的具有同一稳定度和准确度的信号频率[1]。

锁相式频率合成器是一种建立在相位负反馈基础上的闭环控制系统,主要由鉴相器、环路滤波器和压控振荡器组成。

通过锁相频率合成实现的频率源在通信、CATV等领域得到了广泛应用,很多现代电子设备和系统的功能实现都直接依赖于频率源的性能[2,3]。

ADI公司生产的ADF4360-1是电流型电荷泵数字锁相式频率综合器芯片,具有很高的性价比。

1 ADF4360-1的工作原理及主要性能ADF4360-1主要由数字鉴相器、电荷泵、分频器、计数器及双模前置P/(P+1)分频器等组成。

如图1所示。

1.1 工作原理从ADF4360-1外部输入的信号有标准频率源信号和控制信号,14位可编程参考R分频器对外部频率源信号分频后得到参考频率送至鉴相器。

控制信号由时钟信号CLK、数据信号DATA和使能信号LE组成。

在CLK的控制下,串行输入24位数据信号,暂时存放在24位数据寄存器中。

在接收到使能信号LE后,先前输入的24位数据根据地址位到达对应的锁存器[1]。

图1 ADF4360-1内部结构图ADF4360-1的主分频比N由双模预分频器(P/P+1)、可编程5位A计数器及13位B分频器实现,算法为N=B×P+A,输出频率为\:fout=(B×P+A)×fref/R,通过设置A,B,R三个控制字寄存器的控制字来实现对锁相环的控制。

该芯片外围只需添加环路滤波器,根据输出频率大小选择合适的参数,即可输出较稳定的频率。

1.2 主要性能[5]ADF4360-1是美国ADI公司生产的一款高性能锁相频率合成芯片,主要可应用于无线射频通信系统基站(GSM,WCDMA)、手机以及通信检测设备中,为上下变频提供本振信号。

其特性如下:工作电压: 3～3.6 V;输出信号功率可控范围具有四组可编程双模分频器8/9,16/17,31/32;三线串行接口进行编程控制;1.8 V逻辑兼容;输出功率可编程范围是-13～-6 dB;能够进行模拟和数字锁定检测;内部集成VCO;具有软件和硬件掉电模式。

2 系统的设计与实现在中频发射电路中,本振源电路模块对整个系统的稳定性起着至关重要的作用。

本文利用锁相频率合成芯片ADF4360-1设计2.33 GHz本振源信号,为射频发信机正交混频电路提供性能良好的本振载波。

电路框图如图2所示。

图2 本振源系统框图2.1 电路参数设定[5,6]基于锁相环的基本原理,只需要在内部集成VCO的频率合成芯片ADF4360-1外围加环路滤波器,即可实现PLL频率合成电路。

本电路设计中,ADF4360-1的PFD输入频率为200 kHz,因此参考时钟分频R=50。

由公式fout=(B×P+A)×fref/R,可计算出N为11 250,双模前置分频器设置为P/(P+1)=32/33,计数器A设置为18,计数器B设置为351。

根据ADF4360-1芯片资料,三个控制寄存器初始化设置为R寄存器0000C9H,C寄存器8FF128H,N寄存器015F4AH,如表1所示。

本振源电路输出信号功率为-6 dB。

表1 寄存器初始化设置值寄存器名称初始化值(MSB…LSB)R寄存器0000 0000 0000 0000 1100 1001C寄存器1000 1111 1111 0001 0010 1000N寄存器0000 0001 0101 1111 0100 10102.2 环路滤波器电路设计环路滤波器(LPF)具有低通特性,它主要是抑制鉴相器输出电压中的载频分量和高频噪声,降低由VCO控制电压的不纯而引起的寄生输出。

更重要的是它对环路参数调整起着决定性的作用。

利用AD公司提供的专用设计与仿真工具软件ADI simPLL对图2结构形成的无源三阶滤波电路进行仿真、设计。

依照软件提示,逐步设定各项参数,并选择芯片型号和环路滤波器形式,最后生成的电路如图3所示[7,8]。

图3 无源三阶滤波电路2.3 锁相环本振源电路设计完整的硬件原理图如图4所示。

图4 本振源电路硬件图电源电路采用TPS76333和LM317T产生稳定的3.3 V电压供电。

ADF4360-1的参考时钟输入引脚与晶振电路输出端相连,在内部VCO输入引脚VTUNE与内部电荷泵输出引脚CP之间接入三阶环路滤波电路。

核心芯片内部控制寄存器的初始化数值通过单片机控制写入,单片机采用ATMEL公司的AT89C2051。

3 编程控制及目标寄存器初始化[9]单片机P1.5,P1.6,P1.7 三个I/O口分别与芯片CLK,DATA,LE相连。

图5给出了数据输入的时序图。

数据(DATA)在每个时钟(CLOCK)的上升沿从MSB(最高有效位)开始依次写人24位移位寄存器中,直到LSB位写人完成之后,由来自LE的上升沿将存储在24位移位寄存器中的数据一次性锁存人目标寄存器(包括R计数锁存器、N计数锁存器、功能锁存器以及初始化锁存器),再进行下一个目标寄存器的初始化。

寄存器赋值顺序为R-C-N,目标寄存器的选择由移位寄存器最末两位DB0,DB1来决定,其中C和N寄存器的赋值时间间隔应大于5 ms。

图5 配置时序图单片机控制程序(R寄存器)如下:ORG 0000HMOV P3,#0FFHMOV P1,#0FFHMOV P2,#0FFHMOV P0,#0FFH…/*初始化子程序*/MOV33H,#00HMOV32H,#00HMOV31H,#C9H;r0=00 00 C9HLOOP1:CLRP1.5CLRP1.6CLRP1.7MOVR1,#06H;R1作循环计数用MOVA,33HRLCARLCALOOP11:RLCAMOVP1.6, C;向DATA端口写数据CLRCSETBP1.5 ;向CLOCK端口写1NOP ;高电平持续一段时间CLRP1.5 ;向CLOCK端口写0DJNZR1, LOOP11 ;直到送完全部位数据MOVR1, #08H ;R1作循环计数用MOVA,32H;参考分频器的低8位送入累加器A LOOP12:CLRP1.7;向LE端口写0RLCAMOVP1.6, C;向DATA端口写数据CLRCSETBP1.5;向CLOCK端口写1NOP;高电平持续一段时间CLRP1.5;向CLOCK端口写0DJNZR1,LOOP12;直到送完全部低8位数据MOVR1,#08H;R1作循环计数用MOVA,31H;参考分频器的低8位送入累加器ALOOP13:CLRP1.7;向LE端口写0RLCAMOVP1.6,C;向DATA端口写数据CLRCSETBP1.5;向CLOCK端口写1NOP;高电平持续一段时间CLRP1.5;向CLOCK端口写0DJNZR1, LOOP13;直到送完全部低8位数据SETBP1.7;向LE端口写1NOPCLRP1.7;向LE端口写04 结语本文介绍了利用锁相频率合成芯片ADF4360-1为中频射频发信机设计本振信号源,给出了设计的关键参数、控制流程以及部分程序代码。

最后测得相位噪声为-83 dBc/Hz@1 kHz,达到了基本标准。

由于ADF4360-1内部集成VCO、外部通过单片机I/O口写入控制字,因此该系统具有外围电路简单、调试方便、功耗和成本低等特点,可广泛应用于射频电路系统以及无线通信系统中。

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