91A1DD24D10R51中文资料
国产ds1991L-F5 参数说明书
SELOCKEY.SOA§ 1,152-bit secure read/write, nonvolatilememory§ Secure memory cannot be decipheredwithout matching 64-bit password§ Memory is partitioned into 3 blocks of 384bits each§ 64-bit password and ID fields for eachmemory block§ 512-bit scratchpad ensures data transferintegrity§ Operating temperature range: -40°C to+70°C§ Over 10 years of data retentionCOMMON Button FEATURES§ Unique, factory-lasered and tested 64-bitregistration number (8-bit family code + 48-bit serial number + 8-bit CRC tester) assures absolute traceability because no two parts are alike§ Multidrop controller for MicroBUS§ Digital identification and information bymomentary contact§ Chip-based data carrier compactly storesinformation§ Data can be accessed while affixed to object § Economically communicates to bus masterwith a single digital signal at 16.3k bits per second§ Standard 16 mm diameter and 1-Busprotocol ensure compatibility with Button family§ Button shape is self-aligning with cup-shaped probes§ Durable stainless steel case engraved withregistration number withstands harsh environments§ Easily affixed with self-stick adhesivebacking, latched by its flange, or locked with a ring pressed onto its rim§ Presence detector acknowledges when readerfirst applies voltageF5 MICROCAN TMAll dimensions shown in millimetersORDERING INFORMATIONTM1991L-F5F5 MicroCanTM1991MultiKey Button TMTM1991 Button DESCRIPTIONThe TM1991 MultiKey Button is a rugged read/write data carrier that acts as three separate electronic keys, offering 1,152 bits of secure, nonvolatile memory. Each key is 384 bits long with distinct 64-bit password and public ID fields (Figure 1). The password field must be matched in order to access the secure memory. Data is transferred serially via the 1-Bus protocol, which requires only a single data lead and a ground return. The 512-bit scratchpad serves to ensure integrity of data transfers to secure memory. Data should first be written to the scratchpad where it can be read back. After the data has been verified, a copy scratchpad command will transfer the data to the secure memory. This process ensures data integrity when modifying the memory. A 48-bit serial number is factory lasered into each TM1991 to provide a guaranteed unique identity which allows for absolute traceability. The family code for the TM1991 is 02h. The durable MicroCan package is highly resistant to environmental hazards such as dirt, moisture and shock. Its compact button-shaped profile is self-aligning with mating receptacles, allowing the TM1991 to be easily used by human operators. Accessories permit the TM1991 to be mounted on plastic key fobs, photo-ID badges, printed-circuit boards or any smooth surface of an object. Applications include secure access control, debit tokens, work-in-progress tracking, electronic travelers and proprietary data.OPERATIONThe TM1991 is accessed via a single data line using the 1-Bus protocol. The bus master must first provide one of the four ROM Function Commands, 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM. These commands operate on the 64-bit lasered ROM portion of each device and can singulate a specific device if many are present on the 1-Bus line as well as indicate to the bus master how many and what types of devices are present. The protocol required for these ROM Function Commands is described in Figure 9. After a ROM Function Command is successfully executed, the memory functions that operate on the secure memory and the scratchpad become accessible and the bus master may issue any one of the six Memory Function Commands specific to the TM1991. The protocol for these Memory Function Commands is described in Figure 5. All data is read and written least significant bit first.64-BIT LASERED ROMEach TM1991 contains a unique ROM code that is 64 bits long. The first eight bits are a 1-Bus family code. The next 48 bits are a unique serial number. The last eight bits are a CRC of the first 56 bits. (Figure 2.) The 1-Bus CRC is generated using a polynomial generator consisting of a shift register and XOR gates as shown in Figure 3. The polynomial is X8 + X5 + X4 + 1. Additional information about the Dallas 1-Bus Cyclic Redundancy Check is available in the Book of TM19xx Button Standards. The shift register bits are initialized to zero. Then starting with the least significant bit of the family code, one bit at a time is shifted in. After the 8th bit of the family code has been entered, then the serial number is entered. After the 48th bit of the serial number has been entered, the shift register contains the CRC value. Shifting in the eight bits of CRC should return the shift register to all zeros.MEMORY FUNCTION COMMANDSThe TM1991 has six device-specific commands. Three scratchpad commands: Write Scratchpad, Read Scratchpad and Copy Scratchpad and three subkey commands: Write Password, Write Subkey and Read Subkey. After the device is selected, the memory function command is written to the TM1991. The command is comprised of three fields, each one byte long. The first byte is the function code field. This field defines the six commands that can be executed. The second byte is the address field. The first six bits of this field define the starting address of the command. The last two bits of this field are the subkey address code. The third byte of the command is a complement of the second byte (Figure 4).TM1991 For the first use, since the passwords actually stored in the device are unknown, the TM1991 needs to be initialized. This is done by directly writing (i. e., not through the scratchpad) the new identifier and password for the selected subkey using the Write Password command. As soon as the new identifier and password are stored in the device, further updates should be done through the scratchpad.MEMORY MAP Figure 1* Each subkey or the scratchpad has its own unique address.64-BIT LASERED ROM Figure 28-Bit CRC Code48-Bit Serial Number8-Bit Family Code (02H) MSB LSB MSB LSB MSB LSB1-BUS CRC GENERATOR Figure 3TM1991 COMMAND STRUCTURE Figure 42nd byte3rd byte Command1st byteB7 B6B5 B4 B3 B2 B1 B0writescratchpad96H readscratchpad69H 1 1any value00H to 3FHcopyscratchpad3CH0 0 0 0 0 0readSubKey66H writeSubKey99Hany value 10H to 3FHwritepassword5AH Sub-KeyNr.:00or01or100 0 0 0 0 0ones complementof 2nd byteSCRATCHPAD COMMANDSThe 64-byte read/write scratchpad of the TM1991 is not password-protected. Its normal use is to build up a data structure to be verified and then copied to a secure subkey.Write Scratchpad [96H]The Write Scratchpad command is used to enter data into the scratchpad. The starting address for the write sequence is specified in the command. Data can be continuously written until the end of the scratchpad is reached or until the TM1991 is reset. The command sequence is shown in Figure 5, first page, left column.Read Scratchpad [69H]The Read Scratchpad command is used to retrieve data from the scratchpad. The starting address is specified in the command word. Data can be continuously read until the end of the scratchpad is reached or until the TM1991 is reset. The command sequence is shown in Figure 5, first page, center column.Copy Scratchpad [3CH]The Copy Scratchpad command is used to transfer specified data blocks from the scratchpad to a selected subkey. This command should be used when data verification is required before storage in a secure subkey. Data can be transferred in single 8-byte blocks or in one large 64-byte block. There are nine valid block selector codes that are used to specify which block is to be transferred (Figure 6). As a further precaution against accidental erasure of secure data, the 8-byte password of the destination subkey must be entered. If the password does not match, the operation is terminated. After the block of data is transferred to the secure subkey, the original data in the corresponding block of the scratchpad is erased. The command sequence is shown in Figure 5, first page, right column.SUBKEY COMMANDSEach of the subkeys within the TM1991 is accessed individually. Transactions to read and write data to a secured subkey start at the address defined in the command and proceed until the device is reset or the end of the subkey is reached.Write Password [5AH]The Write Password command is used to enter the ID and password of the selected subkey. This command will erase all of the data stored in the secure area as well as overwriting the ID and password fields with the new data. The TM1991 has a built-in check to ensure that the proper subkey was selected. The sequence begins by reading the ID field of the selected subkey; the ID of the subkey to be changed is then written into the part. If the IDs do not match, the sequence is terminated. Otherwise, the subkey contents are erased and 64 bits of new ID data are written followed by a new 64-bit password. The command sequence is shown in Figure 5, 2nd page, right column.MEMORY FUNCTIONS FLOW CHART Figure 5TMTMTMTMMEMORY FUNCTIONS FLOW CHART (cont’d) Figure 5 TMTMTM TMBLOCK SELECTOR CODES OF THE TM1991 Figure 6Block Nr.Address Range LS Byte Codes MS Byte0 to 700 to 3FH56567F51575D5A7F0identifier9A9A B39D646E694C1password9A9A4C629B91694C210H to 17H9A65B3629B6E964C318H to 1FH6A6A436D6B616643420H to 27H9595BC92949E99BC528H to 2FH659A4C9D649169B3630H to 37H6565B39D646E96B3738H to 3FH65654C629B9196B3Write SubKey [99H]The Write Subkey command is used to enter data into the selected subkey. Since the subkeys are secure, the correct password is required to access them. The sequence begins by reading the ID field; the password is then written back. If the password is incorrect, the transaction is terminated. Otherwise, the data following is written into the secure area. The starting address for the write sequence is specified in the command word. Data can be continuously written until the end of the secure subkey is reached or until the TM1991 is reset. The command sequence is shown in Figure 5, 2nd page, center column. Read SubKey [66H]The Read Subkey command is used to retrieve data from the selected subkey. Since the subkeys are secure, the correct password is required to access them. The sequence begins by reading the ID field; the password is then written back. If the password is incorrect, the TM1991 will transmit random data. Otherwise the data can be read from the subkey. The starting address is specified in the command. Data can be continuously read until the end of the subkey is reached or until the TM1991 is reset. The command sequence is shown in Figure 5, 2nd page, left column.1-Bus BUS SYSTEMThe 1-Bus bus is a system which has a single bus master and one or more slaves. In all instances, the TM1991 is a slave device. The bus master is typically a micro-controller. The discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1-Bus signaling (signal types and timing). A 1-Bus protocol defines bus transactions in terms of the bus state during specified time slots that are initiated on the falling edge of sync pulses from the bus master. For a more detailed protocol description, refer to Chapter 4 of the Book of TM19xx Button Standards.HARDWARE CONFIGURATIONThe 1- bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. To facilitate this, each device attached to the 1-Bus bus must have an open drain connections or 3-state outputs. The TM1991 is an open drain part with an internal circuit equivalent to that shown in Figure 7. The bus master can be the same equivalent circuit. If a bidirectional pin is not available, separate output and input pins can be tied together.The bus master requires a pullup resistor at the master end of the bus, with the bus master circuit equivalent to the one shown in Figures 8a and 8b. The value of the pullup resistor should be approximately 5 k W for short line lengths.A multidrop bus consists of a 1-Bus bus with multiple slaves attached. The 1-Bus bus has a maximum data rate of 16.3k bits per second. The idle state for the 1-Bus bus is high. If, for any reason a transactionTM1991needs to be suspended, the bus MUST be left in the idle state if the transaction is to resume. If this does not occur, and the bus is left low for more than 120 m s, one or more of the devices on the bus may be reset.EQUIVALENT CIRCUIT Figure 7BUS MASTER CIRCUIT Figure 8TMTMTMTRANSACTION SEQUENCEThe protocol for accessing the TM1991 via the 1-Bus port is as follows:§Initialization§ROM Function Command§Memory Function Command§Transaction/DataINITIALIZATIONAll transactions on the 1-Bus bus begin with an initialization sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). The presence pulse lets the bus master know that the TM1991 is on the bus and is ready to operate. For more details, see the “1-Bus Signaling” sectionROM FUNCTION COMMANDSOnce the bus master has detected a presence pulse, it can issue one of the four ROM function commands. All ROM function commands are eight bits long. A list of these commands follows (refer to flowchart in Figure 9).Read ROM [33H]This command allows the bus master to read the TM1991’s 8-bit family code, unique 48-bit serial number and 8-bit CRC. This command can be used only if there is a single TM1991 on the bus. If more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-AND result).Match ROM [55H]The match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific TM1991 on a multidrop bus. Only the TM1991 that exactly matches the 64-bit ROM sequence will respond to the subsequent memory function command. All slaves that do not match the 64-bit ROM sequence will wait for a reset pulse. This command can be used with a single or multiple devices on the bus.Skip ROM [CCH]This command can save time in a single drop bus system by allowing the bus master to access the memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus and a read command is issued following the Skip ROM command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain will produce a wired-AND result).Search ROM [F0H]When a system is initially brought up, the bus master might not know the number of devices on the 1-Wire bus or their 64-bit ROM codes. The Search ROM command allows the bus master to use a process of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The ROM search process is the repetition of a simple 3-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master performs this simple 3-step routine on each bit of the ROM. After one complete pass, the bus master knows the contents of the ROM in one device. The remaining number of devices and their ROM codes may be identified by additional passes. See Chapter 5 of the Book of TM19xx Button Standards for a comprehensive discussion of a search ROM, including an actual example.1-BUS SIGNALINGThe TM1991 requires strict protocols to ensure data integrity. The protocol consists of four types of signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1 and Read Data. All these signals except presence pulse are initiated by the bus master. The initialization sequence required to begin any communication with the TM1991 is shown in Figure 10. A reset pulse followed by a presence pulse indicates the TM1991 is ready to send or receive data given the correct ROM command and memory function command. The bus master transmits (TX) a reset pulse (t RSTL , minimum 480 m s).The bus master then releases the line and goes into receive mode (RX). The 1-Bus bus is pulled to a high state via the pullup resistor. After detecting the rising edge on the data pin, the TM1991 waits (t PDH , 15-60m s) and then transmits the presence pulse (t PDL , 60-240 m s).ROM FUNCTIONS FLOW CHART Figure 9TMTMTMTM TMTM TMTMTMTMINITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 10480 m s £ t RSTL < ¥ *480 m s £ t RSTH < ¥(includes recovery time)15 m s £ t PDH < 60 m s 60 m s £ t PDL < 240 m s* In order not to mask interrupt signaling by other devices on the 1-Bus bus, tRSTL + t R should alwaysbe less than 960 m s.READ/WRITE TIME SLOTSThe definitions of write and read time slots are illustrated in Figure 11. All time slots are initiated by the master driving the data line low. The falling edge of the data line synchronizes the TM1991 to the master by triggering a delay circuit in the TM1991. During write time slots, the delay circuit determines when the TM1991 will sample the data line. For a read data time slot, if a “0” is to be transmitted, the delay circuit determines how long the TM1991 will hold the data line low overriding the 1 generated by the master. If the data bit is a “1”, the Button will leave the read data time slot unchanged.READ/WRITE TIMING DIAGRAM Figure 11Write-One Time Slot60 m s £ t SLOT < 120 m s1 m s £ t LOW1< 15 m s 1 m s £ t REC < ¥TMREAD/WRITE TIMING DIAGRAM (cont’d) Figure 11Write-Zero Time Slot60 m s < t LOW0 < t SLOT < 120 m s 1 m s < t REC < ¥Read-Data Time Slot60 m s £ t SLOT < 120 m s 1 m s £ t LOWR < 15 m s 0 £ t RELEASE < 45 m s 1 m s £ t REC < ¥t RDV = 15 m s t SU < 1 m sTMPHYSICAL SPECIFICATIONSSize See mechanical drawingWeight 3.3 gramsHumidity 90% RH at 50°CAltitude 10,000 feetExpected Service Life 10 years at 25°C (150 million transactions, see note 4) Safety Meets UL#913 (4th Edit.); Intrinsically Safe Apparatus,Approved under Entity Concept for use in Class I, Division1, Group A, B, C and D LocationsABSOLUTE MAXIMUM RATINGS*Voltage on any Pin Relative to Ground -0.5V to +7.0VOperating Temperature -40°C to +70°CStorage Temperature -40°C to +70°C*This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.DC ELECTRICAL CHARACTERISTICS (V PUP *=2.8V to 6.0V; -40°C to +70°C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Logic Low V IL-0.30.8V1 Input Logic High V IH 2.2 6.0VOutput Logic Low @ 4 mA V OL0.4VOutput Logic High V OH V PUP 6.0V1,2 Input Resistance V IL500k W3* V PUP = external pullup voltageAC ELECTRICAL CHARACTERISTICS (-40°C to 70°C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Time Slot Period t SLOT60120m sWrite 1 Low Time t LOW1115m sWrite 0 Low Time t LOW060120m sRead Data Valid t RDV exactly 15m sRelease Time t RELEASE01545m sRead Data Setup t SU1m s5 Recovery Time t REC1m sReset Low Time t RSTL480m sReset High Time t RSTH480m s4 Presence Detect High t PDH1560m sPresence Detect Low t PDL60240m sNOTES:1.All voltages are referenced to ground.2.V PUP= external pullup voltage to system supply.3.Input pulldown resistance to ground.4.An additional reset or communication sequence cannot begin until the reset high time has expired.5.Read data setup time refers to the time the host must pull the 1-Bus bus low to read a bit. Data isguaranteed to be valid within 1 m s of this falling edge and will remain valid for 14 m s minimum.。
alienware area51-r4服务手册说明书
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Rev. A00目录1 拆装计算机内部组件之前 (10)开始之前 (10)安全说明 (10)建议工具 (10)螺钉列表 (11)2 拆装计算机内部组件之后 (14)3 技术概览 (15)计算机内部视图 (15)左侧视图 (15)右侧视图 (16)系统板组件 (17)I/O 板组件 (18)4 提起计算机 (19)步骤 (19)5 卸下稳定支脚 (20)步骤 (20)6 装回稳定支脚 (22)步骤 (22)7 卸下侧面面板 (23)步骤 (23)8 装回侧面面板 (24)步骤 (24)9 取出电池 (25)前提条件 (25)步骤 (25)10 装回电池 (26)步骤 (26)完成条件 (26)11 卸下电池盒 (27)前提条件 (27)3步骤 (27)12 装回电池盒 (28)步骤 (28)完成条件 (28)13 卸下硬盘驱动器。
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X9119TV14Z中文资料
Copyright Intersil Americas Inc. 2005, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners
X9119
Ordering Information
• Vary the frequency and duty cycle of timer ICs
• Vary the DC biasing of a pin diode attenuator in RF circuits
• Provide a control variable (I, V, or R) in feedback circuits
Functional Diagram
VCC
Features
• 1024 Resistor Taps – 10-Bit Resolution • 2-Wire Serial Interface for Write, Read, and
Transfer Operations of the Potentiometer • Wiper Resistance, 40Ω Typical @ VCC = 5V • Four Non-Volatile Data Registers • Non-Volatile Storage of Multiple Wiper Positions • Power-on Recall. Loads Saved Wiper Position on
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
BFR91A中文资料
13623
1
BFR91A Marking: BFR91A Plastic case (TO 50) 1 = Collector, 2 = Emitter, 3 = Base
Absolute Maximum Ratings
Tamb = 25_C, unless otherwise specified Parameter Collector-base voltage Collector-emitter voltage Emitter-base voltage Collector current Total power dissipation Junction temperature Storage temperature range Test Conditions Symbol VCBO VCEO VEBO IC Ptot Tj Tstg Value 20 12 2 50 300 150 –65 to +150 Unit V V V mA mW °C °C
Document Number 85031 Rev. 3, 20-Jan-99
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元器件交易网ຫໍສະໝຸດ BFR91AVishay Telefunken Electrical DC Characteristics
Tamb = 25_C, unless otherwise specified Parameter Collector cut-off current Collector-base cut-off current Emitter-base cut-off current Collector-emitter breakdown voltage Collector-emitter saturation voltage DC forward current transfer ratio Test Conditions VCE = 20 V, VBE = 0 VCB = 20 V, IE = 0 VEB = 2 V, IC = 0 IC = 1 mA, IB = 0 IC = 50 mA, IB = 5 mA VCE = 5 V, IC = 30 mA Symbol Min Typ Max Unit ICES 100 mA ICBO 100 nA IEBO 10 mA V(BR)CEO 12 V VCEsat 0.1 0.4 V hFE 40 90 150
ZL30120GGG中文资料
1A full Design Manual is available to qualified customers.To register, please send an email to TimingandSync@.Features•Synchronizes with standard telecom system references and synthesizes a wide variety of protected telecom line interface clocks that are compliant with Telcordia GR-1244-CORE, GR-253-CORE, ITU-T G.813, and compatible with ITU-T G.8261 (formerly G.pactiming)•Internal low jitter APLL provides SONET/SDHclocks including 6.48MHz, 19.44MHz, 38.88MHz, 51.84MHz and 77.76MHz, or 25MHz and 50MHz Synchronous Ethernet output clocks•Programmable output synthesizers (P0, P1)generate general purpose clock frequencies from any multiple of 8kHz up to 100MHz•Jitter performance of <8 ps RMS on the low jitter APLL outputs, and <20 ps RMS on the programmable synthesizer outputs.•Provides 8 reference inputs which support clock frequencies with any multiples of 8kHz up to 77.76MHz in addition to 2kHz•Provides two DPLLs which have independent modes of operation (locked, free-run, holdover) and optional hitless reference switching.•Flexible input reference monitoring automatically disqualifies references based on frequency and phase irregularities•Provides 3 sync inputs for output frame pulse alignment•Generates several styles of output frame pulses with selectable pulse width, polarity, and frequency •Configurable input to output delay, and output to output phase alignment•Supports IEEE 1149.1 JTAG Boundary ScanMay 2006Figure 1 - Block DiagramZL30120SONET/SDH/EthernetMulti-Rate Line Card SynchronizerData SheetOrdering InformationZL30120GGG 100 Pin CABGA Trays ZL30120GGG2100 Pin CABGA**Trays**Pb Free Tin/Silver/Copper-40o C to +85o CZL30120Data SheetApplications•AMCs for AdvancedTCA TM and MicroTCA Systems•Synchronous Ethernet•Multi-Service Edge Switches or Routers•DSLAM Line Cards•WAN Line Cards•RNC/Mobile Switching Center Line Cards•ADM Line CardsZL30120Data SheetTable of Contents1.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111.1 DPLL Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111.2 DPLL Mode Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121.3 Ref and Sync Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131.4 Ref and Sync Monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141.5 Output Clocks and Frame Pulses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151.6 Configurable Input-to-Output and Output-to-Output Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172.0 Software Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183.0 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25ZL30120Data SheetList of FiguresFigure 1 - Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - Automatic Mode State Machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 3 - Reference and Sync Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 4 - Output Frame Pulse Alignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 5 - Behaviour of the Guard Soak Timer during CFM or SCM Failures. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 6 - Output Clock Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 7 - Phase Delay Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17ZL30120Data SheetList of TablesTable 1 - DPLL1 and DPLL2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 2 - Set of Pre-Defined Auto-Detect Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 3 - Set of Pre-Defined Auto-Detect Sync Frequencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 4 - Output Clock and Frame Pulse Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16ZL30120Data Sheet Pin DescriptionPin # Name I/OType DescriptionInput ReferenceC1 B2 A3 C3 B3 B4 C4 A4ref0ref1ref2ref3ref4ref5ref6ref7I d Input References (LVCMOS, Schmitt Trigger). These are input referencesavailable to both DPLL1 and DPLL2 for synchronizing output clocks. All eightinput references can be automatically or manually selected using softwareregisters. These pins are internally pulled down to Vss.B1 A1 A2sync0sync1sync2I d Frame Pulse Synchronization References (LVCMOS, Schmitt Trigger).These are the frame pulse synchronization inputs associated with inputreferences 0, 1 and 2. These inputs accept frame pulses in a clock format (50%duty cycle) or a basic frame pulse format with minimum pulse width of 5ns.These pins are internally pulled down to V ss.Output Clocks and Frame PulsesD10apll_clk0O APLL Output Clock 0 (LVCMOS). This output can be configured to provide anyone of the available SONET/SDH clock outputs up to 77.76MHz, or 25MHz and50MHz. The default frequency for this output is 77.76MHz.G10apll_clk1O APLL Output Clock 1 (LVCMOS). This output can be configured to provide anyone of the available SONET/APLL clock outputs up to 77.76MHz, or 25MHz and50MHz. The default frequency for this output is 19.44MHz.E10apll_fp0O APLL Output Frame Pulse 0 (LVCMOS). This output can be configured toprovide virtually any style of output frame pulse synchronized with an associatedAPLL output clock. The default frequency for this frame pulse output is 8kHz.F10apll_fp1O APLL Output Frame Pulse 1 (LVCMOS). This output can be configured toprovide virtually any style of output frame pulse synchronized with an associatedAPLL output clock. The default frequency for this frame pulse output is 2kHz.K9p0_clk0O Programmable Synthesizer 0 - Output Clock 0 (LVCMOS). This output can beconfigured to provide any frequency with a multiple of 8kHz up to 100MHz inaddition to 2kHz. The default frequency for this output is 2.048MHz.K7p0_clk1O Programmable Synthesizer 0 - Output Clock 1 (LVCMOS). This is aprogrammable clock output configurable as a multiple or division of the p0_clk0frequency within the range of 2kHz to 100MHz. The default frequency for thisoutput is 8.192MHz.K8p0_fp0O Programmable Synthesizer 0 - Output Frame Pulse 0 (LVCMOS). This outputcan be configured to provide virtually any style of output frame pulse associatedwith the p0 clocks. The default frequency for this frame pulse output is 8kHz.J7p0_fp1O Programmable Synthesizer 0 - Output Frame Pulse 1 (LVCMOS). This outputcan be configured to provide virtually any style of output frame pulse associatedwith the p0 clocks. The default frequency for this frame pulse output is 8kHz.ZL30120Data SheetJ10p1_clk0OProgrammable Synthesizer 1 - Output Clock 0 (LVCMOS). This output can be configured to provide any frequency with a multiple of 8kHz up to 100MHz in addition to 2kHz. The default frequency for this output is 1.544MHz (DS1).K10p1_clk1OProgrammable Synthesizer1 - Output Clock 1 (LVCMOS). This is aprogrammable clock output configurable as a multiple or division of the p1_clk0 frequency within the range of 2kHz to 100MHz. The default frequency for this output is 3.088MHz (2x DS1).H10fb_clk OFeedback Clock (LVCMOS). This output is a buffered copy of the feedback clock for DPLL1. The frequency of this output always equals the frequency of the selected reference.E1dpll2_ref ODPLL2 Selected Output Reference (LVCMOS). This is a buffered copy of the output of the reference selector for DPLL2. Switching between input reference clocks at this output is not hitless.Control H5rst_bIReset (LVCMOS, Schmitt Trigger). A logic low at this input resets the device. To ensure proper operation, the device must be reset after power-up. Reset should be asserted for a minimum of 300ns.J5dpll1_hs_enI uDPLL1 Hitless Switching Enable (LVCMOS, Schmitt Trigger). A logic high at this input enables hitless reference switching. A logic low disables hitless reference switching and re-aligns DPLL1’s output phase to the phase of the selected reference input. This feature can also be controlled through software registers. This pin is internally pulled up to Vdd.C2D2dpll1_mod_sel0dpll1_mod_sel1I uDPLL1 Mode Select 1:0 (LVCMOS, Schmitt Trigger). During reset, the levels on these pins determine the default mode of operation for DPLL1 (Automatic, Normal, Holdover or Freerun). After reset, the mode of operation can becontrolled directly with these pins, or by accessing the dpll1_modesel register through the serial interface. This pin is internally pulled up to Vdd.Status H1dpll1_lockOLock Indicator (LVCMOS). This is the lock indicator pin for DPLL1. This output goes high when DPLL1’s output is frequency and phase locked to the input reference.J1dpll1_holdover OHoldover Indicator (LVCMOS). This pin goes high when DPLL1 enters the holdover mode.Serial Interface E2sck I Clock for Serial Interface (LVCMOS). Serial interface clock.F1si I Serial Interface Input (LVCMOS). Serial interface data input pin.G1so O Serial Interface Output (LVCMOS). Serial interface data output pin.E3cs_bI uChip Select for Serial Interface (LVCMOS). Serial interface chip select. This pin is internally pulled up to Vdd.Pin # Name I/O Type DescriptionZL30120Data Sheet G2int_b O Interrupt Pin (LVCMOS). Indicates a change of device status prompting theprocessor to read the enabled interrupt service registers (ISR). This pin is anopen drain, active low and requires an external pulled up to VDD.APLL Loop FilterA6apll_filter A External Analog PLL Loop Filter terminal.B6filter_ref0A Analog PLL External Loop Filter Reference.C6filter_ref1A Analog PLL External Loop Filter Reference.JTAG and TestJ4tdo O Test Serial Data Out (Output). JTAG serial data is output on this pin on thefalling edge of tck. This pin is held in high impedance state when JTAG scan isnot enabled.K2tdi I u Test Serial Data In (Input). JTAG serial test instructions and data are shifted inon this pin. This pin is internally pulled up to Vdd. If this pin is not used then itshould be left unconnected.H4trst_b I u Test Reset (LVCMOS). Asynchronously initializes the JTAG TAP controller byputting it in the Test-Logic-Reset state. This pin should be pulsed low on power-up to ensure that the device is in the normal functional state. This pin is internallypulled up to Vdd. If this pin is not used then it should be connected to GND.K3tck I Test Clock (LVCMOS): Provides the clock to the JTAG test logic. If this pin is notused then it should be pulled down to GND.J3tms I u Test Mode Select (LVCMOS). JTAG signal that controls the state transitions ofthe TAP controller. This pin is internally pulled up to V DD. If this pin is not usedthen it should be left unconnected.Master ClockK4osci I Oscillator Master Clock Input (LVCMOS). This input accepts a 20MHzreference from a clock oscillator (TCXO, OCXO). The stability and accuracy ofthe clock at this input determines the free-run accuracy and the long termholdover stability of the output clocks.K5osco O Oscillator Master Clock Output (LVCMOS). This pin must be left unconnectedwhen the osci pin is connected to a clock oscillator.MiscellaneousA9 A10 B5 B9 B10 C5 D1 D3 G3NC No Connection. Leave unconnected.Pin # Name I/OType DescriptionZL30120Data Sheet J2J6H7K1IC Internal Connection. Connect to ground.F2F3K6IC Internal Connection. Leave unconnected.Power and GroundD9 E4 G8 G9 J8 J9 H6 H8V DD PPPPPPPPPositive Supply Voltage. +3.3V DC nominal.E8 F4V CORE PPPositive Supply Voltage. +1.8V DC nominal.A5 A8 C10AV DD PPPPositive Analog Supply Voltage. +3.3V DC nominal.B7 B8 H2AV CORE PPPPositive Analog Supply Voltage. +1.8V DC nominal.D4 D5 D6 D7 E5 E6 E7 F5 F6 F7 G4 G5 G6 G7 E9 F8 F9 H9V SS GGGGGGGGGGGGGGGGGGGround. 0 Volts.Pin # Name I/OType DescriptionZL30120Data SheetI - InputI d -Input, Internally pulled down I u -Input, Internally pulled up O -Output A -Analog P -Power G -GroundA7C7C8C9D8H3AV SSG G G G G GAnalog Ground. 0 Volts.Pin # Name I/O Type DescriptionZL30120Data Sheet1.0 Functional DescriptionThe ZL30120 Multi-Rate Line Card Synchronizer is a highly integrated device that provides timing and synchronization for network interface cards. It incorporates two independent DPLLs, each capable of locking to one of eight input references and provides a wide variety of synchronized output clocks and frame pulses.1.1 DPLL FeaturesThe ZL30120 provides two independently controlled Digital Phase-Locked Loops (DPLL1, DPLL2) for clock and/or frame pulse synchronization. DPLL1 is the main DPLL and is always enabled. To save on power, DPLL2 is disabled by default. For applications where DPLL2 is required, it must be enabled using the dpll_en bit of the dpll2_ctrl_0register (0x2A). Table 1 shows a feature summary for both DPLLs.FeatureDPLL1DPLL2Modes of Operation Free-run, Normal (locked), Holdover Free-run, Normal (locked), Holdover Loop Bandwidth User selectable: 14Hz, 28Hz, or wideband 1 (890Hz / 56Hz / 14Hz)1. In the wideband mode, the loop bandwidth depends on the frequency of the reference input. For reference frequencies equal to or greater than 64kHz, the loop bandwidth = 890Hz. For reference frequencies equal to or greater than 8kHz and less than 64 kHz, the loop bandwidth = 56Hz. For reference frequencies equal to 2kHz, the loop bandwidth is equal to 14Hz.Fixed: 14HzPhase Slope Limiting User selectable: 885ns/s, 7.5µs/s, 61µs/s, or unlimited User selectable: 61µs/s, or unlimited Pull-in Range Fixed: 130ppmFixed: 130ppmHoldover ParametersSelectable Update Times: 26ms, 1s, 10s, 60s, and Selectable Holdover Post Filter BW: 18mHz, 2.5Hz, 10Hz. Fixed Update Time: 26ms No Holdover Post FilteringHoldover Frequency AccuracyBetter than 1ppb (Stratum 3E) initial frequency offset. Frequency drift depends on the 20MHz external oscillator.Better than 50ppb (Stratum 3) initial frequency offset. Frequency drift depends on the 20MHz external oscillator.Reference Inputs Ref0 to Ref7Ref0 to Ref7Sync Inputs Sync0, Sync1, Sync2Sync inputs are not supported.Input Reference Selection/Switching Automatic (based on programmable priority and revertiveness), or manual Automatic (based on programmable priority and revertiveness), or manual Hitless Ref Switching Can be enabled or disabledCan be enabled or disabled Output Clocks apll_clk0, apll_clk1, p0_clk0, p0_clk1, p1_clk0, p1_clk1, fb_clk.p0_clk0, p0_clk1, p1_clk0, p1_clk1.Output Frame Pulses apll_fp0, apll_fp1, p0_fp0, p0_fp1 synchronized to active sync reference.p0_fp0, p0_fp1 not synchronized to sync reference.External Pins Status IndicatorsLock, HoldoverNoneTable 1 - DPLL1 and DPLL2 FeaturesZL30120Data Sheet1.2 DPLL Mode ControlBoth DPLL1 and DPLL2 independently support three modes of operation - free-run, normal and holdover. The mode of operation can be manually set or controlled by an automatic state machine as shown in Figure 2.Figure 2 - Automatic Mode State MachineFree-runThe free-run mode occurs immediately after a reset cycle or when the DPLL has never been synchronized to areference input. In this mode, the frequency accuracy of the output clocks is equal to the frequency accuracy of the external master oscillator. Lock AcquisitionThe input references are continuously monitored for frequency accuracy and phase regularity. If at least one of the input references is qualified by the reference monitors, then the DPLL will begin lock acquisition on that input. Given a stable reference input, the ZL30120 will enter in the Normal (locked) mode.Normal (locked)The usual mode of operation for the DPLL is the normal mode where the DPLL phase locks to a selected qualified reference input and generates output clocks and frame pulses with a frequency accuracy equal to the frequency accuracy of the reference input. While in the normal mode, the DPLL’s clock and frame pulse outputs comply with the MTIE and TDEV wander generation specifications as described in Telcordia and ITU-T telecommunication standards.HoldoverWhen the DPLL operating in the normal mode loses its reference input, and no other qualified references are available, it will enter the holdover mode and continue to generate output clocks based on historical frequency data collected while the DPLL was synchronized.ResetAnother reference is qualified and availablefor selectionPhase lock on the selected reference is achievedLock AcquisitionNormal (Locked)No references are qualified and available for selectionFree-RunHoldoverSelected referencefailsAll references are monitored for frequency accuracy and phase regularity, and at least one reference is qualified.Normal (Locked)ZL30120Data Sheet1.3 Ref and Sync InputsThere are eight reference clock inputs (ref0 to ref7) available to both DPLL1 and DPLL2. The selected reference input is used to synchronize the output clocks. Each of the DPLLs have independent reference selectors which can be controlled using a built-in state machine or set in a manual mode.Figure 3 - Reference and Sync InputsIn addition to the reference inputs, DPLL1 has three optional frame pulse synchronization inputs (sync0 to sync2)used to align the output frame pulses. The sync n input is selected with its corresponding ref n input, where n = 0, 1,or 2. Note that the sync input cannot be used to synchronize the DPLL, it only determines the alignment of the frame pulse outputs. An example of output frame pulse alignment is shown in Figure 4.Figure 4 - Output Frame Pulse Alignmentref7:0sync2:0DPLL2DPLL1ref napll/p0/p1_clk xapll/p0_fp xWithout a frame pulse signal at the sync input, the output frame pulses will align to any arbitrary cycle of its associated output clock.sync n - no frame pulse signal presentWhen a frame pulse signal is present at the sync input, the DPLL will align the output frame pulses to the output clock edge that is aligned to the input frame pulse.ref n apll/p0/p1_clk xapll/p0_fp xsync nn = 0, 1, 2x = 0, 1n = 0, 1, 2x = 0, 1ZL30120Data Sheet Each of the ref inputs accept a single-ended LVCMOS clock with a frequency ranging from 2kHz to 77.76MHz. Built-in frequency detection circuitry automatically determines the frequency of the reference if its frequency is within the set of pre-defined frequencies as shown in Table 2. Custom frequencies definable in multiples of 8kHz are also available.2 kHz8 kHz64 kHz1.544 MHz2.048 MHz6.48 MHz8.192 MHz16.384 MHz19.44 MHz38.88 MHz77.76 MHzCustom ACustom BTable 2 - Set of Pre-Defined Auto-Detect Clock FrequenciesEach of the sync inputs accept a single-ended LVCMOS frame pulse. Since alignment is determined from the rising edge of the frame pulse, there is no duty cycle restriction on this input, but there is a minimum pulse width requirement of 5ns. Frequency detection for the sync inputs is automatic for the supported frame pulse frequencies shown in Table 3.166.67 Hz(48x 125 µs frames)400 Hz1 kHz2 kHz8 kHz64 kHzTable 3 - Set of Pre-Defined Auto-Detect Sync Frequencies1.4 Ref and Sync MonitoringAll input references (ref0 to ref7) are monitored for frequency accuracy and phase regularity. New references are qualified before they can be selected as a synchronization source, and qualified references are continuously monitored to ensure that they are suitable for synchronization. The process of qualifying a reference depends on four levels of monitoring.Single Cycle Monitor (SCM)The SCM block measures the period of each reference clock cycle to detect phase irregularities or a missing clock edge. In general, if the measured period deviates by more than 50% from the nominal period, then an SCM failure (scm_fail) is declared.ZL30120Data SheetCoarse Frequency Monitor (CFM)The CFM block monitors the reference frequency over a measurement period of 30µs so that it can quickly detect large changes in frequency. A CFM failure (cfm_fail) is triggered when the frequency has changed by more than 3%or approximately 30000ppm.Precise Frequency Monitor (PFM)The PFM block measures the frequency accuracy of the reference over a 10 second interval. To ensure an accurate frequency measurement, the PFM measurement interval is re-initiated if phase or frequency irregularities are detected by the SCM or CFM. The PFM provides a level of hysteresis between the acceptance range and the rejection range to prevent a failure indication from toggling between valid and invalid for references that are on the edge of the acceptance range.When determining the frequency accuracy of the reference input, the PFM uses the external oscillator’s output frequency (f ocsi ) as its point of reference. Guard Soak Timer (GST)The GST block mimics the operation of an analog integrator by accumulating failure events from the CFM and the SCM blocks and applying a selectable rate of decay when no failures are detected.As shown in Figure 5, a GST failure (gst_fail) is triggered when the accumulated failures have reached the upper threshold during the disqualification observation window. When there are no CFM or SCM failures, the accumulator decrements until it reaches its lower threshold during the qualification window.Figure 5 - Behaviour of the Guard Soak Timer during CFM or SCM FailuresAll sync inputs (sync0 to sync2) are continuously monitored to ensure that there is a correct number of reference clock cycles within the frame pulse period.1.5 Output Clocks and Frame PulsesThe ZL30120 offers a wide variety of outputs including two low jitter LVCMOS (apll_clk0, apll_clk1) output clocks and four programmable LVCMOS (p0_clk0, p0_clk1, p1_clk0, p1_clk1) output clocks. In addition to the clock outputs, two LVCMOS frame pulse outputs (apll_fp0, apll_fp1) and two LVCMOS programmable frame pulses (p0_fp0, p0_fp1) are also available.The feedback clock (fb_clk ) of DPLL1 is available as an output clock. Its output frequency is always equal to DPLL1’s selected input frequency.refCFM or SCM failuresupper thresholdlower thresholdt d - disqualification timet q - qualification time = n * t dt dt qgst_failZL30120Data SheetThe output clocks and frame pulses derived from the low jitter APLL are always synchronous with DPLL1, and the clocks and frame pulses generated from the programmable synthesizers can be synchronized to either DPLL1 or DPLL2. This allows the ZL30120 to have two independent timing paths.Figure 6 - Output Clock ConfigurationThe supported frequencies for the output clocks and frame pulses are shown in Table 4.apll_clk0, apll_clk1(LVCMOS)11. The apll_clk x outputs can generate either SONET/SDH or Ethernet frequencies (25MHz, 50MHz). p0_clk0, p1_clk0(LVCMOS)p0_clk1, p1_clk1(LVCMOS)apll_fp0, apll_fp1, p0_fp0, p0_fp1(LVCMOS)22. apll_fp x frequencies are available only when the low jitter apll is generating SONET/SDH frequencies6.48 MHz 2 kHz p x _clk0 p x _clk1 =2M166.67 Hz (48x 125 µs frames)9.72 MHz N * 8 kHz (up to 100MHz)400 Hz 12.96 MHz 1 kHz 19.44 MHz 2 kHz 25.92 MHz 4 kHz 38.88 MHz 8 kHz 51.84 MHz 32 kHz 77.76 MHz 64 kHz25 MHz 50 MHzTable 4 - Output Clock and Frame Pulse Frequenciesp0_clk0p0_fp0p0_clk1p0_fp1 P0 Synthesizerp1_clk0p1_clk1P1 Synthesizerapll_clk0apll_fp0apll_clk1apll_fp1Low Jitter APLLFeedback Synthesizerfb_clkDPLL2DPLL1ZL30120Data Sheet1.6 Configurable Input-to-Output and Output-to-Output DelaysThe ZL30120 allows programmable static delay compensation for controlling input-to-output and output-to-output delays of its clocks and frame pulses.All of the output synthesizers (APLL, P0, P1, Feedback) locked to DPLL1 can be configured to lead or lag the selected input reference clock using the DPLL1 Fine Delay . The delay is programmed in steps of 119.2ps with a range of -128 to +127 steps giving a total delay adjustment in the range of -15.26ns to +15.14ns. Negative values delay the output clock, positive values advance the output clock. Synthesizers that are locked to DPLL2 are unaffected by this delay adjustment.In addition to the fine delay introduced in the DPLL1 path, the APLL, P0, and P1 synthesizers have the ability to add their own fine delay adjustments using the P0 Fine Delay , P1 Fine Delay , and APLL Fine Delay . These delays are also programmable in steps of 119.2ps with a range of -128 to +127 steps.In addition to these delays, the single-ended output clocks of the APLL, P0, and P1 synthesizers can be independently offset by 90, 180 and 270 degrees using the Coarse Delay . The output frame pulses (APLL, P0) can be independently offset with respect to each other using the FP Delay .Figure 7 - Phase Delay AdjustmentsDPLL1DPLL2P0 Fine Delayp0_clk0p0_clk1p0_fp0p0_fp1 P0 SynthesizerCoarse DelayCoarse Delay FP Delay FP Delay fb_clkp1_clk0p1_clk1P1 Fine DelayLow Jitter APLLapll_clk0apll_clk1apll_fp0apll_fp1APLL Fine DelayFeedback SynthesizerDPLL1 Fine DelayCoarse DelayCoarse Delay FP Delay FP DelayCoarse Delay Coarse DelayP1 SynthesizerZL30120Data Sheet 2.0 Software ConfigurationThe ZL30120 is mainly controlled by accessing software registers through the serial peripheral interface (SPI). The device can be configured to operate in a highly automated manner which minimizes its interaction with the system’s processor, or it can operate in a manual mode where the system processor controls most of the operation of the device.The following table provides a summary of the registers available for status updates and configuration of the device.Addr (Hex)RegisterNameResetValue(Hex)Description TypeMiscellaneous Registers00id_reg A4Chip and version identification and reset readyindication registerR01use_hw_ctrl00Allows some functions of the device to becontrolled by hardware pinsR/WInterrupts02ref_fail_isr FF Reference failure interrupt service register R 03dpll1_isr70DPLL1 interrupt service register StickyR 04dpll2_isr00DPLL2 interrupt service register StickyR 05ref_mon_fail_0FF Ref0 and ref1 failure indications StickyR 06ref_mon_fail_1FF Ref2 and ref3 failure indications.StickyR 07ref_mon_fail_2FF Ref4 and ref5 failure indications StickyR 08ref_mon_fail_3FF Ref6 and ref7 failure indications StickyR 09ref_fail_isr_mask00Reference failure interrupt service registermaskR/W 0A dpll1_isr_mask00DPLL1 interrupt service register mask R/W 0B dpll2_isr_mask00DPLL2 interrupt service register mask R/W 0C ref_mon_fail_mask_0FF Control register to mask each failure indicatorfor ref0 and ref1R/W0D ref_mon_fail_mask_1FF Control register to mask each failure indicatorfor ref2 and ref3R/W0E ref_mon_fail_mask_2FF Control register to mask each failure indicatorfor ref4 and ref5R/W。
YAMAH MODUS F11 F01 说明书
Model
Serial No.
Purchase Date
FCC INFORMATION (U.S.A.)
1. IMPORTANT NOTICE: DO NOT MODIFY THIS UNIT!
This product, when installed as indicated in the instructions contained in this manual, meets FCC requirements. Modifications not expressly approved by Yamaha may void your authority, granted by the FCC, to use the product.
全志方案原理图
VCC
AVCC
CORE-VDD UVCC
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
LCD_D20 LCD_D19 LCD_D18 LCD_D15 LCD_D14 LCD_D13 LCD_D12 LCD_D11 LCD_D10 VCC3 LCD_D7 LCD_D6 LCD_D5 LCD_D4 LCD_D3 LCD_D2 VDD5_INT PB3/EINT17 PG4/UART1_RX/EINT4 PG3/UART1_TX/EINT3 PG2/EINT2 PG1/EINT1 PG0/EINT0 VDD5_CPU UBOOT NMI_N RESET_N PB18 PB17 NDQS VCC4 VDD6_CPU NDQ7/SDC2_D7 NDQ6/SDC2_D6 NDQ5/SDC2_D5 NDQ4/SDC2_D4 VDD7_CPU NDQ3/SDC2_D3 NDQ2/SDC2_D2 NDQ1/SDC2_D1 VDD8_CPU NDQ0/SDC2_D0 NRB1/SDC2_CLK NRB0/SDC2_CMD
方框内的元件标号请不要修 改layout时请直接COPY原厂 提供的DRAM参考PCB。
CRYSTAL
X24MI C36 X2 24M X24MO C37 20pF
D
20pF
SA[14:0] SBA[2:0] ND[7:0]
TWI0-SDA TWI0-SCK
C2
东元变频器电路图
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R82 103 C5 7
R512 1502 R7 2 38 31
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东元变频器 INTPBGBA0100AZ 110kVA 144A TECO 56-07785-0005 REY.01 3P160C 0640001 WEIGHT:04KG
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24G15N 用户手册说明书
24G15N安全 (1)标志惯例 (1)电源 (2)安装 (3)清洁 (4)其它 (5)设置 (6)物品清单 (6)安装支架和底座 (7)调整视角 (8)连接显示器 (9)Adaptive-Sync功能 (10)HDR (11)调节显示器 (12)热键 (12)OSD设定 (13)Luminance（明亮度） (14)Color Setup（颜色设置） (15)Picture Boost（窗口增亮） (16)OSD Setup（OSD设置） (17)Game Setting（游戏设置） (18)Extra（其它） (19)Exit（退出） (20)LED指示灯 (21)故障排除 (22)规格 (23)主要规格 (23)预设显示模式 (24)引脚分配 (25)即插即用版权说明.................................................................................................................................................................. ..................................................................................................................................................................2626安全标志惯例以下小节描述此文档中使用的标志惯例。
注释、注意和警告在本指南中，文本块可能带有图标并且以粗体或斜体打印。
这些文本块是注释、注意和警告，如下所示：注释：注意事项指示帮助你更好地使用你的计算机系统的重要信息。
注意：“注意”表示潜在的硬件损坏或数据丢失，并告诉您如何避免出现问题。
91华升富士达主板规格书
91华升富士达主板规格书1.电路板规格；外形图；材质：FR4环氧树脂；板厚：；2.接插件规格；JP 1,JP2:AMP178327；JP3,JP4,JP5:JSTB6P-VH；JP6,JP7,JP8,JP9:AMP17832；JP10:26针双列排线直座；JP11:RS232九针弯座；JP12:14针双列排线直座；JP13:CON8 A；3.主要元气件规格；U1：INTELN1.电路板规格外形图材质：FR4环氧树脂板厚：2.接插件规格JP1,JP2: AMP 178327JP3,JP4,JP5: JST B6P-VHJP6,JP7,JP8,JP9: AMP 178325JP10: 26针双列排线直座JP11: RS232九针弯座JP12: 14针双列排线直座JP13: CON8A3.主要元气件规格U1： INTEL N80C196U2： WSI PSD813F2U6，U11： PHILIPS SJA1000TU3，U5： TI TPIC6B273U7，U10，U12： FAIRCHILD 74HC245K1-K10： OMRON G6B-1114P4.端口定义★ - , - 为外部开关信号输入口，: 输入 X0,检修信号，断开为检修，闭合为自动 (输入类型不可更改): 输入 X1,上行信号. 在检修时闭合为点动上行，在司机时闭合为上行换向(输入类型不可更改): 输入 X2,下行信号. 在检修时闭合为点动下行，在司机时闭合为下行换向(输入类型不可更改): 输入 X3,上行多层终端换速开关, 2 米/秒以上电梯要求使用,(输入类型可更改,出厂值是常闭,低速电梯不用此信号时,请设置输入类型 X3为常开): 输入 X4,下行多层终端换速开关, 2 米/秒以上电梯要求使用,(输入类型可更改,出厂值是常闭，低速电梯不用此信号时,请设置输入类型X4 为常开): 输入 X5,上行限位开关 (输入类型可更改,出厂值是常闭触点） : 输入 X6,上行限位开关 (输入类型可更改,出厂值是常闭触点）: 输入 X7,上行单层终端换速开关. (输入类型可更改,出厂值是常闭触点） : 输入 X8,下行单层终端换速开关. (输入类型可更改,出厂值是常闭触点） : 输入 X9,上平层干簧 (输入类型可更改,出厂值是常开触点): 输入 X10,下平层干簧 (输入类型可更改,出厂值是常开触点）: 输入 X11,调速器故障输出信号 (输入类型可更改,出厂值是常开触点） : 输入 X12,消防开关 (输入类型可更改,出厂值是常开触点） : 输入 X13,安全回路继电器检测 (输入类型不可更改): 输入 X14,门锁回路继电器检测 (输入类型不可更改): 输入 X15,调速器进线接触器检测 (输入类型不可更改)★ - , - 为外部开关信号输入口和需要外部 +24V 电源输入，作为外部输入信号的隔离电源: 输入 X16,调速器出线接触器检测 (输入类型不可更改): 输入 X17,抱闸继电器检测 (输入类型不可更改): 输入 X18,门区信号输入，用于开门再平层和提前开门，闭合有效 (输入类型不可更改): 输入 X19,调速器运行信号检测，检测到此信号闭合则抱闸可以张开 (输入类型不可更改): 输入 X20,提前开门和再平层继电器检测: 输入 X21,火灾管制: 输入 X22,备用: 输入 X23,备用: 输入 X24,备用: 输入 X25,备用: X0-X25 输入信号公共端.: X0-X25 输入信号公共端.: X0-X25 隔离电路电源负极,0V.: X0-X25 隔离电路电源正极,+24V.: X0-X25 传感器用电源正极,+24V.内部与连通,负极用: X0-X25 传感器用电源正极,+24V.内部与连通,负极用★是主机板工作电源，由外部开关电源供电: 空端子: 0V 电源: +24V 电源: 0V 电源: +5V 电源: 空端子★作并联或群控用，作并联时只要连接对应两台主机的三根线: 空端子: TXV+ (+24V 电源输出): TXV- (0V 电源输出): TXA2+: TXA2-: 空端子★接外呼板和轿厢板,必须采用双绞线TXV+和TXV-用一对双绞线,TXA1+和TXA1-用另一对双绞线,推荐线径平方毫米,双绞线的绞合节距 25-35 毫米: 空端子: TXV+ (+24V 电源输出): TXV- (0V 电源输出): TXA1+: TXA1-: 空端子★是安全回路与门锁回路检测: 输入 X26 正电压端,+110V 输入,安全回路: 输入 X26 0V: 输入 X27 正电压端,+110V 输入,门锁回路: 输入 X27 0V: 输入 X28 正电压端,+110V 输入，备用: 输入 X28 0V: 空端子★ , 是继电器输出: 输出继电器 Y0，抱闸输出: 输出继电器 Y1，抱闸强激输出: 输出继电器 Y2, 调速器进线接触器★是继电器输出: 输出继电器 Y3 调速器出线接触器: 输出继电器 Y0,Y1,Y2,Y3 公共端: 输出继电器 Y4，开门继电器: 输出继电器 Y5，关门继电器: 输出继电器 Y6，提前开门或开门再平层继电器: 输出继电器 Y7，备用: 输出继电器 Y4,Y5,Y6,Y7 公共端: 输出继电器 Y8，消防输出指示指示(关门继电器1) : 输出继电器 Y9，电梯故障输出指示(开门继电器1) : 输出继电器 Y8,Y9 公共端★是 MOS 光藕隔离输出: 输出Y10，调速器上行方向: 输出Y11，调速器下行方向: 输出Y12，调速器运行使能: 输出Y13，调速器数字多段速度端口: 输出Y14，调速器数字多段速度端口: 输出Y15，调速器数字多段速度端口: 输出端口Y10-Y15的公共端Y13 Y14 Y15停车 0 0 0爬行 0 1 1检修 1 0 0单层 1 0 1双层 1 1 0多层 1 1 1★，，模拟信号输出: 模拟负载补偿信号，输出到调速器的力矩补偿端，±10V信号: 模拟速度给定，输出到调速器的速度设定端，0-10V信号: 模拟信号0V★是编码器输入接口★如果使用差分输出编码器，则,不接,适用于 CT,QuickMotion,KEB等调速器跳线 J3,J4,J5,J6 连接方式是:< - >< - >< - >< - >如果使用推挽输出编码器,请连接,到PG卡,适用于富士,安川等调速器跳线 J3,J4,J5,J6 连接方式是:< - >< - >< - >< - >: 接PG卡电源正极+12V或+15V输入: 接PG卡电源 0V.: 空端子: 空端子: 编码器 A 相，可以接受集电极开路输出或推挽输出，可接受频率为 0-100KHz: 编码器 B 相，可以接受集电极开路输出或推挽输出可接受频率为 0-100 KHz: 差分编码器 A+: 差分编码器 A-: 差分编码器 B+: 差分编码器 B-JP10: LCD 人机界面接口JP11: RS232/RS485 MODEM 远程监控接口(可以考虑成为手掌机调试接口，协议完全兼容): DCD三亿文库包含各类专业文献、生活休闲娱乐、中学教育、各类资格考试、外语学习资料、高等教育、文学作品欣赏、91华升富士达主板规格书等内容。
访客一体机参数表
1.1、18,可设置VIP人员，输入姓名，编号，如是V1P人员，则提示并打印VIP访客单，不需要选择被访人。
2.19、（可选功能）可直接在系统上进行身份证/IC卡/二维码直接授权门禁过闸机进出，离开刷闸机后系统自动签离、自动记录离开时间。
高端部件：采用比利时进口Me1exis原装红外探测器，精度高、性能稳定、质量可靠，为国内高端
配置。
金属材质：机壳采用金属材质，坚固耐用、不易变形或损坏。
产品特点
快速筛查：主动式采集红外温度数据，不需要人员操作，在小于1秒内快速完成测温。
非接触式测温：固定式红外温度传感器测量人体腕部或额头温度，避免测温人员与被测人员直接接触，引发交叉感染。
*1.6内置条码枪，红外自动连续扫描。
*1.7内置摄像头，CMOS传感器；帧速：120帧/秒；像素：130万。
*1.8内置热敏打印机：打印宽度：80mm,打印长度：26Ommo
1.9接口：USB2.0接口4个；TCP/IP网口1
1套
个；电话线接口2个；电源接口1个；音频输入输出接口各1个。
产品重量：净重10.65kgo
*2.4、拍摄存储功能：可抓拍现场图片并自动保存。（必须提供公安部检验报告或者省部级以上国家权威机构的证明文件）
2.5、登记功能：可采集访客信息，输入被访问人姓名，自动调出人员数据，完善被访人信息。
*2.6、被访人信息登记：（1）被访人姓名模糊查询，输入姓名的第一个字、或首字母、手机号（或房间号、电话号码、分机号）模糊查询，系统自动带出相应的被访人信息；（2）选择被访对象，可根据单位、部门、职工职位、职工姓名、电话等条件进行查询。
2.20、（可选功能）微信预约的访客登记时可扫描二维码通行证，系统自动带出预约信息进行快速登记。（可定制访客机内含二维码扫描器）
LN-9111D微机低周减载装置说明书
1．适用范围LN-9111D微机低周减载装置适用于主要用于低频低压减载，也可用于低频解列和低压解列。
2．主要功能可配置低频5轮，低压5轮。
16路遥信。
3．技术数据3.1额定参数装置电源：直流或交流220V或110V（订货时说明）额定交流：线电压100V，电流5A；频率50Hz功率消耗：电源回路不大于10瓦；交流回路不大于0.5伏安/相3.2技术指标整定范围电压：0.1Un～1.4Un （Un表示额定电压，以下同）保护误差范围电流（电压）：当定值低于额定值时误差不超过0.02In（Un），定值高于额定值时不超过±2% 时间：动作误差时间不大于±20ms，动作时间整定为O秒时，动作时间不大于40ms。
遥信事件记录分辨率：不大于2ms遥控正确率：不低于99.99%3.3 环境条件工作温度：－10℃～＋50℃贮运温度：－25℃～＋70℃大气压力：80kPa～110kPa相对湿度：不大于90％3.4 绝缘性能绝缘电阻：装置各导电电路对外露非带电金属部分及外壳之间，以及电气上无联系的不同电路之间，用开路电压500V的测试仪器分别测定其绝缘电阻值，不小于100MΩ。
介质强度：装置电源回路、交流回路、出口回路对地能承受2kV的工频试验电压，开入量回路之间及对地能承受1kV工频试验电压，历时1分钟,无绝缘击穿或闪络现象。
冲击电压：装置电源回路、交流回路、出口回路之间及对地能承受5kV标准雷电波的短时冲击电压试验,无绝缘击穿或闪络现象。
8-13.5 机械性能装置能承受《GB/T7261-2000 继电器及装置基本试验方法》中第16章规定的严酷等级为I级的振动响应，振动耐久试验。
装置能承受《GB/T7261-2000 继电器及装置基本试验方法》中第17章规定的严酷等级为I级的冲击响应，冲击耐久试验。
装置能承受《GB/T7261-2000 继电器及装置基本试验方法》中第18章规定的严酷等级为I级的碰撞试验。
PD191 单相表用户手册说明书
南京能保电气有限公司版权所有本用户手册适用于PD191型产品V2.*版本程序。
本用户手册和产品今后可能会有小的改动，请注意核对你使用的产品与手册的版本是否相符。
1 说明书单独成册 2015-9-1823更多产品信息，请访问：目录第一章绪论 (1)第一节概述 (1)功能简述 (1)硬件配置 (1)第二节特点及参数 (2)技术特点 (2)技术参数 (2)第三节订货信息 (3)第二章安装 (4)第一节安装须知 (4)过电流保护 (4)浪涌保护 (4)第二节安装尺寸及方法 (4)端子介绍 (5)接线示意图 (6)第三章操作 (8)第一节面板图示 (8)第二节参数设定操作方法 (9)第四章通信 (12)第一节命令格式及示例 (12)第二节电量系数 (13)第三节数据地址 (14)PD191单相表用户手册第一章 绪 论第一节 概述PD191智能配电仪表是一种采集配电信息，具备数据传输的数字仪表，它集数据采集与控制功能为一身。
它可以代替多种仪表、继电器、变送器和其他元件。
PD191智能配电仪表可安装在配电系统内的不同位置。
PD191智能配电仪表，是针对电力系统、工矿企业、公用设施、智能大厦的电力监控需求而设计的配电仪表。
该系列每种产品分别对应测量常规单相电参数,如单相电流、电压、有功、无功功率，功率因数，开关状态等。
它还能接受远方的控制命令，输出相应的出口，完成远方控制功能。
它具有模拟量输出功能，自定义输出的电量。
功能简述硬件配置第二节特点及参数技术特点PD191的设计充分考虑了可靠性、简易性、性价比等方面，现具有以下特点： • 可直接从电流、电压互感器接入信号• 可任意设置PT/CT变比• 2路的开入量（隔离）输入• 2路的开出量（继电器）输出• 1路的模拟量输出4～20mA• 多块仪表可设置不同的通讯地址，多种通信速率供选择• 可通信接入SCADA、PLC系统中• 可与绝大多数PLC相连（GE、Siemens、AB等）• 可与业界多种软件通讯（inTouch、Fix、GMS800、组态王等）技术参数输入信号电压输入•额定电压：100V/380V•过载能力：1.2倍额定值（连续） 2500V/1秒（不连续）•输入负荷：小于0.2VA输入电流•额定电流：5A、1A•过载能力：1.2倍额定值（连续） 100A/1秒（不连续）•输入负荷：小于0.2VA频率输入：45～55 HZ测量精度•电压、电流精度：0.5级•其他电量精度：1级•频率精度：0.1Hz通信•通信接口：RS-485 ，异步半双工，1位起始位，8位数据位，1位停止位，无校验•协议：MODBUS-RTU•波特率：4800～9600 bps工作环境•工作温度：-20℃～60℃• 存储温度：-40℃～75℃•相对湿度：5％～90％不结露信号开入• 接入方式：干接点接入• 光电耦合器隔离：4000VAC.rms信号开出• 输出方式：脉冲输出，遥控脉冲宽度为1秒• 继电器输出容量：5A/250VAC,5A/30VDC外形尺寸和重量• 长宽深：72x72x95mm• 净重：0.25KG电源• 工作电压：AC/DC 60～265V• 最大功耗：≤3W第三节订货信息第二章安装第一节安装须知过电流保护过电流保护建议在装置电源处加入1A的保险丝或空开。
爱尔顿空冷备用生电器系统9千瓦和11千瓦说明书
1Air-cooled standby generator systems 9 kW and 11 kWSystem overview• Complete backup power system featuring afull line of Eaton automatic transfer switchesand generators• Exclusive national Eaton Certified ContractorNetwork (ECCN) contractors for installation,maintenance, and service• Local sales expertise and round-the-clocktelephone pre-/post-sales technical supportEGSX200NSEAEGENA11T able 1. Generator featuresFeatures BenefitsEngine• Overhead valve industrial enginedesign (OHVI)• ”Spiny-lok” cast iron cylinder walls• Electronic ignition/spark advance• Full pressure lubrication system• Low oil pressure shutdown system• High temperature shutdown • Maximizes engine “breathing” for increased fuel efficiency. Plateau-honed cylinder walls and plasma moly rings help engine run cooler, reducing oil consumption. Because heat is the primary cause of engine wear, the OHVI has a significantly longer life than competitive engines • Rigid construction and added durability provide long engine life• Assured smooth, quick start every time• Pressurized lubrication to all vital bearings means better performance, less maintenance, and significantly longer engine life. Now featuring a 2-year/200-hour oil change interval• Superior shutdown protection prevents catastrophic engine damage from low oil• Prevents damage due to overheatingGenerator• Revolving field• Skewed stator (only)• Displaced phase excitation• Automatic voltage regulation• UL T 2200 Listed • Allows for smaller, lightweight unit that operates 25% more efficiently than a revolving armature generator• Produces a smooth output waveform for electronic equipment compatibility• Maximizes motor starting capability• Regulates the output voltage to ±2%, which prevents damaging voltage spikes• Compliant with all safety regulationsNew controller and controls• Auto/Manual/Off illuminated buttons• Utility voltage sensing• Utility interrupt delay• Engine warm up• Engine cool down• Main line circuit breaker• Electronic governor• Smart battery charger• Two-Line LCD multilingual display• Sealed, raised buttons• Generator voltage sensing• Programmable exercise • Selects the operating mode for easy, at-a-glance status indication in any condition• Weather-resistant interface allows smooth programming and operations for the user• Constantly monitors utility voltage, set points 60% dropout, and 80% pickup of standard voltage • Ensures engine is ready to assume the load, set point approximately 5 seconds• Allows engine to cool prior to shutdown, set point approximately 1 minute• Protects generator from overload• Maintains constant 60 Hz frequency• Delivers charge to the battery only when needed at varying rates depending on outdoor air temperature. Compatible with lead acid and AGM-style batteries• Provides homeowners easily visible logs of history, maintenance, and events up to 50 occurrences • Smooth, weather-resistant user interface for programming and operations• Constantly monitors generator voltage to ensure the cleanest power delivered to the home• Operates engine to prevent oil seal drying and damage between power outages by running the generator for 12 minutes every other week. Also offers a selectable setting for weekly or monthly operation providing flexibility and potentially lower fuel costs to the ownerUnit• SAE weather-protective enclosure• Enclosed critical grade muffler• Small, compact, attractive • Sound attenuated enclosures ensure quiet operation and protection against Mother Nature, withstanding winds up to 150 mph. Hinged key locking roof panel for security. Lift-out front for easy access to all routine maintenance items. Electrostatically applied textured epoxy paint for added durability• Quiet, critical grade muffler is mounted inside the unit to prevent injuries. Complies with local dB noise levels• Makes for an easy, eye-appealing installationInstallation system• 1-foot flexible fuel line connector• Direct-to-dirt composite mounting pad• Integral sediment trap • Easy installation• Complex lattice design prevents settling or sinking of the generator system• Prevents particles and moisture from entering the fuel regulator and engine, prolonging engine lifeWarranty a• 5-year limited warranty:• Years 1 and 2—limited comprehensive coverage on mileage, labor, and parts (warranty certification required)• Year 3—limited comprehensive coverage on parts only• Years 4 and 5—limited comprehensive coverage on engine (short block) and alternator (rotor and stator) parts only a For warranty details, refer to the “Eaton Air-Cooled Automatic Standby Generators” warranty statement.T able 2. Compatible automatic transfer switches aFeatures BenefitsEGSU series featuringuniversal active loadmanagement• Truly active load management system• RTC-100 controller with built-in intelligence• Universal compatibility with any generator brand (single-phase, 240 V)• No programming necessary• Whole house surge included (catalog number: CHSPT2ULTRA)• 50 or 60 Hz• Current sensors (CTs) included• Built-in 7-, 14-, and 28-day plant exerciser• Load and no-load transfer• Meets NEC T Article 702.5 for optional standby backup power systems• UL 1008 Listed• Actively balances electrical loads in the household, adjusting tohomeowner’s lifestyle• Complete home surge protector included to protect home electronicsand appliances against surge events• Complete power monitoring for greater accuracy and load management:voltage, current, and frequency• Power monitoring system allows 100% use of power output ratingin the generator• Contractor-friendly installation, requires fewer connections tothe generator• Environmentally friendly: allows downsizing of generator resultingin decrease of greenhouse gas (GHG) emissions, and reduces gasconsumption by 15% or moreEGSX series featuringload shedding• Two sets of contacts for load shedding• Simplified, non-redundant relay-interface system• Terminal block termination; connections labeled to match generatorconnections• Three-point keyhole mounting system for quick, level installation• Optimal wire bending space• Commercial grade main breaker included• UL 1008 compliant• Meets NEC Article 702.5 for optional standby backup power systems• Easy, intuitive installation for labor savings• Compatible with Eaton generators and most standby generator brands• Smallest footprint in the industry (400 A model)Warranty b• 1-year limited warranty from the date of installation or 18 months from the date of shipment, whichever occurs first• Extended and special warranties available:• 24 months—2% of contract price• 30 months—3% of contract price• 36 months—4% of contract pricea For selection information, visit our online green ATS interactive demo at .b For warranty details, refer to Eaton Selling Policy 25-000.T able 3. Automatic transfer switch specificationsAmperes VoltagesNumberof polesServiceentranceNumberof circuitsincluded a FrequencyEnclosuretypeContactorwire sizeranges(s)Numberof cablesper phaseWithstandcurrent(rms) at240 VacMost commongeneratorsizes bCatalognumberEGSU series50120/2402—2450/60NEMA 3R#14–#2/0110,0009, 11, 16 kW EGSU100L24RACA 50120/2402——50/60NEMA 3R#14–#2/0110,0009, 11, 16 kW EGSU100ACA 100120/2402Y—50/60NEMA 3R#14–#2/0110,0009, 11, 16 kW ESGU100NSEACA 100120/2402Y—50/60NEMA 3R#4–300 kcmil125,0009, 11, 16 kW EGSU150NSEACA 200120/2402——50/60NEMA 3R#4–300 kcmil125,00016, 20, 22 kW EGSU200ACA 200120/2402Y—50/60NEMA 3R#4–300 kcmil125,00016, 20, 22 kW EGSU200NSEACA 200120/2402Y—50/60NEMA 3R750 kcmil–2 /300 kcmil–1/01/235,000>22 kW EGSU400NSEACA EGSX series50120/2402Y1250/60NEMA 1#14–#6150009, 11 kW EGSX50L12 50120/2402—1250/60NEMA 3R#14–#6150009, 11 kW EGSX50L12R 100120/2402——50/60NEMA 3R#14–#2/0110,0009, 11, 16 kW EGSX100A 100120/2402Y—50/60NEMA 3R#14–#2/0110,0009, 11, 16 kW EGSX100NSEA 100120/2402—2450/60NEMA 3R#14–#2/0125,0009, 11, 16 kW EGSX100L24RA 150120/2402Y—50/60NEMA 3R#4–300 kcmil125,00016, 20, 22 kW EGSX150NSEA 200120/2402——50/60NEMA 3R#4–300 kcmil125,00016, 20, 22 kW EGSX200A 200120/2402Y—50/60NEMA 3R#4–300 kcmil125,00016, 20, 22 kW EGSX200NSEA 400120/2402Y—50/60NEMA 3R750 kcmil–2 /300 kcmil–1/01/235,000>22 kW EGSX400NSEAa Uses CH type circuit breakers.b For reference only. Generator size must be determined by actual load calculations.T able 4. Generator specificationsCatalog numberEGENA9EGENA11 GeneratorRated maximum continuous power capacity (LP)/(NG)9000/8000 watts a11,000/10,000 watts a Enclosure Aluminum AluminumRated voltage240240Rated maximum continuous load current 240 V b37.5/33.3 NG45.8/41.7 NGTotal harmonic distortion Less than 5%Less than 5%Main line circuit breaker40 A50 APhase Single SingleNumber of rotor poles22Rated AC frequency60 Hz60 HzPower factor 1.0 1.0Battery requirement (not included)Group 26R, 12 V and525 cold-cranking amperes minimumor Group 35AGM 650 cold-crankingamperes minimum Group 26R, 12 V and525 cold-cranking amperes minimum or Group 35AGM 650 cold-cranking amperes minimumUnit weight lb (kg)340/154348 (158)Dimensions in inches (mm) L x W x H 48.00 x 25.00 x 29.00(1219.2 x 635.0 x 736.6)48.00 x 25.00 x 29.00(1219.2 x 635.0 x 736.6)Sound output in dBA at 23 ft with generatoroperating at normal load6663EngineType of engine OHVI OHVI V-TWINNumber of cylinders12Displacement410 cc530 ccCylinder block Aluminum with cast iron sleeve Aluminum with cast iron sleeve Valve arrangement Overhead valve Overhead valveIgnition system Solid-state with magneto Solid-state with magneto Governor system Electronic Electronic Compression ratio9.0:19.5:1Starter12 Vdc12 VdcOil capacity including filter Approximately 1.1 qt/1.0 L Approximately 1.7 qt/1.6 L Operating RPM3,6003,600Fuel consumption cNatural gas ft³/hr (m³/hr): 1/2 loadFull load 90 (2.55)120 (3.4)107 (3.03)159 (4.50)Liquid propane ft³/hr (gal/hr) (liters/hr): 1/2 loadFull load 31.6 (0.87) (3.29)50 (1.37) (5.2)44.4 (1.22) (4.62)71.6 (1.97) (7.45)a Suitable for “optional” standby backup power only, as indicated by NEC Article 702. Not suitable for legally required “emergency” life safety applications as required by NEC Article 700 and NFPA 110/99. All ratings in accordance with BS5514, ISO3046, and DIN6271. Maximum wattage and current are subject to and limited by such factors as fuel BTU content, ambient temperature, altitude, engine power, and condition. Maximum power decreases about 3.5% for each 1000 feet above sea level, and also will decrease about 1% for each 12 °C (10 °F) above 15.5 °C (60 °F).b LP = Liquid propaneNG = Natural gasc Gas pipe sizing is critical for the proper operation of the generator. Fuel pipe must be sized for full load. Required fuel pressure to generator fuel inlet at all load ranges—3.5 to 7 inches water column(7 to 13 mm mercury) for natural gas, 10 to 12 inches water column (19 to 22 mm mercury) for LP gas. For BTU content, multiply ft3/hr x 2500 (LP) or ft3/hr x 1000 (NG). For Megajoule content,multiply m3/hr x 93.15 (LP) or m3/hr x 37.26 (NG).T able 5. Generator controlsFeatures DescriptionTwo-line plain text multilingual LCD display Simple user interface for ease of operationMode buttonsAutoManualOffAutomatic start on utility failure. 7-day exerciser (7-, 14-, and 28-day exerciser when coupled with EGSU ATS)Start with starter control, unit stays on. If utility fails, transfer to load takes placeStops unit. Power is removed. Control and charger still operateReady to run/maintenance messages StandardEngine run hours indication StandardProgrammable start delay between 2 and 1500 seconds Standard (programmable by dealer only)Utility voltage loss/return to utility adjustable From 140 V to 171 V/190 V to 216 VFuture set capable exerciser/exercise set error warning StandardRun/alarm/maintenance logs50 events eachEngine start sequence Cyclic cranking 16 seconds on, 7 rest (90 seconds maximum duration)Starter lockout Starter cannot re-engage unit 5 seconds after engine has stoppedSmart battery charger StandardCharger fault/missing AC warning StandardLow battery/battery problem protection and battery condition indication StandardAutomatic voltage regulation with overvoltage and undervoltage protection StandardUnderfrequency/overload/stepper overcurrent protection StandardSafety fused/fuse problem protection StandardAutomatic low oil pressure/high oil temperature shutdown StandardOvercrank/overspeed at 72 Hz/RPM sense loss shutdown StandardHigh engine temperature shutdown StandardInternal fault/incorrect wiring protection StandardCommon external fault capacity StandardField-upgradable firmware StandardT able 6. Compatible accessories and replacement parts—EGENA generatorsDescription Benefits/features Catalog number Maintenance and general accessoriesBattery pad warmer The pad warmer rests under the battery. Recommended for use if the temperature regularly falls below 0 7F.(Not necessary for use with AGM-style batteries).7101CHOil warmer Oil warmer slips directly over the oil filter. Recommended for use if the temperature regularly falls below 0 7F.7102CH Breather warmer The breather warmer is for use in extreme cold weather applications. For use with standard controllersonly in climates where heavy icing occurs.7103CHMaintenance kit for 9 kW generators Includes all hardware and material necessary to perform scheduled preventive maintenance. Compatiblewith model EGENX9 only.6482CHMaintenance kit for 11 kW generators Includes all hardware and material necessary to perform scheduled preventive maintenance. Compatiblewith model EGENX11 only.6483CH Bisque color paint kit Ideal for touch-up paint/maintenance to generator enclosure against scratches and future corrosion.EGENPAINT Generator fascia Enhances aesthetics. Installs in seconds (standard with EGENX20A and EGENX22A models).EGENFASCIA Air-cooled transportation cart User-friendly assembly, attaches to lifting holes. Smart design allows only one person to lift the unitoff of wooden pallet and position it for final installation.EGENCART MonitoringMobile wireless remote monitor Most advanced generator status monitoring system. Allows connectivity and settings programmingvia smart devices (laptops, smartphone, pad, etc.). Sends automated emails and/or text messagesto multiple users. Requires cell phone signal and subscription.EGENMOBILEIn-house wireless monitor In-house generator status basic monitoring system. No computer connectivity required. 600 ft radiusof wireless coverage.EGENINHOME T able 7. Replacement parts—EGSX ATSComponent Catalog number50 A100 A150 A200 A400 AContactor99-5643-899-5638-1299-5702-1599-5702-1599-5702-16 Wire harness a99-5643-799-5638-1399-5702-1799-5702-1799-5702-18 Neutral bar99-5643-699-5638-799-5702-699-5702-699-5702-13 Ground lugs99-5643-499-5638-599-5702-499-5702-499-5702-4 Service entrance breaker—99-5638-4CSR2150CSR2200KD2400 Contactor lugs99-5643-599-5638-699-5702-599-5702-599-5702-12 a Includes relay and mounting base.T able 8. Replacement parts—EGSU ATSComponent Catalog number100 A150 A200 A400 AController RTC100RTC100RTC100RTC100 Contactor99-5638-1299-5702-1599-5702-1599-5702-16 Wire harness99-5638-1499-5702-799-5702-799-5702-19 Service entrance breaker99-5638-4CSR2150CSR2200KD2400 c Ground bar99-5638-5 a99-5702-49-5702-499-5702-4 Contactor lugs99-5638-699-5702-599-5702-599-5702-12 Neutral bar99-5638-7 b99-5702-699-5702-699-5702-13 Current sensors CS200CS200CS200CS400 Whole house surge protector CHSPT2ULTRA CHSPT2ULTRA CHSPT2ULTRA CHSPT2ULTRAa For EGSU100L24RACA, order ground bar catalog number 99-5638-15.b For EGSU100L24RACA, order neutral bar catalog number 99-5638-17.c For breaker lugs, order catalog number 2TA401K.Figure 1. Air-cooled generator 9 kW and 11 kW—dimensions in inches (mm) Dimensions shown are approximate. Design and specificationssubject to change without notice. For additional information, visitour website at , call our technicalresource center at (877) ETN-CARE (386-2273), or contact yourlocal Eaton authorized distributor.Eaton1000 Eaton Boulevard Cleveland, OH 44122 United States © 2016 EatonAll Rights ReservedPrinted in USAPublication No. TD00405002E / Z19034 December 2016Eaton is a registered trademark.All other trademarks are propertyof their respective owners.Air-cooled standby generator systems 9 kW and 11 kWTechnical Data TD00405002EEffective December 2016Figure 2. Plan view of an EGSX150NSEA/EGSX200NSEA—dimensions in inches (mm)T able 9. Automatic transfer switches approximate dimensions in inches (mm)Amperes Width Height Depth Weight in lb (kg) 5014.25 (362.0)21.00 (533.4) 4.00 (101.6)23 (10.43) 10014.46 (367.3)16.87 (428.5) 5.32 (135.1)25 (11.33)100 with loadcenter14.46 (367.3)29.33 (745.0) 5.32 (135.1)38 (17.23) 15014.46 (367.3)29.33 (745.0) 5.32 (135.1)45 (20.41)200 a14.46 (367.3)29.33 (745.0) 5.32 (135.1)45 (20.41) 40023.14 (587.8)37.56 (954.0)10.00 (254.0)130 (58.96)a Height for 200 A non-SE is 25.08 (637.0).。
DS91M124 125MHz 1 4 M-LVDS Repeater with LVCMOS In
DS91M124 125 MHz 1:4 M-LVDS Repeater with LVCMOS Input Evaluation KitUSER MANUALPart Number: DS91M124EVK NOPBFor the latest documents concerning these products and evaluation kit, visit . Schematics andgerber files are also available at OverviewThe purpose of this document is to familiarize you with the DS91M124 evaluation board, suggest the test setup procedures and instrumentation, and to guide you through some typical measurements that will demonstrate the performance of the device. The board enables the user to examine performance and all functions of theDS91M124 as a standalone device.The DS91M124 is a high-speed 1:4 M-LVDS repeater with a LVCMOS input designed for multipoint applications with multiple drivers or receivers. The device conforms to TIA/EIA-899 standard. It utilizes M-LVDS technology for low power, high-speed and superior noise immunity.DescriptionFigure 1 below represents the top layer drawing of the board with the silkscreen annotations. It is a 2.5 x 3 inch 4 layer printed circuit board (PCB) that features a single DS91M124 (U2) device.Figure 1 -DS91M124EVK Top View DrawingDS91M124 Evaluation in a Point-to-Point LinkThe following is a recommended procedure for using and evaluating the DS91M124EVK. Figure 2 depicts a typical setup and instrumentation used.1. Select a single DS91M124 evaluation board.2. Apply the power to the board (3.3 V typical) between J3 and J4 power tabs, observe the value of I CC,and compare it with the expected value (refer to the datasheet) to ensure that the devices arefunctional.3. Enable one of the U2 driver outputs. This is accomplished by setting the DE0-3 pin to VDD (JP3-6).4. Connect a signal source to the driver input (DI). The signal needs to be a LVCMOS compliant signal.Refer to the DS91M124 datasheet for the receiver input compatibility.5. Connect one of the U2 outputs (A0-3/B0-3) to an oscilloscope and observe the waveforms.Figure 2 – DS91M124 Test SetupFigure 3 shows an eye diagram acquired at the output of the DS91M124 driver loaded with a 100-ohm resistor. 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