Boundary scan
边界扫描技术
互联测试步骤：
• 1）TDI经过各移位寄存器与各IC管脚相关的 单元连接，移位激励数据； • 2）更新输出单元上的数据，对PCB电路板 上的连线施加激励； • 3）在各接收IC的输入管脚捕获PCB电路板上 连线的状态； • 4）检查经过边界扫描寄存器向TDO移出的 最后结果。
扫描测试过程
互联测试工作模式
• • • • 1）串行链工作 2）并行链工作 3）多输出工作 4）旁路工作
测试工作模式
边界扫描测试数学模型
• 边界扫描测试是将由一定数量测试向量构 成的测试矩阵T输入电路板A，依据响应矩 阵R进行诊断。测试矩阵中的每个PTV向量 维数为N，它对应于N个网络的布尔输入， 而R矩阵中的每个PRV向量的维数也为N，它 对应于N个网络的布尔输出。因此，实质上 我们可以将被测电路板看作一个N输入/N输 出的系统 • • • 测试存取口( Test Access Port TA P ) TA P 控制器(TAP Controller) 指令寄存器( Instruction Register IR) 测试数据寄存器(Data Register DR )
• IEEE 1149. 1标准规定
标准边界扫描结构
测试存取口（TAP）
• • • • • • 由四个专用引脚组成: 测试数据输入(Test Data In TD I) 测试数据输出(Test Data Out TDO ) 测试模式选择(Test Mode Select TM S ) 测试时钟(Test Clock TCK )。 (另有一个TRST* 为可选)
边界扫描工作方式
• • • • 内部测试方式 外部测试方式 采样测试方式 电路板正常工作方式
外部测试原理
• 边界扫描外部测试是完成对电路板上的互 连故障进行测试诊断，基本思想是在靠近 器件的输入输出管脚处增加一个移位寄存 器单元。在测试期间，这些寄存器单元用 于控制输入管脚的状态（高或低），并读 输出管脚的状态，利用这种基本思想可以 测试出电路板中器件互连的正确性。在正 常工作期间，这些附加的移位寄存器单元 是“透明” 的，不影响电路板的正常工作。
集成电路边界扫描测试中的电路网表结构分析
集成电路边界扫描测试中的电路网表结构分析集成电路边界扫描测试（Boundary Scan Testing，BST）是一种广泛应用于VLSI设计和制造中的测试技术。
BST是一种将测试功能集成到复杂的芯片设计中的方法，它可以诊断集成电路中的任何一个缺陷，从而提高产品的质量和性能。
BST采用的核心技术是边界扫描技术（Boundary Scan），用于测试芯片的连接性、可编程逻辑器件（Programmable Logic Devices，PLD）和电路的故障诊断。
在BST中，电路网表结构分析是非常关键的一个步骤。
电路网表结构指的是VLSI集成电路中各个模块相互连接的电路线路结构，也就是电路的物理连接方式。
电路网表结构分析的主要目的是找出部分设计错误和模块之间的错误连接，以确保VLSI集成电路在边界扫描测试过程中能够被正确地测试。
电路网表结构分析需要一些专门的工具和软件来实现。
首先，我们需要对VLSI集成电路进行仿真和验证，确定其运行正确。
然后，需要将电路分解成多个模块和其相应的边界扫描单元（Boundary Scan Cells）。
Boundary Scan Cells是一种可设置逻辑器件，可以被串联到某个端口上，常常与电路网表结构密切相关。
在电路网表结构分析的过程中，我们需要同时验证电路网表结构和单元测试。
我们可以通过检查边界扫描链上的信号线路和寄存器电路是否正确来检测电路网表结构错误。
如果有任何电路连接错误，那么边界扫描测试将无法在这些错误地连接的边界扫描单元上进行正确测试，从而导致电路测试失败。
电路网表结构分析在VLSI设计过程中非常重要，它可以帮助我们找出设计中的错误和潜在的问题，最终确保集成电路在真正的测试前可以顺利进行边界扫描测试，从而提高产品的质量和性能。
在今后的VLSI设计工作中，电路网表结构分析将继续发挥重要作用，帮助人们设计出更加合理、优秀的电路设计。
boundaryscan应用实例 -回复
boundaryscan应用实例-回复什么是boundary scan技术？Boundary scan技术，又称JTAG（Joint Test Action Group）技术，是一种用于芯片级电路板测试和诊断的技术。
它使用了IEEE标准1149.1定义的边界扫描链（Boundary Scan Chain），通过在电路板上的闩锁功能来实现对芯片上的引脚的测试和调试。
Boundary scan技术的原理和功能如何工作？Boundary scan技术的原理基于一种边界扫描链结构（Boundary Scan Chain），该链将所有芯片引脚连接起来形成一个环。
这个环具有使能信号和测试控制信号，通过这些信号的控制，可以将测试数据从一个引脚传输到另一个引脚，实现对芯片引脚的测试和调试。
Boundary scan技术的功能主要有以下几个方面：1. 电路连通性测试：通过boundary scan技术，可以检测和诊断电路板上信号线的连通性是否良好，以及是否存在断路和短路。
2. 引脚功能测试：通过boundary scan技术，可以实时测试和诊断芯片引脚的功能是否正常。
这对于芯片级的调试和故障排除非常有用。
3. 元件配置和诊断：通过boundary scan技术，可以识别和配置电路板上的各种元件，例如存储器、逻辑门等。
这可以帮助工程师更好地了解电路板的组成和功能。
4. 容错性检查：通过boundary scan技术，可以检查电路板上的信号线是否遵循电气特性，例如正确的电阻和电容值。
这对于确保电路板的稳定性和可靠性至关重要。
Boundary scan技术的应用实例1. 电子设备制造：Boundary scan技术可以在生产线上用于测试和验证电子设备的电路板，以确保其质量和可靠性。
它可以有效地检测和排除电路板上的连通性问题和故障，提高生产效率和产品质量。
2. 电路板维修：当电子设备发生故障时，boundary scan技术可以用于定位和修复故障点。
Corelis ScanExpress Merge 边界扫描测试执行器 说明书
ScanExpress Merge Boundary -Scan Test ExecutiveCorelis ScanExpress Merge, amember of the ScanExpress suite of boundary -scan test tools, is a software application designed to import and join test files for multiple independent assemblies and assist in configuration of a combined test procedure.Using completed ScanExpress TPG test files and moduleinterconnection data, ScanExpress Merge quickly combines combined test plan files for system testing with minimal user effort.Now boundary -scan tests can be easily extended to test systems that consist of multiple PCBs, multi -chip modules, or coverage extending IO modules—treating them as a single, combined unit for cohesive,complete, and convenient system -level testing.Features• Automatically combines board -leveltest projects for use with system level test generation• Supports all boundary -scan testsincluding infrastructure, interconnect, buswire, clusters, memories, and Flash• Automatically creates connection lists for mated connectors• Includes built -in support for CorelisScanIO ™ and ScanDIMM ™ boundary -scan IO modules• Intuitive step -by -step wizard simplifiesthe merge process• Integrates with ScanExpress TPG ™ forfast and convenient test development and generation• Compliant to IEEE standards 1149.1and 1149.6 • Compatible with Microsoft Windows7/8.1/10Benefits• Test multiple sub -assemblies with asingle test plan for increased test coverage and convenience• Increase overall test coverage toinclude connectors between system assemblies• Painless integration of additionalboundary -scan IO modules for expanded test coverage• Compatible with the ScanExpressTPG Integrated Development Environment (IDE) for automatic development and generationTest Integrate ™Applications• Hierarchical & Modular Systems are tested as individual components or as a whole with the system assembled.•Connector Tests are easily added to any project with ScanDIMM, ScanPCI, and ScanIO modules to increase boundary -scan test coverage.•Backplane Testing is simplified with simple test preparation and automatic mating list generation.•Multi -chip Modules (MCM) can be defined by their internal components, allowing boundary -scan testing System -on -a -Chip (SoC), System -in -a -Package (SIP), and other intra -IC interconnect technologies.Re -useExtendScanExpress Merge1ScanExpress JET test step execution requires a JET family support package license.ScanExpress Runner ™, ScanExpress ADO ™, ScanExpress TPG ™, ScanExpress Flash Generator ™, and ScanExpress JET ™ are trademarks of Corelis, Inc.All other product or service names are the property of their respective owners.© Copyright Corelis, Inc. 2020. All rights reserved. Corelis, Inc. reserves the right to make changes in design or specification at any time and without notice.20650-DS– 3/16/2019Ordering InformationPart Number - 20650For more information, or to order this product online, please visit our website at 13100 Alondra Blvd. Cerritos, CA 90703, USAUS & Canada | +1 888-808-2380 International | +1 562-926-6727 Fax | +1 562-404-6196 ™The ScanExpress Merge software application facilitates combination and generation ofboundary -test test projects for multiple interconnected Units Under Test (UUTs) and external boundary -scan modules. ScanExpress Merge integrates with the ScanExpress TPG test development and generation application to combine test data for multiple assemblies into a single, unified test project.Multiple Target AssembliesIn a typical application, ScanExpress TPG is used to generate tests for each system board independently. After creating the individual tests, ScanExpress Merge combines all test generation files into a single combined file set for testing the complete system, offering increased convenience and additional test coverage.ScanExpress Merge can be used to combine tests for multiple boards connected by a backplane. By combining tests for the individual boards with interconnection defini-tions for the backplane, ScanExpress Merge can create a single, unified test for the assembled system.Graphical User InterfaceThe ScanExpress Merge software application is fully integrated into the ScanExpress TPG development environment. The ScanExpress Merge interactive Graphical User Interface (GUI) guides the user through the process of entering and configuring as-semblies in the merge plan. Once all assembly information has been defined, ScanEx-press Merge automatically loads the combined project into ScanExpress TPG for fur-ther test development and vector generation.ScanExpress Merge Graphical User InterfaceCombining assembly tests can increase overall boundary -scan test coverage.ScanIO Module IntegrationScanExpress Merge automates the process of developing tests for sys-tems that include connections to DIMM memory sockets, PCI slots, and ScanIO connectors. ScanExpress Merge combines the data of the board and the data of the ScanIO, ScanPCI, and ScanDIMM parallel IO modules into a single set of input files for use with the ScanExpress TPG intelligent test pattern generator soft-ware. The process is completely auto-mated to save time—no need to manually describe the connections between the PCB connectors and the modules.。
Boundary scan
什么是boundary scan?边界扫描(Boundary scan )是一项测试技术，是在传统的在线测试不在适应大规模，高集成电路测试的情况下而提出的，就是在IC设计的过程中在IC的内部逻辑和每个器件引脚间放置移位寄存器(shift register).每个移位寄存器叫做一个CELL。
这些CELL准许你去控制和观察每个输入/输出引脚的状态。
当这些CELL连在一起就形成了一个数据寄存器链(data register chain),我门叫它边界寄存器(boundaryregister)。
除了上面的移位寄存器外，在IC上还集成测试访问端口控制器 (TAP controller),指令寄存器(Instruction register)对边界扫描的指令进行解码以便执行各种测试功能。
旁路寄存器(bypass register)提供一个最短的测试通路。
另外可能还会有IDCODE register和其它符合标准的用户特殊寄存器。
下图是一个典型的具有边界扫描功能的IC。
边界扫描器件典型特征及边界扫描测试信号的构成。
如果一个器件是边界扫描器件它一定有下面5个信号中的前四个：1．TDI (测试数据输入)2．TDO (侧试数据输出)3．TMS (测试模式选择输入)4．TCK (测试时钟输入)5．TRST (测试复位输入，这个信号是可选的)测试访问端口控制器(TAP controller)TMS，TCK，TRST构成了边界扫描的测试访问端口控制器(TAP controller)。
TAP (the test access port)是一个通用的端口，用来引入控制信号到边界扫描器件(TCK,TMS,TRST*)并且为边界扫描提供串行的输入，输出信号(TDI,TDO)TAP controller是一个16位的状态机，可以通过TMS(test mode selection)和TCK(test clock input)对TAP controller进行编程控制它的状态，TAP controller控制进入指令寄存器(instruction register)和数据寄存器(data register)数据流。
Boundray scan技术原理
1边界扫描测试技术原理2.边界扫描指令集Extest指令--强制指令用于芯片外部测试，如互连测试测试模式下的输出管脚，由BSC update锁存驱动BSC scan锁存捕获的输入数据移位操作，可以从TDI输入测试激励，并从TDO观察测试响应。
在移位操作后，新的测试激励存储到BSC的update锁存原先EXTEST指令是强制为全“0”的，在IEEE 1149.1—2001中，这条强制取消了。
选择边界扫描寄存器连通TDI和TDO。
在这种指令下，可以通过边界扫描输出单元来驱动测试信号至其他边界扫描芯片，以及通过边界扫描输入单元来从其他边界扫描芯片接受测试信号。
EXTEST指令是IEEE 1149.1标准的核心所在，在边界扫描测试中的互连测试（interconnect test）就是基于这个指令的。
Sample/Preload指令编辑Sample/Preload指令--强制指令在进入测试模式前对BSC进行预装载输入输出管脚可正常操作输入管脚数据和内核输出数据装载到BSC的scan锁存中。
移位操作，可以从TDI输入测试激励，并从TDO观察测试响应。
在移位操作后，新的测试激励存储到BSC的update锁存。
原先这两个指令是合在一起的，在IEEE 1149.1--2001中这两个指令分开了，分成一个SAMPLE指令，一个PRELOAD指令。
选择SAMPLE/PRELOAD指令时，IC工作在正常工作模式，也就是说对IC的操作不影响IC的正常工作。
选择边界扫描寄存器连通TDI和TDO。
SAMPLE指令---通过数据扫描操作（Data Scan）来访问边界扫描寄存器，以及对进入和离开IC的数据进行采样。
PRELOAD指令---在进入EXTEST指令之前对边界扫描寄存器进行数据加载。
Bypass指令编辑Bypass指令--强制指令提供穿透芯片的最短通路。
输入输出管脚可正常操作选择一位的旁路（Bypass）寄存器强制全为1和未定义的指令为Bypass指令BYPASS指令为全“1”。
pub_ac_boundary_scan1
Increasing noise immunity with differential signaling. Allows low voltage signaling (LVDS).
TLD2003, Winterthur
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Copyright by Zentrum für Mikroelektronik Aargau, CH-5210 Windisch.
DIGITAL I/O PINS
Bypass Test Access Port (TAP )
TDI
M U X
ID-Register IR-Register TAP Controller
M U X
TDO
TRST
TMS
TCK
TLD2003, Winterthur
Slide 4/20
Copyright by Zentrum für Mikroelektronik Aargau, CH-5210 Windisch.
1
Status of TMS at the transition of TCK
TLD2003, Winterthur Slide 17/20
Copyright by Zentrum für Mikroelektronik Aargau, CH-5210 Windisch.
The EXTEST_PULSE Instruction
Boundary-Scan Testing of Advanced Digital Networks (IEEE 1149.6)
Agenda Introduction Overview of IEEE Boundary Scan Standards
Copyright by Zentrum für Mikroelektronik Aargau, CH-5210 Windisch.
JLINK使用教程详解，以及与JTAG区别
JLINK使⽤教程详解，以及与JTAG区别对于⼀个新⼿来说，⼀切都不容易。
⽽从头学起也是⼀件⾮常美好的事。
调试ARM，要遵循的调试接⼝协议,JTAG就是其中的⼀种。
当仿真时，IAR、KEIL、ADS等都有⼀个公共的调试接⼝,RDI就是其中的⼀种，那么我们如何完成RDI-->ARM调试协议(JTAG)的转换呢?有以下两种做法：1.在电脑上写⼀个服务程序，把IAR、KEIL和ADS中的RDI命令解析成相关的JTAG协议，然后通后⼀个物理转换接⼝(注意，这个转换只是电⽓物理层上的转换，就像RS232那样的作⽤)发送你的的⽬标板。
H-JTAG就是这样的。
H-JTAG的硬件就仅是⼀个物理电平的转换接⼝，所以很简单。
⽽电脑中装的h-JTAG软件就是前⾯说到的服务程序，负责协议转换的。
2.做⼀个板，⽤此板直接接收来⾃IAR、KEIL和ADS等软件的调试命令，由此板做RDI->JTAG协议的转换。
然后与⽬标板通信，这就是JLINK的⼯作原理。
由上可以看出H-JTAG由于是软件作协议转换的，所以速度较慢，但是硬件简单。
⽽第⼆种⽅法的JLINK⼀般带⼀个强劲的CPU，作硬件协议转换，把以硬件复杂，但速度快。
JTAG的基本原理JTAG(JointTestActionGroup，联合测试⾏动组)是⼀种国际标准测试协议(IEEE1149.1兼容)。
标准的JTAG接⼝是4线——TMS、TCK、TDI、TDO，分别为模式选择、时钟、数据输⼊和数据输出线。
JTAG的主要功能有两种，或者说JTAG主要有两⼤类：1)⼀类⽤于测试芯⽚的电⽓特性，检测芯⽚是否有问题;2)另⼀类⽤于Debug，对各类芯⽚以及其外围设备进⾏调试;⼀个含有JTAGDebug接⼝模块的CPU，只要时钟正常，就可以通过JTAG 接⼝访问CPU的内部寄存器、挂在CPU总线上的设备以及内置模块的寄存器。
本⽂主要介绍的是Debug功能。
JTAG原理分析简单地说，JTAG的⼯作原理可以归结为：在器件内部定义⼀个TAP(TestAccessPort，测试访问⼝)，通过专⽤的JTAG测试⼯具对内部节点进⾏测试和调试。
Boundary Scan测试原理及实现
什么是边界扫描(boundary scan)?Boundary Scan测试原理及实现JTAG标准的IC芯片结构IEEE 1149.1 标准背景JTAG什么是边界扫描(boundary scan)?边界扫描(Boundary scan )是一项测试技术，是在传统的在线测试不在适应大规模，高集成电路测试的情况下而提出的，就是在IC设计的过程中在IC的内部逻辑和每个器件引脚间放置移位寄存器(shift register).每个移位寄存器叫做一个CELL。
这些CELL准许你去控制和观察每个输入/输出引脚的状态。
当这些CELL连在一起就形成了一个数据寄存器链(data register chain),我门叫它边界寄存器(boundaryregister)。
除了上面的移位寄存器外，在IC上还集成测试访问端口控制器 (TAP controller),指令寄存器(Instruction register)对边界扫描的指令进行解码以便执行各种测试功能。
旁路寄存器(bypass register)提供一个最短的测试通路。
另外可能还会有IDCODE register和其它符合标准的用户特殊寄存器。
边界扫描器件典型特征及边界扫描测试信号的构成。
如果一个器件是边界扫描器件它一定有下面5个信号中的前四个：1．TDI (测试数据输入)2．TDO (侧试数据输出)3．TMS (测试模式选择输入)4．TCK (测试时钟输入)5．TRST (测试复位输入，这个信号是可选的)TMS,TCK,TRST构成了边界扫描测试端口控制器(TAP controller)，它负责测试信号指令的输入，输出，指令解码等，TAP controller是一个16位的状态机，边界扫描测试的每个环节都由它来控制，所以要对TAP controller有一个比较清楚的了解。
在后续的文章中还会向大家介绍边界扫描的其它方面。
边界扫描为开发人员缩短开发周期，并且提供良好的覆盖率和诊断信息。
DFT问答（转）
DFT问答（转）Q: Boundary Scan是什么？应⽤场景是什么？实现的⽅法是什么？挑战是什么？A: Boundary Scan就是边界扫描，是由Joint Test action Group起草的规范，最初是为了解决板级芯⽚之间的互联测试的问题，实现⽅法就是在芯⽚内部的每个I/O上⾯加上⼀个Boundary Scan cell ⽤于控制和观测每个I/O的状态，然后把每个I/O的bscell串连起来交由TAP控制器控制。
TAP控制器按照 IEEE1149.1 规范通过5个I/O 串⾏与外界通讯。
虽然Boundary Scan是为了解决板级芯⽚互联的测试⽽设计的，但是也可以⽤来进⾏芯⽚⾃⾝ I/O 的测试，⽐如 VIH/VIL, VOH/VOL, highz, I/O漏电等等的测试，IEEE1149.1 规范⽐较实⽤于纯数字电路的I/O测试，后来为了解决⼀些⾼速差分接⼝的测试，增加了IEEE1149.6 规范，通过在原有协议的基础上增加了两条指令pulse 和transition 来测试差分信号。
关于Boundary Scan的部分，三家EDA公司的DFT tool的manual都有详细的介绍，关于1149.6 AC jtag的部分，⼤部分的串⾏接⼝IP都会⽀持，可以找相关部分参考研究。
关于 AC jtag部分，由于在芯⽚设计和板级设计上都有⼀些特殊考虑，挑战会较⼤⼀些。
由于TAP 只需要5个I/O(或者4个I/O)与外界通讯，并且协议⽐较简单，所以TAP 除了⽤来做boundary Scan的控制之外，还⼤量⽤来做SoC 内部电路的测试控制以及追踪调试。
随着SoC规模、复杂度的增加以及 time-to-market 要求的提⾼，基于IEEE1149 规范，后来⼜提出了 P1500 以及 IEEE1687 规范⽤来解决 embedded IP的测试控制。
相⽐于其他串⾏接⼝，TAP 接⼝操作简单，是对 ATE 机台最为友好的接⼝。
JTAG电路的工作原理
JTAG电路的工作原理JTAG电路的工作原理：JTAG（Joint Test Action Group）是一种用于测试和调试集成电路的标准接口。
它提供了一种快速、简单和可靠的方法来访问和控制电路板上的芯片。
JTAG电路通常由一个测试控制器和多个测试目标组成，测试目标可以是处理器、存储器、逻辑门阵列等。
JTAG电路的工作原理如下：1. 测试控制器：测试控制器是JTAG电路的核心部分，它负责生成和接收JTAG信号。
测试控制器可以是一个专门的硬件设备，也可以是一个嵌入在芯片中的软件模块。
它通过JTAG接口与测试目标进行通信，并控制测试目标的操作。
2. JTAG信号：JTAG信号是通过JTAG接口传输的电信号。
它包括四个主要信号线：TCK（Test Clock）、TMS（Test Mode Select）、TDI（Test Data In）和TDO（Test Data Out）。
TCK是一个时钟信号，用于同步数据传输。
TMS是一个控制信号，用于选择和控制测试目标的操作模式。
TDI是测试数据输入信号，用于向测试目标发送数据。
TDO是测试数据输出信号，用于从测试目标接收数据。
3. 测试模式：JTAG电路支持多种测试模式，包括测试目标的测试模式和调试模式。
在测试模式下，测试控制器可以向测试目标发送测试数据，并从测试目标接收响应数据，以验证电路的功能和性能。
在调试模式下，测试控制器可以读取和修改测试目标的内部状态和寄存器，以进行调试和故障诊断。
4. 芯片级联：JTAG电路支持多个测试目标的级联连接，形成一个测试链。
测试链的第一个测试目标称为主目标，其他测试目标称为从目标。
主目标通过TDO 信号将数据传输到从目标，从目标通过TDI信号将数据传输回主目标。
这种级联连接使得多个测试目标可以通过一个JTAG接口进行访问和控制。
5. Boundary Scan：JTAG电路还支持一种称为Boundary Scan的功能。
Bscan_01
Boundary-Scan has many practical applications. This section introduces the applications and describes how they can be implemented, as well as how they meet your board test needs.
■ ■ ■ ■
What is Boundary-Scan? Why Boundary-Scan? How Can Boundary-Scan Solve These Problems? The Manufacturing Fault Spectrum
© Agilent Technologies 2008
Test Data Registers
G1 MUX 1 TDO
ModeN
Mode1
Mode2
Mode3
TDI
Instruction Register Reset* Clock-DR Shift-DR Update-DR TMS TCK TRST* TAP Controller (16-State Machine)
A description of a boundary-scan device. A description of the Test Access Port (TAP) Controller. A description of the Instruction Register and Data Registers. A description of the Boundary-Scan tests and hold states. A description of the Boundary-Scan instructions. A description of the TAP Controller State Diagram and its importance to boundary-scan testing. A simple test program showing the vectors that the Boundary-Scan Software generates for your board test.
ScanDIMM-SO204 DDR3 Boundary-Scan Based Digital Te
ScanDIMM-SO204/DDR3Boundary-Scan BasedDigital TesterUser's ManualDocument Part Number: 70405 Revision ACopyright © Corelis 2010. All rights reserved.Corelis12607 Hiddencreek WayCerritos, CA 90703-2146Telephone: (562) 926-6727Fax: (562) 404-6196Table of ContentsChapter 1: Product Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features of the ScanDIMM-SO204/DDR3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ScanDIMM-SO204/DDR3 Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Chapter 2: ScanDIMM-SO204/DDR3 Installation. . . . . . . . . . . . . . . . . . . . . . . . 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 OverviewScanDIMM-SO204/DDR3 Hardware. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ScanDIMM-SO204/DDR3 Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Connecting to the Boundary-Scan Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Indicator LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Mating Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 AccessoriesChapter 3: Preparation of Test Input Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 PreparationAdd the ScanDIMM BSDL File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Add BSDL Files Dialog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 TAP Pins Not Found in Netlist Warning (Safe to Ignore). . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Insert a TAP Break. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Testing the Socket Power and Ground Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Chapter 4: Executing Selftest. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Infrastructure Test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 StepsChapter 5: Troubleshooting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 OverviewNotes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Chapter 6: Legal and Contact Information. . . . . . . . . . . . . . . . . . . . . . . . . . . 14Chapter 1:Product Overview IntroductionThe ScanDIMM-SO204/DDR3 Digital Tester module provides an easy-to-use method for structurally testing 204-pin Small Outline Dual Inline Memory Module (SO-DIMM or SODIMM) sockets. Through the use of boundary-scan technology, theScanDIMM-SO204/DDR3 Digital Tester provides 196 fully bi-directional test signals. A Boundary-Scan Test Access Port (TAP) connects to a host computer, which provides virtually unlimited memory depth for testing each of the SO-DIMM socket pins. The 204-pin sockets are often used for Double Data Rate Dynamic Random Access Memory (DDR3 SDRAM) modules. The ScanDIMM-SO204/DDR3 offers an accurate and easy-to-use mechanical and electrical solution for connecting test equipment to SO-DIMM sockets.Features of the ScanDIMM-SO204/DDR3•Tests 204-pin DDR3 SO-DIMM sockets•Tests for opens on the socket's power and ground pins• 1.5V DIMM interface, 3.3V tolerant• 1.8V TAP interface, 3.3V tolerant•LEDs indicate power status and active TAP connection•Compatible with the Corelis ScanExpress boundary-scan test development tools and other third party softwareThe figure below shows the ScanDIMM-SO204/DDR3 module with Pin 1 of the TAP IN connector identified.Figure 1-1. ScanDIMM-SO204/DDR3 module (top view)ScanDIMM-SO204/DDR3 SpecificationsSize and Form FactorMechanical Compatibility JEDEC MO-268C (204-pin DDR3 SO-DIMM)Dimensions67.6 mm x 30.00 mm ± 0.15 mm[2.66 inches x 1.18 inches ± 0.01 inches]PCB thickness 1.00 mm ± 0.10 mm[0.039 ± 0.01 inches]Connector Keying 1.5V-compatibleMaximum Test Clock (TCK) FrequencyMaximum TCK Frequency25 MHzLEDsPWR Indicates the 1.5V power source is presentTAP ON Indicates the TAP is connectedTAP ConnectorsTAP IN Connector10-pin Single Row 0.100-inch spacing(Samtec part no. TSM-110-01-G-SH or equivalent) Power Requirements (Provided by the 204-pin mating socket)1.50 V0.250 A (Maximum)Operating EnvironmentTemperature0° C to 55° CRelative Humidity10% to 90%, non-condensingAbsolute Maximum RatingsTable 1-1. Absolute Maximum RatingsRecommended Operating ConditionsTable 1-2. Recommended Operating ConditionsDC Electrical Characteristics (SO-DIMM Socket Interface)(1.5V DC Over Recommended Operating Conditions)Table 1-3. DC Electrical Characteristics (SO-DIMM Socket Interface)DC Electrical Characteristics (JTAG Interface)(1.8V DC Over Recommended Operating Conditions)Table 1-4. DC Electrical Characteristics (JTAG Interface)Chapter 2:ScanDIMM-SO204/DDR3 Installation OverviewTo ensure reliable operation of the ScanDIMM-SO204/DDR3, it is important to connect it properly to both the Corelisboundary-scan controller and the 204-pin DDR3 SO-DIMM socket on the unit under test (UUT).ScanDIMM-SO204/DDR3 HardwareThe ScanDIMM-SO204/DDR3 product consists of the following components:•ScanDIMM-SO204/DDR3, Corelis P/N 10408•User's Manual, Corelis P/N 70405•Host Adapter Cable, 10-pin, Corelis P/N 15336The ScanDIMM-SO204/DDR3 product is also available in a 'mirrored' version that is functionally identical but has a reversed form factor.The ScanDIMM-SO204/DDR3/Mirrored product consists of the following components:•ScanDIMM-SO204/DDR3/Mirrored, Corelis P/N 10409•User's Manual, Corelis P/N 70405•Host Adapter Cable, 10-pin, Corelis P/N 15336The files related to the ScanDIMM-SO204/DDR3 are installed by the ScanExpress installer.Ensure that all materials listed are present and free from visible damage or defects before proceeding. If anything appears to be missing or damaged, contact Corelis at the number listed on the title page immediately.The figure below shows the ScanDIMM-SO204/DDR3 and the cables that are included with the product.Figure 2-1. ScanDIMM-SO204/DDR3 and Cable AccessoriesScanDIMM-SO204/DDR3 SoftwareThe ScanExpress CD installs the files to a subdirectory of the ScanExpress TPG application.The default location is:"C:\Program Files\Corelis\ScanExpressTPG\ScanDIMM-SO204-DDR3".Table 2-5. ScanDIMM-SO204/DDR3 FilesConnecting to the Boundary-Scan ControllerThe external boundary-scan controller connects to the ScanDIMM-SO204/DDR3 TAP IN connector via the 10-pin Host Adapter Cable.Connect one end of the Host Adapter Cable P/N 15336 to the TAP IN connector of the ScanDIMM-SO204/DDR3.Connect the 10-pin cable from the boundary-scan controller (ScanTAP-4, ScanTAP-8, etc.) to the other end of the adapter cable. The TAP Voltage for the boundary-scan controller should be set to 1.8VThe figure below shows a block diagram for the a typical TAP connection to a ScanDIMM-SO204/DDR3 module.Figure 2-2. Block Diagram of Connection to a ScanDIMM-SO204/DDR3This table shows the pin assignments for the TAP IN connector.Table 2-6. TAP IN Connection ListThe TAP IN connector conforms to the popular Corelis 10-pin TAP connector pinout except that it is a single row (10 x 1) instead of dual row (5 x 2). The Host TAP Adapter Cable P/N 15336 is a 1:1 adapter cable. The pin assignment is standard, connecting to any Corelis controller using the appropriate standard 10-pin TAP cable. It is best to use the PCI-1149.1/Turbo equipped with a ScanTAP-4 Intelligent Pod, with one TAP connected to the ScanDIMM-SO204/DDR3 and with additional TAP(s) connected to the UUT. Other Corelis controllers like the NetUSB-1149.1/E can also be used so that the UUT can connect on a separate TAP.The figure below shows the TAP connections for a ScanDIMM-SO204/DDR3 module on TAP1 and the Target UUT on TAP2.Figure 2-3. Connection of a ScanDIMM-SO204/DDR3 Module and the Target using Separate TAPs Indicator LEDsTwo LEDs indicate the status of the ScanDIMM-SO204/DDR3 module. D1 is labeled PWR. It illuminates if theScanDIMM-SO204/DDR3 is receiving power from the target (through pins 57, 60 and 176). If the LED is not illuminated, the ScanDIMM-SO204/DDR3 module is not powered up. D2 is labeled TAP ON. It indicates that a connection to a controller is detected. The ScanDIMM-SO204/DDR3 module will not operate unless D2 is illuminated.Mating ConnectorsThe table below shows the mating connectors needed to make cables for the Boundary-Scan connector.Table 2-7. Mating Connectors for the ScanDIMM-SO204/DDR3 AccessoriesAdditional TAP Adapter Cables (P/N 15336) can be ordered from Corelis:Table 2-8. Cable Accessories for the ScanDIMM-SO204/DDR3Chapter 3:Preparation of Test Input Files OverviewThe ScanDIMM-SO204/DDR3 integrates easily with a boundary-scan test plan. When the ScanDIMM-SO204/DDR3 is installed in a socket, the socket behaves like a boundary-scan component. Once the ScanDIMM-SO204/DDR3 is plugged into the socket on the target board, the boundary-scan test system will automatically test the socket. However, regeneration of the boundary-scan tests with ScanExpress TPG is required.PreparationCopy the provided BSDL file to your local project directory.Add the ScanDIMM BSDL FileWhile in the "Preparation:BSDL Files" stage of ScanExpress TPG, click "Add..." to launch the "Add BSDL Files" dialog.Figure 3-1. ScanExpress TPG Test Preparation: Select BSDL FilesAdd BSDL Files DialogFigure 3-2. Add BSDL Files DialogUncheck the box "Show Only Devices Connected to JTAG Signals"Select the Device that corresponds to the DIMM socket on the board in the left pane.Select the BSDL File for the ScanDIMM-SO204-DDR3 in the right pane.Click "Add".Click "Close" to exit the Add BSDL Files dialog.TAP Pins Not Found in Netlist Warning (Safe to Ignore)In some cases a popup message may appear that indicates that the ScanDIMM TAP pins are not found in the netlist. The TAP connection between the boundary-scan controller and ScanDIMM module won't be in the board netlist and this warning is safe to ignore.Figure 3-3. TAP Pins Not Found in Netlist Warning (Safe to Ignore)Insert a TAP BreakThe ScanDIMM is now in the scan chain. Insert a "TAP Break" by selecting the last device in the scan chain before the ScanDIMM, right clicking and selecting "Insert TAP Break"Figure 3-4. ScanExpress TPG Test Preparation: ScanDIMM BSDL File AddedTesting the Socket Power and Ground PinsTo test the power and ground pins on the ScanDIMM-SO204/DDR3 socket, the constraint file should have the following syntax added:SENSE_HIGH VDDSENSE_LOW GNDVDD and GND are the net names of the 1.5V SDRAM power and ground signals on the target board. This syntax may already be present to test other power or ground connections in the target system.ScanExpress TPG will automatically add these constraints if the power and ground nets are specified during the Power and Ground screen of the preparation phase.Chapter 4:Executing Selftest OverviewScanExpress Runner (sold separately) can load and run the compact vector file, ScanDIMM-SO204-DDR3_Selftest_inf.cvf, and quickly verify that the ScanDIMM-SO204/DDR3 is functional. Both the ScanExpress Runner software and a Corelis Boundary-Scan controller such as the PCI-1149.1/Turbo are required to execute this file.Infrastructure TestThe infrastructure test verifies the TAP connection between the controller and the ScanDIMM-SO204/DDR3. It also verifies that the boundary-scan infrastructure of the device on the ScanDIMM-SO204/DDR3 is fully functional. The infrastructure test requires a Corelis Boundary-Scan controller, a ScanDIMM-SO204/DDR3 unit and a Host TAP cable (P/N 15336). The following steps execute an infrastructure test.Steps1.Remove any memory modules from the Unit Under Test (UUT) DIMM socket(s) to be tested.2.Install the ScanDIMM-SO204/DDR3 in the socket.3.Connect the Host TAP Adapter cable P/N 15336 to the "TAP IN" connector on the ScanDIMM-SO204/DDR3.4.Connect the 10-pin TAP cable from the external controller to the other end of the Host TAP Adapter cable.5.Apply power to the UUT.6.Make sure that both LEDs on the ScanDIMM-SO204/DDR3 illuminate.7.Double-click on the ScanExpress Runner Icon.8.Select New Test Plan from the File menu and click on the Add button.9.With the file browser, find and select the "ScanDIMM-SO204-DDR3_Selftest_inf.cvf" file. Click OK.10.Select Controller from the Setup menu, then choose the appropriate Boundary-Scan controller.11.Set the TCK frequency to 1 MHz and the TAP voltage to 1.8V.12.Select Run Test. The test should run and pass.The figure below shows a passing infrastructure test.Figure 4-1. ScanExpress Runner Infrastructure TestTroubleshooting OverviewUse the following general guidelines to troubleshoot problems when the ScanDIMM-SO204/DDR3 is added to the test system.1.Make sure the ScanDIMM-SO204/DDR3's TAP Voltage is set to 1.8V2.Make sure power is being supplied to the ScanDIMM-SO204/DDR3, the boundary-scan controller, and the target. TheScanDIMM-SO204/DDR3's green LEDs will be illuminated if power (1.5V) is being supplied to the DIMM socket and the boundary-scan controller is connected.3.Run the provided self-test and make sure that it passes.4.Reduce the TCK (test clock) frequency to 1 MHz. The TCK frequency can be set too high for the scan chain andsometimes using a lower frequency will allow the test steps to pass. Once the scan chain is known to be stable, then the TCK frequency can be increased to the maximum frequency that will allow the test steps to pass.Notes1.DDR3 modules are not backwards compatible with DDR2 modules and DDR3 modules will not fit into DDR2 sockets;forcing them can damage the ScanDIMM and/or the board.Legal and Contact InformationPRINTING HISTORYRevision A, May 2010GENERAL NOTICEInformation contained in this document is subject to change without notice. CORELIS shall not be liable for errors contained herein for incidental or consequential damages in connection with the furnishing, performance, or use of material contained in this manual.This document contains proprietary information that is protected by copyright. All rights reserved. No part of this document may be reproduced or translated to other languages without the prior written consent of CORELIS. This manual is a CORELIS proprietary document and may not be transferred to another party without the prior written permission of CORELIS. CORELIS assumes no responsibility for the use of or reliability of its software on equipment that is not furnished by CORELIS.ENVIRONMENTAL NOTICEThis product must be disposed of in accordance with the WEEE directive.TRADEMARK NOTICEScanExpress and ScanDIMM are trademarks of Corelis Inc.Other products and services named in this manual are trademarks or registered trademarks of their respective companies. All trademarks and registered trademarks in this manual are the property of their respective holders.PRODUCT WARRANTYFor product warranty and software maintenance information, see the PRODUCT WARRANTY AND SOFTWARE MAINTENANCE POLICY statement included with your product shipment.EXCLUSIVE REMEDIESTHE REMEDIES CONTAINED HEREIN ARE THE CUSTOMER'S SOLE AND EXCLUSIVE REMEDIES. CORELIS SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, WHETHER BASED ON CONTRACT, TORT, OR ANY OTHER LEGAL THEORY. Product maintenance agreements and other customer assistance agreements are available for Corelis products. For assistance, contact your nearest Corelis Sales and Service Office.RETURN POLICYNo items returned to CORELIS for warranty, service, or any other reason shall be accepted unless first authorized by CORELIS, either direct or through its authorized sales representatives. All returned items must be shipped pre-paid and clearly display a Return Merchandise Authorization (RMA) number on the shipping carton. Freight collect items will NOT be accepted. Customers or authorized sales representatives must first contact CORELIS with notice of request for return of merchandise. RMA's can only originate from CORELIS. If authorization is granted, an RMA number will be forwarded to the customer either directly or through its authorized sales representative.CONTACT INFORMATIONFor sales inquiries, please contact *****************.For any support related questions, please enter a support request at /support or email *******************. For more information about other products and services that Corelis offers, please visit .。
BSD - BOUNDARY-SCAN DIAGNOSTICS说明书
BSD - BOUNDARY-SCAN DIAGNOSTICS Clear interpretation of JTAG test resultsIntroductionBSD is an optional, advanced software module thatworks as a post-processor for the results data derivedfrom a JTAG Technologies test execution. Applying BSDto test results gives test engineers, rework technici-· Pin stuck-at faults (open pins)· Twist faults (network terminals swapped or crossed) · IEEE std. 1149.6 LVDS network faults – various.Test Application TypesIn all fault cases, precise location data is offered that includes device references and device pin numbers. JTAG Technologies applications that are supported by BSD include:a) Interconnection TestingFor most designs the majority of the test coverage comes from the execution of this test that is used to detect te a memory cluster test. Interpreting the TTR results of a memory test can be difficult, especially on address line faults that can only be derived from incorrect data bus returned values. In these cases BSD offers an extremely valuable function that pin-points the faults precisely.c) Logic Cluster TestingUsing BSD with logic clusters requires the user to define a fault dictionary file (.dic) using Mentor Graphics' Quick-Fault syntax. Full instructions on how to construct a fault dictionary file to detect stuck-at faults are included in the BSD manual that accompanies this option.We are boundary-scan.®1300-BSD-E-1000© The JTAG Technologies logo and other trademarks designed with the symbol “®” are trademarks of JTAG Technologies registered in Europe and/or other countries. JTAG Technologies reserves the right to change design and specifications without notice.We are boundary-scan.®· DRC/DRC2 file – diagnostic record type format. Original DRC format can be used for single PCB test arrange-ments while DRC2 format accommodates test results from projects featuring multiple boards. The resultsBSD Output Options HTML& DRC。
ScanExpress Debugger Boundary-Scan Interactive Ana
ScanExpress DebuggerBoundary -Scan Interactive Analyzer & ToolkitTest probe access is a luxury—modern electronic system design techniques such as blind andburied vias or ball -grid -array (BGA) devices guarantee limited signal access. Test points quickly reduce precious board real -estate and can even degrade performance.ScanExpress Debugger overcomes these limitations to provide the control and visibility necessary to quickly debug and test hardware, using a simple JTAG port to interface with IEEE -1149.1 compliant devices.Whether debugging prototype hardware, enhancing production tests with boundary -scan control, or diagnosing a faulty board in the field, ScanExpress Debugger ’s easy -to -use and versatile interface helps engineers test and debug systems faster and more efficiently.Features• Interactive control and observation of all boundary -scan controllable inputs and outputs • Visual representation of boundary -scan ICs shows pin activity in real -time • Comprehensive pin and net browser with grouping, sort, and filter capability for easy identification and selection of boundary -scan pins • Two scripting modules—advanced and basic—provide easy, automated access to boundary -scan signals • Advanced script debugger boasts powerful code developmentcapabilities including break points, single step, watch window, and more • Intuitive software assists with short and open fault identification on and between BGA and other fine -pitch components • Powerful JTAG protocol command interface for low -level access using simple JTAG scans • TCK test helps find the maximum clock rate for a unit under test (UUT) • Real -time data checking prevents conflicts and unsafe values • Customizable Graphical User Interface (GUI) with window docking • Interfaces with NI LabVIEW, NI LabWindows/CVI, Agilent VEE, Visual Basic, and other third party test executives • Fully complies with IEEE standard 1149.1• Supports Corelis high -performance JTAG controllers• Compatible with Windows XP, Windows Vista, Windows 7, and Windows 8Benefits• Speed up hardware development on products with BGA and fine -pitch components that are not accessible with external probes. • Decrease test complexity by utilizing non -intrusive boundary -scan technology for virtual access. • Modular JTAG toolkit makes boundary -scan test tasks easy for all users.ApplicationsDevelopmentDebug hardware faults in systems with JTAG, even on components with no physical access. ProductionIntegrate boundary -scan control and test scripts into automated test routines. Service & RepairTroubleshoot hard -to -find faults with just a desktop JTAG controller and a PC.Learn More : For more information about Corelis products, please visitOverviewScanExpress Debugger is a software application designed to assist engineers with hardware debug during prototype design verification and testing as well facilitate boundary -scan control in both automated and manual test environments. Utilizing a high -performance Corelis JTAG controller along with user -friendly and intuitive Windows -basedsoftware and a powerful software API, ScanExpress Debugger can take control of a UUT boundary -scan chain and control system signals.Graphical User InterfaceScanExpress Debugger features an interactive GUI with two main views: the pin grid and the script debugger. The pin grid features controls to set and monitor the state of individual pins and groups of pins on the UUT. Data editing and manipulation is easy—common GUI functions such as copy, cut, and paste as well as insertion, deletion, and clearing of data table rows are included. Additional functions allow resetting or updating of the Unit Under Test, selecting board safety options, and enabling continuous sample or update mode. To complement the pin grid, IC display windows can be enabled for any component on the boundary -scan chain, enabling at aScanExpress DebuggerThe ScanExpress product family is a trademark of Corelis, Inc.Product names, logos, brands, and other trademarks featured or referred to are the property of their respective trademark holders.© Copyright Corelis, Inc. 2019. All rights reserved.Corelis, Inc. reserves the right to make changes in design or specification at any time and without notice.20409-DS VERSION 1.2 – 2/04/2019glance visualization of pin activityand convenient functions to directlymanipulate system signals. The script debugger features an integrated development environment for debug andexecution of user -created scripts. The “C ”-style scripting language should be familiar to users with a programming background.Additional ToolsScanExpress Debugger includes additional tools to simplify JTAG debugging. The protocol command interface can be used for low -level register scans, while the simple script interface is ideal for peek -andScanExpress Debugger uses a simple JTAG interface with multiple tools to controland observe signals on the UUTOrdering Information• Part Number 20409For more information about Corelis ScanExpress products, please visit our website at/13100 Alondra Blvd. Cerritos, CA 90703, USAUS & Canada | +1 888-808-2380 International | +1 562-926-6727 Fax | +1 562-404-6196 -poke operations. Tools are alsoincluded to determine the maximum UUT clock rate and test the system for undocumented op codes.Application Programming Interface (API)ScanExpress Debugger includes a DLL interface with powerful JTAG functions for integration into user applications and test environments. The API can be integrated into C language applications or used with popular test executive systems such as National Instruments LabVIEW, National Instruments TestStand, and Agilent VEE to add boundary -scan control to any test environment.The ScanExpress Debugger Grid View and display windows allow convenientcontrol and observation of all boundary -scan signals in a systemTopology File BSDL Files Netlist Fixed Outputs Test ScriptsScanExpress Debugger SoftwareUnit Under Test(UUT)• Powerful pin grid view with IC display windows • Basic scripting for simple peek & poke • Advanced scripting & automation • Low level JTAG scans • Find maximum TCK rate•Discover undocumented op codesIntuitive JTAG/Boundary -Scan Toolkit。
ScanDIMM-240 DDR3 R Boundary-Scan Based Digital Te
ScanDIMM-240/DDR3/RBoundary-Scan BasedDigital TesterUser's ManualDocument Part Number: 70404 Revision CCopyright © Corelis 2010. All rights reserved.Corelis12607 Hiddencreek WayCerritos, CA 90703-2146Telephone: (562) 926-6727Fax: (562) 404-6196Table of ContentsChapter 1: Product Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features of the ScanDIMM-240/DDR3/R. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ScanDIMM-240/DDR3/R Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Chapter 2: ScanDIMM-240/DDR3/R Installation. . . . . . . . . . . . . . . . . . . . . . . . 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 OverviewScanDIMM-240/DDR3/R Hardware. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ScanDIMM-240/DDR3/R Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Connecting to the Boundary-Scan Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Indicator LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Mating Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 AccessoriesChapter 3: Preparation of Test Input Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 PreparationAdd the ScanDIMM BSDL File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Add BSDL Files Dialog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 TAP Pins Not Found in Netlist Warning (Safe to Ignore). . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Insert a TAP Break. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Testing the Socket Power and Ground Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Chapter 4: Executing Selftest. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Infrastructure Test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 StepsChapter 5: Troubleshooting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 OverviewNotes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Chapter 6: Legal and Contact Information. . . . . . . . . . . . . . . . . . . . . . . . . . . 14Chapter 1:Product Overview IntroductionThe ScanDIMM-240/DDR3/R Digital Tester module provides an easy-to-use method for structurally testing 240-pin Registered Dual Inline Memory Module (DIMM) sockets. Through the use of boundary-scan technology, the ScanDIMM-240/DDR3/R Digital Tester provides 232 fully bi-directional test signals. A Boundary-Scan Test Access Port (TAP) connects to a host computer, which provides virtually unlimited memory depth for testing each of the DIMM socket pins. The 240-pin sockets are often used for Double Data Rate Dynamic Random Access Memory (DDR3 SDRAM) modules. The ScanDIMM-240/DDR3/R offers an accurate and easy-to-use mechanical and electrical solution for connecting test equipment to DIMM sockets.Features of the ScanDIMM-240/DDR3/R•Tests 240-pin Registered DDR3 DIMM sockets for opens and shorts•Tests for opens on the socket's power and ground pins• 1.5V DIMM interface, 3.3V tolerant• 1.8V TAP interface, 3.3V tolerant•LEDs indicate power status and whether an active TAP connection is present•Compatible with the Corelis ScanExpress boundary-scan test development tools and other third party softwareThe figure below shows the ScanDIMM-240/DDR3/R module with Pin 1 of the TAP IN connector identified.Figure 1-1. ScanDIMM-240/DDR3/R module (top view)ScanDIMM-240/DDR3/R SpecificationsSize and Form FactorMechanical Compatibility JEDEC MO-269F (240-pin Registered DDR3 DIMM)Dimensions133.35 mm x 30.00 mm ± 0.15 mm[5.25 inches x 1.25 inches ± 0.01 inches]PCB thickness 1.27 mm ± 0.10 mm[0.05 ± 0.01 inches]Connector Keying 1.5V-compatibleMaximum Test Clock (TCK) FrequencyMaximum TCK Frequency25 MHzLEDsPWR Indicates the 1.5V power source is presentTAP ON Indicates the TAP is connectedTAP ConnectorsTAP IN Connector10-pin Single Row 0.100-inch spacing(Samtec part no. TSM-110-01-G-SH or equivalent) TAP OUT Connector10-pin Single Row 0.100-inch spacing(Samtec part no. TSM-110-01-G-SH or equivalent) Power Requirements (Provided by the 240-pin mating socket)1.50 V0.250 A (Maximum)Operating EnvironmentTemperature0° C to 55° CRelative Humidity10% to 90%, non-condensingAbsolute Maximum RatingsTable 1-9. Absolute Maximum RatingsRecommended Operating ConditionsTable 1-10. Recommended Operating ConditionsDC Electrical Characteristics (DIMM Socket Interface)(1.5V DC Over Recommended Operating Conditions)Table 1-11. DC Electrical Characteristics (DIMM Socket Interface)DC Electrical Characteristics (JTAG Interface)(1.8V DC Over Recommended Operating Conditions)Table 1-12. DC Electrical Characteristics (JTAG Interface)Chapter 2:ScanDIMM-240/DDR3/R Installation OverviewTo ensure reliable operation of the ScanDIMM-240/DDR3/R, it is important to connect it properly to both the Corelisboundary-scan controller and the 240-pin DDR3 DIMM socket on the unit under test (UUT).ScanDIMM-240/DDR3/R HardwareThe ScanDIMM-240/DDR3/R product consists of the following components:•ScanDIMM-240/DDR3/R, Corelis P/N 10407•User's Manual, Corelis P/N 70404•Host Adapter Cable, 10-pin, Corelis P/N 15336•TAP OUT to TAP IN daisy-chain cable, 2" long, 10-pin 1:1, Corelis P/N 15337The files related to the ScanDIMM-240/DDR3/R are installed by the ScanExpress installer.Ensure that all materials listed are present and free from visible damage or defects before proceeding. If anything appears to be missing or damaged, contact Corelis at the number listed on the title page immediately.The figure below shows the ScanDIMM-240/DDR3/R and the cables that are included with the product.Figure 2-1. ScanDIMM-240/DDR3/R and Cable AccessoriesScanDIMM-240/DDR3/R SoftwareThe ScanExpress CD installs the files to a subdirectory of the ScanExpress TPG application.The default location is:"C:\Program Files\Corelis\ScanExpressTPG\ScanDIMM-240-DDR3-R".Table 2-13. ScanDIMM-240/DDR3/R FilesConnecting to the Boundary-Scan ControllerThe external boundary-scan controller connects to the ScanDIMM-240/DDR3/R TAP IN connector via the 10-pin Host Adapter Cable.Connect one end of the Host Adapter Cable P/N 15336 to the TAP IN connector of the ScanDIMM-240/DDR3/R.Connect the 10-pin cable from the boundary-scan controller (ScanTAP-4, ScanTAP-8, etc.) to the other end of the adapter cable. The TAP Voltage for the boundary-scan controller should be set to 1.8VThe figure below shows a block diagram for the a typical TAP connection to a ScanDIMM-240/DDR3/R module.Figure 2-2. Block Diagram of Connection to a ScanDIMM-240/DDR3/RThis table shows the pin assignments for the TAP IN connector.Table 2-14. TAP IN Connection ListThe TAP IN connector conforms to the popular Corelis 10-pin TAP connector pinout except that it is a single row (10 x 1) instead of dual row (5 x 2). The Host TAP Adapter Cable P/N 15336 is a 1:1 adapter cable. The pin assignment is standard, connecting to any Corelis controller using the appropriate standard 10-pin TAP cable. It is best to use the PCI-1149.1/Turbo equipped with a ScanTAP-4 Intelligent Pod, with one TAP connected to the ScanDIMM-240/DDR3/R and with additional TAP(s) connected to the UUT. Other Corelis controllers like the NetUSB-1149.1/E can also be used so that the UUT can connect on a separate TAP.The figure below shows the TAP connections for a ScanDIMM-240/DDR3/R module on TAP1 and the Target UUT on TAP2.Figure 2-3. Connection of a ScanDIMM-240/DDR3/R Module and the Target using Separate TAPs Indicator LEDsTwo LEDs indicate the status of the ScanDIMM-240/DDR3/R module. D1 is labeled PWR. It illuminates if theScanDIMM-240/DDR3/R is receiving power from the target (through pins 57, 60 and 176). If the LED is not illuminated, the ScanDIMM-240/DDR3/R module is not powered up. D2 is labeled TAP ON. It indicates that a connection to a controller is detected. The ScanDIMM-240/DDR3/R module will not operate unless D2 is illuminated.Mating ConnectorsThe table below shows the mating connectors needed to make cables for the Boundary-Scan connector.Table 2-15. Mating Connectors for the ScanDIMM-240/DDR3/R AccessoriesAdditional TAP Adapter Cables (P/N 15336) can be ordered from Corelis:Table 2-16. Cable Accessories for the ScanDIMM-240/DDR3/RChapter 3:Preparation of Test Input Files OverviewThe ScanDIMM-240/DDR3/R integrates easily with a boundary-scan test plan. When the ScanDIMM-240/DDR3/R is installed in a socket, the socket behaves like a boundary-scan component. Once the ScanDIMM-240/DDR3/R is plugged into the socket on the target board, the boundary-scan test system will automatically test the socket. However, regeneration of the boundary-scan tests with ScanExpress TPG is required.PreparationCopy the provided BSDL file to your local project directory.Add the ScanDIMM BSDL FileWhile in the "Preparation:BSDL Files" stage of ScanExpress TPG, click "Add..." to launch the "Add BSDL Files" dialog.Figure 3-1. ScanExpress TPG Test Preparation: Select BSDL FilesAdd BSDL Files DialogFigure 3-2. Add BSDL Files DialogUncheck the box "Show Only Devices Connected to JTAG Signals"Select the Device that corresponds to the DIMM socket on the board in the left pane.Select the BSDL File for the ScanDIMM-240-DDR3-R in the right pane.Click "Add".Click "Close" to exit the Add BSDL Files dialog.TAP Pins Not Found in Netlist Warning (Safe to Ignore)In some cases a popup message may appear that indicates that the ScanDIMM TAP pins are not found in the netlist. The TAP connection between the boundary-scan controller and ScanDIMM module won't be in the board netlist and this warning is safe to ignore.Figure 3-3. TAP Pins Not Found in Netlist Warning (Safe to Ignore)Insert a TAP BreakThe ScanDIMM is now in the scan chain. Insert a "TAP Break" by selecting the last device in the scan chain before the ScanDIMM, right clicking and selecting "Insert TAP Break"Figure 3-4. ScanExpress TPG Test Preparation: ScanDIMM BSDL File AddedTesting the Socket Power and Ground PinsTo test the power and ground pins on the ScanDIMM-240/DDR3/R socket, the constraint file should have the following syntax added:SENSE_HIGH VDDSENSE_LOW GNDVDD and GND are the net names of the 1.5V SDRAM power and ground signals on the target board. This syntax may already be present to test other power or ground connections in the target system.ScanExpress TPG will automatically add these constraints if the power and ground nets are specified during the Power and Ground screen of the preparation phase.Chapter 4:Executing Selftest OverviewScanExpress Runner (sold separately) can load and run the compact vector file, ScanDIMM-240-DDR3-R_Selftest_inf.cvf, and quickly verify that the ScanDIMM-240/DDR3/R is functional. Both the ScanExpress Runner software and a Corelis Boundary-Scan controller such as the PCI-1149.1/Turbo are required to execute this file.Infrastructure TestThe infrastructure test verifies the TAP connection between the controller and the ScanDIMM-240/DDR3/R. It also verifies that the boundary-scan infrastructure of the device on the ScanDIMM-240/DDR3/R is fully functional. The infrastructure test requires a Corelis Boundary-Scan controller, a ScanDIMM-240/DDR3/R unit and a Host TAP cable (P/N 15336). The following steps execute an infrastructure test.Steps1.Remove any memory modules from the Unit Under Test (UUT) DIMM socket(s) to be tested.2.Install the ScanDIMM-240/DDR3/R in the socket.3.Connect the Host TAP Adapter cable P/N 15336 to the "TAP IN" connector on the ScanDIMM-240/DDR3/R.4.Connect the 10-pin TAP cable from the external controller to the other end of the Host TAP Adapter cable.5.Apply power to the UUT.6.Make sure that both LEDs on the ScanDIMM-240/DDR3/R illuminate.7.Double-click on the ScanExpress Runner Icon.8.Select New Test Plan from the File menu and click on the Add button.9.With the file browser, find and select the "ScanDIMM-240-DDR3-R_Selftest_inf.cvf" file. Click OK.10.Select Controller from the Setup menu, then choose the appropriate Boundary-Scan controller.11.Set the TCK frequency to 1 MHz and the TAP voltage to 1.8V.12.Select Run Test. The test should run and pass.The figure below shows a passing infrastructure test.Figure 4-1. ScanExpress Runner Infrastructure TestTroubleshooting OverviewUse the following general guidelines to troubleshoot problems when the ScanDIMM-240/DDR3/R is added to the test system.1.Make sure the ScanDIMM-240/DDR3/R's TAP Voltage is set to 1.8V2.Make sure power is being supplied to the ScanDIMM-240/DDR3/R, the boundary-scan controller, and the target. TheScanDIMM-240/DDR3/R's green LEDs will be illuminated if power (1.5V) is being supplied to the DIMM socket and the boundary-scan controller is connected.3.Run the provided self-test and make sure that it passes.4.Reduce the TCK (test clock) frequency to 1 MHz. The TCK frequency can be set too high for the scan chain andsometimes using a lower frequency will allow the test steps to pass. Once the scan chain is known to be stable, then the TCK frequency can be increased to the maximum frequency that will allow the test steps to pass.Notes1.DDR3 modules are not backwards compatible with DDR2 modules and DDR3 modules will not fit into DDR2 sockets;forcing them can damage the ScanDIMM and/or the board.Legal and Contact InformationPRINTING HISTORYRevision A, January 2010Revision B, March 2010Revision C, May 2010GENERAL NOTICEInformation contained in this document is subject to change without notice. CORELIS shall not be liable for errors contained herein for incidental or consequential damages in connection with the furnishing, performance, or use of material contained in this manual.This document contains proprietary information that is protected by copyright. All rights reserved. No part of this document may be reproduced or translated to other languages without the prior written consent of CORELIS. This manual is a CORELIS proprietary document and may not be transferred to another party without the prior written permission of CORELIS. CORELIS assumes no responsibility for the use of or reliability of its software on equipment that is not furnished by CORELIS.ENVIRONMENTAL NOTICEThis product must be disposed of in accordance with the WEEE directive.TRADEMARK NOTICEScanExpress and ScanDIMM are trademarks of Corelis Inc.Other products and services named in this manual are trademarks or registered trademarks of their respective companies. All trademarks and registered trademarks in this manual are the property of their respective holders.PRODUCT WARRANTYFor product warranty and software maintenance information, see the PRODUCT WARRANTY AND SOFTWARE MAINTENANCE POLICY statement included with your product shipment.EXCLUSIVE REMEDIESTHE REMEDIES CONTAINED HEREIN ARE THE CUSTOMER'S SOLE AND EXCLUSIVE REMEDIES. CORELIS SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, WHETHER BASED ON CONTRACT, TORT, OR ANY OTHER LEGAL THEORY. Product maintenance agreements and other customer assistance agreements are available for Corelis products. For assistance, contact your nearest Corelis Sales and Service Office.RETURN POLICYNo items returned to CORELIS for warranty, service, or any other reason shall be accepted unless first authorized by CORELIS, either direct or through its authorized sales representatives. All returned items must be shipped pre-paid and clearly display a Return Merchandise Authorization (RMA) number on the shipping carton. Freight collect items will NOT be accepted. Customers or authorized sales representatives must first contact CORELIS with notice of request for return of merchandise. RMA's can only originate from CORELIS. If authorization is granted, an RMA number will be forwarded to the customer either directly or through its authorized sales representative.CONTACT INFORMATIONFor sales inquiries, please contact *****************.For any support related questions, please enter a support request at /support or email *******************. For more information about other products and services that Corelis offers, please visit .。
芯片中的CP测试是什么
芯片中的CP一般指的是CP测试，也就是晶圆测试(Chip Probing)。
一、CP测试是什么CP测试在整个芯片制作流程中处于晶圆制造和封装之间，测试对象是针对整片晶圆(Wafer)中的每一个Die，目的是确保整片(Wafer)中的每一个Die都能基本满足器件的特征或者设计规格书，通常包括电压、电流、时序和功能的验证。
CP测试的具体操作是在晶圆制作完成之后，成千上万的裸DIE(未封装的芯片)规则的分布满整个Wafer。
由于尚未进行划片封装，只需要将这些裸露在外的芯片管脚，通过探针(Probe)与测试机台(Tester)连接，进行芯片测试就是CP测试。
图1 CP Test在芯片产业价值链上的位置二、为什么要做CP测试因为通常在芯片封装阶段时，有些管脚会被封装在芯片内部，导致有些功能无法在封装后进行测试，因此Wafer中进行CP测试最为合适。
图2 Wafer上规则的排列着DIE而且Wafer制作完成之后，由于工艺偏差、设备故障等原因引起的制造缺陷，分布在Wafer上的裸DIE中会有一定量的残次品。
CP测试的目的就是在封装前将这些残次品找出来(Wafer Sort)，同时还可以避免被封装后无法测试芯片性能，优化生产流程，简化步骤，同时提高出厂的良品率，缩减后续封装测试的成本。
另外，有些公司会根据CP测试的结果，将芯片划分等级，将这些产品投入不同的市场，购买者需要注意这一点。
三、测试内容有哪些1、SCANSCAN用于检测芯片逻辑功能是否正确。
DFT设计时，先使用DesignCompiler插入ScanChain，再利用ATPG(Automatic Test Pattern Generation)自动生成SCAN测试向量。
SCAN测试时，先进入Scan Shift模式，ATE将pattern加载到寄存器上，再通过Scan Capture模式，将结果捕捉。
再进入下次Shift模式时，将结果输出到ATE进行比较。
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Boundary Scan测试原理及实现Boundary scan 的目的：Boundary scan是一种用于测试数字集成电路的技术，它能找出，开路，短路，和功能不良的数字器件，另外它还能完成一些功能测试。
相对于传统的数字器件的向量测试，它还有以下几个优点：具有较短的测试开发时间；能用于探针接触有困难的那些器件的测试；能减少维修时间和维修成本，故障诊断范围可以到PIN脚。
一般理论：Boundary-Scan 测试的时候发送一组信号流到被测的数字器件的转换寄存器单元里面。
而这个单元可以在每一个输入，输出，和双向引脚以及器件的逻辑中心那里找到。
那些信号在寄存器周围转换并且从器件输出，然后用输出的信号和输入的信号之间的差异来比较并判断出错。
例如有两个引脚之间短路或者电源与地脚短路之类的，它都会报错。
几个boundary scan 器件可以被连接到一个链上，从而一些相同的基础测试可以同时执行。
当然，boundary scan还有许多的附加的测试能力，但是这种使用转换寄存器来检查输出的信号流是整个boundary scan测试理论的基础。
两种软件包：在Agilent 3070上有两个不同类型的boundary scan测试软件：他们是：in-circuit boundary scan和HP interconnectplus. 其中in-circuit boundary scan是Agilent 3070标准软件包中自带的，它可以生成标准的单独的数字器件的在线boundary scan测试。
而HP interconnectplu是一个可选软件，它可以生成链式的boundary scan测试程序，同时，它也能自动生成单独器件的boundary scan测试程序。
BOUNDARY-SCAN 的硬件boundary scan器件的设计boundary scan测试软件遵从IEEE 1149.1的标准，遵从此类标准的IC在每个引脚和逻辑中心之间都有一个独立单元。
这些相互独立的单元们连接到一个转换寄存器也叫boundary scan寄存器中，他负责控制和观察每个输入，输出，和双向引脚的值。
每一个boundary scan的器件都有一个特殊的输入引脚（TDI），一个特殊的输出引脚（TDO），TDI作为boundary scan寄存器的输入端，而TDO则连接到boundary scan寄存器的输出端。
在TCK（时钟控制）的基础上，由TAP（test access port）来控制整个工作流程，工作模式选择（TMS）和复位信号（TRST*）有两种boundary-scan测试依赖于boundary-scan器件本身，假如一个元件设计者在设计的时候把IDCODE放到寄存器中，boundary-scan就可以去确认此器件的制造商，PN，和版本号之类的信息，假如此器件还有内嵌的自测（BIST）时，boundary-scan还可以运行这种自测并且报错。
指令寄存器：指令寄存器包含了指令的解码。
也包含了一些数据寄存所使用的特殊指令。
ByPass寄存器：你可以使用ByPass寄存器通过那些没有被使用的Boundary –Scan寄存器链来进行数据传输的工作。
假想你有一个很复杂的IC被用其它的技术象TESTJET之类的去测试而不用boundary-Scan，你也许会决定省略掉这个Boundary-Scan寄存器的长度并用单个单元的ByPass寄存器来代替。
在下图中，使用ByPass寄存器可以包含12个boundary-Scan寄存器，事实上boundary-Scan寄存器的个数一般都很大，所以采用ByPass寄存器，会节约一些测试时间。
身份辨别寄存器：身份辨别寄存器是一个32位的寄存器，它包含了元器件的一些制造信息。
身份辨别寄存器有时也称IDCODE寄存器，因为IDCODE指令显示了身份辨别寄存器中的内容，并不是所有的boundary-scan器件都有IDCODE寄存器，IEEE 1149.1明确指出IDCODE只是一个选项。
Boundary-scan 单元的功能：下图显示了一个典型数据寄存器单元它能灵活的扮演输入或输出单元。
灰色的Internal logic 和Outout Pin阐明了输出的配置。
而紫色的Input pin和Internal logic阐明了输入的配置，对于双向PIN来说，你可以只选用一个单独的单元就行了。
转换，更新和测试模式用其它的颜色来标明：TAP控制器：TAP控制器是一种16位态的设备，它控制boundary-scan测试的操作。
由于TAP控制器管理着大多数的数据和指令寄存器，理解TAP控制器在另一种意义上说等于理解了boundary-Scan, TAP控制器通过TCK，TMS，TRST*来实现控制。
控制线：三个输入控制线：TCK，TMS，TRST*，TCK是一个方波时钟信号，Agilent3070用一个50%的DUTY CYCLE来实现它，TMS信号通过状态图控制着TAP控制器的动作，一般在TCK的上升沿触发TMS，有时也会在TCK的下降沿触发。
而TRSTR*用于复位动作。
例如下图所示，TRST信号一般是在接近序列的中间出现。
测试-逻辑-复位：在测试-逻辑-复位状态时，测试逻辑被禁用从而使此器件可以正常工作，当器件第一次被打开的时候，只要有ID寄存器存在，那个指令寄存器就会引入IDCODE指令，假如没有的话，会引入ByPass寄存器。
一般的，测试-逻辑-复位在TAPcontroller 上电的时候才工作的，测试程序员能够通过使TRST*为低电平或使TMS为高电平并持续至少5个TCK周期来迫使TAP控制器进入上电的状态。
Run-Test/Idle:Run-Test/Idle允许在指令寄存器的指令的基础下激活被选种的测试逻辑电平，TAP controller 在TMS 保持低电平的状态下，会保持Run-Test/Idle的状态，而当TMS转换为高电平的时候，它转移到Select-DR-Scan上去。
Select-DR-Scan：这个TAP控制器扮演一个开关的角色，在下一个TCK的上升沿TAP控制器会开始数据寄存器的扫描或者转到Select-IR-Scan的状态上面。
Capture –DR:在Capture –DR的状态时，夹具上连接到输入PIN的测试针的值，会替换一部分当前被指令选中的部分数据寄存器。
并不是所有的指令都在这个状态做任何事，一些指令可以在数据寄存器现存的数据的基础上工作，TAP控制器会在一个时钟周期内保持这种状态，然后再转移到Exit1-IR或 Shift-IR。
Shift-DR:在Shift-DR的状态，数据寄存器就好象一个转换寄存器在TDI和TDO数据之间并从TDI转移到数据寄存器然后再通过TDO在每一个TCK的上升沿从数据寄存器中出去。
数据寄存器会保持这种状态直到TMS变为高电平，然后设备会转移到Exit1-DR的状态。
Exit1-DR在到达Exit1-DR状态后，TAP controller转移到Pause-DR 或者Update-DR在TCK下一个上升沿，转到Update-DR时，扫描的过程就结束了，当移动到Pause-DR时可以暂停TAP controller的状态进程，此时可以允许测试机调用内存。
Pause-DR当Pause-DR状态时，它允许一个暂停来通过指令寄存器来转换数据，一种情况是TAP controller执行其他的任务时可以使用此种状态，TAP controller会保持这种状态知道TMS变为高电平，然后TAP controller会转移到Exit2-DR状态。
Exit2-DR在到达Exit2-DR状态之后，在下一个TCK的上升沿时TAP controller会转移到Shift-DR或Update-DR。
转移到Shift-DR时会从新开始扫描，转移到Update-DR时中止扫描的进程。
Update-DR在TCK的下降沿时，Update-DR状态从boundaryscan寄存器锁住数据到boundaryscan寄存器的并联输出。
在到达这个状态之后，状态设备转移到Run-Test/Idle或Select-DR-scan，当一个测试转移到Select-DR-scan时比转移到RUN-Test/Idle要快一个时钟周期，转到RUN-Test/Idle去压制ground bounce的影响是一个好办法。
Select-IR-ScanTAPcontroller 充当一个开关的角色。
在TCK下一个上升沿时，TAPcontroller开始IR扫描进程或者重置TAPcontroller到TEST-Logic-Reset状态。
IR—SCAN进程放在TDI和TDO之间的指令寄存器中，并在下一个TAPcontroller指令中转换。
Capture-IRCapture-IR状态在TCK的上升沿时从集成电路板上纳入一个逻辑电平到指令寄存器。
一般都是01之类的信号，用于测试boudary-Scan 电路的完整性。
其他的信号被设计员另外再特指标明或把值赋给变量，在Capture-IR状态待满一个时钟周期后，TAP controller转移到EXIT-IR或Shift-IR。
Shift –IR在Shift –IR的状态，指令寄存器在TDI和TDO之间扮演一个转换寄存器的角色，在Capture-IR抓到的数据在TCK的上升沿时转换到TDO并且一个新的指令从TDI转换进来。
TAP controller直到TMS变为高电平才会改变状态到Exit1-IR.Exit1-IR.到达Exit1-IR 状态之后，在下一个TCK的上升沿时转换到Pause-IR或者Update-IR. 转移到Update-IR时中止扫描的进程。
当移动到Pause-IR时可以暂停TAP controller的状态进程，此时可以允许测试机调用内存。
Pause-IR当Pause-IR状态时，它允许一个暂停来通过指令寄存器来转换数据，一种情况是TAP controller执行其他的任务时可以使用此种状态，TAP controller会保持这种状态知道TMS变为高电平，然后TAP controller会转移到Exit2-IR状态。
Exit2-IR在到达Exit2-IR状态之后，在下一个TCK的上升沿时TAP controller会转移到Shift-DR或Update-IR。
转移到Shift-IR时会从新开始扫描，转移到Update-IR 时中止扫描的进程。
Update-IR在TCK的下降沿时，Update-IR状态latches the instruction register from the flip-flops into latches where the instruction decodeed，一旦一个新的指令被锁住它立刻转变为当前的指令。