ADL5534-EVALZ中文资料
ADL5542 RF IF增益模块说明书
ADI 中文版数据手册是英文版数据手册的译文，敬请谅解翻译中可能存在的语言组织或翻译错误，ADI 不对翻译中存在的差异或由此产生的错误负责。
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50 MHz 至6 GHz RF/IF 增益模块ADL5542Rev. BDocument Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Speci cations subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2007–2013 Analog Devices, Inc. All rights reserved. Technical Support 功能框图2GND 7GND1RFIN 8RFOUT3GND 6GND4CB 5VPOSINPUT MATCHOUTPUT MATCHBIAS CONTROL ADL554206879-001图1.产品特性固定增益：20 dB 工作频率高达6 GHz 输入/输出内部匹配50 Ω集成偏置控制电路输出IP3 46 dBm (500 MHz)40 dBm (900 MHz)1 dB 输出压缩：20.6 dB (900 MHz)噪声系数：3 dB (900 MHz)5 V 单电源供电小尺寸8引脚LFCSP 封装与15 dB 增益的ADL5541引脚兼容1 kV ESD(1C 类)概述ADL5542是一款宽带20 dB 线性放大器，工作频率高达6 GHz ，可用于各种有线电视、蜂窝和仪器仪表设备。
ADL9005-EVALZ Evaluation Board User Guide
ADL9005-EVALZ Evaluation Board User GuideUG-1859One Technology Way • P .O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • Evaluating the ADL9005 Wideband, Low Noise Amplifier, Single Positive Supply,0.01 GHz to 26.5 GHzPLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS.Rev. 0 | Page 1 of 6FEATURES2-layer Rogers 4350B evaluation board with heat spreader End launch, 2.9 mm RF connectorsThrough calibration path (depopulated)EVALUATION KIT CONTENTSADL9005-EVALZ evaluation boardEQUIPMENT NEEDEDRF signal generator RF spectrum analyzer RF network analyzer5 V, 200 mA power supply External dc blockWideband, bias tee (Marki Microwave BT2-0040)GENERAL DESCRIPTIONThe ADL9005-EV AL Z consists of a 2-layer printed circuit board (PCB) fabricated from 10 mil thick, Rogers 4350B, copper clad, mounted to an aluminum heat spreader. The heat spreader assists in providing thermal relief to the device as well as mechanical support to the PCB. Mounting holes on the heat spreader allow attachment to larger heat s ink s for improved thermal management.The RFIN and RFOUT ports on the ADL9005-EV ALZ are populated with 2.9 mm, female coaxial connectors, and the respective RF traces have a 50 Ω characteristic impedance. The ADL9005-EV ALZ is populated with components suitable for use over the entire −40°C to +85°C operating temperature range of the ADL9005.To calibrate out board trace losses, a through calibration path, THRU CAL, is provided between the RFINTHRU and THRUCAL connectors. RFINTHRU and THRUCAL must be populated with RF connectors to use the through calibration path. The power voltages and ground path are accessed through surface-mounted technology (SMT) test points.An external wideband bias tee must be connected to RFOUT to provide bias current and ac coupling on RFOUT. The BT2-0040 from Marki Microwave is recommended.Alternatively, dc bias can be provided by connecting the dc supply voltage to the VDDOPT SMT test point.EVALUATION BOARD PHOTOGRAPHS24818-001Figure 1. ADL9005-EVALZ Top Side24818-002Figure 2. ADL9005-EVALZ Bottom SideThe RF traces are 50 Ω, grounded, coplanar waveguide. The package ground leads and the exposed pad directly connect to the ground plane. Multiple vias are used to connect the top and bottom ground planes with particular focus on the area directly beneath the ground pad to provide adequate electrical conduction and thermal conduction to the heat spreader.For full details on the ADL9005, see the ADL9005 data sheet, which must be consulted in conjunction with this user guide when using the ADL9005-EV ALZ.UG-1859ADL9005-EVALZ Evaluation Board User GuideRev. 0 | Page 2 of 6TABLE OF CONTENTSFeatures .............................................................................................. 1 Evaluation Kit Contents ................................................................... 1 Equipment Needed ........................................................................... 1 General Description ......................................................................... 1 Evaluation Board Photographs ....................................................... 1 Revision History ............................................................................... 2 Evaluation Board Hardware ............................................................ 3 Providing DC Bias Through a Connectorized Bias Tee ..............3 Providing DC Bias Through the ACG4/V DD2 Pin .........................3 Through Calibration Path ............................................................4 Evaluation Board Schematic and Artwork .....................................5 Ordering Information .......................................................................6 Bill of Materials (6)REVISION HISTORY2/2021—Revision 0: Initial VersionADL9005-EVALZ Evaluation Board User GuideUG-1859Rev. 0 | Page 3 of 6EVALUATION BOARD HARDWAREPROVIDING DC BIAS THROUGH A CONNECTORIZED BIAS TEEA 5 V , 200 mA supply is required to provide the bias to the ADL9005 when using the ADL9005-EV ALZ. Connect the 5 V supply through an external bias tee, such as the Marki Microwave BT2-0040, to the RFOUT port (see Figure 3). Connect the same 5 V supply to the VBIAS SMT test point. A connectorized dc blocking capacitor must be connected to the RFIN port because there is not an ac coupling capacitor on the RF input trace on the ADL9005-EV ALZ. The R1 value (default value is 300 Ω) sets the total current (I DQ ) to 80 mA.DC BLOCK24818-003Figure 3. ADL9005-EVALZ Operation Using a Connectorized Bias TeeRecommended Bias SequencingTo avoid damaging the device, careful attention must be paid to the sequencing of the RF input, the bias voltage, and the drain bias voltage. The following power-up sequencing is recommended: 1. Connect GND.2. Increase the voltage on the VBIAS SMT test point and theexternal bias tee to 5 V . 3. Apply the RF signal.The following power-down sequencing is recommended: 1. Turn off the RF signal.2. Reduce the voltage on the VBIAS SMT test point andthe external bias tee to 0 V .PROVIDING DC BIAS THROUGH THE ACG4/V DD2 PINAn alternative way to bias the ADL9005 when using the ADL9005-EV ALZ is by applying 8.5 V to the ACG4/V DD2 pin through the VDDOPT SMT test point and by applying 5 V to the R BIAS pin through the VBIAS SMT test point.The VDDOPT SMT test point connects directly to the ACG4/ V DD2 pin on the ADL9005. The higher 8.5 V supply is required to make up for the voltage drop across an internal resistor so that the internal drain bias voltage is still equal to 5 V . Applying this 8.5 V supply voltage to the VDDOPT SMT test point removes the need for an external bias tee, which must be replaced with a connectorized dc block on the RFOUT port (see Figure 4).With 5 V applied to the VBIAS SMT test point and the default value of R1 at 300 Ω, the resulting I DQ is 80 mA. The VBIAS SMT test point can also be connected directly to the 8.5 V supply. However, to do this, the R1 value must be increased to 850 Ω to maintain an I DQ of 80 mA.DC BLOCKDCBLOCK24818-004Figure 4. ADL9005-EVALZ Operation with V DD Applied Through theVDDOPT SMT Test PointRecommended Bias Sequencing when Providing Bias Through the VDDOPT SMT Test PointThe following sequencing is recommended for power-up when providing bias through the VDDOPT SMT test point: 1. Connect GND.2. Increase the voltage on the VDDOPT SMT test point to 8.5 V .3. Increase the voltage on the VBIAS SMT test point to 5 V .4.Apply the RF signal.The following sequencing is recommended for power-down when providing bias through the VDDOPT SMT test point: 1. Remove the RF signal.2. Decrease the voltage on the VBIAS SMT test point to 0 V .3. Decrease the voltage on the VDDOPT SMT test point to 0 V .UG-1859ADL9005-EVALZ Evaluation Board User GuideRev. 0 | Page 4 of 6THROUGH CALIBRATION PATHThe ADL9005-EV ALZ includes a calibration path (see the evaluation board schematic in Figure 6). RFINTHRU and THRUCAL must be populated with RF connectors to use the through calibration path. Figure 5 shows the insertion loss, input return loss and output return loss of the through calibration path.Table 1 lists the insertion loss of the through calibration path.FREQUENCY (GHz)246810121416182022242628–40–36–32–28–24–20–16–12–8–40I N S E R T I O N L O S S A N D R E T U R N L O S S (d B )24818-005Figure 5. Insertion Loss and Return Loss (Input and Output) of theThrough Calibration PathTable 1. Insertion Loss of the Through Calibration PathFrequency (GHz) Insertion Loss (dB) 0.01 +0.04 0.25 −0.013 0.5 −0.02 0.75 −0.023 1 −0.04 3 −0.1 5 −0.1 7 −0.2 9 −0.2 11 −0.3 13 −0.3 15 −0.5 17 −0.6 19 −0.5 21 −0.6 23 −0.7 25 −0.8 27−1.1ADL9005-EVALZ Evaluation Board User GuideUG-1859Rev. 0 | Page 5 of 624818-006Figure 6. ADL9005-EVALZ Schematic24818-007Figure 7. ADL9005-EVALZ Assembly Drawing (RFINTHRU and THRUCAL Not Installed)UG-1859ADL9005-EVALZ Evaluation Board User GuideRev. 0 | Page 6 of 6ORDERING INFORMATIONBILL OF MATERIALSTable 2.Reference Designator Description Manufacturer Manufacturer Number C1, C12 4.7 μF capacitors, tantalum, do not install (DNI) AVX TAJA475K020RNJ C2, C8 0.01 μF capacitors, ceramic, 0402, DNI KEMET C0402C103J3RACTU C4, C10 100 pF capacitors, ceramic, 0402 Samsung CL05C101JB5NNNC C5 100 pF capacitors, ceramic, 0402, DNI Samsung CL05C101JB5NNNC C6, C7 4.7 μF capacitors, tantalum AVX TAJA475K020RNJ C9, C11 0.01 μF capacitors, ceramic, 0402 KEMETC0402C103J3RACTU R1 300 Ω resistor, surface-mounted device (SMD), 0402 MULTICOMP (SPC) 0402WGF3000TCE R2, R3 0 Ω resistors, SMD, 0402, DNI PanasonicERJ-2GE0R00X RFINTHRU, THRUCAL Connectors, K jack edge, DNI SRI Connector Gage Co. 25-146-1000-92 VBIAS, VDDOPT, AGND Connectors, SMT test points Keystone Electronics 5016RFIN, RFOUT Connectors, K jack edge SRI Connector Gage Co. 25-146-1000-92 VGG2 Connectors, SMT test points, DNIKeystone Electronics 5016 U1Wideband, low noise amplifier, single positive supply, 0.01 GHz to 26.5 GHzAnalog Devices, Inc.ADL9005ESD CautionESD (electrostatic discharge) sensitive device . Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.Legal Terms and ConditionsBy using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc. (“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal, temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY . Customer understands and agrees that the Evaluation Board is provided for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional limitations: Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third Party to access the Evaluation Board. As used herein, the term “Third Party” includes any entity other than ADI, Customer, their employees, affiliates and in-house consultants. The Evaluation Board is NOT sold to Customer; all rights not expressly granted herein, including ownership of the Evaluation Board, are reserved by ADI. CONFIDENTIALITY . This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI. Customer may not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of use of the Evaluation Board or termination of this Agreement, Customer agrees to promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board, including but not limited to soldering or any other activity that affects the material content of the Evaluation Board. Modifications to the Evaluation Board must comply with applicable law, including but not limited to the RoHS Directive. TERMINATION. ADI may terminate this Agreement at any time upon giving written notice to Customer. Customer agrees to return to ADI the Evaluation Board at that time. L IMITATION OF L IABIL ITY . THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED “AS IS” AND ADI MAKES NO WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT. ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS, ENDORSEMENTS, GUARANTEES, OR WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THE EVALUATION BOARD INCLUDING, BUT NOT LIMITED TO, THE IMPL IED WARRANTY OF MERCHANTABILITY , TITL E, FITNESS FOR A PARTICUL AR PURPOSE OR NONINFRINGEMENT OF INTEL LECTUAL PROPERTY RIGHTS. IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER’S POSSESSION OR USE OF THE EVALUATION BOARD, INCLUDING BUT NOT LIMITED TO LOST PROFITS, DELAY COSTS, LABOR COSTS OR LOSS OF GOODWILL. ADI’S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE AMOUNT OF ONE HUNDRED US DOLLARS ($100.00). EXPORT. Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will comply with all applicable United States federal laws and regulations relating to exports. GOVERNING LAW. This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of Massachusetts (excluding conflict of law rules). Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and Customer hereby submits to the personal jurisdiction and venue of such courts. The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed. ©2021 Ana log Devices, Inc. All rights reserved. Tra dema rks a nd registered tra dema rks a re the property of their respective owners. UG24818-2/21(0)。
CS5344-CZZ中文资料
Master Clgle-Ended Analog Input
High-Z AINR Sampling
Network
High-Pass Filter
Low-Latency Digital Filters
SDOUT
The CS5343/4 also features a high-impedance sampling network which eliminates costly external components such as op-amps.
The CS5343/4 is available in a 10-pin TSSOP package for both Commercial (-10° to +70° C) and Automotive grades (-40° to +85° C). The CDB5343 Customer Demonstration Board is also available for device evaluation and implementation suggestions. Please refer to the “Ordering Information” on page 21 for complete details.
4.1.1 Slave Mode Operation ........................................................................................................... 13 4.1.2 Master Mode Operation ......................................................................................................... 14
Circuits from the Lab
ADI 中文版数据手册是英文版数据手册的译文，敬请谅解翻译中可能存在的语言组织或翻译错误，ADI 不对翻译中存在的差异或由此产生的错误负责。
如需确认任何词语的准确性，请参考ADI 提供的最新英文版数据手册。
Circuits from the Lab™ reference circuits are engineered and tested for quick and easy system integration to help solve today’s analog, mixed-signal, and RF design challenges. For more information and/or support, visit /CN0248.ADRF6510 30 MHz 双通道可编程滤波器和可变增益放大器ADL5387 50 MHz 至2 GHz 正交解调器ADL5336集成48 dB 增益控制范围和可编程RMS 检波器的LF 至1 GHz VGA基于IQ 解调器，具有中频和基带可变增益以及可编程基带滤波功能的中频至基带接收机Rev. 0Circuits from the Lab™ circuits from Analog Devices have been designed and built by Analog Devices engineers. Standard engineering practices have been employed in the design and construction of each circuit, and their function and performance have been tested and veri ed in a lab environment at room temperature. However , you are solely responsible for testing the circuit and determining its suitability and applicability for your use and application. Accordingly , in no event shall Analog Devices be liable for direct, indirect, special, incidental, consequential or punitive damages due to any cause whatsoever connected to the use of any Circuits from the Lab circuits. (Continued on last page)One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ©2012 Analog Devices, Inc. All rights reserved.ADRF6510IQRFDIV BY 2ADL53872xLO0°90°ADF4350ADL5336AD9248BITSBITS10285-001VCO CORE图1. 直接变频接收机原理示意图(所有连接和去耦均未显示)CN-0248电路笔记连接/参考器件评估和设计支持电路评估板ADRF6510评估板(ADRF6510-EVALZ)ADL5387评估板(ADL5387-EVALZ) ADL5336评估板(ADL5336-EVALZ) AD8130评估板(AD8130-EBZ)，需要两个设计和集成文件原理图、布局文件、物料清单电路功能与优势该电路是灵活的频率捷变中频至基带接收机。
MHz至GHzRFIF增益模块ADL
MHz至GHz RF-IF增益模块—ADL50 MHz至4 GHz RF/IF增益模块—ADL5601ADL5601是一款15dB宽带线性放大器，最高工作频率为4GHz。
该器件可广泛用于手机、有线电视（CATV）、军事和仪器仪表设备等应用领域。
ADL5601通过内部匹配的增益模块可提供极大的动态范围。
在整个4GHz频率范围内，同时还提供极低的噪声指数和非常高的OIP3规格参数。
ADL5601的增益为15dB，可在频率、温度、电源波动的条件下保持稳定，且具有良好的器件一致性。
该器件内部在输入端和输出端与50Ω电阻匹配，可非常容易地应用于各种系统中。
仅需输入/输出交流耦合电容、电源去耦电容和外部电感器件即可工作。
ADL5601使用InGaP HBT工艺制造，ESD额定电压为±1.5 kV (Class 1C)。
该器件采用散热效率高的SOT-89封装。
ADL5601在5V单电源下静态电流为83mA，额定工作温度范围为-40°C至+85°C。
同时提供配置齐全的RoHS兼容*估板。
ADL5601 功能框图特性：●15dB固定增益●工作频率范围为50MHz至4GHz●动态范围极高的增益模块●输入/输出内部与50Ω电阻匹配●集成的偏置控制电路●在900MHz，OIP3为43.0 dBm●在900MHz，P1dB为19.0 dBm●在900MHz，噪声指数为3.7 dB●5V单电源●83mA的低静态电流●高散热效率的SOT-89封装●ESD额定电压±1.5 kV (Class 1C)。
运放NE5534一些参数的讲解
NE5534运放芯片一些资料整理：极限参数：直流指标：运放主要直流指标有输入失调电压、输入失调电压的温度漂移（简称输入失调电压温漂）、输入偏置电流、输入失调电流、输入偏置电流的温度漂移（简称输入失调电流温漂）、差模开环直流电压增益、共模抑制比、电源电压抑制比、输出峰-峰值电压、最大共模输入电压、最大差模输入电压。
NE5532的直流指标如下：∙输入失调电压Vos：输入失调电压定义为集成运放输出端电压为零时，两个输入端之间所加的补偿电压。
输入失调电压实际上反映了运放内部的电路对称性，对称性越好，输入失调电压越小。
输入失调电压是运放的一个十分重要的指标，特别是精密运放或是用于直流放大时。
输入失调电压与制造工艺有一定关系，其中双极型工艺（即上述的标准硅工艺）的输入失调电压在±1~10mV之间；采用场效应管做输入级的，输入失调电压会更大一些。
对于精密运放，输入失调电压一般在1mV 以下。
输入失调电压越小，直流放大时中间零点偏移越小，越容易处理。
所以对于精密运放是一个极为重要的指标。
∙输入失调电压的温度漂移（简称输入失调电压温漂）ΔVos/ΔT：输入失调电压的温度漂移定义为在给定的温度范围内，输入失调电压的变化与温度变化的比值。
这个参数实际是输入失调电压的补充，便于计算在给定的工作范围内，放大电路由于温度变化造成的漂移大小。
一般运放的输入失调电压温漂在±10~20μV/℃之间，精密运放的输入失调电压温漂小于±1μV/℃。
输入偏置电流定义为当运放的输出直流电压为零时，其两输入端的偏置电流平均值。
输入偏置电流对进行高阻信号放大、积分电路等对输入阻抗有要求的地方有较大的影响。
输入偏置电流与制造工艺有一定关系，其中双极型工艺（即上述的标准硅工艺）的输入偏置电流在±10nA~1μA之间；采用场效应管做输入级的，输入偏置电流一般低于1nA。
∙输入失调电流的温度漂移（简称输入失调电流温漂）ΔIos/ΔT：∙最大共模输入电压Vcm：最大共模输入电压定义为，当运放工作于线性区时，在运放的共模抑制比特性显著变坏时的共模输入电压。
NE5534_中文资料
NE55345533/5534分别是双/单路高效低噪音运算放大器。
相比于那些如TL083的放大器而言，它们拥有更好的噪声性能，更高的外部驱动能力以及更加高的小信号输入和更高的功率带宽。
这使得它们特别适合应用于高质量和专业的音频设备以及仪器仪表，控制电路和电话信道功率放大器。
它的内部补偿大于或等于三，其频率响应可以在外部通过补偿电容针对不同的应用需求（单位增益放大器，电容负载性，转换速率，降低自激等等的要求）优化。
如果超低噪声是首要的要求，那么建议仔细阅读5533A/5534A类型的保证噪声特性的说明。
高性能运算放大器结合良好的直流和交流的特点。
一些特点包括很低噪音、高驱动输出能力,高单位增益和最大的输出摆动带宽和高,低失真,转换速率。
这些运算放大器的内部得到补偿等于或大于三个。
频率响应各种的优化使应用程序可以通过使用外部补偿电容器赔偿金之间能够被获得。
这些设备特征有输入保护二极管、输出保护短路,使用剩余和平衡来补偿电压无效的能力。
特性：·小信号的带宽：10MHZ·输出驱动能力：600 Ω，10VRMS at 在VS=±18V·输入噪声：4nV/HZ^2·直流电压增益：100000·交流电压增益：6000在频率为10KHZ·功率带宽：200KHZ·转换速率：每秒13V·大电源电压范围：从±3V到±20V引脚配置NE/SA/SE5534/5534A平衡1 8 平衡/补偿反相输入2 7 V+同相输入 3 6 输出V- 4 5 补偿绝对最大额定参数（额定值）电源电压 ±22V输入电压差分输入电压 ±0.5V功耗8N封装1150Mw10秒可承受的焊接温度300︒C备注：1．二极管起过流保护作用，因此，除非电路中有限流电阻，否则当差分输入超过0.6V时，将有大电流输入。
最大的电流应该控制在 ±10mA以内。
NE5534-D芯片资料
30
100
−
−
38
−
50
100
−
−
38
−
Unit mV mV mV/°C nA nA pA/°C nA nA nA/°C mA
V dB mV/V V/mV
V
kW mA
3
NE5534, SA5534, SE5534, NE5534A, SA5534A, SE5534A
RIN
Output Short Circuit Current
ISC
3. For NE5534/5534A, TMIN = 0°C, TMAX = 70°C. 4. For SA5534/5534A, TMIN = −40°C, TMAX = +85°C. 5. For SE5534/5534A, TMIN = −55°C, TMAX = +125°C.
1. Diodes protect the inputs against overvoltage. Therefore, unless current-limiting resistors are used, large currents will flow if the differential input voltage exceeds 0.6 V. Maximum current should be limited to "10 mA.
−
Overtemperature "10 "12
−
RL w 600 W;
"15 "16
−
VS = "18 V
RL w 2.0 kW
"13 "13.5
−
AD5554BRS中文资料
Symbol N INL DNL IOUTX IOUTX GFSE TCVFS RFBX VREFX RREFX RREFX CREFX IOUTX COUTX VIL VIH IIL CIL VOL VOH tCH tCL tCSS tCSH tPD tLDAC tDS tDH tLDS tLDH VDD RANGE IDD ISS PDISS PSS
元器件交易网
a
FEATURES AD5544 16-Bit Resolution AD5554 14-Bit Resolution 2 mA Full-Scale Current ؎ 20%, with VREF = ؎ 10 V 2 s Settling Time V SS BIAS for Zero-Scale Error Reduction @ Temp Midscale or Zero-Scale Reset Four Separate 4Q Multiplying Reference Inputs SPI-Compatible 3-Wire Interface Double Buffered Registers Enable Simultaneous Multichannel Change Internal Power ON Reset Compact SSOP-28 Package APPLICATIONS Automatic Test Equipment Instrumentation Digitally-Controlled Calibration
Quad, Current-Output Serial-Input, 16-Bit/14-Bit DACs AD5544/AD5554
FUNCTIONAL BLOCK DIAGRAM
CS5532-BSZR;CS5534-BSZR;CDB5532U;中文规格书,Datasheet资料
Copyright © Cirrus Logic, Inc. 2008CS5532/34-BS24-bit ∆Σ ADCs with Ultra-low-noise PGIAFeaturesChopper-stabilized PGIA (ProgrammableGain Instrumentation Amplifier, 1x to 64x)– 6 nV/√Hz @ 0.1 Hz (No 1/f noise) at 64x –1200pA Input Current with Gains >1 Delta-sigma Analog-to-digital Converter –Linearity Error: 0.0007% FS–Noise-free Resolution: Up to 23 bits Two- or Four-channel Differential MUX Scalable Input Span via Calibration –±5 mV to differential ±2.5VScalable V REF Input: Up to Analog Supply Simple Three-wire Serial Interface –SPI™ and Microwire™ Compatible –Schmitt Trigger on Serial Clock (SCLK) R/W Calibration Registers Per Channel Selectable Word Rates: 6.25 to 3,840 Sps Selectable 50 or 60 Hz RejectionPower Supply Configurations–VA+ = +5 V; VA- = 0 V; VD+ = +3 V to +5 V–VA+ = +2.5 V; VA- = -2.5 V; VD+ = +3 V to +5 V –VA+ = +3 V; VA- = -3 V; VD+ = +3 VGeneral DescriptionThe CS5532/34 are highly integrated ∆Σ Analog-to-Digi-tal Converters (ADCs) which use charge-balance techniques to achieve 24-bit performance. The ADCs are optimized for measuring low-level unipolar or bipolar signals in weigh scale, process control, scientific, and medical applications.To accommodate these applications, the ADCs come as either two-channel (CS5532) or four-channel (CS5534)devices and include a very low-noise, chopper-stabilized instrumentation amplifier (6 nV/√Hz @ 0.1 Hz) with se-lectable gains of 1×, 2×, 4×, 8×, 16×, 32×, and 64×.These ADCs also include a fourth-order ∆Σ modulator followed by a digital filter which provides twenty selectable output word rates of 6.25, 7.5, 12.5, 15, 25, 30, 50, 60, 100,120, 200, 240, 400, 480, 800, 960, 1600, 1920, 3200, and 3840 Sps (MCLK =4.9152MHz).To ease communication between the ADCs and a micro-controller, the converters include a simple three-wire se-rial interface which is SPI™ and Microwire™ compatible with a Schmitt-trigger input on the serial clock (SCLK).High dynamic range, programmable output rates, and flexible power supply options makes these ADCs ideal solutions for weigh scale and process control applications.ORDERING INFORMATIONSee page 47VA+C1C2VREF+VREF-VD+DIFFERENTIAL 4TH ORDER ∆ΣMODULATORPGIA 1,2,4,8,16PROGRAMMABLE SINC FIR FILTERMUX(CS5534SHOWN)AIN1+AIN1-AIN2+AIN2-AIN3+AIN3-AIN4+AIN4-SERIAL INTERFACELATCHCLOCK GENERATORCALIBRATION SRAM/CONTROLLOGICDGNDCSSDI SDO SCLKOSC2OSC1A1A0/GUARD VA-32,64OCT ‘08TABLE OF CONTENTS1.CHARACTERISTICS AND SPECIFICATIONS (4)ANALOG CHARACTERISTICS (4)TYPICAL RMS NOISE (NV) (7)TYPICAL NOISE-FREE RESOLUTION(BITS) (7)5 V DIGITAL CHARACTERISTICS (8)3 V DIGITAL CHARACTERISTICS (8)DYNAMIC CHARACTERISTICS (9)ABSOLUTE MAXIMUM RATINGS (9)SWITCHING CHARACTERISTICS (10)2.GENERAL DESCRIPTION (12)2.1.Analog Input (12)2.1.1. Analog Input Span (13)2.1.2. Multiplexed Settling Limitations (13)2.1.3. Voltage Noise Density Performance (13)2.1.4. No Offset DAC (14)2.2.Overview of ADC Register Structure and Operating Modes (14)2.2.1. System Initialization (15)2.2.2. Serial Port Interface (22)2.2.3. Reading/Writing On-Chip Registers (23)2.3.Configuration Register (23)2.3.1. Power Consumption (23)2.3.2. System Reset Sequence (23)2.3.3. Input Short (24)2.3.4. Guard Signal (24)2.3.5. Voltage Reference Select (24)2.3.6. Output Latch Pins (24)2.3.7. Offset and Gain Select (25)2.3.8. Filter Rate Select (25)2.4.Setting up the CSRs for a Measurement (27)2.5.Calibration (30)2.5.1. Calibration Registers (30)2.5.2. Performing Calibrations (31)2.5.3. Self Calibration (31)2.5.4. System Calibration (32)2.5.5. Calibration Tips (32)2.5.6. Limitations in Calibration Range (33)2.6.Performing Conversions (33)2.6.1. Single Conversion Mode (33)2.6.2. Continuous Conversion Mode (34)2.6.3. Examples of Using CSRs to Perform Conversions and Calibrations (35)ing Multiple ADCs Synchronously (36)2.8.Conversion Output Coding (36)2.9.Digital Filter (38)2.10.Clock Generator (39)2.11.Power Supply Arrangements (39)2.12.Getting Started (43)2.13.PCB Layout (43)3.PIN DESCRIPTIONS (44)4.SPECIFICATION DEFINITIONS (46)5.ORDERING INFORMATION (47)6.ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION (47)7.PACKAGE DRAWINGS (48)LIST OF FIGURESFigure 1. SDI Write Timing (Not to Scale) (11)Figure 2. SDO Read Timing (Not to Scale) (11)Figure 3. Multiplexer Configuration (12)Figure 4. Input models for AIN+ and AIN- pins (13)Figure 5. Measured Voltage Noise Density (13)Figure 6. CS5532/34 Register Diagram (14)Figure 7. Command and Data Word Timing (22)Figure 8. Guard Signal Shielding Scheme (24)Figure 9. Input Reference Model when VRS = 1 (25)Figure 10. Input Reference Model when VRS = 0 (25)Figure 11. Self Calibration of Offset (32)Figure 12. Self Calibration of Gain (32)Figure 13. System Calibration of Offset (32)Figure 14. System Calibration of Gain (32)Figure 15. Synchronizing Multiple ADCs (36)Figure 16. Digital Filter Response (WR = 60 Sps) (38)Figure 18. 120 Sps Filter Phase Plot to 120 Hz (38)Figure 17. 120 Sps Filter Magnitude Plot to 120 Hz (38)Figure 19. Z-Transforms of Digital Filters (38)Figure 20. On-chip Oscillator Model (39)Figure 21. CS5532 Configured with a Single +5 V Supply (40)Figure 22. CS5532 Configured with ±2.5 V Analog Supplies (41)Figure 23. CS5532 Configured with ±3 V Analog Supplies (41)Figure 24. CS5532 Configured for Thermocouple Measurement (42)Figure 25. Bridge with Series Resistors (42)LIST OF TABLESTable 1. Conversion Timing – Single Mode (34)Table 2. Conversion Timing – Continuous Mode (35)Table 3. Command Byte Pointer (35)Table 4. Output Coding for 24-bit CS5532 and CS5534 (37)1. CHARACTERISTICS AND SPECIFICATIONSANALOG CHARACTERISTICS(VA+, VD+ = 5 V ±5%; VREF+ = 5 V; VA-, VREF-, DGND = 0 V; MCLK = 4.9152 MHz; OWR (Output Word Rate) = 60 Sps; Bipolar Mode; Gain = 32)(See Notes 1 and 2.)Notes: 1.Applies after system calibration at any temperature within -40 °C ~ +85 °C.2.Specifications guaranteed by design, characterization, and/or test. LSB is 24 bits.3. This specification applies to the device only and does not include any effects by external parasiticthermocouples. The PGIA contributes 5 nV of offset drift, and the modulator contributes 640/G nV of offset drift, where G is the amplifier gain setting.4.Drift over specified temperature range after calibration at power-up at 25 °C.ParameterMin Typ Max Unit Accuracy Linearity Error -±0.0007±0.0015%FS No Missing Codes 24--Bits Bipolar Offset -±16±32LSB 24Unipolar Offset-±32±64LSB 24Offset Drift(Notes 3 and 4)-640/G +5-nV/°C Bipolar Full-scale Error -±8±31ppm Unipolar Full-scale Error -±16±62ppm Full-scale Drift(Note 4)-2-ppm/°CANALOG CHARACTERISTICS (Continued)(See Notes 1 and 2.)Notes: 5.The voltage on the analog inputs is amplified by the PGIA, and becomes V CM ± Gain*(AIN+ - AIN-)/2 atthe differential outputs of the amplifier. In addition to the input common mode + signal requirements for the analog input pins, the differential outputs of the amplifier must remain between (VA- + 0.1 V) and (VA+ - 0.1 V) to avoid saturation of the output stage.6.See the section of the data sheet which discusses input models.7.Input current on AIN+ or AIN- (with Gain =1), or VREF+ or VREF- may increase to 250nA if operatedwithin 50mV of VA+ or VA-. This is due to the rough charge buffer being saturated under these conditions.ParameterMin TypMaxUnitAnalog InputCommon Mode + Signal on AIN+ or AIN-Bipolar/Unipolar ModeGain = 1 Gain = 2, 4, 8, 16, 32, 64(Note 5)VA-VA- + 0.7--VA+VA+ - 1.7V V CVF Current on AIN+ or AIN-Gain = 1 (Note 6, 7)Gain = 2, 4, 8, 16, 32, 64--501200--nA pA Input Current Noise Gain = 1 Gain = 2, 4, 8, 16, 32, 64--2001--pA/√Hz pA/√Hz Input Leakage for Mux when Off (at 25 °C)-10-pA Off-channel Mux Isolation -120-dB Open Circuit Detect Current 100300-nA Common Mode Rejection dc, Gain = 1dc, Gain = 6450, 60 Hz ---90130120---dB dB dB Input Capacitance -60-pF Guard Drive Output -20-µA Voltage Reference Input Range (VREF+) - (VREF-)1 2.5(VA+)-(VA-)V CVF Current (Note 6, 7)-50-nA Common Mode Rejection dc 50, 60 Hz --120120--dB dB Input Capacitance 11-22pF System Calibration Specifications Full-scale Calibration Range Bipolar/Unipolar Mode 3-110%FS Offset Calibration Range Bipolar Mode -100-100%FS Offset Calibration Range Unipolar Mode -90-90%FSANALOG CHARACTERISTICS (Continued)(See Notes 1 and 2.)8.All outputs unloaded. All input CMOS levels.9.Power is specified when the instrumentation amplifier (Gain ≥ 2) is on. Analog supply current is reducedby approximately 1/2 when the instrumentation amplifier is off (Gain = 1).10.Tested with 100 mV change on VA+ or VA-.ParameterMinTypMaxUnitPower SuppliesDC Power Supply Currents (Normal Mode)I A+, I A-I D+- - 130.5151mA mA Power ConsumptionNormal Mode (Notes 8 and 9)Standby Sleep---70450080--mW mW µW Power Supply Rejection (Note 10)dc Positive Supplies dc Negative Supply--115115--dB dBTYPICAL RMS NOISE (nV)(See notes 11, 12, 13 and 14)Notes:11.The -B devices provide the best noise specifications.12.Wideband noise aliased into the baseband. Referred to the input. Typical values shown for 25 °C.13.For Peak-to-Peak Noise multiply by 6.6 for all ranges and output rates.14.Word rates and -3dB points with FRS = 0. When FRS = 1, word rates and -3dB points scale by 5/6.TYPICAL NOISE-FREE RESOLUTION(BITS)(See Notes 15 and 16)15.Noise-free resolution listed is for bipolar operation, and is calculated as LOG((Input Span)/(6.6xRMSNoise))/LOG(2) rounded to the nearest bit. For unipolar operation, the input span is 1/2 as large, so one bit is lost. The input span is calculated in the analog input span section of the data sheet. The noise-free resolution table is computed with a value of 1.0 in the gain register. Values other than 1.0 will scale the noise, and change the noise-free resolution accordingly.16.“Noise-free resolution” is not the same as “effective resolution”. Effective resolution is based on theRMS noise value, while noise-free resolution is based on a peak-to-peak noise value specified as 6.6 times the RMS noise value. Effective resolution is calculated as LOG((Input Span)/(RMS Noise))/LOG(2).Specifications are subject to change without notice.Output Word Rate (Sps)-3 dB Filter Frequency (Hz)Instrumentation Amplifier Gain x64x32x16x8x4x2x17.5 1.948.59101526509915 3.88121315213770139307.751718213052991966015.524252942731402771203134364259103198392240628013626051410202050409048012211319436973014502900581096023015927452310302060411082301,920390260470912181036207230145003,84078013602690538010800215004300086000Output Word Rate (Sps)-3 dB Filter Frequency (Hz)Instrumentation Amplifier Gainx64x32x16x8x4x2x17.5 1.942021222323232315 3.8820212222222222307.75192021222222226015.5192021212121211203118192021212121240621717181818181848012217171717171717960230161617171717171,920390161616161616163,840780131313131313135 V DIGITAL CHARACTERISTICS(VA+, VD+ = 5 V ±5%; VA-, DGND = 0 V; See Notes 2 and 17.)3 V DIGITAL CHARACTERISTICS(T A = 25 °C; VA+ = 5V ±5%; VD+ = 3.0V±10%; VA-, DGND = 0V; See Notes 2 and 17.)17.All measurements performed under static conditions.ParameterSymbol Min Typ Max Unit High-level Input Voltage All Pins Except SCLKSCLK V IH 0.6 VD+(VD+) - 0.45--VD+VD+V Low-level Input Voltage All Pins Except SCLKSCLK V IL 0.00.0-0.80.6V High-level Output Voltage A0 and A1, I out = -1.0 mASDO, I out = -5.0 mA V OH (VA+) - 1.0(VD+) - 1.0--V Low-level Output Voltage A0 and A1, I out = 1.0 mASDO, I out = 5.0 mAV OL --(VA-) + 0.40.4V Input Leakage Current I in -±1±10µA SDO Tri-State Leakage Current I OZ --±10µA Digital Output Pin CapacitanceC out-9-pFParameterSymbol Min Typ Max Unit High-level Input Voltage All Pins Except SCLKSCLK V IH 0.6 VD+(VD+) - 0.45-VD+VD+V Low-level Input Voltage All Pins Except SCLKSCLK V IL 0.00.0-0.80.6V High-level Output Voltage A0 and A1, I out = -1.0 mASDO, I out = -5.0 mA V OH (VA+) - 1.0(VD+) - 1.0--V Low-level Output Voltage A0 and A1, I out = 1.0 mASDO, I out = 5.0 mAV OL --(VA-) + 0.40.4V Input Leakage Current I in -±1±10µA SDO Tri-State Leakage Current I OZ --±10µA Digital Output Pin CapacitanceC out-9-pFDYNAMIC CHARACTERISTICS18.The ADCs use a Sinc 5 filter for the 3200 Sps and 3840 Sps output word rate (OWR) and a Sinc 5 filterfollowed by a Sinc 3 filter for the other OWRs. OWR sinc5 refers to the 3200 Sps (FRS = 1) or 3840 Sps (FRS = 0) word rate associated with the Sinc 5 filter.19.The single conversion mode only outputs fully settled conversions. See Table 1 for more details aboutsingle conversion mode timing. OWR SC is used here to designate the different conversion time associated with single conversions.20.The continuous conversion mode outputs every conversion. This means that the filter’s settling timewith a full scale step input in the continuous conversion mode is dictated by the OWR.ABSOLUTE MAXIMUM RATINGS(DGND = 0 V; See Note 21.)Notes:21.All voltages with respect to ground.22.VA+ and VA- must satisfy {(VA+) - (VA-)} ≤ +6.6 V.23.VD+ and VA- must satisfy {(VD+) - (VA-)} ≤ +7.5 V.24.Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pins.25.Transient current of up to 100 mA will not cause SCR latch-up. Maximum input current for a power supply pin is ±50 mA.26.Total power dissipation, including all input currents and output currents.WARNING:Operation at or beyond these limits may result in permanent damage to the device.Normal operation is not guaranteed at these extremes.ParameterSymbol Ratio Unit Modulator Sampling Ratef s MCLK/16Sps Filter Settling Time to 1/2 LSB (Full Scale Step Input)Single Conversion mode (Notes 18, 19, and 20)Continuous Conversion mode, OWR < 3200 Sps Continuous Conversion mode, OWR ≥ 3200 Spst s t s t s1/OWR SC5/OWR sinc5 + 3/OWR5/OWRs s sParameterSymbol Min Typ Max Unit DC Power Supplies(Notes 22 and 23)Positive Digital Positive Analog Negative Analog VD+VA+VA--0.3-0.3+0.3---+6.0+6.0-3.75V V V Input Current, Any Pin Except Supplies (Notes 24 and 25)I IN --±10mA Output Current I OUT--±25mA Power Dissipation (Note 26)PDN --500mW Analog Input Voltage VREF pins AIN PinsV INR V INA (VA-) -0.3(VA-) -0.3--(VA+) + 0.3(VA+) + 0.3V V Digital Input VoltageV IND -0.3-(VD+) + 0.3V Ambient Operating Temperature T A -40-85°C Storage Temperature T stg-65-150°CSWITCHING CHARACTERISTICS(VA+ = 2.5 V or 5 V ±5%; VA- = -2.5V±5% or 0 V; VD+ = 3.0 V ±10% or 5 V ±5%;DGND = 0 V; Levels: Logic 0 = 0 V, Logic 1 = VD+; C L = 50 pF; See Figures 1 and 2.)Notes:27.Device parameters are specified with a 4.9152 MHz clock.28.Specified using 10% and 90% points on waveform of interest. Output loaded with 50pF.29.Oscillator start-up time varies with crystal parameters. This specification does not apply when using anexternal clock source.ParameterSymbol Min Typ MaxUnitMaster Clock Frequency (Note 27)External Clock or Crystal OscillatorMCLK1 4.91525MHz Master Clock Duty Cycle 40-60%Rise Times(Note 28)Any Digital Input Except SCLKSCLKAny Digital Output t rise-----50 1.0100-µs µs ns Fall Times(Note 28)Any Digital Input Except SCLKSCLKAny Digital Output t fall-----50 1.0100-µs µs ns Start-upOscillator Start-up Time XTAL = 4.9152 MHz(Note 29)t ost-20-ms Serial Port Timing Serial Clock Frequency SCLK 0-2MHz Serial Clock Pulse Width High Pulse Width Lowt 1t 2250250----ns nsSDI Write TimingCS Enable to Valid Latch Clock t 350--ns Data Set-up Time prior to SCLK rising t 450--ns Data Hold Time After SCLK Rising t 5100--ns SCLK Falling Prior to CS Disable t 6100--nsSDO Read Timing CS to Data Validt 7--150ns SCLK Falling to New Data Bit t 8--150ns CS Rising to SDO Hi-Zt 9--150ns分销商库存信息:CIRRUS-LOGICCS5532-BSZR CS5534-BSZR CDB5532U。
cs553234中文资料
--
nV/℃
双极全量程误差
--
±8
单极全量程误差
--
±16
全量程偏移（参见注 4）
--
2
模拟输入
普通模式+信号（在 AIN+或 AIN-双极性/
±31
Ppm
±62
ppm
--
ppm/℃
单极性模式）
增益=1
增益=2，4，8，16，32，64（参见注 5）
在 AIN+或 AIN-处的 CVF 电流增益=1（注 6，7）
值将会改变噪声，无噪声分辨率相应地会改变。
16.无噪声分辨率不同于有效分辨率。有效分辨率是基于噪声的均方根（即：
RMS 值）；而无噪声分辨率则是基于一个峰-峰噪声值，该数值定义为 6.6 乘以噪
声的 RMS 值。有效分辨率按：LOG(输入间距/噪声 RMS 值)/LOG2 计算出来的。
规格如有变更，恕不另行通知。
--
pA
--
dB
开路检测电流
100
300
--
nA
共模抑制
dc，增益=1 dc，增益=64 50，60Hz
输入容抗
--
90
--
dB
--
130
--
dB
--
120
--
dB
--
60
--
pF
保护驱动输出
--
20
参考电压输出
--
µA
范围 CVF 电流
共模抑制
（VREF+）-(VREF-)
1
（参见注 6，注 7） --
-- (VD+)+0.3
V
AD转换IC--使用手册中文版
2
DS289P速率选择 .................................................... 22 2.3.9 配置寄存器描述 .................................................. 22 2.4 通道设置寄存器 CSR 的设置.............................................. 23 2.4.1 通道设置寄存器描述 .............................................. 23 2.5 校准.................................................................. 25 2.5.1 校准寄存器 ...................................................... 25 2.5.2 增益寄存器 ...................................................... 25 2.5.3 偏移寄存器 ...................................................... 26 2.5.4 执行校准 ........................................................ 27 2.5.5 自校准 .......................................................... 27 2.5.6 系统校准 ........................................................ 27 2.5.7 校准技巧 ........................................................ 27 2.5.8 校准范围限制 .................................................... 28 2.6 执行转换.............................................................. 28 2.6.1 单次转换模式（MC=0 ） ........................................... 28 2.6.2 连续转换模式（MC=1 ） ........................................... 28 2.6.3 利用 CSR 进行转换和校准的例子.................................... 29 2.7 同时使用多个 ADC ...................................................... 29 2.8 转换输出编码.......................................................... 30 2.8.1 转换数据寄存器描述 .............................................. 31 2.9 数字滤波器............................................................ 32 2.10 时钟发生器........................................................... 32 2.11 电源配置............................................................. 32 2.12 准备开始............................................................. 35 2.13 PCB 布线............................................................. 35 3. 引脚描述 .................................................................. 36 4. 术语解释 .................................................................. 37 5. 订货指南 .................................................................. 38 6. 封装图 .................................................................... 38
SE5534中文资料
DC ELECTRICAL CHARACTERISTICS
TA=25°C, VS=±15V, unless otherwise specified. 1, 2, 3 SYMBOL VOS Offset voltage ∆VOS/∆T IOS Offset current ∆IOS/∆T IB Input current ∆IB/∆T ICC VCM CMRR PSRR AVOL Supply current per op amp Common mode input range Common mode rejection ratio Power supply rejection ratio Large-signal voltage gain RL≥600Ω, VO=±10V Over temperature RL≥600Ω Over temperature RL≥600Ω, VS=±18V RL≥2kΩ Over temperature 50 25 ±12 ±10 ±15 ±13 ±12 50 Over temperature ±12 80 ±13 100 10 100 ±13 ±12 ±16 ±13.5 ±12.5 100 38 50 25 15 ±12 ±10 ±15 ±13 ±12 30 Over temperature 5 4 6.5 9 ±12 70 Over temperature 200 400 800 1500 5 4 ±13 100 10 100 ±13 ±12 ±16 ±13.5 ±12.5 100 38 100 8 10 Over temperature 5 10 200 500 200 500 1500 2000 PARAMETER TEST CONDITIONS SE5534/5534A Min Typ 0.5 Max 2 3 5 20 300 400 NE5533/5533A NE/SA5534/5534A Min Typ 0.5 Max 4 5 mV mV µV/°C nA nA pA/°C nA nA nA/°C mA mA V dB µV/V V/mV V/mV V V V V V kΩ mA UNIT
ADL5530中文资料
Rev. 0 | Page 2 of 12
元器件交易网
ADL5530
SPECIFICATIONS
VPOS = 5 V and TA = 25°C, unless otherwise noted.
Table 1.
Parameter
Conditions
OVERALL FUNCTION (See Table 2)
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
Frequency Range1
Gain (S21)
Input Return Loss (S11)
Output Return Loss (S22)
Reverse Isolation (S12)
FREQUENCY = 70 MHz
Gain
vs. Temperature
−40°C ≤ TA ≤ +85°C
The ADL5530 is fabricated on a GaAs pHEMPT process. The device is packaged in a 3 mm × 2 mm LFCSP that uses an exposed paddle for excellent thermal impedance. It operates from −40°C to +85°C. A fully populated evaluation board is also available.
CS5334中文资料
Features•CS5334Dynamic Range: 100 dBTHD+N: -90 dB•CS5335Dynamic Range: 105 dBTHD+N: -95 dB•128X Oversampling •Fully Differential Inputs•Linear Phase Digital Anti-Alias Filtering21.7 kHz passband (fs = 48kHz)85 dB stop band attenuation 0.0025 dB pass band ripple•High Pass Filter - DC offset removal •Peak Signal Level DetectorHigh Resolution and Bar Graph ModesGeneral DescriptionThe CS5334 and CS5335 are 2-channel, single +5V supply, pin compatable analog-to-digital converters for digital audio systems. The CS5334 and CS5335 perform sampling, analog-to-digital conversion and anti-alias fil-tering, generating 20-bit values for both left and right inputs in serial form. The output word rate can be up to 50 kHz per channel.The CS5334 and CS5335 use 4th-order, delta-sigma modulation with 128X oversampling followed by digital filtering and decimation, which removes the need for an external anti-alias filter. These ADCs use a differential architecture which provides excellent noise rejection.The CS5334 and CS5335 have a filter passband to 21.7kHz. The filter has linear phase, 0.0025 dB pass-band ripple, and >85 dB stopband rejection. An on-chip high pass filter is also included to remove DC offsets.ORDERING INFORMATION:Model Temp. Range Package Type CS5334-KS -10° to 70°C 20-pin Plastic SSOP CS5335-KS -10° to 70°C 20-pin Plastic SSOPCrystal Semiconductor Corporation NOV ’9620-Bit, Stereo A/D Converter for Digital AudioPUDGNDSDATA AGNDDIF1DIF0HP DEFEATCMOUTCS5334 CS5335This document contains information for a new product. CrystalSemiconductor reserves the right to modify this product without notice.Preliminary Product InformationSpecifications are subject to change without noticeANALOG CHARACTERISTICS (T A = 25°C; VA+ = VD+ = 5V; -1 dBFS Input Sinewave, 997 Hz;Fs = 48 kHz; MCLK = 12.288 MHz; SCLK = 3.072 MHz; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified; Logic 0 = 0V, Logic 1 = VD+)CS5334CS5335ParameterSymbolMin Typ Max Min Typ Max Units Resolution20--20--Bits Dynamic PerformanceDynamic RangeA-weightedTBD TBD 10097--TBD TBD 105102--dB dB Total Harmonic Distortion + Noise-1 dB -20 dB -60 dBTHD+N----90-77-37TBD TBD TBD ----95-82-42TBD TBD TBD dB dB dB Interchannel Phase Deviation -0.01--0.01-Degree Interchannel Isolation(dc to 20 kHz)-100--105-dB dc AccuracyInterchannel Gain Mismatch -0.05--0.05-dB Gain Error --±5--±5%Gain Drift -200--200-ppm/°C Offset Errorwith HPFHP defeat with CAL--0+/-100----0+/-100--LSB LSBAnalog InputInput Voltage Range (Differential)VIN 1.9 2.0 2.1 1.9 2.0 2.1Vrms Input Impedance ZIN-30--30-k ΩInput Bias Voltage- 2.2-- 2.2-V Power SuppliesPower Supply CurrentI A I DPower Down (I A +I D )---38250.2TBD TBD ----40250.2TBD TBD -mA mA mA Power DissipationNormal Power Down--3151.0TBD ---3251.0TBD -mW mW Power Supply Rejection Ratio-50--55-dBDIGITAL FILTER CHARACTERISTICS (T A = 25 °C; VA+ = VD+ = 5V ± 5%; Fs = 48 kHz)Parameter Symbol Min Typ Max Units Passband(Note 1)0.02-21.7kHz Passband Ripple--±0.0025dB Stopband(Note 1)26.3-6118kHz Stopband Attenuation(Note 2)85--dB Group Delay (Fs = Output Sample Rate)t gd-32/Fs-s Group Delay Variation vs. Frequency∆t gd--0µs High Pass Filter CharacteristicsFrequency Response:-3 dB(Note 1)-0.01 dB --0.920--HzHzPhase Deviation@ 20 Hz(Note 1)- 2.6-Degree Passband Ripple--0dB Notes: 1.Filter characteristic scales with output sample rate.2.The analog modulator samples the input at 6.144 MHz for an output sample rate of 48 kHz. There isno rejection of input signals which are multiples of the sampling frequency ( n x 6.144 MHz ±21.7kHzwhere n = 0,1,2,3...).DIGITAL CHARACTERISTICS (T A = 25 °C; VA+ = VD+ = 5V ± 5%)Parameter Symbol Min Typ Max Units High-Level Input Voltage V IH 2.4--V Low-Level Input Voltage V IL--0.8V High-Level Output Voltage at lo = -20 µA V OH(VD+)-1.0--V Low-Level Output Voltage at lo = 20 µA V OL--0.4V Input Leakage Current I in--10µAABSOLUTE MAXIMUM RATINGS (AGND = 0V, all voltages with respect to ground.)Parameter Symbol Min Typ Max Units DC Power Supply:VA+-0.3-+6.0V Input Current, Any Pin Except Supplies(Note 3)Iin--±10mA Analog Input Voltage(Note 4)V INA-0.7-(VA+)+0.7V Digital Input Voltage(Note 4)V IND-0.7-(VA+)+0.7V Ambient Temperature (power applied)T A-55-+125°C Storage Temperature T stg-65-+150°C Notes: 3.Any Pin except supplies. Transient currents of up to +/- 100 mA on the analog input pins will not cause SCR latch-up.4.The maximum over/under voltage is limited by the input current.WARNING:Operation at or beyond these limits may result in permanent damage to the device.Normal operation is not guaranteed at these extremes.SWITCHING CHARACTERISTICS(T A = 25 °C; VA+ = 5V ± 5%; Inputs: Logic 0 = 0V, Logic 1 = VA+ = VD+; C L = 20 pF)Parameter Symbol Min Typ Max Units Output Sample Rate F s 2.0-50kHz MCLK Period MCLK / LRCK = 256t clkw78-1953ns MCLK Low MCLK / LRCK = 256t clkl31--ns MCLK High MCLK / LRCK = 256t clkh31--ns MCLK Period MCLK / LRCK = 384t clkw52-1302ns MCLK Low MCLK / LRCK = 384t clkl20--ns MCLK High MCLK / LRCK = 384t clkh20--ns MCLK Period MCLK / LRCK = 512t clkw39-976ns MCLK Low MCLK / LRCK = 512t clkl15--ns MCLK High MCLK / LRCK = 512t clkh15--ns MASTER MODESCLK falling to LRCK (Note 5)t mslr-10-10ns SCLK falling to SDATA valid(Note 5)t sdo-10-35ns SCLK Duty cycle-50-% SCLK falling to Frame Valid(Note 5)t sfo-10-(Note 6)ns LRCK edge to OVFL Valid t ovfl-10-30ns LRCK edge to OVFL edge delay t ovfl-10-(Note 10)ns SLAVE MODELRCK duty cycle255075% SCLK Period t sclkw(Note 7)--ns SCLK Pulse Width Low(Note 8)t sclkl(Note 11)--ns SCLK Pulse Width High (Note 9)t sclkh50--ns SCLK falling to SDATA valid(Note 5)t dss--(Note 11)ns LRCK edge to MSB valid t lrdss--(Note 11)ns SCLK rising to LRCK edge delay(Note 12)t slr150--ns LRCK edge to rising SCLK setup time(Note 12)t slr2(Note 11)--ns SCLK falling to Frame delay t sfo--(Note 13)nsNotes: 5.SCLK rising for Mode 1. 6.1(1024)(F s)+ 30ns7.1(96)(F s)8.Pulse Width High for Mode 19.Pulse Width Low for Mode 110.1(512)(F s)+ 20ns11.1(512)(F s)+ 50ns12.SCLK Falling for Mode 113.1(384)(F s)+35nsSDATASCLK input (SLAVE mode)(SLAVE mode)LRCK inputtt OVFLSCLK to LRCK & SDATA - SLAVE modeFormat 2SCLK outputSDATALRCK outputOVFLSCLK to SDATA & LRCK - MASTER modeFormat 2SCLK output*SDATALRCK outputOVFLSCLK to SDATA & LRCK - MASTER modeFormat 0 and 1SDATASCLK input*(SLAVE mode)(SLAVE mode)LRCK inputOVFLSCLK to LRCK & SDATA - SLAVE modeFormat 0 & 1 SCLK*FRAMESCLK to Frame Delay*SCLK is inverted for Format 1***Figure 1. Typical Connection DiagramSYSTEM DESIGNThe CS5334 and CS5335 are 20-bit, 2-channel Analog-to-Digital Converters designed for digital audio applications. These devices use two one-bit delta-sigma modulators which simultaneously sample the analog input signals at 128 times the output sample rate (Fs). The resulting serial bit streams are digitally filtered, yielding a pair of 20-bit values. This technique yields nearly ideal conversion performance independent of input frequency and amplitude. The converter does not require difficult-to-design or expensive anti-alias filters and does not require external sample-and-hold amplifiers or a voltage reference. V ery few external components are required to support these ADCs. Normal power supply decoupling components and a resistor and capacitor on each input for anti-aliasing are all that’s required, as shown in Figure 1.An on-chip voltage reference provides for a dif-ferential input signal range of 2.0 Vrms. Output data is available in serial form, coded as 2’s complement, 20-bit numbers. Typical power consumption is 325 mW which can be reduced to 1.0 mW using the power-down feature.Master ClockThe master clock (MCLK) is the clock source for the delta-sigma modulator sampling and digi-tal filters. In Master Mode, the frequency of this clock must be 256× Fs. In Slave Mode, the mas-ter clock must be either 256×, 384× or 512× Fs.Table 1 shows some common master clock fre-quencies.SERIAL DATA INTERFACEThe CS5334 and CS5335 support three serial data formats, including I 2S, which are selected via the digital input format pins DIF0 and DIF1.The digital input format determines the relation-ship between the serial data, left/right clock and serial clock. Table 2 lists the three formats, along with the associated figure number. The serial data interface is accomplished via the serial data output, SDA TA, serial data clock, SCLK, and the left/right clock, LRCK.Serial DataThe serial data block consists of 20 bits of audiodata presented in 2’s-complement format with the MSB-first, followed by 4 bits of zero and 8Peak Signal Level, PSL, bits as shown in Fig-ure 2. The data is clocked from SDA TA by the serial clock and the channel is determined by the Left/Right clock.LRCK (kHz)MCLK (MHz)256 X 384 X 512 X328.192012.288016.384044.111.289616.934422.57924812.288018.432024.5760Table 1. Common Clock FrequenciesSDATA FRAME20 AudioFigure 2. Data Block and FrameDIF1DIF0FORMAT FIGURE 00030114102511power-down -Table 2. Digital Input FormatsSDATAFRAMESCLKLRCKMASTERSLAVE20-Bit Left Justified Data20-Bit Left Justified DataData Valid on Rising Edge of 64x SCLKData Valid on Rising Edge of SCLK MCLK equal to 256x F s MCLK equal to 256x, 384x or 512x F sFigure 3. Serial Data Format 0SDATAFRAMESCLKLRCKMASTERSLAVE20-Bit Left Justified Data20-Bit Left Justified DataData Valid on Falling Edge of 64x SCLK Data Valid on Falling Edge of SCLK MCLK equal to 256x F sMCLK equal to 256x, 384x or 512x F sFigure 4. Serial Data Format 1SDATAFRAMESCLKLRCK MASTERSLAVEI 2S 20-Bit DataI 2S 20-Bit DataData Valid on Rising Edge of 64x SCLK Data Valid on Rising Edge of SCLK MCLK equal to 256x F s MCLK equal to 256x, 384x or 512x F sFigure 5. Serial Data Format 2Serial ClockThe serial clock shifts the digitized audio data from the internal data registers via the SDA TA pin. SCLK is an output in Master Mode. Internal dividers will divide the master clock by 4 to generate a serial clock which is 64× Fs. In Slave Mode, SCLK is an input with a serial clock typically between 48× and 128× Fs. How-ever, the serial clock must be a minimum of 64×Fs to access the Peak Signal Level bits.Left / Right ClockThe Left/Right clock determines which channel, left or right, is to be output on SDA TA. Although the outputs for each channel are transmitted at different times, Left/Right pairs represent simul-taneously sampled analog inputs. In Master Mode, LRCK is an output whose frequency is equal to Fs. In Slave Mode, LRCK is an input whose frequency must be equal to the output sample rate, Fs.Master ModeIn Master mode, SCLK and LRCK are outputs which are internally derived from the Master Clock. Internal dividers will divide MCLK by 4 to generate a SCLK which is 64× Fs and by 256 to generate a LRCK which is equal to Fs. Master mode is only supported with a 256× master clock. The CS5334/5 is placed in the Master mode with a 47 kΩ pull-down resistor on the OVFL pin.Slave ModeLRCK and SCLK become inputs in SLA VE mode. LRCK must be externally derived from MCLK and be equal to Fs. The serial clock is typically between 64× and 128× Fs. A 48× Fs serial clock is possible though will not allow ac-cess to the Peak Signal Level bits. Master clock frequencies of 256×, 384× and 512× Fs are sup-ported. The ratio of the applied master clock to the left/right clock is automatically detected dur-ing power-up and internal dividers are set to gen-erate the appropriate internal clocks.Analog ConnectionsFigure 1 shows the analog input connections. The analog inputs are presented to the modula-tors via the AINR+/- and AINL+/- pins. Each analog input pin will accept a maximum of 1 Vrms centered at +2.2 V olt as shown in Fig-ure 6. Input signals can be AC or DC coupled and the CMOUT output may be used as a refer-ence for DC coupling. However, CMOUT is not buffered and the maximum current is 10 µA. The CS5334 and CS5335 sample the analog in-puts at 128×Fs, 6.144 MHz for a 48 kHz sample-rate. The digital filter rejects all noise above 26.3 kHz except for frequencies right around 6.144 MHz ± 21.7 kHz (and multiples of 6.144 MHz). Most audio signals do not have sig-nificant energy at 6.144 MHz. Nevertheless, a 150 Ω resistor in series with each analog input and a 2.2 nF capacitor across the inputs will at-tenuate any noise energy at 6.144 MHz, in addition to providing the optimum source imped-ance for the modulators. The use of capacitors which have a large voltage coefficient must be avoided since these will degrade signal linearity. NPO and COG capacitors are acceptable. If ac-tive circuitry precedes the ADC, it is recommended that the above RC filter is placed between the active circuitry and the AINR and AINL pins. The above example frequencies scale linearly with sample rate.3.6 V2.2 V0.78 V3.6 V2.2 V0.78 VCS5334CS5335AIN+AIN-Full Scale Input level= (AIN+) - (AIN-)= 5.67 VppFigure 6. Full Scale Input LevelsHigh Pass FilterThe operational amplifiers in the input circuitry driving the CS5334/5 may generate a small DC offset into the A/D converter. The CS5334 and CS5335 include a high pass filter after the deci-mator to remove any DC offset which could result in recording a DC level, possibly yielding "clicks" when switching between devices in a multichannel system. The high pass filter can be disabled with the HP DEFEA T pin. The high pass filter works by continuously subtracting a measure of the dc offset from the output of the decimation filter. If the HP DEFEA T pin is taken high during normal operation, the current value of the dc offset register is frozen and this dc offset will continue to be subtracted from the conversion result. This feature makes it possible to perform a system calibration by;1. removing the signal source (or grounding the input signal) at the input to the subsystem con-taining the CS5334/5,2. running the CS5334/5 with the HP DEFEA T pin low (high pass filter enabled) until the filter settles (approximately 1 second), and3. taking the HP DEFEA T pin high, disabling the high pass filter and freezing the stored dc offset.A system calibration performed in this way will eliminate offsets anywhere in the signal path be-tween the calibration point and the CS5334/5.The characteristics of the first-order high pass filter are outlined below for an output sample rate of 48 kHz. This filter response scales line-arly with sample rate.Frequency response:-3 dB @ 0.9 Hz-0.01 dB @ 20 Hz Phase deviation: 2.6 degrees @ 20 Hz Passband ripple:None INPUT LEVEL MONITORINGThe CS5334 and CS5335 include independent Peak Input Level Monitoring for each channel. The analog-to-digital converter continually moni-tors the peak digital signal for both channels, prior to the digital limiter, and records these val-ues in the Active registers. This information can be transferred to the Output registers by a high to low transition on the Peak Update pin (PU) which will also reset the Active register. The Ac-tive register contains the peak signal level since the previous peak update request.The 8-bit contents of the output registers are available in all interface modes and are present in the data block as shown in Figure 2. The monitoring function can be formatted to indicate either High Resolution Mode or Bar Graph Mode. The monitoring function is determined on power-up by the presence of a 47 kohm pull-down resistor on FRAME. The addition of a 47 kohm pull-down resistor on the FRAME pin sets the monitoring function to the Bar Graph mode.High Resolution ModeBits P7-P0 indicate the peak input level since the previous peak update (or low transition on the Peak Update pin). If the full scale input level is exceeded (Bit P7 high), bits P5-P0 represent the peak value up to 3 dB above full-scale in 1 dB steps. If the ADC input level is less than full-scale, bits P5-P0 represent the peak value from -60 dB to 0 dB of full scale in 1 dB steps. The PSL outputs are accurate to within 0.25 dB. Bit P6 provides a coarse means of determining an ADC input idle condition. Bit P7 indicates an ADC overflow condition, if the ADC input levelis greater than full-scale.P7 - Overrange0 - Analog input less than full-scale level1 - Analog input greater than full-scaleP6 - Idle channel0 - Analog input >-60 dB from full-scale1 - Analog input <-60 dB from full-scaleP5 to P0 - Peak Signal Level Bits (1 dB steps) Inputs <0 dB P5 - P00 dB000000-1 dB000001-2 dB000010-60 dB111100Inputs >0 dB P5 - P00 dB000000+1 dB000001+2 dB000010+3 dB000011Bar Graph ModeThis mode provides a decoded output format which indicates the peak Peak Signal Level in a "Bar Graph" format.Input Level P7 - P0Overflow111111110 dB to -3 dB01111111-3 dB to -6 dB00111111-6 dB to -10 dB00011111-10 dB to -20 dB00001111-20 dB to -30 dB00000111-30 dB to -40 dB00000011-40 dB to -60 dB00000001< - 60 dB00000000OverflowOverflow indicates analog input overrange, for both the Left and Right channels, since the last update request on the Peak Update pin. A value of 1 indicates an overrange condition. The left channel information is output on OVFL during the left channel portion of LRCK. The right channel information is available on OVFL during the right channel portion of LRCK. InitializationUpon initial power-up, the digital filters and delta-sigma modulators are reset and the internal voltage reference is powered down. The CS5334/5 will remain in the power-down mode until valid clocks are presented. A valid MCLK is required to exit power-down in Master Mode. However, in Slave Mode, MCLK and LRCK of the proper ratio are required to exit power-down. MCLK occurrences are also counted over one LRCK period to determine the MCLK / LRCK frequency ratio in Slave Mode. Power is then ap-plied to the internal voltage reference, the analog inputs will move to approximately 2.2V and out-put clocks will begin (Master Mode only). This process requires 32 periods of LRCK and is fol-lowed by the initialization sequence. Initialization with High Pass Filter Enabled 28,672 LRCK cycles are required for the initiali-zation sequence with the high pass filter enabled. This time is dominated by the settling time re-quired for the high pass filter.Initialization and Internal Calibration with High Pass Filter DisabledIf the HP DEFEA T pin is high (high pass filter disabled) during the initialization sequence, the CS5334/5 will perform an internal dc calibration by:1. disconnecting the internal ADC inputs from the input pins,2. connecting the (differential) ADC inputs to acommon reference voltage,DS237PP2113. running the high pass filter with a fast settling time constant,4. freezing the dc offset register, and5. reconnecting the internal ADC inputs to the input pins.This procedure takes 4,160 cycles of LRCK. Unlike the system calibration procedure de-scribed in the High Pass Filter section, a dc calibration performed during start-up will only eliminate offsets internal to the CS5334/5, and should result in output codes which accurately reflect the differential dc signal at the pins.Power-DownThe CS5334 and CS5335 have a power-down mode wherein typical consumption drops to 1.0 mW. This is initiated when a loss of clock is de-tected (either LRCK or MCLK in Slave Mode orDIF0 / DIF1 are at a logic 1. The initialization sequence will begin whenever valid clocks arerestored. If the MCLK / LRCK frequency ratio changes during power-down, the CS5334/5 will adapt to these new operating conditions. How-ever, only the RST method of power-down will include the Master/Slave decision in the initiali-zation sequence.Grounding and Power Supply DecouplingAs with any high resolution converter, the CS5334 and CS5335 require careful attention to power supply and grounding arrangements to op-timize performance. Figure 1 shows the recommended power arrangements with V A+ connected to a clean +5 volt supply. VD+ should be derived from V A+ through a 2 ohm resistor. VD+ should not be used to power additional digital circuitry. All mode pins which require VD+ should be connected to pin 6 of the CS5334/5. All mode pins which require DGND should be connected to pin 5 of the CS5334/5. AGND and DGND, Pins 4 and 5, should be con-nected together at the CS5334/5. DGND for the CS5334/5 should not be confused with the ground for the digital section of the system. The CS5334/5 should be positioned over the analog ground plane near the digital / analog ground plane split. The analog and digital ground planes must be connected elsewhere in the system. The CS5334/5 evaluation board, CDB5334/5, demon-strates this layout technique. This technique minimizes digital noise and insures proper power supply matching and sequencing. Decoupling ca-pacitors should be located as near to theCS5334/5 as possible.12DS237PP2Digital FilterFigures 7-10 show the performance of thedigital filter included in the CS5334/5. Allplots are normalized to Fs. Assuming a samplerate of 48 kHz, the 0.5 frequency point on theplot refers to 24 kHz. The filter frequency re-sponse scales precisely with the sample rate.Figure 7. CS5334/5 Digital Filter Stopband Rejection Figure 9. CS5334/5 Digital Filter Passband RippleFigure 8. CS5334/5 Digital Filter Transition Band Figure 10.CS5334/5 Digital Filter Transition Band DS237PP213PIN DESCRIPTIONSPower Supply ConnectionsV A+ - Positive Analog Power, Pin 3.Positive analog supply. Nominally +5 volts.VD+ - Positive Digital Power, Pin 6.Positive digital supply. Nominally +5 volts.AGND - Analog Ground, Pin 4.Analog ground reference.DGND - Digital Ground, Pin 5.Digital ground reference.Analog InputsAINR-, AINR+ - Differential Right Channel Analog Input, Pin 14 and Pin 13.Analog input connections of the right channel differential inputs. Typically 2 Vrms differential (1Vrms for each input pin) for a full-scale analog input signal.AINL-, AINL+ - Differential Left Channel Analog Input, Pin 16 and Pin 17.Analog input connections of the left channel differential inputs. Typically 2 Vrms differential (1Vrms for each input pin) for a full-scale analog input signal.Analog OutputsCMOUT - Common Mode Output, Pin 15.This output, nominally 2.2V , can be used to bias the analog input circuitry to the common mode voltage of the CS5334/5.High Pass Filter Defeat HP DEFEATDIF0 Digital Interface Format 0OverFlow OVFLDIF1 Digital Interface Format 1Analog Power VA+RST Reset Analog Ground AGNDAINL+ Non-Inverting Left Channel Input Digital Ground DGNDAINL- Inverting Left Channel Input Digital Power VD+CMOUT Common Mode Output Master Clock MCLKAINR- Inverting Right Channel Input Serial Data Clock SCLKAINR+ Non-Inverting Right Channel Input Serial Data Output SDATALRCK Left/ Right Clock Frame Signal FRAME PUPeak Update14DS237PP2Digital InputsMCLK - Master Clock, Pin 7.Clock source for the delta-sigma modulator sampling and digital filters.In Master Mode, the frequency of this clock must be 256× the output sample rate, Fs.In Slave Mode, the frequency of this clock must be either 256×, 384× or 512× Fs.DIF0, DIF1 - Digital Interface Format, Pins 19 and 20.These two pins select one of 3 digital interface formats or power-down. The format determines the relationship between SCLK, LRCK and SDA TA. The formats are detailed in Figures 3-5.A low logic level on this pin activates Reset.HP DEFEAT - High Pass Filter Defeat, Pin 1.A high logic level on this pin disables the digital high pass filter. A low logic level on this pinenables the high pass filter.PU - Peak Update, Pin 11.Transfers the Peak Signal Level contents of the Active Registers to the Output Registers on a high to low transition on this pin. This transition will also reset the Active register.Digital Inputs / OutputsLRCK - Left/Right Clock, Pin 12.LRCK determines which channel, left or right, is to be output on SDA TA. The relationship between LRCK, SCLK and SDA TA is controlled by DIF0 and DIF1. Although the outputs for each channel are transmitted at different times, Left/Right pairs represent simultaneously sampled analog inputs. In Master Mode, LRCK is an output clock whose frequency is equal to the output sample rate, Fs. In Slave Mode, LRCK is an input clock whose frequency must be equal to Fs.SCLK - Serial Data Clock, Pin 8.Clocks the individual bits of the serial data out from the SDA TA pin. The relationship between LRCK, SCLK and SDA TA is controlled by DIF0 and DIF1.In Master Mode, SCLK is an output clock with a frequency of 64x the output sample rate, Fs.In Slave Mode, SCLK is an input.Digital OutputsSDATA - Serial Data Output, Pin 9.Two’s complement MSB-first serial data of 20 bits is output on this pin. Included in the serial data output is the 8-bit Input Signal Level Bits. The data is clocked out via the SCLK clock and the channel is determined by LRCK. The relationship between LRCK, SCLK and SDA TA is controlled by DIF0 and DIF1.DS237PP215OVFL - Overflow, Pin 2.Overflow indicates analog input overrange, for both the Left and Right channels, since the last update request on the PEAK UPDA TE (PU) pin. A value of 1 in the register indicates an overrange condition. The left channel information is output on OVFL during the left channel portion of LRCK. The right channel information is available on OVFL during the right channel portion of LRCK. The registers are updated with a high to low transition on the PEAK UPDA TE pin. A 47 kohm pull-down resistor on this pin will set the CS5334/5 in Master Mode. FRAME - Frame Signal, Pin 10.Frames the Peak Signal Level (PSL) Bits. FRAME goes high coincident with the leading edge of the first PSL bit and falls coincident with the trailing edge of the last PSL bit as shown in Figures 3-5. A 47 kohm pull-down resistor on this pin will set the Peak Signal Level Monitoring format to "Bar Graph" mode.PARAMETER DEFINITIONSDynamic RangeThe ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made with a -60dBFs signal. 60dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels.Total Harmonic Distortion + Noise (THD+N)The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified band width (typically 10 Hz to 20 kHz), including distortion components.Expressed in decibels. Measured at -1 and -20 dBFs as suggested in AES17-1991 Annex A. Frequency ResponseA measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplituderesponse at 1 kHz. Units in decibels.Interchannel IsolationA measure of crosstalk between the left and right channels. Measured for each channel at theconverter’s output with no signal at the input under test and a full-scale signal applied to the other channel. Units in decibels.Interchannel Gain MismatchThe gain difference between left and right channels. Units in decibels.Gain ErrorThe deviation from the nominal full-scale analog input for a full-scale digital output.16DS237PP2。
ANALOG DEVICES ADL5534 说明书
20 MHz to 500 MHzDual IF AmplifierADL5534 Rev. 0Information furnished by Analog Devices is believed to be accurate and reliable. However, noresponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners. O ne Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.FEATURESFixed gain of 20 dBOperation up to 500 MHzInput/output internally matched to 50 ΩIntegrated bias control circuitOIP3 of 40 dBm at 70 MHzP1dB of 20.4 dBm at 70 MHzNoise figure of 2.5 dB at 70 MHz Temperature and power supply stable Single 5 V power supply FUNCTIONAL BLOCK DIAGRAM9NC12CLIN1 NCNC = NO CONNECT410NC NC211NCNC36836-1 NC13RFOUT16RFIN1RFOUT24NCNC5NCCLIN2RFIN2Figure 1.GENERAL DESCRIPTIONThe ADL5534 contains two broadband, fixed-gain, linear amplifiers and operates at frequencies up to 500 MHz. The device can be used in a wide variety of equipment, including cellular, satellite, broadband, and instrumentation equipment. The ADL5534 has a fixed gain of 20 dB, which is stable over frequency, temperature, power supply, and from device-to-device. The amplifiers are single-ended and internally matched to 50 Ω. Only input/output ac-coupling capacitors, power supply decoupling capacitors, and an external bias inductor are required for operation of each amplifier. The ADL5534 is fabricated on a GaAs HBT process. The device is packaged in a 16-lead 5 mm × 5 mm LFCSP that uses an exposed paddle for excellent thermal impedance. The ADL5534 consumes 98 mA of current per amplifier on a single 5 V supply, and is fully specified for operation from −40°C to +85°C.A similar amplifier, ADL5531 (available from Analog Devices, Inc.) is the 20 dB gain single-channel version. Fully populated evaluation boards for both the ADL5531 and ADL5534 are available.ADL5534Rev. 0 | Page 2 of 16TABLE OF CONTENTSFeatures .............................................................................................. 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Typical Scattering Parameters ..................................................... 4 Absolute Maximum Ratings ............................................................ 5 ESD Caution .................................................................................. 5 Pin Configuration and Function Descriptions ............................. 6 Typical Performance Characteristics ............................................. 7 Basic Connections .............................................................................9 Using Baluns to Combine Both Amplifiers Into a SingleAmplifier ..................................................................................... 10 ADC Driving Application ......................................................... 11 Soldering Information and Recommended PCB LandPattern .......................................................................................... 12 Evaluation Board ............................................................................ 13 Outline Dimensions ....................................................................... 15 Ordering Guide .. (15)REVISION HISTORY6/08—Revision 0: Initial VersionADL5534SPECIFICATIONSVPOS = 5 V and T A = 25°C, unless otherwise noted.Table 1.Parameter Conditions Min Typ Max Unit OVERALL FUNCTIONFrequency Range 20 500 MHz Gain (S21) 190 MHz 20.4 dB Input Return Loss (S11) 190 MHz −18.0 dB Output Return Loss (S22) 190 MHz −29.0 dB Reverse Isolation (S12) 190 MHz −23.0 dB FREQUENCY = 70 MHzGain 21.0 dB vs. Frequency ±5 MHz ±0.04 dB vs. Temperature −40°C ≤ T A ≤ +85°C ±0.20 dB vs. Supply 4.75 V to 5.25 V ±0.20 dB Output 1 dB Compression Point 20.4 dBm Output Third-Order Intercept ∆f = 1 MHz, output power (P OUT) = 0 dBm per tone 40.0 dBm Noise Figure 2.5 dB Device-to-Device Isolation Measured at output with input applied to alternate device −46.0 dB FREQUENCY = 190 MHzGain 19.520.4 21 dB vs. Frequency ±50 MHz ±0.15 dB vs. Temperature −40°C ≤ T A ≤ +85°C ±0.20 dB vs. Supply 4.75 V to 5.25 V ±0.17 dB Output 1 dB Compression Point 20.6 dBm Output Third-Order Intercept ∆f = 1 MHz, output power (P OUT)= 0 dBm per tone 39.0 dBm Noise Figure 2.7 dB Device-to-Device Isolation Measured at output with input applied to an alternate device −38.0 dB FREQUENCY = 380 MHzGain 19.019.8 20.5 dB vs. Frequency ±50 MHz ±0.18 dB vs. Temperature −40°C ≤ T A ≤ +85°C ±0.22 dB vs. Supply 4.75 V to 5.25 V ±0.16 dB Output 1 dB Compression Point 20.4 dBm Output Third-Order Intercept ∆f = 1 MHz, output power (P OUT)= 0 dBm per tone 36.0 dBm Noise Figure 3.0 dB Device-to-Device Isolation Measured at output with input applied to an alternate device −34.0 dB POWER INTERFACE RFOUT1, RFOUT2 pinsSupply Voltage 4.75 5 5.25 V Supply Current Per amplifier 98 110 mA vs. Temperature −40°C ≤ T A ≤ +85°C ±15 mA Power Dissipation 0.5 WRev. 0 | Page 3 of 16ADL5534Rev. 0 | Page 4 of 16TYPICAL SCATTERING PARAMETERSVPOS = 5 V and T A = 25°C; the effects of the test fixture have been de-embedded up to the pins of the device. Table 2.Freq. (MHz) S11 S21 S12 S22Magnitude (dB) Angle (°) Magnitude (dB) Angle (°) Magnitude (dB) Angle (°) Magnitude (dB) Angle (°) 20 −22.72 −102.04 21.79 174.78 −24.08 5.82 −18.56 −42.21 50 −20.40 −138.34 21.07 171.81 −23.40 6.92 −21.33 −71.17 100 −19.83 −160.87 20.66 169.90 −23.11 7.81 −25.56 −90.45 150 −19.95 −170.03 20.51 167.16 −23.01 9.36 −27.64 −95.94 200 −20.29 −174.24 20.39 164.06 −22.93 11.42 −27.78 −94.45 250 −20.72 −176.35 20.27 160.68 −22.85 13.45 −26.69 −91.22 300 −20.93 −175.04 20.16 157.31 −22.77 15.66 −24.58 −89.94 350 −21.06 −174.10 20.01 153.74 −22.69 17.74 −22.78 −90.89 400 −21.43 −171.87 19.85 150.30 −22.61 20.07 −20.76 −91.14 450 −21.58 −168.25 19.68 146.82 −22.51 22.24 −18.97 −92.39 500 −21.75 −163.79 19.45 142.72 −22.36 24.88 −17.10 −92.91ADL5534Rev. 0 | Page 5 of 16ABSOLUTE MAXIMUM RATINGSTable 3.Parameter RatingSupply Voltage on RFOUT1, RFOUT2 5.5 VInput Power on RFIN1, RFIN2 10 dBmInternal Power Dissipation (Paddle Soldered) 900 mWθJA (Junction-to-Air) 54°C/WMaximum Junction Temperature 150°COperating Temperature Range −40°C to +85°C Storage Temperature Range−65°C to +150°CStresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stressrating only; functional operation of the device at these or anyother conditions above those indicated in the operationalsection of this specification is not implied. Exposure to absolutemaximum rating conditions for extended periods may affectdevice reliability.ESD CAUTIONADL5534Rev. 0 | Page 6 of 16PIN CONFIGURATION AND FUNCTION DESCRIPTIONS9NC12CLIN1NC10NC NC 11NC NC 06836-002NC 3R F O U T 16R F I N 1R F O U T 24N CN C 5N CC L I N 2R F I N 2Figure 2. Pin ConfigurationTable 4. Pin Function DescriptionsPin No.Mnemonic Description1, 2, 3, 4, 6, 9, 10, 11, 14, 15 NC No Connect. 5, 16 RFIN2, RFIN1 RF Input. Requires a dc blocking capacitor. Use a 10 nF capacitor for normal operation.7, 12 CLIN2, CLIN1 A 1 nF capacitor connected from Pin 7 to ground and Pin12 to ground provides decoupling for the on-board linearizer.8, 13RFOUT2, RFOUT1RF Output and Bias. DC bias is provided to this pin through an inductor. A 470 nH inductor is recommended for normal operation. The RF path requires a dc blocking capacitor. Use a 10 nF capacitor for normal operation.Exposed PaddleGND. Solder this paddle to a low impedance ground plane.ADL5534Rev. 0 | Page 7 of 16TYPICAL PERFORMANCE CHARACTERISTICS0246810121416182022050100150200250300350400450500121518212427303336394245P 1d B A N D O I P 3 (d B m )06836-003FREQUENCY (MHz)N O I S E F I G U R E A N D G A I N (d B )Figure 3. Noise Figure, Gain, P1dB, and OIP3 vs. Frequency 19.019.219.419.619.820.020.220.420.620.821.021.221.45010015020025030035040045050006836-004FREQUENCY (MHz)G A I N (d B )Figure 4. Gain vs. Frequency and Temperature–35–30–25–20–15–10–5601001401802202603003403804204602050006836-005FREQUENCY (MHz)S –P A R A M E T E R S (d B )Figure 5. Input Return Loss (S11), Output Return Loss (S22), and ReverseIsolation (S12) vs. Frequency19.019.520.020.521.021.522.022.523.0262830323436384042O I P 3 (d B m )06836-006FREQUENCY (MHz)P 1d B (d B m )Figure 6. P1dB and OIP3 vs. Frequency and Temperature–4–224681012141618–62006836-007P OUT (dBm)O I P 3 (d B m )Figure 7. OIP3 vs. Output Power and Frequency1.01.52.02.53.03.54.04.55.005010015020025030035040045050006836-008FREQUENCY (MHz)N O I S E F I G U R E (d B )Figure 8. Noise Figure vs. Frequency and TemperatureADL5534Rev. 0 | Page 8 of 1610203040506037.037.838.639.440.241.041.806836-009OIP3 (dBm)P E R C E N T A G E (%)Figure 9. OIP3 Distribution at 190 MHz010203040501006070809006836-010P1dB (dBm)P E R C E N T A G E (%)19.019.419.820.220.621.021.421.8Figure 10. P1dB Distribution at 190 MHz19.820.020.220.420.620.821.01020304050706006836-012GAIN (dB)P E R C E N T A G E (%)Figure 11. Gain Distribution at 190 MHz–55–50–45–40–35–30–25601001401802202603003403804204602050006836-011FREQUENCY (MHz)I N P U T T O A L T E R N A T E O U T P U T I S O L A T I O N (d B )Figure 12. Device-to-Device Isolation vs. Frequency2.02.22.42.62.83.03.23.43.63.84.0050100150200250300350400450500FREQUENCY (MHz)06836-013N O I S E F I G U R E (d B )Figure 13. Noise Figure vs. Frequency at 25°C, Multiple Devices Shown506070809010011012013014015006836-014TEMPERATURE (°C)S U P P L Y C U R R E N T (m A )Figure 14. Supply Current vs. Temperature and Supply VoltageADL5534Rev. 0 | Page 9 of 16BASIC CONNECTIONS06836-015Figure 15. Basic ConnectionsTable 5. Recommended Components for Basic ConnectionsFrequencyC1, C2, C3, C4, C7, C8 L1, L2 C5, C6 C9, C10 20 MHz to 500 MHz10 nF470 nH1 nF1 μFThe basic connections for operating the ADL5534 are shown in Figure 15. Recommended components are listed in Table 5. The inputs and outputs should be ac-coupled with appropriately sized capacitors (device characterization was performed with 10 nF capacitors). DC bias is provided to the amplifier via the L1 and L2 inductors connected to the RFOUT1 and RFOUT2 pins. The recommended inductors for L1 and L2 are Coilcraft, 1008CS-471XJLC or equivalent. The bias voltage should be decoupled using 10 nF and 1 μF capacitors. A bias voltage of 5 V is required.ADL5534Rev. 0 | Page 10 of 1606836-016Figure 16. Connections for Operating as a Balanced AmplifierUSING BALUNS TO COMBINE BOTH AMPLIFIERS INTO A SINGLE AMPLIFIERThe ADL5534 is ideal for use in a balanced amplifier confi-guration. To accomplish this, flux-coupled RF transformers with a 2:1 impedance ratio can be used for wide band operation. Alternatively, a balun can be constructed using lumped element components for operation over a narrow frequency range. Figure 16 shows the necessary connections for configuring the ADL5534 for operation as a balanced amplifier. Figure 17 shows the performance of the ADL5534 operating in a balanced configuration.010203040506070809051015202530354045O I P 2 (d B m )06836-017FREQUENCY (MHz)G A I N , N O I S E F I G U R E , P 1d B , O I P 3 (d B , d B m )Figure 17. Performance of the ADL5534 Operating in BalancedConfiguration06836-018Figure 18. Narrow-Band IF Sampling Solution for Unbuffered ADCADC DRIVING APPLICATIONThe ADL5534 is a high linearity, fixed gain IF amplifier suitable for use as an ADC driver. The ADL5534 has a differential input and output impedance of 100 Ω. A flux-coupled RF transformer with a 2:1 impedance ratio was used to perform the single-ended-to-differential conversion at the input of the ADL5534. The interface between the ADL5534 and the AD9640 is a third-order low pass filter presenting a 100 Ω differential impedance to the source and load. The ADL5534 must be ac-coupled to prevent dc bias from entering the inputs of the ADC. Capacitors of 100 pF were chosen to reduce any low frequency noise coming from the ADL5534 and provide dc blocking. The measured results for this interface shows 0.5 dB insertion loss for a 20 MHz bandwidth centered around 92 MHz. The wideband response for the interface is shown in Figure 19. The single-tone results in Figure 20 show an SNR of 69.3 dB and an SFDR of 82 dBc. The two-tone results in Figure 21 show an IMD3 of −80.5 dBc and an SFDR of 78 dBc.06836-019FREQUENCY (MHz)N O R M A L I Z E D L O S S (d B )–45–40–35–30–25–20–15–10–50550100150200250300350400Figure 19. Measured Frequency Response of ADC interfacein Figure 18(d B F S )FREQUENCY (MHz)06836-020SNR = 69.334dBc SFDR = 82.267dBcNOISE FLOOR = –109.519dBFUND = –1.05dBFs SECOND = –82.262dBcTHIRD = –88.688dBc 61218243036424854600–15–30–45–60–75–90–105–120–135Figure 20. Measured Single-Tone Performance of the Circuit in Figure 18(d B F S )FREQUENCY (MHz)06836-021SFDR =78.267dBcNOISE FLOOR =–110.131dB FUND 1= –7.181dBFsFUND 2= –7.191dBFsIMD (2F1 –F2)= –80.538dBcIMD (2F2 –F1)= –82.086dBc 61218243036424854600–15–30–45–60–75–90–105–120–135Figure 21. Measured Two-Tone Performance of the Circuit in Figure 18SOLDERING INFORMATION AND RECOMMENDED PCB LAND PATTERNFigure 22 shows the recommended land pattern for ADL5534. To minimize thermal impedance, the exposed paddle on the package underside should be soldered down to a ground plane. If multiple ground layers exist, they should be stitched together using vias. Pin 1 to Pin 4, Pin 6, Pin 9 to Pin 11, and Pin 14 to Pin 15 can be left unconnected, or can be connected to ground. Connecting these pins to ground improves device-to-device isolation and slightly enhances thermal impedance. For more information on land pattern design and layout, refer to the AN-772 Application Note , A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP).06836-022Figure 22. Recommended Land PatternEVALUATION BOARDFigure 23 shows the schematic for the ADL5534 evaluation board. The board is powered by a single 5 V supply. The components used on the board are listed in Table 6.Transformers (T1 and T2) are provided so the ADL5534 can be configured as a balanced amplifier. Applying 5 V to VPOS biases the amplifier corresponding to RFIN1 and RFOUT1. Applying 5 V to VPOS1 biases the amplifiercorresponding to RFIN2 and RFOUT2. To bias both amplifiers from a single supply, connect 5 V to VPOS or VPOS1 and attach a jumper across W3.06836-023Figure 23. Evaluation Board SchematicTable 6. Evaluation Board Configuration OptionsComponent DescriptionDefault Condition C1, C2, C3, C4 AC coupling capacitors10 nF, Size 0402 C5, C6Provides decoupling for the on-board linearizer1 nF, Size 0603 C11, C12, C13, C14, C15, C16 Optional components used for configuring ADL5534 as a balanced amplifier Open, Size 0402C9, C10 Power-supply decoupling capacitors 1 μF, Size 0603 C7, C8Power-supply decoupling capacitors10 nF, Size 0603 R1, R2, R3, R4, R5, R6, R7, R8 Optional components used for configuring ADL5534 as a balanced amplifier Open, Size 0603 T1, T2T1 and T2 are 50 Ω to100 Ω impedance transformers used to configure the ADL5534 as a balanced amplifier; T1 and T2 are used to present a 100 Ω differential impedance to the ADL5534 Installed (Mini-Circuits® ADT2-1T-1P+) L1, L2DC bias inductor470 nH, Size 1008 VPOS, GND, VPOS1, GND1 Clip-on terminals for power supplyVPOS, VPOS1; red GND, GND1; black W1, W2 2-pin jumper for connection of ground and supply via cable W1, W2 W32-pin jumper used to connect VPOS to VPOS1W306836-024Figure 24. Evaluation Board Layout (Top)06836-025Figure 25. Evaluation Board Layout (Bottom)COMPLIANT TO JEDEC STANDARDS MO-220-VHHB010606-0OUTLINE DIMENSIONSCOPLANARITY0.08PLANEFigure 26. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]5 mm × 5 mm Body, Very Thin QuadCP-16-6Dimensions shown in millimetersORDERING GUIDEModel Temperature Range Package Description Package Option Ordering QuantityADL5534ACPZ-R71−40°C to +85°C 16-Lead LFCSP_VQ, 7” Tape and Reel CP-16-6 1500 ADL5534ACPZ-R21−40°C to +85°C 16-Lead LFCSP_VQ, 7” Tape and Reel CP-16-6 250ADL5534-EVALZ 1Evaluation Board 11Z = RoHS Compliant Part.NOTES©2008 Analog Devices, Inc. All rights reserved. Trademarks andregistered trademarks are the property of their respective owners.D06836-0-6/08(0)。
MPC5534AVZ66资料
Freescale Semiconductor Data Sheet: Product PreviewDocument Number: MPC5534Rev. 0, 06/2006Contents©Freescale Semiconductor, Inc., 2006. All rights reserved.• Preliminary—Subject to Change Without NoticeThis document contains information on a new product. Specifications and information herein are subject to change without notice.This document provides electrical specifications, pin assignments, and package diagrams for the MPC5534 microcontroller device. For functional characteristics, refer to the MPC5534 Microcontroller Reference Manual .1OverviewThe MPC5534 microcontroller (MCU) is a member of the MPC5500 family of microcontrollers based on the PowerPC™ Book E architecture. This family of parts contains many new features coupled with highperformance CMOS technology to provide substantial reduction of cost per feature and significant performance improvement over the MPC500 family.The host processor core of this device is compatible with the PowerPC Book E architecture. It is 100% user mode compatible (with floating point library) with the classic PowerPC instruction set. The Book E architecture has enhancements that improve the PowerPC architecture’s fit in embedded applications. This core also has additional instructions, including digital signal processing (DSP) instructions, beyond the classic1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 43.1Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 43.2Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . 53.3Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83.4EMI (Electromagnetic Interference) Characteristics 83.5ESD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 93.6VRC/POR Electrical Specifications. . . . . . . . . . . . . 93.7Power Up/Down Sequencing. . . . . . . . . . . . . . . . . 103.8DC Electrical Specifications. . . . . . . . . . . . . . . . . . 123.9Oscillator & FMPLL Electrical Characteristics. . . . 193.10eQADC Electrical Characteristics . . . . . . . . . . . . . 203.11H7Fb Flash Memory Electrical Characteristics . . . 223.12AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 233.13AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254Mechanicals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454.1Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454.2Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . 465Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49MPC5534 Microcontroller Data Sheetby:Microcontroller DivisionMPC5534 Microcontroller Data Sheet, Rev. 0Preliminary—Subject to Change Without NoticeOverviewFreescale Semiconductor2PowerPC instruction set. This family of parts contains many new features coupled with high performance CMOS technology to provide significant performance improvement over the MPC565.The host processor core of the MPC5534 also includes an instruction set enhancement allowing variable length encoding (VLE). This allows optional encoding of mixed 16- and 32-bit instructions. With this enhancement, it is possible to achieve significant code size footprint reduction.The MPC5534 has a single level of memory hierarchy consisting of 64-Kbyte on-chip SRAM and 1Mbyte of internal Flash memory. Both the SRAM and the Flash memory can hold instructions and data. The External Bus Interface has been designed to support most of the standard memories used with the MPC5xx family. The MPC5534 does not support arbitration between itself and other masters on the external bus. It must be either the only master on the external bus or act as a slave-only device.The complex I/O timer functions of the MPC5534 are performed by an Enhanced Time Processor Unit engine (eTPU). The eTPU engine controls 32 hardware channels. The eTPU has been enhanced over the MPC500 family’s TPU by providing 24-bit timers, double action hardware channels, variable number of parameters per channel, angle clock hardware, and additional control and arithmetic instructions. The eTPU can be programmed using a high-level programming language.The less complex timer functions of MPC5534 are performed by the enhanced Modular Timer System (eMIOS). The eMIOS 24 hardware channels are capable of single action, double action, pulse width modulation (PWM) and modulus counter operation. Motor control capabilities include edge-aligned and center-aligned PWM.Off-chip communication is performed by a suite of serial protocols including CANs, enhanced SPIs (Deserialize/Serialize Peripheral Interface) and SCIs. The DSPIs support pin reduction through hardware serialization and deserialization of timer channels and GPIO signals.The MPC5534 MCU has an on-chip 40-channel Enhanced Queued Dual Analog-to-Digital Converter (eQADC), with 5V conversion range.The System Integration Unit (SIU) performs several chip-wide configuration functions. Pad configuration and General-Purpose Input and Output (GPIO) are controlled from the SIU. External interrupts and reset control are also found in the SIU. The Internal Multiplexer sub-block (IMUX) provides multiplexing of eQADC trigger sources, daisy chaining the DSPIs and external interrupt signal multiplexing.Ordering InformationMPC5534 Microcontroller Data Sheet, Rev. 0Preliminary—Subject to Change Without NoticeFreescale Semiconductor32Ordering InformationFigure 1. MPC5500 Family Part Number ExampleTable 1. Orderable Part NumbersFreescale Part Number 11All devices are PPC5534, rather than MPC5534, until the product qualifications. Not all configurations will be available in the PPC parts.DescriptionSpeed (MHz)Max Speed 2(MHz) (f MAX )2Speed is the nominal maximum frequency. Max Speed is the maximum speed allowed including any frequency modulation.Temperature MPC5534MVZ80MPC5534 Lead free 324 package 8080-40° C to 125° C MPC5534MZQ80MPC5534 Lead 324 package 8080-40° C to 125° C MPC5534MVM80MPC5534 Lead free 208 package 8080-40° C to 125° C MPC5534MVF80MPC5534 Lead 208 package 8080-40° C to 125° C MPC5534MVZ66MPC5534 Lead free 324 package 6666-40° C to 125° C MPC5534MZQ66MPC5534 Lead 324 package 6666-40° C to 125° C MPC5534MVM66MPC5534 Lead free 208 package 6666-40° C to 125° C MPC5534MVF66MPC5534 Lead 208 package 6666-40° C to 125° C MPC5534MVZ40MPC5534 Lead free 324 package 4040-40° C to 125° C MPC5534MZQ40MPC5534 Lead 324 package 4040-40° C to 125° C MPC5534MVM40MPC5534 Lead free 208 package 4040-40° C to 125° C MPC5534MVF40MPC5534 Lead 208 package4040-40° C to 125° CM PC M 80R2Qualification StatusCore CodeDevice NumberTemperature Range Package IdentifierOperating Frequency (MHz)Tape and Reel StatusTemperature Range M = -40° C to 125° C A = -55° C to 125° CPackage IdentifierVF = 208MAPBGA SnPb VM = 208MAPBGA Pb-free ZQ = 324PBGA SnPb VZ = 324PBGA Pb-freeOperating Frequency 40 = 40MHz 66 = 66MHz 80 = 80MHzNote: Not all options are available on all devices. Refer to T able 1.Tape and Reel Status R2 = Tape and Reel (blank) = Trays Qualification Status P = Pre Qualification M = Full Spec Qualified5534ZQMPC5534 Microcontroller Data Sheet, Rev. 0Preliminary—Subject to Change Without NoticeElectrical CharacteristicsFreescale Semiconductor43Electrical CharacteristicsThis section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MCU.3.1Maximum RatingsTable 2. Absolute Maximum Ratings 1Num CharacteristicSymbol Min Max 2Unit 1 1.5V Core Supply Voltage 3V DD – 0.3 1.7V 2Flash Program/Erase Voltage V PP – 0.3 6.5V 3Flash Core Voltage V DDF – 0.3 1.7V 4Flash Read Voltage V FLASH – 0.3 4.6V 5SRAM Standby Voltage V STBY – 0.3 1.7V 6Clock Synthesizer Voltage V DDSYN – 0.3 4.6V 7 3.3V I/O Buffer VoltageV DD33–0.3 4.6V 8Voltage Regulator Control Input Voltage V RC33–0.3 4.6V 9Analog Supply Voltage (reference to V SSA )V DDA – 0.3 5.5V 10I/O Supply Voltage (Fast I/O Pads) 4V DDE – 0.3 4.6V 11I/O Supply Voltage (Slow/Medium I/O Pads) 4V DDEH – 0.3 6.5V12DC Input Voltage 5VDDEH powered I/O Pads, except eTPUB15 and SINB (DSPI_B_SIN)VDDEH powered I/O Pads (eTPUB15 and SINB)VDDE powered I/O Pads V IN–1.06–0.37–1.066.586.584.69V13Analog Reference High Voltage (reference to VRL)V RH – 0.3 5.5V 14VSS Differential Voltage V SS – V SSA – 0.10.1V 15VDD Differential Voltage V DD – V DDA – V DDA V DD V 16V REF Differential Voltage V RH – V RL – 0.3 5.5V 17V RH to VDDA Differential Voltage V RH – V DDA – 5.5 5.5V 18V RL to VSSA Differential Voltage V RL – V SSA – 0.30.3V 19V DDEH to V DDA Differential Voltage V DDEH – V DDA –V DDA V DDEH V 20V DDF to V DD Differential VoltageV DDF – V DD –0.30.3V 21This spec has been moved to T able 9, spec 43a.22VSSSYN to VSS Differential Voltage V SSSYN – V SS –0.10.1V 23V RCVSS to V SS Differential VoltageV RCVSS – V SS–0.10.1V 24Maximum DC Digital Input Current 10 (per pin, applies to all digital pins)5I MAXD –22mA 25Maximum DC Analog Input Current 11 (per pin, applies to all analog pins)I MAXA –33mA26Maximum Operating T emperature Range 12 — Die Junction T emperatureT J– 40.0150.0o CElectrical CharacteristicsMPC5534 Microcontroller Data Sheet, Rev. 0Preliminary—Subject to Change Without NoticeFreescale Semiconductor53.2Thermal Characteristics27Storage Temperature Range T STG – 55.0150.0o C 28Maximum Solder Temperature 13T SDR —260.0oC29Moisture Sensitivity Level 14MSL—3Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability or cause permanent damage to the device.2Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum specifications for device stress have not yet been determined.31.5V +/– 10% for proper operation. This parameter is specified at a maximum junction temperature of 150C.4All functional non-supply I/O pins are clamped to VSS and VDDE or VDDEH.5AC signal over and undershoot of the input voltages of up to +/– 2.0 volts is permitted for a cumulative duration of 60 hours over the complete lifetime of the device (injection current does not need to be limited for this duration).6Internal structures will hold the voltage above –1.0 volt if the injection current limit of 2 mA is met.7Internal structures will not clamp to a safe voltage. External protection must be used to ensure that voltage on the pin stays above –0.3 volts.8Internal structures hold the input voltage below this maximum voltage on all pads powered by VDDEH supplies, if the maximum injection current specification is met (2 mA for all pins) and VDDEH is within Operating Voltage specifications.9Internal structures hold the input voltage below this maximum voltage on all pads powered by VDDE supplies, if the maximum injection current specification is met (2 mA for all pins) and VDDE is within Operating Voltage specifications.10T otal injection current for all pins (including both digital and analog) must not exceed 25mA.11T otal injection current for all analog input pins must not exceed 15mA.12Lifetime operation at these specification limits is not guaranteed.13Solder profile per CDF-AEC-Q100.14Moisture sensitivity per JEDEC test method A112.Table 3. Thermal CharacteristicsNum CharacteristicSymbol UnitValue208 MAPBGA324 PBGA1Junction to Ambient 1, 2Natural Convection (Single layer board)R θJA°C/W42342Junction to Ambient 1, 3Natural Convection(Four layer board 2s2p)R θJA°C/W 26233Junction to Ambient (@200 ft./min., Single layer board)R θJMA°C/W 34284Junction to Ambient (@200 ft./min.,Four layer board 2s2p)R θJMA°C/W 22205Junction to Board 4(Four layer board 2s2p)R θJB°C/W 1515Table 2. Absolute Maximum Ratings 1 (continued)Num CharacteristicSymbol Min Max 2UnitMPC5534 Microcontroller Data Sheet, Rev. 0Preliminary—Subject to Change Without NoticeElectrical CharacteristicsFreescale Semiconductor63.2.1General Notes for Specifications at Maximum Junction TemperatureAn estimation of the chip junction temperature, T J , can be obtained from the equation:T J = T A + (R θJA × P D )where:T A = ambient temperature for the package (o C)R θJA = junction to ambient thermal resistance (o C/W)P D = power dissipation in the package (W)The supplied thermal resistances are provided based on JEDEC JESD51 series of standards to provide consistent values for estimations and comparisons. The difference between the values determined on the single-layer (1s) board and on the four-layer board with two signal layers and a power and a ground plane (2s2p) clearly demonstrate that the effective thermal resistance of the component is not a constant. It depends on the construction of the application board (number of planes), the effective size of the board which cools the component, how well the component is thermally and electrically connected to the planes, and the power being dissipated by adjacent components.Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance between through vias leave the planes virtually disconnected, the thermal performance is also greatly reduced.As a general rule, the value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the application board has one oz (35 micron nominal thickness) internal planes, the components are well separated, and the overall power dissipation on the board is less than 0.02 W/cm 2.6Junction to Case 5R θJC °C/W 8107Junction to Package Top 6Natural ConvectionΨJT°C/W22Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.2Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.3Per JEDEC JESD51-6 with the board horizontal.4Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package.5Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature.6Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2.Table 3. Thermal Characteristics (continued)Num CharacteristicSymbol UnitValue208 MAPBGA324 PBGAElectrical CharacteristicsMPC5534 Microcontroller Data Sheet, Rev. 0Preliminary—Subject to Change Without NoticeFreescale Semiconductor7The thermal performance of any component depends strongly on the power dissipation of surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device.At a known board temperature, the junction temperature is estimated using the following equation:T J = T B + (R θJB × P D )where:T J = junction temperature (o C)T B = board temperature at the package perimeter (o C/W)R θJB = junction to board thermal resistance (o C/W) per JESD51-8P D = power dissipation in the package (W)When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. The application board should be similar to the thermal test condition, with the component soldered to a board with internal planes.Historically, the thermal resistance has frequently been expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance:R θJA = R θJC + R θCA where:R θJA = junction to ambient thermal resistance (o C/W)R θJC = junction to case thermal resistance (o C/W)R θCA = case to ambient thermal resistance (o C/W)R θJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, R θCA . For instance, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This description is most useful for packages with heat sinks where some 90% of the heat flow is through the case to the heat sink to ambient. For most packages, a better model is required.A more accurate two-resistor thermal model can be constructed from the junction to board thermal resistance and the junction to case thermal resistance. The junction to case covers the situation where a heat sink will be used or where a substantial amount of heat is dissipated from the top of the package. The junction to board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. This model can be used for either hand estimations or for a computational fluid dynamics (CFD) thermal model.To determine the junction temperature of the device in the application after prototypes are available, the Thermal Characterization Parameter (ΨJT ) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation:T J = T T + (ΨJT × P D )MPC5534 Microcontroller Data Sheet, Rev. 0Preliminary—Subject to Change Without NoticeElectrical CharacteristicsFreescale Semiconductor8where:T T = thermocouple temperature on top of the package (o C)ΨJT = thermal characterization parameter (o C/W)P D = power dissipation in the package (W)The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over thethermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire.References:Semiconductor Equipment and Materials International 805 East Middlefield Rd Mountain View, CA 94043 (415) 964-5111MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or 303-397-7956.JEDEC specifications are available on the WEB at .• 1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within anAutomotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47–54.• 2. G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled Applications,” Electronic Packaging and Production, pp. 53–58, March 1998.• 3. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board ThermalResistance and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212–220.3.3PackageThe MPC5534 is available in packaged form. Package options are listed in Section 2, “Ordering Information .”Refer to Section 4, “Mechanicals,” for pinouts and package drawings.3.4EMI (Electromagnetic Interference) CharacteristicsTable 4. EMI Testing Specifications 1Num CharacteristicMin. Value Typ. ValueMax. Value Unit 1Scan Range 0.15—1000MHz 2Operating Frequency ——80MHz 3V DD Operating Voltages—1.5—VElectrical CharacteristicsMPC5534 Microcontroller Data Sheet, Rev. 0Preliminary—Subject to Change Without NoticeFreescale Semiconductor93.5ESD Characteristics3.6VRC/POR Electrical Specifications4V DDSYN , V RC33, V DD33, V FLASH , V DDE Operating Voltages — 3.3—V 5VPP , VDDEH, VDDA Operating Voltages — 5.0—V 6Maximum Amplitude ——142323dBuV7Operating Temperature——25oCEMI testing and I/O port waveforms per SAE J1752/3 issued 1995-03. Qualification testing is performed on the MPC5554 and applied to MPC5500 family as generic EMI performance data.2As measured with “single-chip” EMI program.3As measured with “expanded” EMI program.Table 5. ESD Ratings 1, 21All ESD testing is in conformity with CDF-AEC-Q100 Stress T est Qualification for Automotive Grade Integrated Circuits.2A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specificationrequirements. Complete DC parametric and functional testing shall be performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specificationCharacteristicSymbolValue Unit ESD for Human Body Model (HBM)2000V HBM Circuit DescriptionR11500Ohm C100pFESD for Field Induced Charge Model (FDCM)500 (all pins)V 750 (corner pins)Number of Pulses per pin:Positive Pulses (HBM)Negative Pulses (HBM) ——11——Interval of Pulses—1secondTable 6. VRC/POR Electrical SpecificationsNum CharacteristicSymbol Min Max Units 1 1.5V (VDD) POR Negated (Ramp Up)1.5V (VDD) POR Asserted (Ramp Down)V_POR15 1.11.1 1.351.35V 2 3.3V (VDDSYN) POR Negated (Ramp Up)3.3V (VDDSYN) POR Asserted (Ramp Down)V_POR33 2.02.0 2.852.85V 3RESET Pin Supply (VDDEH6) POR Negated (Ramp Up)RESET Pin Supply (VDDEH6) POR Asserted (Ramp Down)V_POR5 2.02.0 2.852.85V 4VRC33 voltage before regulator controller allows the pass transistor to start turning onV_TRANS_ST ART1.02.0VTable 4. EMI Testing Specifications 1 (continued)Num CharacteristicMin. ValueTyp. ValueMax. ValueUnitMPC5534 Microcontroller Data Sheet, Rev. 0Preliminary—Subject to Change Without NoticeElectrical CharacteristicsFreescale Semiconductor103.7Power Up/Down SequencingPower sequencing between the 1.5-V power supply and VDDSYN or the RESET power supplies is required if the user provides an external 1.5-V power supply and ties VRC33 to ground. To avoid this power sequencing requirement, power up VRC33 within the specified operating range, even if not using the on-chip voltage regulator controller. Refer to Section 3.7.1, “Power Up Sequence (If VRC33 Grounded)” and Section 3.7.2, “Power Down Sequence (If VRC33 Grounded).”Another power sequencing requirement is that VDD33 must be of sufficient voltage before POR negates, so that the values on certain pins are treated as 1s when POR does negate. Refer to Section 3.7.3, “Input Value of Pins During POR Dependent on VDD33.”5VRC33 voltage when regulator controller allows the pass transistor to completely turn on 1, 2V_TRANS_ON 2.0 2.85V 6VRC33 voltage above which the regulator controller will keep the 1.5V supply in regulation 3, 4V_VRC33REG 3.0—V 7Current which can be sourced by VRCCTL I_VRCCTL 5mA– 40C 11.0—mA 25C 9.0—mA 150C (Tj)7.5—mA 8Voltage differential during power up that VDD33 can lag VDDSYN or VDDEH6 before VDDSYN and VDDEH6 reach V_POR33 and V_POR5 minimums respectivelyVDD33_LAG—1.0V9Absolute value of Slew Rate on power supply pins —50V/ms10Required Gain:Idd / I_VRCCTL (@vdd = 1.35v, f sys = 80MHz)4, 6BETA 7– 40C 35.08——25C 40.08——150C (Tj)50.08500—User must be able to supply full operating current for the 1.5V supply when the 3.3V supply reaches this range.2Current limit may be reached during ramp up and should not be treated as short circuit current.3At peak current for device.4Assumes that the Freescale recommended board requirements and transistor recommendations are met. Board signaltraces/routing from the VRCCTL package signal to the base of the external pass transistor and between the emitter of the pass transistor to the VDD package signals should have a maximum of 100 nH inductance and minimal resistance (<1 ohm). VRCCTL should have a nominal 1µF phase compensation capacitor to ground. VDD should have a 20 µF (nominal) bulk capacitor (> 4 µF over all conditions, including lifetime). High frequency bypass capacitors consisting of eight 0.01 µF , two 0.1 µF , and one 1 µF capacitors should be place around the package on the VDD supply signals.5I_VRCCTL measured at the following conditions: VDD=1.35V , VRC33=3.1V , V_VRCCTL=2.2V .6Values are based on IDD from high use applications as explained in the IDD Electrical Specification.7BET A is measured on a per part basis and is calculated as IDD / I_VRCCTL and represents the worst case external transistor BET A.8Preliminary value. Final specification pending characterization.Table 6. VRC/POR Electrical Specifications (continued)Num CharacteristicSymbol Min Max UnitsElectrical CharacteristicsAlthough there is no power sequencing required between VRC33 and VDDSYN during power up, for the VRC stage turn-on to operate within specification, VRC33 must not lead VDDSYN by more than 600 mV or lag by more than 100 mV . Higher spikes in the emitter current of the pass transistor will occur if VRC33 leads or lags VDDSYN by more than these amounts. The value of that higher spike in current depends on the board power supply circuitry and the amount of board level capacitance.Furthermore, when all of the PORs negate, the system clock will start to toggle, adding another large increase of the current consumption from VRC33. If VRC33 lags VDDSYN by more than 100 mV , this increased current consumption can drop VDD low enough to assert the 1.5-V POR again. Oscillations are even possible because when the 1.5-V POR asserts, the system clock stops, causing the voltage on VDD to rise until the 1.5-V POR negates again. Any oscillations stop when VRC33 is powered sufficiently.When powering down, VRC33 and VDDSYN do not have a delta requirement to each other, because the bypass capacitors internal and external to the device are already charged.When not powering up or down, VRC33 and VDDSYN do not have a delta requirement to each other for the VRC to operate within specification.Although there are no power up/down sequencing requirements to prevent issues like latch-up, excessive current spikes, etc., the state of the I/O pins during power up/down varies depending on power. Table 7 gives the pin state for the sequence cases for all pins with pad type pad_fc (fast type), and Table 8 for all pins with pad type pad_mh (medium type) and pad_sh (slow type).3.7.1Power Up Sequence (If VRC33 Grounded)In this case, the 1.5-V VDD supply must rise to 1.35-V before the 3.3-V VDDSYN and the RESET power supplies rises above 2.0 V. This ensures that digital logic in the PLL on the 1.5-V supply will not begin to operate below the specified operation range lower limit of 1.35 V . Since the internal 1.5-V POR is disabled,Table 7. Power Sequence Pin States (Fast Pads)V DDE V DD33V DD pad_fc (Fast)Output DriverStateCommentLOW X X Low Functional I/O pins are clamped to VSS and VDDEVDDE LOW X High VDDE VDD33LOW High Impedance POR asserted.VDDEVDD33VDDFunctionalNo POR assertedTable 8. Power Sequence Pin States (Medium and Slow Pads)V DDEH V DD pad_mh/pad_sh (Medium and Slow)Output DriverCommentLOW X Low Functional I/O pins are clamped to VSS and VDDEH VDDEH LOW High Impedance POR asserted VDDEHVDDFunctionalNo POR asserted。
LT5534说明书
LT5534 DESCRIPTIONDemonstration circuit 748A is a wide range RF power detector featuring the LT®5534.The LT5534 is a 50MHz to 3GHz monolithic RF power detector capable of measuring RF signals over a 60dB dynamic range. The RF signal in a decibel scale is precisely converted into DC voltage on a linear scale. The 60dB input dynamic range is achieved using cas-caded RF detectors and RF limiters. Their outputs are summed to generate an accurate log-linear DC volt-age proportional to the input RF signal in dB. The output is buffered with a low output impedance driver. The LT5534 features superior temperature stability and fast transient response (typical full-scale setting time is 38ns).Design files for this circuit board are available. Call the LTC factory.Table 1. Typical Performance Summary (V CC = 3V, EN = 3V, T A = 25°C, source impedance = 50Ω, unless otherwise noted. Test circuit shown in Figure 1.)PARAMETER CONDITION VALUESupply Voltage 2.7V to 5.25VSupply Current 7mAInput Impedance 2kΩOutput Impedance 32ΩOutput DC voltage No RF Input Signal 142mVfRF= 50MHzRF Input Power Range -58dBm to +2dBmDynamic Range ±3dB Linearity Error, T A = -40°C to 85°C 60dBOutput Slope 44mV/dBOutput Variation vs. Temperature P in = -48dBm to -14dBm, T A = -40°C to 85°C 0.007dB/°CfRF= 900MHzRF Input Power Range -60dBm to 0dBmDynamic Range ±3dB Linearity Error, T A = -40°C to 85°C 60dBOutput Slope 41mV/dBOutput Variation vs. Temperature P in = -48dBm to -14dBm, T A = -40°C to 85°C 0.008dB/°CfRF= 1900MHzRF Input Power Range -63dBm to -2dBmDynamic Range ±3dB Linearity Error, T A = -40°C to 85°C 61dBOutput Slope 36.6mV/dBOutput Variation vs. Temperature P in = -48dBm to -14dBm, T A = -40°C to 85°C 0.012dB/°COutput intercept 50Ω External Termination, T A = -40°C to 85°C -64dBmfRF= 2500MHzRF Input Power Range -63dBm to -3dBmDynamic Range ±3dB Linearity Error, T A = -40°C to 85°C 60dBOutput Slope 35mV/dBOutput Variation vs. Temperature P in = -48dBm to -14dBm, T A = -40°C to 85°C 0.025dB/°CQUICK START PROCEDUREDemonstration circuit 748A is easy to set up to evalu-ate the performance of the LT5534. Refer to Figure 1 for proper measurement equipment setup and follow the procedure below:NOTE:Demonstration circuit 748A is optimized for evaluations over the frequency range from 50MHz to 2.5GHz. Its RF input port is well matched with better than 10dB return loss up to 2.5GHz. At higher fre-quencies, return loss can be improved with proper matching.1.Connect DC power supply negative (-) output to demo board Gnd pin (E3 or E5).2.Connect DC power supply positive (+) output (2.7V to 5.25V) to demo board Vcc pin (E1).NOTE:Do not exceed 5.5V, the absolute maximum supply voltage.3.Connect voltmeter negative (-) lead to demo board Gnd pin (E3 or E5).4.Connect voltmeter positive (+) lead to the demo board Vout pin (E2).5.Connect RF signal generator output to demo board RF in port (SMA connector J1) via coaxial cable.ing a jumper cable, connect demo board Vcc pin (E1) to EN pin (E4). Now the detector is enabled (on) and is ready for measurement.NOTE:Make sure that the power is not applied to the EN pin before it is applied to the Vcc pin. The volt-age on the EN pin must never exceed the voltage on the Vcc pin.7.Apply an RF input signal and measure Vout DC voltage.NOTE:Do not exceed +10dBm, the absolute maxi-mum RF input power.8.The dynamic range is defined as the range over which the linearity error is within ±3dB. The linear-ity error is calculated by the difference between the incremental slope of the output and the average output slope from -48dBm to -14dBm.Figure 1.Proper Measurement Equipment Setup。
NE5534IP资料
PACKAGING INFORMATIONOrderable DeviceStatus (1)Package Type Package DrawingPins Package Qty Eco Plan (2)Lead/Ball Finish MSL Peak Temp (3)NE5534AD ACTIVE SOIC D 875Green (RoHS &no Sb/Br)CU NIPDAU Level-2-260C-1YEAR NE5534ADE4ACTIVE SOIC D 875Green (RoHS &no Sb/Br)CU NIPDAU Level-2-260C-1YEAR NE5534ADG4ACTIVE SOIC D 875Green (RoHS &no Sb/Br)CU NIPDAU Level-2-260C-1YEAR NE5534ADR ACTIVE SOIC D 82500Green (RoHS &no Sb/Br)CU NIPDAU Level-2-260C-1YEAR NE5534ADRE4ACTIVE SOIC D 82500Green (RoHS &no Sb/Br)CU NIPDAU Level-2-260C-1YEAR NE5534ADRG4ACTIVE SOIC D 82500Green (RoHS &no Sb/Br)CU NIPDAU Level-2-260C-1YEAR NE5534AJG OBSOLETE CDIP JG 8TBD Call TI Call TINE5534AP ACTIVE PDIP P 850Pb-Free (RoHS)CU NIPDAU N /A for Pkg Type NE5534APE4ACTIVE PDIP P 850Pb-Free (RoHS)CU NIPDAU N /A for Pkg Type NE5534D ACTIVE SOIC D 875Green (RoHS &no Sb/Br)CU NIPDAU Level-2-260C-1YEAR NE5534DE4ACTIVE SOIC D 875Green (RoHS &no Sb/Br)CU NIPDAU Level-2-260C-1YEAR NE5534DG4ACTIVE SOIC D 875Green (RoHS &no Sb/Br)CU NIPDAU Level-2-260C-1YEAR NE5534DR ACTIVE SOIC D 82500Green (RoHS &no Sb/Br)CU NIPDAU Level-2-260C-1YEAR NE5534DRE4ACTIVE SOIC D 82500Green (RoHS &no Sb/Br)CU NIPDAU Level-2-260C-1YEAR NE5534DRG4ACTIVE SOIC D 82500Green (RoHS &no Sb/Br)CU NIPDAU Level-2-260C-1YEAR NE5534IP OBSOLETE PDIP P 8TBD Call TI Call TINE5534P ACTIVE PDIP P 850Pb-Free (RoHS)CU NIPDAU N /A for Pkg Type NE5534PE4ACTIVE PDIP P 850Pb-Free (RoHS)CU NIPDAU N /A for Pkg Type NE5534PSR ACTIVE SO PS 82000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM NE5534PSRE4ACTIVE SO PS 82000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM NE5534PSRG4ACTIVE SO PS 82000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SA5534AD ACTIVE SOIC D 875Green (RoHS &no Sb/Br)CU NIPDAU Level-2-260C-1YEAR SA5534ADE4ACTIVE SOIC D 875Green (RoHS &no Sb/Br)CU NIPDAU Level-2-260C-1YEAR SA5534ADG4ACTIVE SOIC D 875Green (RoHS &no Sb/Br)CU NIPDAU Level-2-260C-1YEAR SA5534ADR ACTIVE SOIC D 82500Green (RoHS &no Sb/Br)CU NIPDAU Level-2-260C-1YEAR SA5534ADRE4ACTIVESOICD82500Green (RoHS &CU NIPDAULevel-2-260C-1YEAR4-Jun-2007Orderable DeviceStatus (1)Package Type Package DrawingPins Package QtyEco Plan (2)Lead/Ball FinishMSL Peak Temp (3)no Sb/Br)SA5534ADRG4ACTIVE SOIC D 82500Green (RoHS &no Sb/Br)CU NIPDAU Level-2-260C-1YEAR SA5534AP ACTIVE PDIP P 850Pb-Free (RoHS)CU NIPDAU N /A for Pkg Type SA5534APE4ACTIVE PDIP P 850Pb-Free (RoHS)CU NIPDAU N /A for Pkg Type SA5534D ACTIVE SOIC D 875Green (RoHS &no Sb/Br)CU NIPDAU Level-2-260C-1YEAR SA5534DE4ACTIVE SOIC D 875Green (RoHS &no Sb/Br)CU NIPDAU Level-2-260C-1YEAR SA5534DG4ACTIVE SOIC D 875Green (RoHS &no Sb/Br)CU NIPDAU Level-2-260C-1YEAR SA5534DR ACTIVE SOIC D 82500Green (RoHS &no Sb/Br)CU NIPDAU Level-2-260C-1YEAR SA5534DRE4ACTIVE SOIC D 82500Green (RoHS &no Sb/Br)CU NIPDAU Level-2-260C-1YEAR SA5534DRG4ACTIVE SOIC D 82500Green (RoHS &no Sb/Br)CU NIPDAU Level-2-260C-1YEAR SA5534P ACTIVEPDIP P 850Pb-Free (RoHS)CU NIPDAU N /A for Pkg Type SA5534PE4ACTIVE PDIP P 850Pb-Free (RoHS)CU NIPDAU N /A for Pkg Type SA5534PS ACTIVE SO PS 880Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SA5534PSE4ACTIVE SO PS 880Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SA5534PSG4ACTIVE SO PS 880Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SA5534PSR ACTIVE SO PS 82000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SA5534PSRE4ACTIVE SO PS 82000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SA5534PSRG4ACTIVESOPS82000Green (RoHS &no Sb/Br)CU NIPDAULevel-1-260C-UNLIM(1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan -The planned eco-friendly classification:Pb-Free (RoHS),Pb-Free (RoHS Exempt),or Green (RoHS &no Sb/Br)-please check /productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS):TI's terms "Lead-Free"or "Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all 6substances,including the requirement that lead not exceed 0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1)lead-based flip-chip solder bumps used between the die and package,or 2)lead-based die adhesive used between the die and leadframe.The component is otherwise considered Pb-Free (RoHS compatible)as defined above.Green (RoHS &no Sb/Br):TI defines "Green"to mean Pb-Free (RoHS compatible),and free of Bromine (Br)and Antimony (Sb)based flame retardants (Br or Sb do not exceed 0.1%by weight in homogeneous material)4-Jun-2007(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annualbasis.PACKAGE OPTION ADDENDUM4-Jun-2007TAPE AND REEL BOXINFORMATIONDevicePackage Pins SiteReel Diameter (mm)Reel Width (mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant NE5534ADR D 8SITE 2733012 6.4 5.2 2.1812Q1NE5534DR D 8SITE 2733012 6.4 5.2 2.1812Q1NE5534PSR PS 8SITE 41330168.2 6.6 2.51216Q1SA5534ADR D 8SITE 2733012 6.4 5.2 2.1812Q1SA5534DR D 8SITE 2733012 6.4 5.2 2.1812Q1SA5534PSRPS8SITE 41330168.26.62.51216Q14-Oct-2007DevicePackagePins Site Length (mm)Width (mm)Height (mm)NE5534ADR D 8SITE 27342.9336.620.64NE5534DR D 8SITE 27342.9336.620.64NE5534PSR PS 8SITE 41346.0346.033.0SA5534ADR D 8SITE 27342.9336.620.64SA5534DR D 8SITE 27342.9336.620.64SA5534PSRPS8SITE 41346.0346.033.04-Oct-2007IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries(TI)reserve the right to make corrections,modifications,enhancements, improvements,and other changes to its products and services at any time and to discontinue any product or service without notice. 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20 MHz to 500 MHzIF Gain BlockPreliminary Technical DataADL5534Rev. PrD 5/07Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners.One Technology Way, P.O. Box 9106, N orwood, MA 02062-9106, U.S.A.Tel: 781.329.4700 Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.FEATURESFUNCTIONAL BLOCK DIAGRAMFixed gain of 20 dBOperation up to 500 MHz 1RFIN12 NC 3 NC 4RFIN211CLIN112RFOUT110RFOUT29CLIN25G N D 67G N D 815G N D16G N D14G N D13G N DG N D G N D +41.8 dBm OIP3 at 70 MHz Noise Figure 2.5 dB at 70 MHzTemperature and power supply stable Power supply: 5 VPower supply current: 90 mA per amplifier 1000 V ESD (Class 1C)Figure 1. Block DiagramGENERAL DESCRIPTIONThe ADL5534 contains two broadband, fixed-gain, linear amplifiers in an 4x4 mm LFCSP package and operates at frequencies up to 500 MHz. The device can be used in a wide variety of wired and wireless devices including cellular, GSM and WCDMA, and broadband applications.The ADL5534 has a fixed gain 20 dB and is stable over frequency, temperature, power supply and from device to device. It achieves an OIP3 of 41.8 dBm with an outputcompression point of +20.2 dBm and a noise figure of 2.5 dB. The ADL5534 is single-ended and internally matched to 50 Ω with an input return loss of 10 dB. Only input/output ac-coupling capacitors, a power supply decoupling capacitor and external inductor are required for operation. This IF amplifier operates with supply voltage of +5V , consuming 90 mA of supply current per amplifier. Fabricated on a GaAs HBT process and has an ESD rating of 1000 V (Class 1C). The device is packaged in a 4mm x 4mm LFCSP that uses an exposed paddle for excellent thermal impedance and operates from −40°C to +85°C. A fully populated evaluation board is available.ADL5534Preliminary Technical DataRev. PrD 5/07 | Page 2 of 9TABLE OF CONTENTSFeatures..............................................................................................1 Functional Block Diagram..............................................................1 General Description.........................................................................1 Revision History...............................................................................2 Specifications.....................................................................................3 Absolute Maximum Ratings............................................................4 ESD Caution...................................................................................4 Pin Configuration and Function Descriptions..............................5 Typical Performance Characteristics..............................................6 EV ALUATION BOARD...................................................................7 OUTLINE DIMENSIONS...............................................................9 ORDERING GUIDE (9)REVISION HISTORY5/07—Rev. PrD: Preliminary VersionPreliminary Technical DataADL5534Rev. PrD 5/07 | Page 3 of 9SPECIFICATIONSV CC = 5 V , T = 25°C, unless otherwise noted. Table 1.Parameter Conditions MinTyp Max Unit OVERALL FUNCTIONFrequency Range 20 500 MHz Gain vs. Frequency ± 50 MHz. Center Frequency = 190 MHz or 380 MHz ±0.15 dB Input Return Loss (S11) 30 MHz to 500 MHz -10 dB Output Return Loss (S22) 30 MHz to 500 MHz -10 dB Isolation (RFIN1 to RFOUT2 and RFIN2 to RFOUT1)Frequency = 200 MHz -29.8 dB Isolation (RFIN1 to RFOUT2 and RFIN2 to RFOUT1)Frequency = 500 MHz-22.5dBFREQUENCY = 70 MHzGain 19.8 dB vs. Temperature −40°C ≤ T A ≤ +85°C ±.25 dB Output 1 dB Compression Point 20.0 dBm Output Third-Order Intercept ∆f = 1 MHz, Output Power (P OUT ) = 0 dBm (per tone) 41.8 dBm Noise Figure 2.5 dB FREQUENCY = 190 MHzGain 19.4 dB vs. Temperature −40°C ≤ T A ≤ +85°C ±.25 dB Output 1 dB Compression Point 20.2 dBm Output Third-Order Intercept ∆f = 1 MHz, Output Power (P OUT ) = 0 dBm (per tone) 40.1 dBm Noise Figure 2.7 dB FREQUENCY = 380 MHzGain 18.8 dB vs. Temperature −40°C ≤ T A ≤ +85°C ±.25 dB Output 1 dB Compression Point 20.1 dBm Output Third-Order Intercept ∆f = 1 MHz, Output Power (P OUT ) = 0 dBm (per tone) 37.0 dBm Noise Figure 2.9 dB POWER INTERFACE Pins RFOUT, Vcc Supply Voltage 4.75 5 5.25 V Supply Current Current Consumption is Specified Per Amplifier 90 mA vs. Temperature −40°C ≤ T A ≤ +85°C (Specified Per Amplifier) 104 mA Power DissipationVPOS = 5V (Specified Per Amplifier)450 mWADL5534Preliminary Technical DataRev. PrD 5/07 | Page 4 of 9ABSOLUTE MAXIMUM RATINGSTable 2.Parameter Rating Stresses above those listed under Absolute Maximum Ratingsmay cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operationalsection of this specification is not implied. Exposure to absolutemaximum rating conditions for extended periods may affect device reliability. Supply Voltage, VPOS 5.5 V Input Power Per Amplifier(re: 50 Ω) +12 dBm 650 mW Internal Power Dissipation Per Amplifier (Paddle Soldered) θJA (Paddle Soldered) TBD °C/W 150 °C Maximum Junction Temperature −40°C to +85°C ESD CAUTION Operating Temperature Range −65°C to +150°C Storage Temperature Range (Soldering 60 sec) 240°CPreliminary Technical DataADL5534Rev. PrD 5/07 | Page 5 of 9PIN CONFIGURATION AND FUNCTION DESCRIPTIONS1RFIN12 NC 3 NC 4RFIN211CLIN112RFOUT110RFOUT29CLIN2567G N D 815G N D16G N D14G N D13G N DG N D G N D G N DFigure 2.Table 3. Pin Function DescriptionsPin No. Mnemonic Description1, 3 RFIN1, RFIN2 RF Input: Requires a DC blocking capacitor. Use a 10 nF capacitor for normal operation.10, 12RFOUT1, RFOUT2 RF Output and Bias: DC bias is provided to this pin through an inductor. A 470 nH inductor is recommended for normal operation. RF path requires a DC blocking capacitor. Use a 10 nF capacitor for normal operation. GNDGround. Connect this pin to a low impedance ground plane.5, 6, 7,8, 13,14,15,16 2, 4 NC No Connect.9, 11 CLIN1, CLIN2 A 1 nF capacitor connected between 9 and ground an Pin11 and ground provides decoupling for the on board linearizer.Internally connected to GND. Solder to a low impedance ground planeExposedPaddleADL5534Preliminary Technical DataRev. PrD 5/07 | Page 6 of 9TYPICAL PERFORMANCE CHARACTERISTICS100200300400500600Frequency (MHz)N F , G A I N ,P 1d B , O I P 3 (d B , d B m )100200300400500600Freq (MHz)R e t u r n L o s s & I s o l a t i o n (d B )Figure 3 ADL5534 Gain, Noise Figure, OIP3 and P1dB vs FrequencyFigure 5 ADL5534 Input / Output Return Loss and Reverse Isolation vsFrequency-6-4-202468101214161820Pout (dBm)Figure 4 ADL5534 OIP3 vs Pout and FrequencyPreliminary Technical DataADL5534Rev. PrD 5/07 | Page 7 of 9EVALUATION BOARDFigure 6 shows the schematic for the ADL5531 evaluation board. The board is powered by a single 5 V supply. Thecomponents used on the board are listed in. Table 4Applying 5V to Vpos will bias the amplifier corresponding to RFIN1 - RFOUT2. Applying 5 V toVpos1 will bias the amplifiercorresponding to RFIN2 – RFOUT2 To bias both amplifiers from a single supply, connect 5V to Vpos or Vpos1 and attach a jumper across W3Figure 6. Evaluation Board SchematicTable 4. Evaluation Board Configuration OptionsComponent Function Default Value C1, C2, C3, C4 AC-coupling capacitors. 10 nF 0402 C5, C6 Provides decoupling for the on board linearizer.1 nF 0603 Optional components used for Configuring ADL5534 as a balanced amplifier. Open 0603R1, R2, R3, R4, R5,R6, R7 R8 T1, T2 T1 and T2 are 50 Ω t o100 Ω impedance transformers used to configure the ADL5534as a balanced amplifier. T1 and T2 are used to present a 100 Ω differential impedance to the ADL5534.MiniCircuits ADT2-1T-1P OpenOptional components used for Configuring ADL5534 as a balanced amplifier. C11-C14: Open 0402 C11, C12, C13, C14, C15, C16 C15,C16: Open 0402 C9, C10 Power Supply decoupling capacitors capacitor. 1 uF 0603 C7, C8 Power Supply decoupling capacitors capacitor. 10 nF 0603 L1, L2DC bias inductor.470 nH 1008CS VCC & GND Clip-on terminals for power supply.VCC Red GND Black W1,W2 2-pin jumper for connection of ground and supply via cable.W32-pin jumper use to connect Vpos to Vpos1OpenPreliminary Technical DataADL5534Rev. PrD 5/07 | Page 8 of 9Preliminary Technical DataADL5534Rev. PrD 5/07 | Page 9 of 9OUTLINE DIMENSIONSFigure 9. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]4mm × 4 mm Body, Very Thin, Quad LeadCP-16-13Dimensions shown in millimetersORDERING GUIDEModelTemperature Range Package Description Package Option Branding Ordering Quantity ADL5534ACPZ-R7−40°C to +85°C 8-Lead LFCSP Tape and Reel CP-16-13 1ADL5534ACPZ-WP −40°C to +85°C 8-Lead LFCSP Wa e Pack CP-16-13 1ADL5534-EVALZEvaluation Board1Z = Pb-free part.©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06836-0-5/07(PrD)COMPLIANT TO JEDEC STANDARDS MO-220-VGGC.0.500.40COPLANARITY0.081.000.850.800.230.18BOTTOM VIEW031006-A。