IR2121中文资料
PI2121-EVAL1;中文规格书,Datasheet资料
IntroductionThe PI2121-EVAL1 allows the user to test the basic principle and operational characteristics of an Active ORing function in a redundant power architecture, while also experiencing the benefits and value of the PI2121 solution versus conventional Active ORing solutions. The PI2121-EVAL1 evaluation board is configured to receive two independent power source inputs,per a typical redundant power architecture, through two Active ORing channels that are combined to form aredundant power output. Each channel is capable of up to 24A, and is suitable for redundant bus voltages up to 5 V. For high current Active ORing, above 24 A, the two channels provided on the evaluation board can be paralleled in amaster/slave configuration and OR'd with a second evaluation board.The PI2121-EVAL1 evaluation board is designed withoptimized PCB layout and component placement to represent a realistic high density final design for an embedded Active ORing solution for ≤5V bus applications requiring up to 24 A.This evaluation board is intended as an easy and simple way to test the electrical and thermal performance of the PI2121 Full-Function Active ORing solution.Both dynamic and steady state testing of the PI2121 can be completed on the PI2121-EVAL1 evaluation board, in addition to using the key features of the product. Dynamic testing can be completed under a variety of system level fault conditions to check for response time to faults.This document provides basic instructions for initial start-up and configuration of the evaluation board. Furtherinformation on the functionality of the PI2121 can be found in the PI2121 product data sheet.PI2121-EVAL1Cool-ORing ™ SeriesPI2121-EVAL1 Full-Function Active ORingEvaluation Board User Guide®PI2121-EVAL1 Evaluation Board featuring the Cool-ORing PI2121 Full-Function Active ORing Solution.Cool-ORing™ SeriesThe PI2121-EVAL1 Evaluation Board is intended to acquaint the user with the benefits and features of the Cool-ORing TM PI2121full function Active ORing solution. It is not designed to be installed in end-use equipment.Please read this document before setting up the PI2121-EVAL1Evaluation Board and refer to the PI2121 product data sheet for device specifications, functional description and characteristics.During operation, the power devices and surrounding structures can be operated safely at high temperatures.•Remove power and use caution when connecting and disconnecting test probes and interface lines to avoid inadvertent short circuits and contact with hot surfaces.•When testing electronic products always use approved safety glasses. Follow good laboratory practice and procedures.The Cool-ORing PI2121 is a complete full-function Active ORing solution with a high-speed ORing MOSFET controller and a very low on-state resistance MOSFET designed for use in redundant power system architectures. The PI2121 Cool-ORing solution is offered in an extremely small, thermally enhanced 5 mm x 7 mm LGA package and can be used in low voltage (≤5 Vbus) high side Active ORing applications. ThePI2121 enables extremely low power loss with fast dynamic response to fault conditions, critical for high availability systems. A master/ slave feature allows the paralleling ofPI2121 solutions for high current Active ORing requirements. The PI2121, with its 1.5 mΩinternal MOSFET provides very high efficiency and low power loss during steady state operation, while achieving high-speed turn-off of the internal MOSFET during input power source fault conditions that cause reverse current flow. The PI2121 provides an active low fault flag output to the system during excessive forward current, light load, reverse current, over-voltage,under-voltage, and over-temperature fault conditions.A temperature sensing function indicates a fault if the maximum junction temperature exceeds 160°C. Theunder-voltage and over-voltage thresholds are programmable via an external resistor divider.Figure 1 shows a photo of the PI2121-EVAL1 evaluation board, with two PI2121 used to form the two Active ORing channels. The board is built with two identical Active ORing circuits with options and features that enable the user to fullyexplore the capabilities of the PI2121 Cool-ORing solution. Figure 1 –PI2121-EVAL1 Evaluation Board (1.8" x 1.8")Terminals RatingVin1, Vin28V / 24 AVaux1, Vaux2, (R7 = R14 = 10 Ω)-0.3 to 17.3 V / 40 mAsee Vaux sectionSL-0.3 to 8.0 V / 10 mAFT-0.3 to 17.3 V / 10 mATerminal DescriptionVin1Power Source Input #1or bus input designed to accommodate up to 24 A continuous current.Vaux1Auxiliary Input Voltage #1to supply PI2121 (SiP1) VC power. Vaux1 should be equal to Vin1 plus5 V or higher. See details in Auxiliary Power Supply (Vaux) section of the PI2121 data sheet.Rtn1Vaux1 Return Connection: Connected to Ground planeGnd Vin & Vout Return Connection:Three Gnd connections are available and are connected to a commonpoint, the Ground plane. Input supplies Vin1 & Vin2 and the output load at Vout should all beconnected to their respective local Gnd connection.SL1PI2121 (SiP1) Slave Input-Output Pin:For monitoring SiP1 slave pin. When SiP1 is configured as theMaster, this pin functions as an output that drives slaved PI2121 devices. When SiP1 is configured inSlave mode, SL1 serves as an input.SL2PI2121 (SiP2) Slave Input-Output Pin:For monitoring SiP2 slave pin. When SiP2 is configured as theMaster, this pin functions as an output that drives slaved PI2121 devices. When SiP2 is configured inSlave mode, SL2 serves as an input.Vin2Power Source Input #2or bus input designed to accommodate up to 24 A continuous current.Vaux2Auxiliary Input Voltage #2to supply PI2121 (SiP2) VC power. Vaux2 should be equal to Vin2 plus 5 V or higher.See details in Auxiliary Power Supply (Vaux) section of the PI2121 data sheet.Rtn2Vaux2 Return Connection: Connected to Ground planeFT1PI2121 (SiP1) Fault Pin:Monitors SiP1 fault conditionsFT2PI2121 (SiP2) Fault Pin: Monitors SiP2 fault conditionsVout Output: SiP1 and SiP2 D pins connection, connect to the load high side.Table 1 –PI2121-EVAL1 Evaluation Board terminals descriptionCool-ORing TM PI2121 Product DescriptionJumper DescriptionJ1, J3BK Jumpers: Connect jumper across M for master mode and across S for slave mode. Remove jumper to adjust reverse fault blanking time using Rbk. Rbk is R6 for SiP1 and R13 for SiP2 shown in the schematic, Figure 2.J2Slave Jumper: Remove the jumper unless one of the PI2121 is configured in slave mode.Table 2 –PI2121-EVAL1 Evaluation Board jumpers descriptionFigure 2 –PI2121-EVAL1 Evaluation Board schematic.Item QTY Reference Designator Value Description Footprint Manufacturer 12C1, C2 1 µF Capacitor, MLCC X5R, 06031 µF,16 V21C322 µF Capacitor, MLCC X7R,121022 µF, 25 V34C4, C5, C6, C7Not installed120642D1, D2LED, Super Red THIN 0603Lite-On, Inc.,58FT1, FT2, Rtn1, Rtn2, Turret Test point TURRET-1528Keystone SL1, SL2, Vaux1, Vaux2Electronics67Gnd1, Gnd2, Gnd3, Gnd4,Turret Test point TURRET-1502Keystone Vin1, Vin2, Vout1, Vout2Electronics 72J1, J3Header Pins 0.1" pitch 2 x 3mm81J2Header Pins 0.1" pitch 2 x 2mm92R1, R88.45 KΩResistor, 8.45 KΩ, 1%0603102R2, R913.3 KΩResistor,13.3 KΩ,1%0603114R3, R4, R10, R11 2.00 KΩResistor, 2.00 KΩ,1%0603122R5, R12 4.99 KΩResistor, 4.99 KΩ,1%0603132R6, R13Not Installed0603142R7, R1410Resistor, 10, 5%0603152SiP1, SiP2PI2121Picor Full-Function 24 A 5x7mm;17 pins PICORCool-ORing SolutionTable 3 –PI2121-EVAL1 Evaluation Board bill of materialsInitial Test Set UpTo test the PI2121-EVAL1 evaluation board it is necessary to configure the jumpers (J1, J2 and J3) first based on the required board configuration.Failure to configure the jumpers prior to the testing may result in improper circuit behavior.Baseline Test Procedure (Refer to Figure 3)1.0 Recommended Equipment1.1Two DC power supplies - 0-10 V; 25 A.1.2DC power supply 12 V; 100 mA.1.3DC electronic load - 50 A minimum.1.4Digital Multimeter 1.5Oscilloscope.1.6Appropriately sized interconnect cables.1.7Safety glasses.1.8PI2121 Product Data sheet.Figure 3 –Layout configuration for a typical redundant power application, using PI2121 with both solutions configured in Master Mode.Reference Designator Value Functional Description C1, C21µF VC Bypass Capacitor C322µF Output (Load) CapacitorC4, C5, C6, C7Not installedSnubber to reduce voltage ringing when the device turns off D1, D2LED To indicate a fault exist when it is onJ1, J3Jumper To select between Master and Slave Modes J2Jumper Connection between SL1 and SL2R1, R88.45K ΩUV Voltage Divider Resistor ( R2UV in Figure 4)R2, R913.3K ΩOV Voltage Divider Resistor ( R2OV in Figure 4)R3, R10 2.00K ΩUV Voltage Divider Resistor ( R1UV in Figure 4)R4, R11 2.00K ΩOV Coltage Divider Resistor ( R1OV in Figure 4)R5, R12 4.99K ΩLED Current LimiterR6, R13Not InstalledBK Delay Timer Programmable Resistor R7, R1410ΩVC Bias Resistor SiP1, SiP2PI2121Cool ORing SiP.Table 4 –Component functional descriptionBefore initial power-up follow these steps to configure the evaluation board for specific end application requirements: 2.0 Undervoltage (UV) and Overvoltage (OV) resistors set up:2.1UV and OV programmable resistors are configuredfor a 3.3 V Vin (BUS voltage) application in a two-resistor voltage divider configuration as shown inFigure 4. UV is set to 2.6 V and OV is set for 3.8 V,R1OV and R1UV are 2.00 KΩ1%. If PI2121-EVAL1 isrequired to be used in a different Vin voltageapplication please follow the following steps tochange the resistor values.2.1.1It is important to consider the maximumcurrent that will flow in the resistor dividerand maximum error due to UV and OV inputcurrent.R1UV=V(UV TH)I RUV2.1.2Set R1UV and R1OV value based on systemallowable minimum current and 1% error;I RUV ≥ 100 µAR2UV=R1UV (V(UV)–1)V(UV TH)Where:V(UV TH) : UV threshold voltageV(UV) : UV voltage set (0.5 V typ)I RUV: R1UV currentR2OV=R1OV (V(OV)–1)V(OV TH)Where:V(OV TH) : OV threshold voltageV(OV) : OV voltage set (0.5 V typ)I ROV: R1OV currentFigure 4 –UV & OV two-resistor divider configuration2.1.3Example for 2.0 V Vin (BUS voltage), to set UV and OV for ±10% Vin set UV at 1.8 V and OV at 2.2 V.R2UV= R1UV (V(UV)–1) = 2.00 KΩ*( 1.8 V–1)= 5.20 KΩ(or 5.23 KΩ% standard value)V(UV TH)0.5 VR2OV= R1OV (V(OV)–1) = 2.00 KΩ*( 2.2 V–1)= 6.80 KΩ(or 6.81 KΩ% standard value)V(OV TH)0.5 V3.0Blanking timer setup:3.1The blanking timer provides noise filtering fortypical switching power conversion that mightcause premature reverse current detection bymasking the reverse fault condition. The shortestblanking time is 50 ns when the BK pin isconnected to ground. Connecting an externalresistor (R BK, reference designators R6 for SiP1 andR13 for SiP2) between the BK pin and ground willincrease the blanking time as shown in Figure 5.Where:R BK≤ 200 KΩNote:When BK is connected to VC for slave mode .operation,then the blanking time will be 270 ns typically.4.0Auxiliary Power Supply (Vaux):4.1The PI2121 ORing solution has a separate input (VC)that provides power to the control circuitry andthe internal gate driver. An internal voltage regulator(VC) clamps the VC voltage to 15.5 V typically.4.2Connect an independent power source to the Vauxinputs of PI2121-EVAL1 Evaluation Board to supplypower to the VC inputs. The Vaux voltage should be5 V higher than Vin (redundant power source outputvoltage) to fully enhance the internal MOSFET.4.310 Ωbias resistors (Rbias, reference designators R7and R14) are installed on the PI2121-EVAL1 boardbetween each Vaux input and VC pin of thePI2121 solution.4.4If Vaux is higher than the Clamp voltage, 15.5 Vtypical, the Rbias value has to be changed usingthe following equations:4.4.1Select the value of Rbias using the followingequation:Rbias =Vaux min–VC clampMAXIC max4.4.2Calculate Rbias maximum power dissipation:Pd Rbias= (Vaux max–VC clampMIN)2RbiasWhere:Vaux min: Vaux minimum voltageVaux max: Vaux maximum voltageVC ClampMAX:Maximum controllerclamp voltage, 16.0 VVC ClampMIN:Minimum controllerclamp voltage, 14.0 VIC max: Controller maximum bias current,use 4.2 mA4.4.3For example, if the minimum Vaux = 22 Vand the maximum Vaux = 28 VRbias = Vaux min–VC clampMAX =22 V–16 V = 1.429 KΩIC m a x 4.2 mA,use 1.43 KΩ1% resistorPd Rbias= (Vaux max–VC clampMIN)2= (28 V–14.0 V)2=137 mWRbias 1.43 KΩNote:Minimize the resistor value for low Vaux voltagelevels to avoid a voltage drop that may reduce the VCvoltage lower than required to drive the gate of theinternal MOSFET. Figure 5 –BK Resistor selection versus Blanking Time5.0Hook Up of the Evaluation Board5.1OV and UV resistors values are configured for a 3.3 Vinput voltage. If you are using the evaluationboard in a different input voltage level you have toadjust the resistor values by replacing R1, R2, R8and R9, or remove R2, R3, R9 and R10 to disable UVand OV. Please refer to the UV/OV section fordetails to set R1, R2, R8 and R9 proper values.5.2Verify that the jumpers J1 and J3 are installed formaster mode [across M] and no Jumper on J2.5.3Connect the positive terminal of PS1 power supplyto Vin1. Connect the ground terminal of PS1 to itslocal Gnd. Set the power supply to 3.3 V.Keep PS1 output disabled (OFF).5.4Connect the positive terminal of PS2 power supplyto Vin2. Connect the ground terminal of PS2 to itslocal Gnd. Set the power supply to 3.3 V. Keep PS2output disabled (OFF).5.5Connect the positive terminal of PS3 power supplyto Vaux1 and Vaux2. Connect the ground terminalof this power supply to Rtn1 and Rtn2. Set thepower supply to 12 V. Keep PS3 output disabled(OFF).5.6Connect the electronic load to the output betweenVout and Gnd. Set the load current to 10 A.5.7Enable (turn ON) PS1 power supply output.5.8Turn on the electronic load.5.9Verify that the electronic load input voltagereading is one diode voltage drop below 3.3 V.5.10Enable (turn ON) PS3 power supply output.5.11Verify that the electronic load voltage readingincreases to a few millivolts below 3.3 V. Thisverifies that the PI2121 (SiP1) internal MOSFET is inconduction mode.5.12D1 should be off. This verifies that there is nofault condition.5.13Reduce PS1 output voltage to 2 V,5.14D1 should turn on, this verifies that the circuit is inan under-voltage fault condition.5.15Increase PS1 output to 3.3 V, D1 should turn off,then increase PS1 output to 4 V, D1 should turn onindicating an over-voltage fault condition5.16Verify that Vin2 is at 0V. This verifies that thePI2121 (SiP2) internal FET is off.5.17D2 should be on. This is due to a reverse voltagefault condition caused by the bus voltage beinghigh with respect to the input voltage (Vin2).5.18Enable (turn ON) PS2 output.5.19Verify that both PS1 and PS2 are sharing loadcurrent evenly by looking at the supply current.5.20Disable (turn OFF) PS1, PS2 and PS3 outputs.5.21Enable (turn ON) PS2 output then Enable PS3 output. 5.22Verify that the electronic load voltage reading isfew millivolts below 3.3 V. This verifies that the PI2121(SiP2) internal MOSFET is in conduction mode.5.23D2 should be off. This verifies that there is nofault condition.5.24Reduce PS2 output voltage to 2 V,5.25D2 should turn on, this verifies that the circuit is inan under-voltage fault condition.5.26Increase PS2 output to 3.3 V, D2 should turn off,then increase PS2 output to 4 V, D2 should turn onindicating an over voltage fault condition.5.27Verify that Vin1 is at 0V. This verifies that thePI2121 (SiP1) internal FET is off.5.28D1 should be on. This is due to a reverse voltagefault condition caused by the bus voltage beinghigh with respect to the input voltage (Vin1).6.0Slave Mode: Slave Mode can be demonstrated in two setups; either by using one PI2121-EVAL1 evaluation boardas a single ORing function with both PI2121 effectively in parallel or two PI2121-EVAL1 evaluation boards to demonstrate a true redundant 48 A system. The followingtest steps uses a single PI2121-EVAL1 in a slave mode application.Note:In this experiment SiP 1 is configured in master mode and SiP2 is configured in slave mode.6.1BK pin (J1) of the master device will be connectedto ground [across M] while the slaved device BK pin(J3) is connected to VCC [across S]. Place a jumperacross J2 to connect slave pins together.6.2Connect the positive terminal of PS1 power supplyto Vin1. Connect the ground terminal of this powersupply to Gnd. Set the power supply to 3.3 V. KeepPS1 output disabled (OFF).6.3Connect the positive terminal of PS2 power supplyto Vin2. Connect the ground terminal of this powersupply to Gnd. Set the power supply to 3.3 V. KeepPS2 output disabled (OFF).6.4Connect the positive terminal of PS3 power supplyto Vaux1 and Vaux2. Connect the ground terminalof this power supply to Rtn1 and Rtn2. Set thepower supply to 12 V. Keep PS3 output disabled (OFF).6.5Connect the electronic load between Vout andGnd. Set the load current to 10 A.6.6Enable (Turn ON) PS2, and PS3 outputs, and keepPS1 output disabled (OFF).6.7Turn on the electronic load.6.8Verify that electronic load voltage drops to a diodedrop below PS2. This verifies that the SiP2 internal FET is off due to the Master (SiP1) not being on.6.9Enable (turn on) PS1 output:6.10Verify that the electronic load input voltagereading is a few millivolts below 3.3 V and PS1 and PS2 are sharing the load current evenly. This verifies that both internal MOSFET's of SiP1 and SiP2 are in conduction mode.7.0Input short circuit test7.1To emulate a real application, the BUS supplies forthis test should have a solid output source such as DC-DC converter that supplies high current and can be connected very close to the evaluation board to reduce stray parasitic inductance. Or use theprospective supply sources of the end application where the PI2121 will be used.7.2Stray parasitic inductance in the circuit cancontribute to significant voltage transientconditions, particularly when the internal MOSFET is turned-off after a reverse current fault has been detected. When a short is applied at the output of the input power sources and the evaluation board input (Vin), a large reverse current is sourced from theevaluation board output through the ORing internal MOSFET. The reverse current in theMOSFET may reach over 60 A in some conditions before the MOSFET is turned off. Such highcurrent conditions will store high energy even in a small parasitic element, and can be represented as . A 1 nH parasitic inductance with 60 A reverse current will generate 1.8 µJ. When the MOSFET is turned off, the stored energy will be released and will produce a high negative voltage at the MOSFET source and high positive voltage at the MOSFET drain. This event will create a high voltage difference across the drain and source of the MOSFET.7.3Apply a short at one of the inputs (Vin1 or Vin2)when the evaluation board is configured with both SiP's (SiP1 and SiP2) in master mode. The short can be applied electronically using a MOSFETconnected between Vin and Gnd or simply by connecting Vin to Gnd. Then measure theresponse time between when the short is applied and the SiP internal MOSFET is disconnected (or turned off). An example for PI2121 response time to an input short circuit is shown in Figure 6.Figure 6 –Plot of PI2121 response time to reverse current detection 12L i 28.0Internal MOSFET Rds(on) Measurement:8.1The SiP1 internal MOSFET Rds(on) can be measuredwith a voltmeter between the S1 and D1 Kelvinconnection. The potential between S1 and D1 isthe voltage drop across the internal MOSFET and:Rds(on) = V S1–V D1I inWhere:V S1–V D1: Voltage drop across the internal MOSFETI in: Input current.Note:The Rds(on) value is temperature dependent and thejunction temperature increases directly proportional topower dissipation.Thermal ImagesFigure 7a–PI2121 mounted on PI2121-EVAL1, Iout=24 A, TA=25°C, Air Flow=0 LFMFigure 7b–PI2121 mounted on PI2121-EVAL1 Iout=24 A,TA=25°C, Air Flow=200 LFMFigure 8a–PI2121-EVAL1 layout top layer. Scale 2.0:1Figure 8b–PI2121-EVAL1 layout mid layer 2. Scale 2.0:1Figure 8c–PI2121-EVAL1 layout mid layer 1. Scale 2.0:1Figure 8d–PI2121-EVAL1 layout Bottom layer. Scale 2.0:1分销商库存信息: VICORPI2121-EVAL1。
ir2101中文资料
数据表PD60043典型连接具有浮动通道设计的引导操作完全可操作+600V耐受性负转换电压dV/dt免疫网关驱动电源范围从10个欠压锁定3.3V，5V，15V逻辑输入兼容匹配传播延迟两个通道输入（IR2101）输入（IR2102）描述高压，高速功率MOSFET-igbt 驱动器独立的高低压侧参考输出通道。
专有的HVIC latchimmune CMOS技术支持加固单片结构。
逻辑输入标准CMOS LSTLOUTPUT，下降3.3Vlogic。
输出驱动器具有高脉冲电流缓冲高低压侧驱动程序包产品概要偏置600V最大130mA 270mA输出10开/关（典型）160 150ns延迟匹配50 ns IR2101 IR2102 IR2101 LeadSOIC LeadPDIP阶段设计的最小驱动器交叉传导。
浮动沟道can N沟道功率MOSFET高侧配置，工作电压高达600伏。
网站HOLO-COM-HIN-LIN-HIN-up-HOLO-COM-HIN-LIN-HIN-up-CC（参考引线分配修正引脚配置）。
图表仅显示电气连接。
请参阅我们的应用注意事项电路板布局。
第二章：IR2101/符号定义最小最大单元高压侧浮动电源电压-0.3 625高压侧浮动电源偏移电压HO高压侧浮动输出电压CC低压侧逻辑固定电源电压-0.3 25 L低压侧输出电压-0.3逻辑输入电压（HIN LIN）-0.3 0.3dV/dt允许的偏移电源电压瞬变50V/ns包装功耗导线pdip）导线soic）0.625Rth JA热电阻，连接导线pdip）导线soic）接头温度存储温度-55 150导线温度（焊接，10秒）300绝对最大额定值绝对最大额定值指示持续极限，超过该极限值可能会发生损坏设备。
所有电压参数均为绝对电压参考的热电阻功率耗散额定值，在安装在板上的静止空气条件下测量。
SymbolDefinition 最小最大单位高压侧浮动电源绝对电压高压侧浮动电源偏移电压注HO高压侧浮动输出电压CCLow side logicfixed supply voltage 10 20 Low side output voltage Logicinput voltage （HIN LIN）（IR2101）LIN）（IR2102）环境温度-40 125注释逻辑操作+600V。
ir2110中文资料_数据手册_参数
IR2110（-1-2）（S）的PBF / IR2113（-1-2）（S）的PBF功能框图铅定义符号说明 V乙 SD LIN V DD脉冲 GEN [R小号 Q V SS UV 检测延迟 HV水平转移 V CC脉冲过滤 UV检测 V DD / V CC水平转移 V DD / V CC水平转移 LO V小号 COM [R小号 Q [R小号 RQ HIN HO V DD逻辑供应 HIN高端栅极驱动器输出（HO）的逻辑输入，同相 SD逻辑输入关闭 LIN低端栅极驱动器输出（LO） 的逻辑输入，IR2110同相 V SS逻辑地 V B高端浮动供应 HO高端栅极驱动输出 V S高端浮动供应回报 V CC低端供应 LO低端栅极 驱动输出 COM低端回报 关断时间与V CC / V BS 电源电压的关系图9A.关机时间与温度的关系 0 50 100 150 200 250 10 12 14 16 18 20大.典型. 0 50 100 150 200 250 -50 -25 0 25 50 75 100 125温度（°C）大.典型. 0 50 100 150 200 250 02 46 8 10 12 14 16 18 20 VDD电源电压（V）马克斯 .典型 图 9C. 关断时间与V DD IR2110电源电压的关系图10A.上升时间与温度的关系 0 20 40 60 80 100 -50 -25 0 25 50 75 100 125温度（°C） 大.典型.图10B.打开上升时间与电压的关系 0 20 40 60 80 100 10 12 14 16 18 20 V BIAS IR2110电源电压（V）大.典型.图11A.关闭下降 时间与温度的关系 0 10 20三十 40 50 -50 -25 0 25 50 75 100 125温度（°C）大.典型. V CC / V BS 电源电压（V） 图19B. V DD 电源电流与V DD 电压的关系图20A.逻辑“1”输入电流与温度的关系 0 20 40 60 80 100 -50 -25 0 25 50 75 100 125温度 （°C）大.典型. 图17B. V BS 电源电流与电压的关系 0 100 200 300 400 500 10 12 14 16 18 20 V BS 浮动电源电压（V）大.典型. 图 18A. V CC 电源电流与温度的关系 0 125 250 375 500 625 -50 -25 0 25 50 75 100 125温度（°C）大.典型. 图18B. V CC 电源电流与电压 的关系 0 125 250 375 500 625 10 12 14 16 18 20 V CC 固定电源电压（V）大.典型. 图19A. V DD 电源电流与温度的关系 0 20 40 60 80 100 -50 -25 0 25 50 75 100 125温度（°C）大.典型. 0 10 20三十 40 50 60 02468 10 12 14 16 18 20 V DD 逻辑电源电压 PBF功能框图铅定义符号说明 V乙 SD LIN V DD脉冲 GEN [R小号 Q V SS UV检测延迟 HV水平转移 V CC脉冲过滤 UV检测 V DD / V CC水平转移 V DD / V CC水平转移 LO V小号 COM [R小号 Q [R小号 RQ HIN HO V DD逻辑供应 HIN高端栅极驱动器输 出（HO）的逻辑输入，同相 SD逻辑输入关闭 LIN低端栅极驱动器输出（LO）的逻辑输入，同相 V SS逻辑地 V B高端浮动供应 HO高端栅极驱动输出 V S高端浮动供应回报 V CC低端供应 LO低端栅极驱动输出 COM低端回报
IR2101S中文资料
Data Sheet No. PD60043-NFeaturesHIGH AND LOW SIDE DRIVERProduct Summary 1IR2101/IR2102 (S)Absolute Maximum RatingsAbsolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions.Note 1: Logic operational for V S of -5 to +600V. Logic state held for V S of -5V to -V BS . (Please refer to the Design Tip DT97-3 for more details).Recommended Operating ConditionsThe input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. The V S offset rating is tested with all supplies biased at 15V differential.IR2101/IR2102 (S)Static Electrical CharacteristicsV BIAS (V CC , V BS ) = 15V and T A = 25°C unless otherwise specified. The V IN , V TH and I IN parameters are referenced to COM. The V O and I O parameters are referenced to COM and are applicable to the respective output leads: HO or LO.Dynamic Electrical CharacteristicsV BIAS (V CC , V BS ) = 15V, C L = 1000 pF and T A = 25°C unless otherwise specified.IR2101/IR2102 (S)IR2101/IR2102 (S) Lead DefinitionsSymbol DescriptionHIN Logic input for high side gate driver output (HO), in phase (IR2101)HIN Logic input for high side gate driver output (HO), out of phase (IR2102)LIN Logic input for low side gate driver output (LO), in phase (IR2101)LIN Logic input for low side gate driver output (LO), out of phase (IR2102)V B High side floating supplyHO High side gate drive outputV S High side floating supply returnV CC Low side and logic fixed supplyLO Low side gate drive outputCOM Low side returnLead Assignments8 Lead PDIP8 Lead SOICIR2101IR2101S8 Lead PDIP8 Lead SOICIR2102IR2102SIR2101/IR2102 (S)Figure 1. Input/Output Timing DiagramHIN LINHO LOHIN LIN Figure 3. Delay Matching Waveform DefinitionsHIN LIN50%50%IR2101/IR2102 (S)IR2101/IR2102 (S)IR2101/IR2102 (S)IR2101/IR2102 (S)IR2101/IR2102 (S)IR2101/IR2102 (S)Case outlines。
EG-2102CA中文资料(epson)中文数据手册「EasyDatasheet - 矽搜」
EG-2102CA
Differential LV-PECL
EG-2121CA EG-2102CA LVDS
Remarks
f
53.125 MHz to 500 MHz
100 MHz to 700 MHz
53.125 MHz to 700 MHz
Please contact usfor available frequencies.
A PHPA
N PHPN
A DHPA
N DHPN
A LHPA
N LHPN
A VHPA
N VHPN
Frequency tolerance
HR: ±100 × 10 (-5°C to +85°C) GP: ±50 × 10 (0°C to +70°C)
PHRA PGPA
PHRN PGPN
DHRA DGPA
∆V
-
50 mV
Output change, DC characteristics
V
-
1.25 V Typ. 1.125 V to 1.375 V Offset, DC characteristics
∆V
-
150 mV
Offset change, DC characteristics
R
50
100
LV-PECL: Terminated to V -2.0 V LVDS: Connected between OUT to
为提供优质可靠产品,服务满足客户需求, 爱普生拓优科梦早日作出努力取得ISO9000系列认证,并已取得ISO9001为在日本国内外所有营业场所.我们还通过ISO / TS 16949认证是由 大型汽车制造厂商要求规格.
IR2125中文资料
Product Summary
VOFFSET
500V max.
IO+/-
1A / 2A
VOUT
12 - 18V
VCSth
230 mV
ton/off (typ.) 150 & 150 ns
Description
The IR2125 is a high voltage, high speed power MOSFET and IGBT driver with over-current limiting protection circuitry. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. Logic inputs are compatible with standard CMOS or LSTTL outputs. The output driver features a high pulse current buffer stage designed for minimum driver cross-conduction. The protection circuitry detects over-current in the driven power transistor and limits the gate drive voltage. Cycle by cycle shutdown is programmed by an external capacitor which directly controls the time interval between detection of the over-current limiting conditions and latched shut-
52421中文资料
52421 SOLID STATE THERMOSTAT CONTROLLERSpace Application Series...MiiHYBRID MICROELECTRONICS PRODUCTS DIVISIONFeatures:•Operates With RTD Temperature Sensor •Output Is Either “ON” Or “OFF”•Standard And Custom Factory Settings Of: - Resistance Control Set Points (Temperatures), - Hysteresis, (Minimum/Maximum) And- Timing (On/Off Delays)- Test (Load Power On/Off) Capability •Optional Mounting Configurations Available Applications:Meets The Demanding Requirements Of Space Platform Environments, Where PreciseTemperature Control Is Required.DESCRIPTIONM icropac’s Space level Thermostat Controller 52421 operates with external RTD (Resistance Temperature Device) temperature sensor and provides a power switched (On / Off) output within a temperature window. The RTD sensor is conditioned then controls a high-side MOSFET power switch for an external HEATER.M odels are available with dual channels providing either “OR” or “AND” configurations.W ired combinations of the “OR” configuration device, along with a single channel device, provides a tri-redundancy control system which guarantees both the power ON and power OFF states of the HeaterA BSOLUTE MAXIMUM RATINGSO perating Temperature (T A)........................................................................................................................-55°C to +125°C S torage Temperature (T STG).......................................................................................................................-65°C to +165°C M aximum Steady State V IN..............................................................................................................................+132 Volts DC P eak Transient Input V IN(T)...........................................................................................................+180 Volts DC for 5 Secs. S teady State Load Current…(Source or Sink)......................................................................................................1.1Amps.A PPLICABLE QUALITY STANDARDS OF MICROPAC INDUSTRIES, INC.•MIL-PRF-38534 Class H and Class K Qualified.•MIL-PRF-19500 JAN S Qualified.•MIL-STD-883 Test Methods and Procedures•ISO 9001 Quality StandardMicropac Industries cannot assume any responsibility for any circuits shown or represent that they are free from patent infringement.52421SOLID STATE THERMOSTAT CONTROLLER GENERAL ELECTRICAL SPECIFICATIONS(25°C unless otherwise stated)TEST CONDITIONS MIN MAX UNITSQuiescent Power Supply Current Terminal #1 = +126 VDCI LOAD (Terminals 3 and 4) = 0 ARTD = Max5.5mAOver voltage Current Spikes Between Terminals #1 and #2 = +180 VDCFor 5 secondsRTD = Min50.0mAHeater Current Terminals #3 - #4 = Heater LoadTerminal #1 = +120 VDC 1.1A Output Off Current Terminal #1 = +126 VDCBetween Terminals #3 and #4 =R shunt ≤ 10 ohmsRTD = MaxT CASE = 25°CT CASE = 125°C or T CASE = -55°C ±250±1uAmAFull Load Saturation Voltage Terminal #1 = +120 VDCTest Load, 120 ohms ±5%, 250 WattsRTD = MinV SAT, Measured between Terminals #4 and #2T CASE = 25°CT CASE = 125°C or T CASE = -55°C1.92.8VVSelf Test Input Impedance Terminal #1 = +120 VDCRTD = MaxAs Measured between Terminals #8 and #95,000,000ΩOn Time, Load Current Terminal #1 = +120 VDCRTD switched Max to MinMeasuring the 10-90 time of the rising HeaterLoad Current, Terminals #3 and #41.0mSOff Time, Load Current Terminal #1 = +120 VDCRTD switched Min to MaxMeasuring the 90-10 time of the fallingHeater Load Current, Terminals #3 and #42.0mSMicropac Industries cannot assume any responsibility for any circuits shown or represent that they are free from patent infringement.52421SOLID STATE THERMOSTAT CONTROLLERDUAL CHANNEL TERMINAL NUMBER DESCRIPTIONTERMINAL REF DESCRIPTION1Vin Positive power supply voltage2AGND Power return for all function3+H Current source for Heater (High Side)4-H Current return for Heater5RTD1-H Current source for RTD #16RTD1-L Current return RTD #17RTD1-S for RTD #1 Shield to case8ST1 Self Test #1, “ON”9ST1 Return Self test #1 CommonPackage DimensionsTYPICAL PRESET “RTD” PROFILES AVAILABLEP/N TBD P/N TBD P/N TBD P/N TBD P/N TBDTon-80°F-70°F-60°F-50°F-42°FToff-73°F-63°F-53°F-43°F -35°FP/N TBD P/N TBD P/N TBD P/N TBDTon-28°F-10°F0°F23°FToff-21°F-3°F7°F30°FRTD SENSORS NOT PROVIDED BY Micropac Industries, Inc.The above preset thresholds and switching levels are based on the use of standard 1000 ohm RTDs.Example: IEC-751, 1000 ohms at 0°C (ice point), resistance curve with an alpha of 0.003891 and withan error not to exceed 0.75 °F.Micropac Industries cannot assume any responsibility for any circuits shown or represent that they are free from patent infringement.52421SOLID STATE THERMOSTAT CONTROLLER`Micropac Industries cannot assume any responsibility for any circuits shown or represent that they are free from patent infringement.。
INA213AIDCKT中文资料
Reference Voltage
Supply
RSHUNT
Load
REF
GND
+2.7V to +26V
V+
CBYPASS 0.01mF
to
0.1mF
INA21x
OUT
R1
R3 IN-
Output
IN+
R2
R4
PRODUCT
INA210 INA211 INA212 INA213 INA214
GAIN
ELECTRICAL CHARACTERISTICS
Boldface limits apply over the specified temperature range, TA = –40°C to +125°C. At TA = +25°C, VSENSE = VIN+ – VIN–. INA210, INA213 and INA214: VS = +5V, VIN+ = 12V, VREF = VS/2, unless otherwise noted. INA211 and INA212: VS = +12V, VIN+ = 12V, VREF = VS/2, unless otherwise noted.
These devices operate from a single +2.7V to +26V power supply, drawing a maximum of 100µA of supply current. All versions are specified over the extended operating temperature range (–40°C to +125°C), and offered in an SC70 package.
IR2117S中文资料
FeaturesData Sheet No. PD60146 Rev NSINGLE CHANNEL DRIVERProduct SummaryIR2117(S)/IR2118(S) & (PbF) 1IR2117(S)/IR2118(S) & (PbF)2Absolute Maximum RatingsAbsolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured Note 1: Logic operational for V S of -5 to +600V. Logic state held for V S of -5V to -V BS . (Please refer to the Design Tip DT97-3 for more details).IR2117(S)/IR2118(S) & (PbF)3Dynamic Electrical CharacteristicsV BIAS (V CC , V BS ) = 15V, C L = 1000 pF and T A = 25°C unless otherwise specified. The dynamic electrical characteristics are measured using the test circuit shown in Figure 3.Static Electrical CharacteristicsV BIAS (V CC , V BS ) = 15V and T A = 25°C unless otherwise specified. The V IN , V TH and I IN parameters are referenced to COM. The V O and I O parameters are referenced to COM and are applicable to the respective output leads: HO or LO.IR2117(S)/IR2118(S) & (PbF) 4Functional Block Diagram (IR2118)IR2117(S)/IR2118(S) & (PbF)5SymbolDescriptionV CC Logic and gate drive supplyINLogic input for gate driver output (HO), in phase with HO (IR2117)IN Logic input for gate driver output (HO), out of phase with HO (IR2118)COM Logic groundV B High side floating supply HO High side gate drive output V SHigh side floating supply returnLead Assignments8 Lead PDIP 8 Lead SOICIR2118IR2118S12348765V CC IN COMV B HO VS12348765V CC IN COMV B HO V S8 Lead PDIP 8 Lead SOICIR2117IR2117S12348765V CC IN COMV B HO V S12348765V CC IN COMV B HO V SIR2117(S)/IR2118(S) & (PbF)6IR2117/IR2118Figure 2. Floating Supply Voltage Transient Test CircuitIN(IR2117)HOIN(IR2118)IR2117/IR2118<50 V/nsIR2117(S)/IR2118(S) & (PbF)7IR2117(S)/IR2118(S) & (PbF)8IR2117(S)/IR2118(S) & (PbF)9IR2117(S)/IR2118(S) & (PbF)10IR2117(S)/IR2118(S) & (PbF)11(A (A V S ()V S ()IR2117(S)/IR2118(S) & (PbF)12(A ()()()IR2117(S)/IR2118(S) & (PbF)13()t ()() ()IR2117(S)/IR2118(S) & (PbF)14() ()V S ()()IR2117(S)/IR2118(S) & (PbF)15t ()t ()IR2117(S)/IR2118(S) & (PbF)1602550751001251501E+21E+31E+41E+51E+6Frequency (Hz)J u n c t i o n T e m p e r a t u r e (°C )320V140V10V2550751001251501E+21E+31E+41E+51E+6Frequency (Hz)J u n c t i o n T e m p e r a t u r e (°C )320V 140V10V02550751001251501E+21E+31E+41E+51E+6Frequency (Hz)J u n c t i o n T e m p e r a t u r e (°C )320V 140V 10V2550751001251501E+21E+31E+41E+51E+6Frequency (Hz)J u n c t i o n T e m p e r a t u r e (°C )320V 140V10VCase outlinesIR2117(S)/IR2118(S) & (PbF)18Per SCOP 200-002IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105This product has been qualified per industrial levelData and specifications subject to change without notice. 4/2/2004。
ir2110中文资料_数据手册_参数
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IR2110（-1-2）（S）的PBF / IR2113（-1-2）（S）的PBF功能框图铅定义符号说明 V乙 SD LIN V DD脉冲 GEN [R小号 Q V SS UV 检测延迟 HV水平转移 V CC脉冲过滤 UV检测 V DD / V CC水平转移 V DD / V CC水平转移 LO V小号 COM [R小号 Q [R小号 RQ HIN HO V DD逻辑供应 HIN高端栅极驱动器输出（HO）的逻辑输入，同相 SD逻辑输入关闭 LIN低端栅极驱动器输出（LO） 的逻辑输入，IR2110同相 V SS逻辑地 V B高端浮动供应 HO高端栅极驱动输出 V S高端浮动供应回报 V CC低端供应 LO低端栅极 驱动输出 COM低端回报 关断时间与V CC / V BS 电源电压的关系图9A.关机时间与温度的关系 0 50 100 150 200 250 10 12 14 16 18 20大.典型. 0 50 100 150 200 250 -50 -25 0 25 50 75 100 125温度（°C）大.典型. 0 50 100 150 200 250 02 46 8 10 12 14 16 18 20 VDD电源电压（V）马克斯 .典型 图 9C. 关断时间与V DD IR2110电源电压的关系图10A.上升时间与温度的关系 0 20 40 60 80 100 -50 -25 0 25 50 75 100 125温度（°C） 大.典型.图10B.打开上升时间与电压的关系 0 20 40 60 80 100 10 12 14 16 18 20 V BIAS IR2110电源电压（V）大.典型.图11A.关闭下降 时间与温度的关系 0 10 20三十 40 50 -50 -25 0 25 50 75 100 125温度（°C）大.典型. V CC / V BS 电源电压（V） 图19B. V DD 电源电流与V DD 电压的关系图20A.逻辑“1”输入电流与温度的关系 0 20 40 60 80 100 -50 -25 0 25 50 75 100 125温度 （°C）大.典型. 图17B. V BS 电源电流与电压的关系 0 100 200 300 400 500 10 12 14 16 18 20 V BS 浮动电源电压（V）大.典型. 图 18A. V CC 电源电流与温度的关系 0 125 250 375 500 625 -50 -25 0 25 50 75 100 125温度（°C）大.典型. 图18B. V CC 电源电流与电压 的关系 0 125 250 375 500 625 10 12 14 16 18 20 V CC 固定电源电压（V）大.典型. 图19A. V DD 电源电流与温度的关系 0 20 40 60 80 100 -50 -25 0 25 50 75 100 125温度（°C）大.典型. 0 10 20三十 40 50 60 02468 10 12 14 16 18 20 V DD 逻辑电源电压 PBF功能框图铅定义符号说明 V乙 SD LIN V DD脉冲 GEN [R小号 Q V SS UV检测延迟 HV水平转移 V CC脉冲过滤 UV检测 V DD / V CC水平转移 V DD / V CC水平转HIN HO V DD逻辑供应 HIN高端栅极驱动器输 出（HO）的逻辑输入，同相 SD逻辑输入关闭 LIN低端栅极驱动器输出（LO）的逻辑输入，同相 V SS逻辑地 V B高端浮动供应 HO高端栅极驱动输出 V S高端浮动供应回报 V CC低端供应 LO低端栅极驱动输出 COM低端回报
ir2101中文资料_数据手册_参数
8-Lead SOIC IR2101S/IR2102S
8-Lead PDIP IR2101/IR2102
input is compatible with standard CMOS or LSTTL
output, down to 3.3V logic. The output drivers feature a high pulse current buffer stage designed for minimum
Min.
VS + 10 Note 1
VS 10 0 0 -40
Max.
VS + 20 600 VB 20 VCC VCC 125
Units
V °C
Note 1: Logic operational for VS of -5 to +600V. Logic state held for VS of -5V to -VBS. (Please refer to the Design Tip DT97-3 for more details).
driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in
the high side configuration which operates up to 600 volts.
IO+/-
130 mA / 270 mA
VOUT
10 - 20V
ton/off (typ.)
160 & 150 ns
Delay Matching
50 ns
phase with inputs (IR2102)
l321中文资料
Converter - Brake - Inverter Module(CBI2)Symbol Conditions Maximum Ratings VRRM1600VI FAV TC= 80°C; sine 180°19AI DAVM TC= 80°C; rectangular; d = 1/318AI FSM TVJ= 25°C; t = 10 ms; sine 50 Hz160APtot TC= 25°C85WSymbol Conditions Characteristic Values(TVJ = 25°C, unless otherwise specified)min.typ.max.VF IF= 10 A; TVJ= 25°C 1.3 1.6VTVJ= 125°C 1.3VI R VR= VRRM;TVJ= 25°C0.1mATVJ= 125°C1mAt rr VR= 100 V;IF= 10 A; di/dt = -10 A/µs1µsRthJC (per diode) 1.47K/WThree Phase Brake Chopper Three Phase Rectifier InverterVRRM = 1600V VCES= 1200 V VCES= 1200 VI DAVM = 26 A IC25= 20 A IC25= 20 AI FSM = 160 A VCE(sat)= 2.3 V VCE(sat)= 2.3 V15IXYS reserves the right to change limits, test conditions and dimensions.89Application: AC motor drives withq Input from single or three phase gridq Three phase synchronous orasynchronous motorq electric braking operationFeaturesq High level of integration - only one powersemiconductor module required for thewhole driveq Fast rectifier diodes for enhanced EMCbehaviourq NPT IGBT technology with lowsaturation voltage, low switchinglosses, high RBSOA and short circuitruggednessq Epitaxial free wheeling diodes withHiperfast and soft reverse recoveryq Industry standard package with insulatedcopper base plate and soldering pins forPCB mountingq Temperature sense includedSymbol Conditions Maximum RatingsVCES TVJ= 25°C to 150°C1200VVGESContinuous± 20VVGEMTransient± 30VIC25TC= 25°C20AIC80TC= 80°C15ARBSOA VGE = ±15 V; RG= 82 Ω; TVJ= 125°C ICM= 20AClamped inductive load; L = 100 µH VCEK ≤ VCESt SC VCE= 720 V; VGE= ±15 V; RG= 82 Ω; TVJ= 125°C10µs(SCSOA)non-repetitivePtot TC= 25°C105WSymbol Conditions Characteristic Values(TVJ = 25°C, unless otherwise specified)min.typ.max.Symbol Conditions Maximum RatingsIF25TC= 25°C17AIF80TC= 80°C11AEquivalent Circuits for SimulationConductionD11 - D16Rectifier Diode (typ. at TJ= 125°C)V= 1.11 V; R= 19 mΩT1 - T6 / D1 - D6IGBT (typ. at VGE= 15 V; TJ= 125°C)V= 1.32V; R= 131 mΩFree Wheeling Diode (typ. at TJ= 125°C)V= 1.39 V; R= 56 mΩT7 / D7IGBT (typ. at VGE= 15 V; TJ= 125°C)V= 1.32 V; R= 131 mΩFree Wheeling Diode (typ. at TJ= 125°C)V= 1.39 V; R= 56 mΩThermal ResponseD11 - D16Rectifier Diode (typ.)Cth1= 0.093 J/K; Rth1= 1.212 K/WCth2= 0.778 J/K; Rth2= 0.258K/WT1 - T6 / D1 - D6IGBT (typ.)Cth1= 0.09 J/K; Rth1= 0.954 K/WCth2= 0.809J/K; Rth2= 0.246 K/WFree Wheeling Diode (typ.)Cth1= 0.043 J/K; Rth1= 2.738 K/WCth2= 0.54 J/K; Rth2= 0.462 K/WT7 / D7IGBT (typ.)Cth1= 0.09 J/K; Rth1= 0.954 K/WCth2= 0.809 J/K; Rth2= 0.246 K/WFree Wheeling Diode (typ.)Cth1= 0.043 J/K; Rth1= 2.738 K/WCth2= 0.54 J/K; Rth2= 0.462 K/WSymbol Conditions Maximum RatingsV CES T VJ = 25°C to 150°C 1200V V GES Continuous ± 20V V GEM Transient ± 30V I C25T C = 25°C 20A I C80T C = 80°C15A RBSOA V GE = ±15 V; R G = 82 Ω; T VJ = 125°C I CM = 20A Clamped inductive load; L = 100 µHV CEK ≤ V CESt SCV CE = 720 V; V GE = ±15 V; R G = 82 Ω; T VJ = 125°C 10µs (SCSOA)non-repetitive P tot T C = 25°C 105WSymbolConditionsCharacteristic ValuesSymbol Conditions Maximum RatingsV RRM T VJ = 25°C to 150°C 1200V I F25T C = 25°C 17A I F80T C = 80°C 11ASymbol Conditions Characteristic ValuesDimensions in mm (1 mm = 0.0394")0102030405001002003004005000.00.40.81.21.6I FA P tot W K/W Z thJCFig. 41Fig. 6Fig. 112345670123456751015202530V CEV V CEA V G-di/dt46810121416V V GEI 01234V V FI FFig. 7Typ. output characteristics Fig. 8Typ. output characteristicsFig. 9Typ. transfer characteristicsFig. 10Typ. forward characteristics offree wheeling diodeFig. 11Typ. turn on gate chargeFig. 12Typ. turn off characteristics offree wheeling diodeFig. 17Reverse biased safe operating areaFig. 18Typ. transient thermal impedanceRBSOA0.000010.00010.0010.010.1110200400600800100012001400V CEts VFig. 19Typ. output characteristicsFig. 20Typ. forward characteristics offree wheeling diodeFig. 23Typ. transient thermal impedanceFig. 24Typ. thermistorresistance versustemperature123456V V CEI 0123451015202530VV FI FA 0.00.51.01.52.02.5E off mJ t0.000010.00010.0010.010.11100.00010.0010.010.1110ts Z thJC255075100125150T°C。
IR2110中文资料
摘要：介绍了IR2110的内部结构和特点，高压侧悬浮驱动的原理和自举元件的设计。
针对IR2110的不足提出了几种扩展应用的方案，并给出了应用实例。
关键词：悬浮驱动；栅电荷；自举；绝缘门极1引言在功率变换装置中，根据主电路的结构，其功率开关器件一般采用直接驱动和隔离驱动两种方式。
采用隔离驱动方式时需要将多路驱动电路、控制电路、主电路互相隔离，以免引起灾难性的后果。
隔离驱动可分为电磁隔离和光电隔离两种方式。
光电隔离具有体积小，结构简单等优点，但存在共模抑制能力差，传输速度慢的缺点。
快速光耦的速度也仅几十kHz。
电磁隔离用脉冲变压器作为隔离元件，具有响应速度快（脉冲的前沿和后沿），原副边的绝缘强度高，dv/dt 共模干扰抑制能力强。
但信号的最大传输宽度受磁饱和特性的限制，因而信号的顶部不易传输。
而且最大占空比被限制在50％。
而且信号的最小宽度又受磁化电流所限。
脉冲变压器体积大，笨重，加工复杂。
凡是隔离驱动方式，每路驱动都要一组辅助电源，若是三相桥式变换器，则需要六组，而且还要互相悬浮，增加了电路的复杂性。
随着驱动技术的不断成熟，已有多种集成厚膜驱动器推出。
如EXB840/841、EXB850/851、M57959L/AL、M57962L/AL、HR065等等，它们均采用的是光耦隔离，仍受上述缺点的限制。
美国IR公司生产的IR2110驱动器。
它兼有光耦隔离（体积小）和电磁隔离（速度快）的优点，是中小功率变换装置中驱动器件的首选品种。
2IR2110内部结构和特点IR2110采用HVIC和闩锁抗干扰CMOS制造工艺，DIP14脚封装。
具有独立的低端和高端输入通道；悬浮电源采用自举电路，其高端工作电压可达500V，dv/dt=±50V/ns，15V下静态功耗仅116mW；输出的电源端（脚3,即功率器件的栅极驱动电压）电压范围10～20V；逻辑电源电压范围（脚9）5～15V，可方便地与TTL，CMOS电平相匹配，而且逻辑电源地和功率地之间允许有±5V的偏移量；工作频率高，可达500kHz；开通、关断延迟小，分别为120ns和94ns；图腾柱输出峰值电流为2A。
RI-I02-114A-S1中文资料
FEATURES APPLICATIONSDESCRIPTIONRI-I02-114A-S1,,RI-I02-114B-S1SCBS829–NOVEMBER2006Tag-it™HF-I PRO TRANSPONDER INLAYSLARGE RECTANGLE•Product Authentication•ISO/IEC15693-2,-3;ISO/IEC18000-3Compliant•Ticketing•Stored Value•13.56-MHz Operating Frequency•256-Bit User Memory in8-Bit×32-Bit Blocks•User and Factory Lock Per Block•Application Family Identifier(AFI)•Fast Simultaneous Identification(Anti-Collision)•Password Protected Write Command•Command to Disable IC FunctionalityTexas Instruments Tag-it™HF-I pro transponder inlays consist of13.56-MHz high-frequency(HF)transponders that are compliant with the ISO/IEC15693and ISO/IEC18000-3global open standards.These products offer a user-accessible memory of256bits,organized in eight blocks,and an extended command set including password protect write available in five different antenna shapes,with frequency offset for integration into paper, PVC,or other substrates.The Tag-it HF-I pro transponder inlays are manufactured with TI’s patented laser tuning process to provide consistent read performance.Prior to delivery,the transponders undergo complete functional and parametric testing,in order to provide the high quality that customers have come to expect from TI.The Tag-it HF-I pro transponder inlays are well suited for a variety of applications including,but not limited to, product authentication,library,supply-chain management,asset management,and ticketing/stored value applications.Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.Tag-it is a trademark of Texas Instruments.PRODUCTION DATA information is current as of publication date.Copyright©2006,Texas Instruments Incorporated Products conform to specifications per the terms of the TexasInstruments standard warranty.Production processing does notnecessarily include testing of all parameters.RI-I02-114A-S1,,RI-I02-114B-S1SCBS829–NOVEMBER 2006SPECIFICATIONS (1)PART NUMBERRI-I02-114A-S1RI-I02-114B-S1Supported standardISO/IEC 15693-2,-3;ISO/IEC 18000-3Recommended operating frequency 13.56MHz13.86MHz ±200kHz 14.4MHz ±200kHz (includes frequency offset to Passive resonance frequency (at 25°C)(includes frequency offset to compensate further integration intocompensate PVC lamination)paper)Typical required activation field strength to read (at 25°C)94dB µA/m (2)94dB µA/m (3)Typical required activation field strength to write (at 25°C)97dB µA/m (2)97dB µA/m (3)Factory-programmed read-only number 64bitsMemory (user programmable)256bits organized in 8-bit ×32-bit blocksTypical programming cycles (at 25°C)100,000Data retention time (at 55°C)>10yearsSimultaneous identification of tags Up to 50tags per second (reader/antenna dependent)Antenna size 45mm ×76mm (~1.77in ×~2.99in)Foil width 48mm ±0.5mm (1.89in ±0.02in)Foil pitch 96mm +0.1mm/–0.4mm (~3.78in)Base material Substrate:PET (polyethylenetherephtalate);Antenna:aluminumOperating temperature–25°C to 70°CStorage temperature (single inlay)–40°C to 85°C (warpage may occur at upper temperature range)Storage temperature (on reel)–40°C to 40°CSingle-row tape wound on cardboard reel with 500-mm diameterReel outer width:approximately 60mm (~2.36in)DeliveryReel inner width:approximately 50mm (~1.97in)Hub diameter:76.2mm (3in)Typical quantity of good units per reel 5,000(1)For highest possible read-out coverage,operate readers at a modulation depth of 20%or higher.(2)After integration into paper (3)After PVC laminationSUPPORTED COMMAND SETREQUEST MODE (1)REQUESTREQUEST CODEINVENTORYADDRESSEDNON-ADDRESSEDAFI OPT.FLAGISO 15693Mandatory and Optional Commands Inventory 0x01ü––ü0/–Stay Quiet0x02–ü––0/–Read_Single_Block 0x20–üü––/1Write_Single_Block 0x21–üü––/1Lock_Block0x22–üü––/1TI Custom Commands Kill0xA4–ü–––/1WriteSingleBlockPwd 0xA5–ü–––/1(1)ü=Implemented,–=Not applicable2Submit Documentation FeedbackUser data(256bits)UID Number(64bits)AFI 0x060x080x090x0A BlockAddrU =UserLock0x0BPasswordRI-I02-114A-S1,,RI-I02-114B-S1SCBS829–NOVEMBER 2006MEMORY ORGANIZATION3Submit Documentation FeedbackIMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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SG3525,IR2110中文资料+引脚图+应用电路图
SG3525中文资料引脚图应用电路图随着电能变换技术的发展，功率MOSFET在开关变换器中开始广泛使用。
为此，美国硅通用半导体公司推出了SG3525，以用于驱动N沟道功率MOSFET。
SG3525是一种性能优良、功能齐全和通用性强的单片集成PWM控制芯片，它简单可靠及使用方便灵活，输出驱动为推拉输出形式，增加了驱动能力；内部含有欠压锁定电路、软启动控制电路、PWM 锁存器，有过流保护功能，频率可调，同时能限制最大占空比。
其性能特点如下：1)工作电压范围宽：8～35V。
2)内置5．1 V±1．0％的基准电压源。
3)芯片内振荡器工作频率宽100Hz～400 kHz。
4)具有振荡器外部同步功能。
5)死区时间可调。
为了适应驱动快速场效应管的需要，末级采用推拉式工作电路，使开关速度更陕，末级输出或吸入电流最大值可达400mA。
6)内设欠压锁定电路。
当输入电压小于8V时芯片内部锁定，停止工作(基准源及必要电路除外)，使消耗电流降至小于2mA。
7)有软启动电路。
比较器的反相输入端即软启动控制端芯片的引脚8，可外接软启动电容。
该电容器内部的基准电压Uref由恒流源供电，达到2．5V的时间为t=(2．5V／50μA)C，占空比由小到大(50％)变化。
8)内置PWM(脉宽调制)。
锁存器将比较器送来的所有的跳动和振荡信号消除。
只有在下一个时钟周期才能重新置位，系统的可靠性高。
l 脉宽调制器SG3525简介1．1 结构框图SG3525是定频PWM电路，采用原理16引脚标准DIP封装。
其各引脚功能如图1所示，内部原理框图如图2所示。
1．2 引脚功能说明直流电源Vs从脚15接入后分两路，一路加到或非门；另一路送到基准电压稳压器的输入端，产生稳定的元器件作为电源。
振荡器脚5须外接电容CT，脚6须外接电阻RT。
振荡器频率厂由外接电阻RT和电容CT决定，振荡器的输出分为两路，一路以时钟脉冲形式送至双稳态触发器及两个或非门；另一路以锯齿波形式送至比较器的同相输入端，比较器的反向输入端接误差放大器的输出，误差放大器的输出与锯齿波电压在比较器中进行比较，输出一个随误差放大器输出电压高低而改变宽度的方波脉冲，再将此方波脉冲送到或非门的一个输入端。
ERA中文资料（minicircuits）中文数据手册「EasyDatasheet-矽搜」
ERA中文资料（minicircuits）中文数据手册「EasyDatasheet-矽搜」ERAERA-SM50?低电量,高达+13.5 dBm 范围内输出JFREQ.GHzMODEL u NO.ERA-1ERA-2ERA-3ERA-1SM ERA-21SM ERA-2SM ERA-33SM ERA-3SM ERA-8SMf L - f U DC-8DC-6DC-3DC-8DC-8DC-6DC-3DC-3DC-20.11over frequency, GHz 234688.2——8.28.9————Min.@2 GHz91316911.213151617所有规格在25℃MAXIMUM DYNAMIC POWER (dBm)RANGE at 2 GHz*at 2 GHz*Output Input (1 dB (no Comp.)Typ. Min. dmg)12.0 10.013.0 11.012.5 9.012.0 10.012.6 10.613.0 11.013.5 11.512.5 9.012.5 —151513151515131313GAIN , dB T ypicalVSWR (:1)T yp.In OutNF IP3Device 3-f U** DC-3 3-f U ** I (dB) (dBm) DC-3P Current Volt.Typ. Typ. GHz GHz GHz GHz (mA ) (mW) (mA ) Typ Min Max4.3 264.0 263.5 254.3 264.7 264.0 26 1.5 1.81.3 1.41.5 —1.5 1.81.1 1.41.3 1.4 1.5 1.91.2 1.61.4 —1.5 1.91.3 1.91.2 1.61.25 —1.4 —1.82.275 33075 33075 33075 33075 33075 33075 33075 33065 2504040354040404035363.4 3.04.13.4 3.0 4.13.2 3.0 4.13.4 3.0 4.13.5 3.0 4.13.4 3.0 4.14.3 3.8 4.83.2 3.0 4.13.7 3.2 4.2ABSO-LUT E MAX.RAT ING 3DC OPERAT ING POWER 4at Pin 3T HERMAL CASE RESIS- ST YLE T ANCE θjcTyp.°C/W178155154183194160140159140Note BC O N N E C T I O NPRICE $Qty.(30)12.3 12.1 11.8 10.9 9.7 7.916.2 15.8 15.2 14.4 13.1 11.222.1 21.0 18.7 16.8 ——12.3 12.1 11.8 10.9 9.7 7.914.2 13.9 13.2 12.2 10.8 8.716.2 15.8 15.2 14.4 13.1 11.219.3 18.7 17.4 15.9 —22.1 21.0 18.7 16.8 —31.5 25.0 19.0 15.0 12.0———VV105 cb 1.37VV105 cb 1.52VV105 cb 1.67WW107 cb 1.42WW107 cb 1.57WW107 cb 1.57WW107 cb 1.72WW107 cb 1.72WW107 cb 1.223.9 28.5 1.6 —3.5 25 1.5 —3.1 25 1.4 1.8特征l l l l低热阻小型微波放大器频率范围,直流到8GHz,可用到10GHz高达18.4 dBm 的典型. （16.5 dBm 的分钟）输出功率模型识别M odelERA-1, ERA-1SM ERA-2, ERA-2SM ERA-21SM ERA-3, ERA-3SM ERA-33SM ERA-4,-4SM ERA-4X SM ERA-5, ERA-5SM ERA-50SM ERA-51SM ERA-5X SM ERA-6, ERA-6SM ERA-8SM 记号(s ee note below)122133344X 550515X 6E8绝对最大额定值工作温度：-45°C 至85°C 储存温度：-65℃至150℃Note: Prefix letter (optional) designates assembly———location. Suffix letters (optional) are for w aferidentification.prefix letter number注意：Aqueous was hable at 1 GHz for ERA-4,5,6, 4SM,4XSM ,5SM,5XSM, 50SM, 51SM, 6SM, 8SM.f u is the upper frequency limit for each model as s hown in the table;for ERA-8SM VSW R (In & Out) is s pecified at DC-1GHz & 1-4 GHz.*** Gain and VSW R are s pecified at 1.5 GHz.J Low frequency cutoff determined by external coupling capacitors .A. Environmental s pecifications and re-flow s oldering information available inGeneral Information Section.B. Units are non-hermetic unles s otherwis e noted. For details on cas edimens ions & finis hes s ee “Cas e Styles & Outline Drawings ”.C. Prices and Specifications s ubject to change without notice.D. For Quality Control Procedures s ee Table of Contents , Section 0,"Mini-Circuits Guarantees Quality" article. For Environmental Specifications s ee Amplifier Selection Guide.1. Model number des ignated by alphanumeric code mark ing.2. ERA-SM models available on tape and reel.3. Permanent damage may occur if any of thes e limits are exceeded. Thes eratings are not intended for continuous normal operation.4. Supply voltage mus t be connected to pin 3 through a bias res is tor in orderapplication.html. Reliability predictions are applicable at s pecified current & normal operating conditions .u ***suffix letterMTTF vs. Junction Temp.(For all ERA Models except ERA -5, ERA -5SM)1,000,000100,000平均无故障时间（年）10,0001,00010010180100120140160180 200Junction Temp. (?C)040618插入式及表面贴装ERAERA-SM中等功率,高达18.4 dBm 的输出JFREQ.GHzMODEL u NO.ERA-6ERA-4ERA-5ERA-6SM ERA-4SM NEW ERA-4X SM NEW ERA-5X SM f L - f UDC-4DC-4DC-4DC-4DC-4DC-4DC-40.11over frequency, GHz 234Min.@2 GHz10.5111610.5111216141616所有规格在25℃MAXIMUM DYNAMIC POWER (dBm)RANGE at 2 GHz*at 2 GHz*Output Input (1 dB (no Comp.)Typ. Min. dmg)17.9 1617.3 1518.4 16.517.9 1617.3 1517.0 15.017.8 16.518.1 16.518.4 16.517.2 16.020201320202013131313GAIN , dB T ypicalVSWR (:1)T yp.In OutNF IP3Device (dB) (dBm) DC-3 3-fU ** DC-3 3-f U ** I P Current Volt.Typ. Typ. GHz GHz GHz GHz (mA ) (mW) (mA ) Typ Min Max4.5 36 1.3 1.24.2 34 1.2 1.24.3 32.5 1.3 1.34.54.24.23.536343533 1.31.21.21.2 1.21.21.21.3 1.6 1.81.3 1.81.2 1.31.61.31.21.21.81.81.41.4120 650120 650120 650120120100120650650650650706565706565656565605.0 4.6 5.64.5 4.2 5.54.9 4.2 5.55.04.54.54.94.64.24.24.25.65.55.55.5ABSO-LUT E MAX.RAT ING 3DC OPERAT INGPOWER 4at Pin 3T HERMAL CASE RESIS- ST YLE T ANCE θjcTyp.°C/W170163278175168196133154283177Note BC O N N E C T I O NPRICE $Qty.(30)12.6 12.5 12.2 11.7 11.314.3 14.0 13.4 12.7 11.820.2 19.5 18.5 16.714.312.614.314.720.512.514.014.219.512.213.413.517.611.712.71 2.015.511.311.811.813.7VV105 cb 3.85VV105 cb 3.85VV105 cb 3.85WW107WW107WW107WW107cb 3.90cb 3.90cb 1.69cb 1.69ERA-51SM DC-4 18.0 17.4 16.1 14.8 12.5ERA-5SM DC-4 20.2 19.5 17.6 15.6 14.0ERA-50SM *** DC-1.5 20.7 19.4 18.3 ——4.1 33 1.1 1.24.3 32.5 1.3 1.33.5 32.5 1.3 — 1.2 1.91.2 1.31.2 —120 650120 650120 650 4.5 4.25.54.9 4.2 5.54.4 4.0 4.9WW107 cb 3.90WW107 cb 3.90WW107 cb 2.95查看建议的PCB 布局PL-075的时代车型R BIAS"1%" Resistor Values (ohms) for Optimum Biasing of ERA ModelsVccERA -1ERA -1SM 90.9113137162187215237261287309332357383412ERA -2ERA -2SM 88.7113137162187215237261287309332365392412ERA -21SM 88.7113137162187215237261287316340365392412ERA -3ERA -3SM 107133162191221249280309340365392422453475ERA -33SM 69.893.1115140165191215243267287316340365392ERA -4,4SM,4XSM38.352.366.580.695.3110127143158174187205221237ERA -5,5SM33.248.763.478.795.3110124140158174187205221232ERA -50SM,ERA -6,-51SM,5XSM ERA -6SM40.230.153.643.268.156.282.569.897.684.511397.612711314 3127158140174154191169205182221196237210ERA -8SM88.7118143174200226255280309340365392422453典型偏置配置7891011121314151617181920MTTF 与结温. （E RA-5,E RA-5SM ）1,000NSN 指南MCL NO.NSN5962-01-459-90755996-01-516-54385962-01-459-74105962-01-459-9314ERA-1SM ERA-3SM ERA-4SM ERA-5SM引脚连接PORT RF IN RF OUT DCCASE GND NOT USED DEM O BOARDcb 1332,4—ERA-T B平均无故障时间（年）100101140160180结温. （C ）( C)200220可用的设计师套装KIT NO.Model TypeNo. of Units in KitDes criptionPrice $per k itK1-ERA K2-ERA K1-ERA SM K2-ERA SM K3-ERA SM ERA ERA ERA -SM ERA -SM ERA -SM 302030203010每1,2,310每4,5 10每撒上,撒下,3SM 的10每4SM ,5SM 的10每4SM ,5SM ,6SM 的49.9569.9549.9569.9599.95040618。
LT1121HV资料
12ELECTRICAL CHARACTERISTICSThe ● denotes specifications which apply over the full operating temperature range, otherwise specifications are T J = 25°C. PARAMETER CONDITIONS MIN TYP MAX UNITS Minimum Input Voltage I LOAD = 500mA, T J > 0°C0.9 1.05V (Notes 5,14)I LOAD = 500mA, T J < 0°C0.9 1.10V ADJ Pin Voltage (Notes 4, 5)V IN = 1.5V, I LOAD = 1mA196200204mV1.15V < V IN < 10V, 1mA < I LOAD < 500mA●193200206mV Regulated Output Voltage LT3021-1.2V IN = 1.5V, I LOAD = 1mA 1.176 1.200 1.224V (Note 4) 1.5V < V IN < 10V, 1mA < I LOAD < 500mA● 1.157 1.200 1.236V LT3021-1.5V IN = 1.8V, I LOAD = 1mA 1.470 1.500 1.530V1.8V < V IN < 10V, 1mA < I LOAD < 500mA● 1.447 1.500 1.545VLT3021-1.8V IN = 2.1V, I LOAD = 1mA 1.764 1.800 1.836V2.1V < V IN < 10V, 1mA < I LOAD < 500mA● 1.737 1.800 1.854V Line Regulation (Note 6)LT3021∆V IN = 1.15V to 10V, I LOAD = 1mA●–1.750+1.75mV LT3021-1.2∆V IN = 1.5V to 10V, I LOAD = 1mA●–10.5010.5mVLT3021-1.5∆V IN = 1.8V to 10V, I LOAD = 1mA●–13013mVLT3021-1.8∆V IN = 2.1V to 10V, I LOAD = 1mA●–15.8015.8mV Load Regulation (Note 6)LT3021V IN = 1.15V, ∆I LOAD = 1mA to 500mA–20.42mV LT3021-1.2V IN = 1.5V, ∆I LOAD = 1mA to 500mA–616mVLT3021-1.5V IN = 1.8V, ∆I LOAD = 1mA to 500mA–7.5 1.57.5mVLT3021-1.8V IN = 2.1V, ∆I LOAD = 1mA to 500mA–929mV Dropout Voltage (Notes 7, 12)I LOAD = 10mA4575mVI LOAD = 10mA●110mVI LOAD = 500mA155190mVI LOAD = 500mA●285mV GND Pin Current I LOAD = 0mA●110250µA V IN = V OUT(NOMINAL) + 0.4V I LOAD = 10mA920µA (Notes 8, 12)I LOAD = 100mA 2.25mAI LOAD = 500mA● 6.2010mA Output Voltage Noise C OUT = 4.7µF, I LOAD = 500mA, BW = 10Hz to 100kHz, V OUT = 1.2V300µV RMS ADJ Pin Bias Current V ADJ = 0.2V, V IN = 1.2V (Notes 6, 9)2050nA Shutdown Threshold V OUT = Off to On●0.610.9V V OUT = On to Off●0.250.61V SHDN Pin Current (Note 10)V SHDN = 0V, V IN = 10V●±1µA V SHDN = 10V, V IN = 10V●3 9.5µA Quiescent Current in Shutdown V IN = 6V, V SHDN= 0V39µA Ripple Rejection (Note 6)LT3021V IN – V OUT = 1V, V RIP = 0.5V P-P, f RIPPLE = 120Hz,70dBI LOAD = 500mALT3021-1.2V IN – V OUT = 1V, V RIPPLE = 0.5V P-P, f RIPPLE = 120Hz,60dBI LOAD = 500mALT3021-1.5V IN – V OUT = 1V, V RIPPLE = 0.5V P-P, f RIPPLE = 120Hz,58dBI LOAD = 500mALT3021-1.8V IN – V OUT = 1V, V RIPPLE = 0.5V P-P, f RIPPLE = 120Hz,56dBI LOAD = 500mA3 3021fa45678910113021faThe LT3021 regulator has internal thermal limiting (with hysteresis) designed to protect the device during overload conditions. For normal continuous conditions, do not exceed the maximum junction temperature rating of 125°C.Carefully consider all sources of thermal resistance from junction to ambient including other heat sources mounted in proximity to the LT3021.The underside of the LT3021 DH package has exposed metal (14mm 2) from the lead frame to where the die is attached.This allows heat to directly transfer from the die junction to the printed circuit board metal to control maximum operating junction temperature. The dual-in-line pin ar-rangement allows metal to extend beyond the ends of the package on the topside (component side) of a PCB. Con-nect this metal to GND on the PC B. The multiple IN and OUT pins of the LT3021 also assist in spreading heat to the PCB.The LT3021 S8 package has pin 4 fused with the lead frame. This also allows heat to transfer from the die to the printed circuit board metal, therefore reducing the thermal resistance. Copper board stiffeners and plated through-holes can also be used to spread the heat generated by power devices.The following tables list thermal resistance for several different board sizes and copper areas for two different packages. Measurements were taken in still air on 3/32"FR-4 board with one ounce copper.Table 1. Measured Thermal Resistance For DH PackageCOPPER AREA THERMAL RESISTANCETOPSIDE*BACKSIDE BOARD AREA (JUNCTION-TO-AMBIENT)2500mm22500mm22500mm 230°C/W 900mm 22500mm 22500mm 235°C/W 225mm 22500mm 22500mm 250°C/W 100mm 22500mm 22500mm 255°C/W 50mm 22500mm 22500mm 265°C/WTable 2. Measured Thermal Resistance For S8 PackageCOPPER AREATHERMAL RESISTANCE TOPSIDE*BACKSIDE BOARD AREA (JUNCTION-TO-AMBIENT)2500mm 22500mm 22500mm 270°C/W 1000mm 22500mm 22500mm 270°C/W 225mm 22500mm 22500mm 278°C/W 100mm 22500mm 22500mm 284°C/W 50mm22500mm22500mm296°C/W*Device is mounted on topside.Calculating Junction TemperatureExample: Given an output voltage of 1.2V, an input voltage range of 1.8V ±10%, an output current range of 1mA to 500mA, and a maximum ambient temperature of 70°C,what will the maximum junction temperature be for an application using the DH package?The power dissipated by the device is equal to:I OUT(MAX)(V IN(MAX) – V OUT ) + I GND (V IN(MAX))whereI OUT(MAX) = 500mA V IN(MAX) = 1.98VI GND at (I OUT = 500mA, V IN = 1.98V) = 10mA soP = 500mA(1.98V – 1.2V) + 10mA(1.98V) = 0.41W The thermal resistance is in the range of 35°C /W to 70°C/W depending on the copper area. So the junction temperature rise above ambient is approximately equal to:0.41W(52.5°C/W) = 21.5°CThe maximum junction temperature equals the maximum junction temperature rise above ambient plus the maxi-mum ambient temperature or:T JMAX = 21.5°C + 70°C = 91.5°C Protection FeaturesThe LT3021 incorporates several protection features that make it ideal for use in battery-powered circuits. In addi-tion to the normal protection features associated with monolithic regulators, such as current limiting and ther-mal limiting, the device also protects against reverse-input voltages, reverse-output voltages and reverse output-to-input voltages.Current limit protection and thermal overload protection protect the device against current overload conditions at the output of the device. For normal operation, do not exceed a junction temperature of 125°C.The IN pins of the device withstand reverse voltages of 10V. The LT3021 limits current flow to less than 1µA and no negative voltage appears at OUT. The device protects both itself and the load against batteries that are plugged in backwards.APPLICATIO S I FOR ATIOW UUU123021faThe LT3021 incurs no damage if OUT is pulled below ground. If IN is left open circuit or grounded, OUT can be pulled below ground by 10V. No current flows from the pass transistor connected to OUT. However, current flows in (but is limited by) the resistor divider that sets the output voltage. C urrent flows from the bottom resistor in the divider and from the ADJ pin’s internal clamp through the top resistor in the divider to the external circuitry pulling OUT below ground. If IN is powered by a voltage source,OUT sources current equal to its current limit capability and the LT3021 protects itself by thermal limiting. In this case, grounding SHDN turns off the LT3021 and stops OUT from sourcing current.The LT3021 incurs no damage if the ADJ pin is pulled above or below ground by 10V. If IN is left open circuit or grounded and ADJ is pulled above ground, ADJ acts like a 25k resistor in series with a 1V clamp (one Schottky diode in series with one diode). ADJ acts like a 25k resistor in series with a Schottky diode if pulled below ground. If IN is powered by a voltage source and ADJ is pulled below its reference voltage, the LT3021 attempts to source its current limit capability at OUT. The output voltage in-creases to V IN – V DROPOUT with V DROPOUT set by whatever load current the LT3021 supports. This condition can potentially damage external circuitry powered by the LT3021 if the output voltage increases to an unregulated high voltage. If IN is powered by a voltage source and ADJ is pulled above its reference voltage, two situations can occur. If ADJ is pulled slightly above its reference voltage,the LT3021 turns off the pass transistor, no output current is sourced and the output voltage decreases to either the voltage at ADJ or less. If ADJ is pulled above its no load recovery threshold, the no load recovery circuitry turns on and attempts to sink current. OUT is actively pulled low and the output voltage clamps at a Schottky diode above ground. Please note that the behavior described above applies to the LT3021 only. If a resistor divider is con-nected under the same conditions, there will be additional V/R current.In circuits where a backup battery is required, several different input/output conditions can occur. The output voltage may be held up while the input is either pulled to ground, pulled to some intermediate voltage or is left openAPPLICATIO S I FOR ATIOW UUU circuit. In the case where the input is grounded, there is less than 1µA of reverse output current.If the LT3021 IN pin is forced below the OUT pin or the OUT pin is pulled above the IN pin, input current drops to less than 10µA typically. This occurs if the LT3021 input is connected to a discharged (low voltage) battery and either a backup battery or a second regulator circuit holds up the output. The state of the SHDN pin has no effect on the reverse output current if OUT is pulled above IN.Input Capacitance and StabilityThe LT3021 is designed to be stable with a minimum capacitance of 3.3µF placed at the IN pin. Ceramic capaci-tors with very low ESR may be used. However, in cases where a long wire is used to connect a power supply to the input of the LT3021 (and also from the ground of the LT3021 back to the power supply ground), use of low value input capacitors combined with an output load current of 20mA or greater may result in an unstable application. This is due to the inductance of the wire forming an LC tank circuit with the input capacitor and not a result of the LT3021 being unstable.The self-inductance, or isolated inductance, of a wire is directly proportional to its length. However, the diameter of a wire does not have a major influence on its self-inductance. For example, the self inductance of a 2-AWG isolated wire with a diameter of 0.26 in. is about half the inductance of a 30-AWG wire with a diameter of 0.01 in.One foot of 30-AWG wire has 465nH of self inductance.The overall self-inductance of a wire can be reduced in two ways. One is to divide the current flowing towards the LT3021 between two parallel conductors and flows in the same direction in each. In this case, the farther the wires are placed apart from each other, the more inductance will be reduced, up to a 50% reduction when placed a few inches apart. Splitting the wires basically connects two equal inductors in parallel. However, when placed in close proximity from each other, mutual inductance is added to the overall self inductance of the wires. The most effective way to reduce overall inductance is to place the forward and return-current conductors (the wire for the input and the wire for ground) in very close proximity. Two 30-AWG wires separated by 0.02 in. reduce the overall self-induc-tance to about one-fifth of a single isolated wire.133021faAPPLICATIO S I FOR ATIOW UUU If the LT3021 is powered by a battery mounted in close proximity on the same circuit board, a 3.3µF input capaci-tor is sufficient for stability. However, if the LT3021 is powered by a distant supply, use a larger value input capacitor following the guideline of roughly 1µF (in addi-tion to the 3.3µF minimum) per 8 inches of wire length. As power supply output impedance may vary, the minimum input capacitance needed to stabilize the application mayalso vary. Extra capacitance may also be placed directly on the output of the power supply; however, this will require an order of magnitude more capacitance as opposed to placing extra capacitance in close proximity to the LT3021.Furthermore, series resistance may be placed between the supply and the input of the LT3021 to stabilize the appli-cation; as little as 0.1Ω to 0.5Ω will suffice.14Information furnished by Linear Technology C orporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.15163021faPART NUMBER DESCRIPTIONCOMMENTSLT1121/LT1121HV 150mA, Micropower LDOs V IN : 4.2V to 30V/36V, V OUT : 3.75V to 30V, V DO = 0.42V, I Q = 30µA,I SD = 16µA, Reverse-Battery Protection, SOT-223, S8, Z Packages LT1129700mA, Micropower LDOV IN : 4.2V to 30V, V OUT : 3.75V to 30V, V DO = 0.4V, I Q = 50µA, I SD = 16µA,DD, SOT-223, S8, TO220-5, TSSOP20 PackagesLT1761100mA, Low Noise Micropower LDOV IN : 1.8V to 20V, V OUT : 1.22V to 20V, V DO = 0.3V, I Q = 20µA, I SD < 1µA,Low Noise: < 20µV RMSP-P , Stable with 1µF Ceramic Capacitor,ThinSOT PackageLT1762150mA, Low Noise Micropower LDO V IN : 1.8V to 20V, V OUT : 1.22V to 20V, V DO = 0.3V, I Q = 25µA, I SD < 1µA,Low Noise: <20µV RMSP-P , MS8 PackageLT1763500mA, Low Noise Micropower LDO V IN : 1.8V to 20V, V OUT : 1.22V to 20V, V DO = 0.3V, I Q = 30µA, I SD < 1µA,Low Noise: < 20µV RMSP-P , S8 PackageLT1764/LT1764A3A, Low Noise, Fast Transient Response LDOsV IN : 2.7V to 20V, V OUT : 1.21V to 20V, V DO = 0.34V, I Q = 1mA, I SD < 1µA,Low Noise: <40µV RMSP-P , “A” Version Stable with Ceramic Capacitors,DD, TO220-5 PackagesLTC1844150mA, Low Noise, Micropower VLDO V IN : 1.6V to 6.5V, V OUT(MIN) = 1.25V, V DO = 0.09V, I Q = 35µA,I SD < 1µA, Low Noise: < 30µV RMS , ThinSOT PackageLT1962300mA, Low Noise Micropower LDOV IN : 1.8V to 20V, V OUT : 1.22V to 20V, V DO = 0.27V, I Q = 30µA, I SD < 1µA,Low Noise: < 20µV RMSP-P , MS8 PackageLT1963/LT1963A1.5A, Low Noise, Fast Transient Response LDOsV IN : 2.1V to 20V, V OUT : 1.21V to 20V, V DO = 0.34V, I Q = 1mA, I SD < 1µA,Low Noise: < 40µV RMSP-P , “A” Version Stable with Ceramic Capacitors,DD, TO220-5, SOT223, S8 PackagesLT301050mA, High Voltage, Micropower LDOV IN : 3V to 80V, V OUT : 1.275V to 60V, V DO = 0.3V, I Q = 30µA, I SD < 1µA,Low Noise: <100µV RMSP-P , Stable with 1µF Output Capacitor, Exposed MS8 PackageLT3020100mA, Low Voltage LDOV IN : 0.9V to 10V, V OUT : 0.2V to 5V (min), V DO = 0.15V, I Q = 120µA,Noise: <250µV RMSP-P , Stable with 2.2µF Ceramic Capacitors,DFN-8, MS8 PackagesLTC3025300mA, Low Voltage Micropower LDO V IN : 0.9V to 5.5V, V OUT : 0.4V to 3.6V (min), V DO = 0.05V, I Q = 54µA,Stable with 1µF Ceramic Capacitors, DFN-6 PackageLTC30261.5A, Low Input Voltage VLDO RegulatorV IN : 1.14V to 3.5V (Boost Enabled), 1.14V to 5.5V (with External 5V),V DO = 0.1V, I Q = 950µA, Stable with 10µF Ceramic Capacitors, 10-Lead MSOP and DFN-10 PackagesLT3150Low V IN , Fast Transient Response, VLDO ControllerV IN : 1.1V to 10V, V OUT : 1.21V to 10V, V DO = Set by External MOSFET R DS(ON), 1.4MHz Boost Converter Generates Gate Drive, SSOP16 PackageLT/TP 0705 500 • PRINTED IN USA© LINEAR TECHNOLOGY CORPORA TION 2005Linear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417(408) 432-1900 ● FAX: (408) 434-0507 ● RELATED PARTS。
IR2122;中文规格书,Datasheet资料
Preliminary Data Sheet No. PD60130-KCURRENT SENSING SINGLE CHANNEL DRIVERProduct Summary 1FeaturesIR2122(S )IR2122(S)2Absolute Maximum RatingsAbsolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-eters are absolute voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are measured Note 1: Logic operational for V S of -5 to +600V. Logic state held for V S of -5V to -V BS . (Please refer to the Design TipDT97-3 for more details).Recommended Operating ConditionsThe Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the recommended conditions. The V S offset rating is tested with all supplies biased at 15V differential.IR2122(S)3Dynamic Electrical CharacteristicsV BIAS (V CC , V BS ) = 15V, C L = 1000 pF and T A = 25°C unless otherwise specified. The dynamic electrical characteristics are measured using the test circuit shown in Figure 3.IR2122(S)4Lead DefinitionsLeadSymbol DescriptionV CC Logic and gate drive supplyLogic input for gate driver output (HO), out of phase with HO Indicates over-current shutdown has occurred, negative logic COM Logic groundV B High side floating supply HO High side gate drive output V S High side floating supply returnCSCurrent sense input to current sense comparatorFunctional Block DiagramLead Assignments8 Lead PDIP 8 Lead SOICIR2122IR2122SFAULT INIR2122(S)5分销商库存信息: IRIR2122。
IR2110相关知识(精华版)
请问怎么确定IR2110能驱动多大的MOS管啊？手册上IR2110的输出电压是10—20V,电流是2A,MOS管是电压驱动型，要2A的电流有什么用啊？随着PWM技术在变频、逆变频等领域的运用越来越广泛，以及IGBT、Power MOSFET等功率性开关器件的快速发展，使得PWM控制的高压大功率电源向着小型化、高频化、智能化、高效率方向发展。
本文采用电压脉宽型PWM控制芯片SG3525A，以及高压悬浮驱动器IR2110，用功率开关器件IGBT模块方案实现高频逆变电源。
另外,用单片机控制技术对此电源进行控制，使整个系统结构简单，并实现了系统的数字智能化。
SG3525A性能和结构SG3525A是电压型PWM集成控制器，外接元器件少,性能好，包括开关稳压所需的全部控制电路。
其主要特性包括：外同步、软启动功能；死区调节、欠压锁定功能；误差放大以及关闭输出驱动信号等功能;输出级采用推挽式电路结构，关断速度快，输出电流±400mA；可提供精密度为5V±1%的基准电压;开关频率范围100Hz~400KHz.其内部结构主要包括基准电压源、欠压锁定电路、锯齿波振荡器、误差放大器等,如图1所示。
IR2110性能和结构IR2110是美国IR公司生产的高压、高速PMOSFET和IGBT的理想驱动器.该芯片采用HVIC和闩锁抗干扰制造工艺，集成DIP、SOIC封装.其主要特性包括：悬浮通道电源采用自举电路，其电压最高可达500V;功率器件栅极驱动电压范围10V~20V；输出电流峰值为2A; 逻辑电源范围5V~20V，而且逻辑电源地和功率地之间允许+5V的偏移量；带有下拉电阻的COMS施密特输入端，可以方便地与LSTTL和CMOS 电平匹配；独立的低端和高端输入通道,具有欠电压同时锁定两通道功能；两通道的匹配延时为10ns;开关通断延时小，分别为120ns和90ns;工作频率达500kHz。
其内部结构主要包括逻辑输入，电平转换及输出保护等,如图2所示.设计原理高压侧悬浮驱动的自举原理IR2110用于驱动半桥的电路如图3所示。
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shutdown time n Output in phase with input
VOFFSET IO+/VOUT VCSth
5V max. 1A / 2A 12 - 18V 230 mV
Logic “1” Input Voltage
14
Logic “0” Input Voltage
15
CS Input Positive Going Threshold
16
CS Input Negative Going Threshold
17
High Level Output Voltage, VBIAS - VO
The Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the recommended conditions. The VS offset rating is tested with all supplies biased at 15V differential.
24
VCC Supply Undervoltage Positive Going
25
Threshold
VCC Supply Undervoltage Negative Going 26 Threshold
2.2 —
—
V
VCC = 12V to 18V
—
— 0.8
VCC = 12V to 18V
150 230 320
Symbol
VIH VIL VCSTH+ VCSTHVOH VOL IQCC IIN+ IINICS+ ICSVCCUV+
VCCUV-
IERR
IERR+
IERRIO+
IO-
Parameter
Value
Definition
Figure Min. Typ. Max. Units Test Conditions
mA
ERR > VERR+
ERR Pull-Down Current
29
16 30 —
VIN = 0V
Output High Short Circuit Pulsed Current
30
1.0 1.6 —
VO = 0V, VIN = 5V
PW ≤ 10 µs
A
Output Low Short Circuit Pulsed Current
VBIAS (VCC) = 15V, CL = 3300 pF and TA = 25°C unless otherwise specified. The dynamic electrical characteristics are defined in Figures 2 through 5.
Symbol
31
2.0 3.3 —
VO = 15V, VIN = 0V
PW ≤ 10 µs
CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL B-93
元器件交易网
IR2121
Functional Block Diagram
V CC UV
DETECT
元器件交易网
Data Sheet No. PD-6.018D
IR2121
CURRENT LIMITING LOW SIDE DRIVER
Features
Product Summary
n Gate drive supply range from 12 to 18V n Undervoltage lockout n Current detection and limiting loop to limit driven
ton/off (typ.) Package
150 & 150 ns
Typical Connection
VCC
VCC
VCC
IN
IN
OUT
ERR
CS
COM
VS
TO LOAD
CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL B-91
元器件交易网
IN
1.8V
PRE DRIVER
ERR
ERROR TIMING
COM
1.8V
VCC
BUFFER
OUT
500 ns BLANK
VS 0.23V
-
+
CS
AMPLIFER
COMPARATOR
Lead Definitions
Lead Symbol Description
VCC IN
ERR
Logic and gate drive supply Logic input for gate driver output (OUT), in phase with OUT Serves multiple functions; status reporting, linear mode timing and cycle by cycle logic shutdown
Description
The IR2121 is a high speed power MOSFET and IGBT driver with over-current limiting protection circuitry. Latch immune CMOS technology enables ruggedized monolithic construction. Logic inputs are compatible with standard CMOS or LSTTL outputs. The output driver features a high pulse current buffer stage designed for minimum cross-conduction. The protection circuitry detects over-current in the driven power transistor and limits the gate drive voltage. Cycle-by-cycle shutdown is programmed by an external capacitor which directly controls the time interval between detection of the over-current limiting condition and latched shutdown. The output can be used to drive an N-channel power MOSFET or IGBT in the low side configuration.
ton toff tsd tr tf tcs terr
Parameter Definition
Turn-On Propagation Delay Turn-Off Propagation Delay ERR Shutdown Propagation Delay Turn-On Rise Time Turn-Off Fall Time CS Shutdown Propagation Delay CS to ERR Pull-Up Propagation Delay
—
— 1.0
VCS = 0V
8.3 8.9 9.6
V 7.3 8.0 8.7
ERR Timing Charge Current
27
65
100 130 µA VIN = 5V, VCS = 3V
ERR < VERR+
ERR Pull-Up Current
28
8.0 15 —
VIN = 5V, VCS = 3V
VBIAS (VCC) = 15V and TA = 25°C unless otherwise specified. The VIN, VTH and IIN parameters are referenced to COM. The VO and IO parameters are referenced to VS .
IR2121
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are measured under board mounted and still air conditions.
Figure
7 8 9 10 11 12 13
Min.
— — — — — — —
Value
Typ. Max. Units
150 200 ns
150 190
1.7 2.2 µs
43 60
ns
26 35
0.7 1.2
µs
9.0 12
Test Conditions
CERR = 270 pF
Static Electrical Characteristics