电路原理_skja_45
电路原理_skja_01
i(t )
1 2 1 2 Li ( t ) (t ) 0 2 2L
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电容(capacitor)元件
一、元件特性 描述电容的两个基本变量: u, q i + u + C
def
对于线性电容，有：
q =Cu
–
–
q C u
C 称为电容器的电容
电容 C 的单位：F (法)
+
uRi
k
u
电阻R单位名称：欧(姆)
符号:
令
G称为电导 单位名称：西(门子) 符号: S (Siemens) G i 则 欧姆定律表示为 i G u
G 1/R
+
u
线性电阻元件的伏安特性为 一条过原点的直线
R tg
u
0
i
线性电阻R是一个与电压和电流无关的常数。
(2) 电阻的电压和电流的参考方向相反 i R (G)
四、电感和电容的串并联 电感的串联
Leq Lk
k 1 n
电感的并联
n 1 1 Leq k 1 Lk n 1 1 Ceq k 1 C k
电容的串联
电容的并联
C eq C k
k 1
n
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i
参考方向
i>0 表示电流的参考方向与实际方向相同 i<0 表示电流的参考方向与实际方向相反
例
I1
10V
I1 = 1A 10
I1
10V I1 = -1A 10
电流参考方向的两种表示： 用箭头表示 用双下标表示 IAB A 3. 为什么要引入参考方向 ？ (a) 复杂电路的某些支路 B I
电路原理skja10
例1 用节点法列写以UA、 UB为节点电压的方程。
G1 UA
G2 UB G3
+US1
G4 IS
G5
+US2
解： 电路可改画为 G1 UA G2 UB G3
US1
G4 IS
G5
US2
( G 2 G 3 ) u n 1 ( G 2 G 3 G 4 G 5 ) u n 2 G 2 u S 2 G 5 u S 1
G21
G22
isn2
G11、G22 自电导
G12 、G21 互电导 恒为负
iR出 iS入
G11un1+G12un2 = iSn1 G11un1+G12un2 = iSn1 (3) 节点方程的一般形式
iS1
R1 R
+ uR2 _ R3
11
1
(R1R2)Un1R2Un2iS1
1
11
R 2U n1(R 3R 2)U n2gm uR2
uR2U n1U n2
G12G21
讨论：有R时方程如何列？
例3 试列写下图含理想电压源电路的节点电压方程。
+
I
1
G1 G3 G2
方法1: 设电压源电流为I， 增加一个节点电压
思考：含理想受控电压源时如何列方程？
支路法、回路法和节点法的比较：
(1) 方程数的比较
KCL方程
支路法
n-1
回路法
0
节点法 n-1
KVL方程 b-(n-1) b-(n-1)
0
方程总数
b b-(n-1)
电路原理第四版范承志
电路原理第四版范承志电路原理是电子工程领域中的重要基础课程，对于电子电路的设计、分析和应用具有重要意义。
其中，《电路原理第四版》是一本由范承志编写的经典教材，本文将从该教材的内容出发，对电路原理进行总结和探讨。
第一章：电路基本概念电路是电子器件的组合，通过电流的流动实现各种功能。
电路中的元件包括电源、电阻、电容和电感等。
在电路中，电流和电压是基本的物理量，其关系可以通过欧姆定律、基尔霍夫定律等来描述和分析。
第二章：基本电路分析方法电路的分析方法包括基本的电压、电流分析方法以及戴维南定理、诺顿定理等。
通过这些方法，可以对电路进行简化和等效处理，从而更好地理解和分析电路的工作原理。
第三章：电路的定常状态分析电路的定常状态是指在电路中各元件参数不随时间变化的情况下，电路的稳定工作状态。
通过对电路的定常状态分析，可以得到电路的直流工作点和交流工作点，从而进一步分析电路的性能和特性。
第四章：电阻器电阻器是电路中最常用的元件之一，它可以用来限制电流、分压和做功等。
在电路中，电阻器的等效电路模型可以通过串并联等效法进行分析和计算。
第五章：电容器电容器是电路中用来存储和释放电荷的元件，具有充电和放电的特性。
在电路中，电容器的充放电过程可以通过RC电路模型进行分析和计算。
第六章：电感器电感器是电路中用来储存和释放磁场能量的元件，具有电磁感应的特性。
在电路中，电感器的充放电过程可以通过RL电路模型进行分析和计算。
第七章：电源与电源电路电源是电路中提供电能的装置，可以分为直流电源和交流电源。
电源电路是将输入电能转化为输出电能的电路，常见的电源电路有稳压电源、开关电源等。
第八章：二端网络二端网络是指由两个端口连接的电路，可以通过传输特定的电信号或频率来实现特定的功能。
常见的二端网络有放大器、滤波器、功率放大器等。
第九章：小信号分析小信号分析是指在电路中对于小幅度信号进行线性化处理和分析。
通过小信号分析，可以得到电路的频率响应和增益等重要性能指标。
45相量形式的基尔霍夫定律
4.6.1用相量法分析串联电路 对于RLC串联电路来说，其阻抗为
Z = Z R + Z L + Z C = R + jωL + 1 jωC
1 = R + j ωL − ωC
1 = R 2 + ωL − ωC
2
ωL −
arctg R
1 ωC
(4-53)
0 • •
=U L =UC
•
•
为参考向量，相量图如
故电流表的读数为 即(1) (2)
2 A = I R + (I C − I L ) 2 A
A = 5 2 + (25 − 20) 2 = 7.07 A
图4-26 例4-9相量图
A = 5 + ( 25 − 10) = 40.31A
2 2
从【例4-9】题的解法二，可以体会到应用向量图分析电路的要点，那就是： （1）首先要选好一个参考相量，这个参考相量的选择，必须能方便地将电路 中其它电压、电流相量，根据电路的具体结构及参数特点逐一画出，把所给的 条件转化成相量图中的几何关系。 （2）最后根据相量图中的相量关系，使问题得到解决。一般对串联电路，选 电流作参考方向较方便，如【例4-8】题。对并联电路，则选电压作参考相量较 方便，如【例4-9】题。有些问题通过相量图分析将很直观和简便。
2 2 U S = U R + U L = 30 2 + 60 2 = 67.08V
图4-24例4-8解法二图
由题解图4-24b）可得
2 U S = U R + (U C − U L ) 2 = 15 2 + (100 − 80) 2 = 258V
上海理工大学电路原理期末考试卷
上海理工大学电路原理期末考试卷Document number【980KGB-6898YT-769T8CB-246UT-18GG08】电路原理 课程考核试卷 A ■、 B□课程代码： 学分/学时数 64 任课教师_______ ___课程性质：必修■、限选□、任选□ 考试形式： 开卷□、闭卷 ■适用年级/专业 ___________ 考试时间 120 分钟………………………………………………………………………………………………………学号 姓名 得分_________1．（12分） 求图示电路中的电流i 2和各元件的功率。
i 24Ω2Ω61i i 124A2．（12分） 试用叠加定理求解图示电路中Uac 的电压。
2Ω1Ω1Ωb 2Ωa cd 8V4V3．（12分） 电路如图所示，用网孔法列出求U x 的标准方程组（不必求解）。
VU4．（14分） 图示正弦交流电路中，已知L R U U ==10V ，R =C ω1=10。
试求S I 。
-S I LU U +5．（12分）电路如图所示，求 I240∠︒V Ω-j2Ω6．（12分） 图示对称三相星形联接电路中,若已知V U O BC 90380-∠=•,线电流 I A =∠︒230A。
求，每相的负载Z ，三相有功功率P 、三相无功功率Q 。
C7．（12分） 电路如图所示，当t =0时开关打开，打开前电路已处于稳态。
用三要素法求u t C ()，t ≥0。
100uC8．（14分） 图示电路中()i 102-= A ，()u 404-= V 。
用拉普拉斯变换法求u4u 4。
清华大学电路原理课件--电路原理_skja_35
相序的实际意义：对三相电动机，如果相序反了，就会反转。 A 1 B 2 C 3
正转 A 1 C 2 B 3 反转
D
D
以后如果不加说明，一般都认为是正相序。
6. 三相制（Three-Phase System）的优点 三相制相对于单相制在发电、输电、用电方面有很多优点， 主要有： (1) 三相发电机比单相发电机输出功率高。 (2) 经济：在相同条件下(输电距离，功率，电压和损失) 三相供电比单相供电省铜。 (3) 性能好：三相电路的瞬时功率是一个常数，对三相电 动机来说，意味着产生机接转矩均匀，电机振动小。
U0
3 U 150
利用相量图得到相电压和线电压之间的关系：
U CN
UCA
30
o
U AB
U CN
30
o
UCA
U AN
UB C
U AN30o源自U BNU AB
U BN
UB C
一般表示为：
U AB U BC U CA
3 U AN 30 3 U B N 30 3 U CN 30
o
o
即线电压等于对应的相电压。
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三相电路
第一讲 （总第三十五讲）
对称三相电源
一、对称三相电源的产生 通常由三相同步发电机产生，三相绕组在空间互差 120°，当转子转动时，在三相绕组中产生感应电压，从 而形成对称三相电源。 A Y º I º N S X 三相同步发电机示意图
Z
w
B
C
1. 瞬时值表达式 A B + uA –
C + uC –
清华大学电路原理课件--电路原理_skja_09
i5 = i S
(5)
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回路电流法 (loop current method)
思路： 为减少未知量(方程)的个数，假想每个回路 中有一个回路电流。
a
i1 R1 uS1 + –
i2 R2 il1 + uS2 –
b
i3 il2 R3
设回路电流为 il1、 il2。 回路电流自动满足KCL 支路电流是回路电流的组合 i1= il1，i2= il2- il1， i3= il2。
1
3
i5 i6
4
R5
节点 1：i1 + i2 – i6 =0 节点 2：– i2 + i3 + i4 =0 节点 3：– i4 – i5 + i6 =0 节点 4：– i1 – i3 + i5 =0
这4个方程是不独立的
uS –
一般情况： 对有n个节点的电路，只有n-1个独立的KCL方程。任 意划去其中一个方程，剩余的就是独立方程。 独立节点：与独立KCL方程对应的节点。 被划去的节点通常被设为电路的参考节点。 由KVL所能列写的独立方程数为： l = b - (n-1) 上例 l = b - (n-1)=3
总有支路相互交叉 ∴是非平面电路
支路法列写方程的一般步骤： (1) 标定各支路电流参考方向； (2) 选定(n–1)个节点，列写其KCL方程；
(3) 选定b–(n–1)个独立回路，列写其KVL方程； (元件特性代入)
(4) 求解上述方程，得到b个支路电流。
例1
I1 R1 I2 R2 I1
a I3 R3
回路2中所有电压源电压升的代数和
一般情况，对于具有 l=b-(n-1) 个回路的电路，有 R11i1+R12i2+ …+R1l il=uSl1 R21i1+R22i2+ …+R2l il=uSl2 … Rl1i1+Rl2i2+ …+Rll il=uSll
清华大学电路原理课件--电路原理_skja_56-21页精选文档
•
I1
+
•
U1
Za Zb
Zc
Z
•
I1
+
•
I2
+
•
U2
Z11U I 11 I 20 ZaZb Z21UI 12 I20 ZbZ
Z12
U1 I2
I10
Zb
Z22U I 22 I 10 ZbZc
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谢谢！
xiexie!
谢谢！
xiexie!
电路结构左右对称的一般为对称二端口。 上例中，Ya=Yc=Y时， Y11=Y22=Y+ Yb
对称二端口只有两个参数是独立的。
对称二端口是指两个端口电气特性上对称，结构不 对称的二端口，其电气特性可能是对称的。这样的二端 口也是对称二端口。
•
I1
+
•
U1
3 3
6 5
•
I2
+
•
U2
YY11
1Y2 2Y2
二端口概述
在工程实际中，研究信号及能量的传输和信号变换时， 经常碰到如下形式的电路。
K
放大器
R
C
C
n:1
滤波器 变压器
1. 端口 (port)
i1 +
u1 i1
N
2. 二端口（two-port)
端口由一对端钮构成，且满足 如下端口条件：从一个端钮流 入的电流等于从另一个端钮流 出的电流。
当一个电路与外部电路通过两个端口连接时称 此电路为二端口网络。
i1 +
u1 i1
i2 +
N
i2
u2
3. 二端口网络与四端网络的关系
AD7865ASZ-1;AD7865ASZ-3;AD7865ASZ-2;AD7865ASZ-1REEL;AD7865ASZ-2REEL;中文规格书,Datasheet资料
REV.BInformation furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.aAD7865One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781/329-4700World Wide Web Site: Fax: 781/326-8703© Analog Devices, Inc., 2000Four-Channel, Simultaneous Sampling, Fast, 14-Bit ADCFEATURESFast (2.4s) 14-Bit ADCFour Simultaneously Sampled Inputs Four Track/Hold Amplifiers0.35s Track/Hold Acquisition Time 2.4 s Conversion Time per ChannelHW/SW Select of Channel Sequence for Conversion Single Supply OperationSelection of Input Ranges: ؎10 V, ؎5 V and ؎2.5 V,0 V to 5 V and 0 V to 2.5 VHigh Speed Parallel Interface Which Also Allows Interfacing to 3 V Processors Low Power, 115 mW TypPower Saving Mode, 15W TypOvervoltage Protection on Analog Inputs APPLICATIONS AC Motor ControlUninterruptible Power Supplies Industrial Power Meters/Monitors Data Acquisition Systems Communications GENERAL DESCRIPTIONThe AD7865 is a fast, low power, four-channel simultaneous sampling 14-bit A/D converter that operates from a single 5V supply. The part contains a 2.4 µs successive approximation ADC, four track/hold amplifiers, 2.5 V reference, on-chip clock oscillator, signal conditioning circuitry and a high speed parallel interface. The input signals on four channels are sampled simul-taneously thus preserving the relative phase information of the signals on the four analog inputs. The part accepts analog input ranges of ±10V, ±5 V, ±2.5 V, 0 V to 2.5 V and 0 V to 5 V.The part allows any subset of the four channels to be converted in order to maximize the throughput rate on the selected sequence.The channels to be converted can be selected either via hard-ware (channel select input pins) or via software (programming the channel select register).A single conversion start signal (CONVST ) simultaneously places all the track/holds into hold and initiates conversion sequence for the selected channels. The EOC signal indicates the end of each individual conversion in the selected conversion sequence.The BUSY signal indicates the end of the conversion sequence.Data is read from the part via a 14-bit parallel data bus using the standard CS and RD signals. Maximum throughput for a single channel is 350 kSPS. For all four channels the maximum through-put is 100 kSPS.The AD7865 is available in a small (0.3 sq. inch area) 44-lead PQFP.PRODUCT HIGHLIGHTS1. The AD7865 features four Track/Hold amplifiers and a fast (2.4 µs) ADC allowing simultaneous sampling and then con-version of any subset of the four channels.2. The AD7865 operates from a single 5V supply and con-sumes only 115 mW typ, making it ideal for low power and portable applications.3. The part offers a high speed parallel interface for easy con-nection to microprocessors, microcontrollers and digital signal processors.4. The part is offered in three versions with different analog input ranges. The AD7865-1 offers the standard industrial ranges of ±10 V and ±5 V; the AD7865-2 offers a unipolar range of 0 V to 2.5 V or 0 V to 5 V and the AD7865-3 offers the common signal processing input range of ±2.5 V.5. The part features very tight aperture delay matching between the four input sample and hold amplifiers.FUNCTIONAL BLOCK DIAGRAMV /SL1CLK/SL2SEL V DV V V V V V V V V V /REV. B–2–AD7865–SPECIFICATIONS(V DD = 5 V ؎ 5%, AGND = DGND = 0 V, V REF = Internal. Clock = Internal; all specifi-cations T MIN to T MAX unless otherwise noted.)ParameterA, Y Versions 1B Version Unit Test Conditions/CommentsSAMPLE AND HOLD–3 dB Full Power Bandwidth 33MHz typ Aperture Delay 2020ns max Aperture Jitter5050ps typ Aperture Delay Matching44ns maxDYNAMIC PERFORMANCE 2f IN = 100 kHz, f S = 350 kSPS Signal to (Noise + Distortion) Ratio 3@ 25°CAD7865-1, AD7865-37878dB min Typically 80 dB AD7865-27777dB min Typically 78 dBT MIN to T MAXAD7865-1, AD7865-37777dB min AD7865-27676dB min Total Harmonic Distortion 3, 4–86–86dB max Peak Harmonic or Spurious Noise 3, 4–86–86dB maxIntermodulation Distortion 3fa = 49 kHz, fb = 50 kHz2nd Order Terms –95–95dB typ 3rd Order Terms–95–95dB typ Channel-to-Channel Isolation 3, 5–88–88dB max f IN = 50 kHz Sine Wave DC ACCURACY Any ChannelResolution1414BitsRelative Accuracy (INL)3±2±1.5LSB max Typically 0.6 LSBsDifferential Nonlinearity (DNL)3±1±1LSB max No Missing Codes Guaranteed AD7865-1Positive Gain Error 3±10±8LSB max Typically ±2 LSBs Positive Gain Error Match 388LSB max Typically 2 LSBs Negative Gain Error 3±10±8LSB max Typically ±2 LSBs Negative Gain Error Match 388LSB max Typically 2 LSBs Bipolar Zero Error±12±10LSB max Typically ±2 LSBs Bipolar Zero Error Match 66LSB max Typically 1.5 LSBs AD7865-2Positive Gain Error 3±16±16LSB max Typically ±2 LSBs Positive Gain Error Match 388LSB max Typically 2 LSBs Unipolar Offset Error 3±10±10LSB max Typically ±2 LSBs Unipolar Offset Error Match 31010LSB max Typically 2 LSBs AD7865-3Positive Gain Error 3±16±14LSB max Typically ±6 LSBs Positive Gain Error Match 388LSB max Typically 2 LSBs Negative Gain Error 3±16±14LSB max Typically ±6 LSBs Negative Gain Error Match 388LSB max Typically 2 LSBs Bipolar Zero Error±14±12LSB max Typically ±5 LSBs Bipolar Zero Error Match 86LSB maxTypically 2 LSBsANALOG INPUTS AD7865-1Input Voltage Range ±5,±10±5,±10Volts Input Current 1, 11, 1mA maxV IN = –5 V and –10 V Respectively,Typically 0.7 mAAD7865-2Input Voltage Range 0 V to 2.5 V,0 V to 2.5 V,0 V to 5 V 0 V to 5 V Volts Input Current 1010µA max V IN = 2.5 V, 0 V to 2.5 V Range, Typ 1 µA 11mA max V IN = 5 V, 0 V to 5 V Range, Typ 0.7 mAAD7865-3Input Voltage Range ±2.5±2.5Volts Input Current11mA maxV IN = –2.5 V, Typically 0.7 mA/REV. B–3–AD7865Parameter A, Y Versions1 B Version Unit Test Conditions/CommentsREFERENCE INPUT/OUTPUTV REF IN Input Voltage Range 2.375/2.625 2.375/2.625V MIN/V MAX 2.5 V ± 5%V REF IN Input Capacitance61010pF maxV REF OUT Output Voltage 2.5 2.5V nomV REF OUT Error @ 25°C±10±10mV maxV REF OUT Error T MIN to T MAX±20±20mV maxV REF OUT Temperature Coefficient2525ppm/°C typV REF OUT Output Impedance66kΩ typ See Reference SectionLOGIC INPUTSInput High Voltage, V INH 2.4 2.4V min V DD = 5 V ± 5%Input Low Voltage, V INL0.80.8V max V DD = 5 V ± 5%Input Current, I IN±10±10µA maxInput Capacitance, C IN61010pF maxLOGIC OUTPUTSOutput High Voltage, V OH 4.0 4.0V min I SOURCE = 400 µAOutput Low Voltage, V OL0.40.4V max I SINK = 1.6 mADB13–DB0High ImpedanceLeakage Current±10±10µA maxCapacitance61010pF maxOutput CodingAD7865-1, AD7865-3 Two’s ComplementAD7865-2 Straight (Natural) BinaryCONVERSION RATEConversion Time 2.4 2.4µs max For Single ChannelTrack/Hold Acquisition Time2, 30.350.35µs maxThroughput Time350350kSPS max For Single Channel100100kSPS max For All Four Channels POWER REQUIREMENTSV DD55V nom±5% for Specified PerformanceI DDAD7865-1Typically 23 mA, Logic Inputs = 0 V or V DD Normal Mode3232mA maxStandby Mode2020µA maxAD7865-2Typically 20 mA, Logic Inputs = 0 V or V DD Normal Mode3030mA maxStandby Mode2020µA maxAD7865-3Typically 23 mA, Logic Inputs = 0 V or V DD Normal Mode3232mA maxStandby Mode2020µA maxPower DissipationAD7865-1Normal Mode160160mW max Typically 115mW. V DD = 5 VStandby Mode100100µW max Typically 15µWAD7865-2Normal Mode150150mW max Typically 100mW. V DD = 5 VStandby Mode100100µW max Typically 15µWAD7865-3Normal Mode160160mW max Typically 115mW. V DD = 5 VStandby Mode100100µW max Typically 15µW NOTES1Temperature ranges are as follows : A, B Versions: –40°C to +85°C, Y Version: –40°C to +105°C.2Performance measured through full channel (SHA and ADC).3See Terminology.4Total Harmonic Distortion and Peak Harmonic or Spurious Noise are specified at –83 dBs for the AD7865-2.5Measured between any two channels with the other two channels grounded.6Sample tested @ 25°C to ensure compliance.Specifications subject to change without notice./REV. BAD7865–4–TIMING CHARACTERISTICS1, 2Parameter A, B, Y Versions Unit Test Conditions/Commentst CONV 2.4µs max Conversion Time, Internal Clock3.2µs max Conversion Time, External Clock (5 MHz)t ACQ 0.35µs max Acquisition Timet BUSYNo. of Channels Selected Number of Channels Multiplied by t CONV × (t CONV )µs max t WAKE-UP —External V REF 31µs max STBY Rising Edge to CONVST Rising Edge t 135ns min CONVST Pulsewidtht 270ns min CONVST Rising Edge to BUSY Rising EdgeRead Operation t 30ns min CS to RD Setup Time t 40ns min CS to RD Hold Time t 535ns min Read Pulsewidtht 6435ns max Data Access Time after Falling Edge of RD , V DRIVE = 5 V 40ns max Data Access Time after Falling Edge of RD , V DRIVE = 3 V t 755ns min Bus Relinquish Time after Rising Edge of RD 30ns max t 815ns min Time Between Consecutive Reads t 9120ns min EOC Pulsewidth180ns max t 1070ns max RD Rising Edge to FRSTDATA Edge (Rising or Falling)t 1115ns max EOC Falling Edge to FRSTDATA Falling Delay t 120ns min EOC to RD DelayWrite Operation t 1320ns min WR Pulsewidtht 140ns min CS to WR Setup Time t 150ns min WR to CS Hold Timet 165ns min Input Data Setup Time of Rising Edge of WR t 175ns min Input Data Hold TimeExternal Clock t 18200ns minCONVST Falling Edge to CLK Rising EdgeNOTES 1Sample tested at 25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6V.2See Figures 6, 7 and 8.3Refer to the Standby Mode Operation section. The MAX specification of 1 µs is valid when using a 0.1 µF decoupling capacitor on the V REF pin.4Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4 V.5These times are derived from the measured time taken by the data outputs to change 0.5V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances.Specifications subject to change without notice.TO OUTPUTPINFigure 1.Load Circuit for Access Time and Bus Relinquish Time(V DD = 5 V ؎ 5%, AGND = DGND = 0 V, V REF = Internal, Clock = Internal; all specificationsT MIN to T MAX unless otherwise noted.)/REV. BAD7865–5–CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection.Although the AD7865 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.ABSOLUTE MAXIMUM RATINGS *(T A = 25°C unless otherwise noted)V DD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V V DD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V V DRIVE to DGND . . . . . . . . . . . . . . . . . . . . . . . . . V DD + 0.3 V Analog Input Voltage to AGNDAD7865-1 (±10 V Input Range) . . . . . . . . . . . . . . . . ±18 V AD7865-1 (±5 V Input Range) . . . . . . . . . . . . . . . . . . ±9 V AD7865-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . –1 V to +18 V AD7865-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . –4 V to +18 V Reference Input Voltage to AGND . . . –0.3 V to V DD + 0.3V Digital Input Voltage to DGND . . . . . –0.3 V to V DD + 0.3 V Digital Output Voltage to DGND . . . . –0.3 V to V DD + 0.3 VOperating Temperature RangeCommercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C Automotive (Y Version) . . . . . . . . . . . . . . –40°C to +105°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C PQFP Package, Power Dissipation . . . . . . . . . . . . . . 450 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 95°C/W Lead Temperature, SolderingVapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C*Stresses above those listed under Absolute Maximum Ratings may cause perma-nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.ORDERING GUIDEInput Relative Temperature Package Package Model RangesAccuracy RangesDescriptionOption AD7865AS-1±5 V, ±10 V ±2 LSB –40°C to +85°C Plastic Lead Quad Flatpack S-44AD7865BS-1±5 V, ±10 V ±1.5 LSB –40°C to +85°C Plastic Lead Quad Flatpack S-44AD7865YS-1±5 V, ±10 V±2 LSB –40°C to +105°C Plastic Lead Quad Flatpack S-44AD7865AS-20 V to 2.5 V, 0 V to 5 V ±2 LSB –40°C to +85°C Plastic Lead Quad Flatpack S-44AD7865BS-20 V to 2.5 V, 0 V to 5 V ±1.5 LSB –40°C to +85°C Plastic Lead Quad Flatpack S-44AD7865YS-20 V to 2.5 V, 0 V to 5 V ±2 LSB –40°C to +105°C Plastic Lead Quad Flatpack S-44AD7865AS-3±2.5 V ±2 LSB –40°C to +85°C Plastic Lead Quad Flatpack S-44AD7865BS-3±2.5 V ±1.5 LSB –40°C to +85°C Plastic Lead Quad Flatpack S-44AD7865YS-3±2.5 V±2 LSB–40°C to +105°CPlastic Lead Quad FlatpackS-44PIN CONFIGURATIONB 0B 1B 2B 3B 4B 5D G N DD R I VE D V D DB 6O CA G N DA G N DV I N 4BV I N 4AV I N 3BV I N 3AV I N 2BBUSY FRSTDATA CONVST CS RD WR CLK IN/SL1INT /EXT CLK/SL2SL3SL4H /S SEL AV DD V REF AGNDV I N 2AV I N 1BV I N 1AS T B Y/REV. BAD7865–6–PIN FUNCTION DESCRIPTIONSPin Mnemonic Description1BUSY Busy Output. The busy output is triggered high by the rising edge of CONVST and remains high until conversion is completed on all selected channels.2FRSTDATA First Data Output. FRSTDATA is a logic output which, when high, indicates that the Output Data Register Pointer is addressing Register 1—See Accessing the Output Data Registers.3CONVSTConvert Start Input. Logic Input. A low-to-high transition on this input puts all track/holds into their hold mode and starts conversion on the selected channels. In addition, the state of the Channel Sequence Selection is also latched on the rising edge of CONVST .4CS Chip Select Input. Active low logic input. The device is selected when this input is active.5RD Read Input. Active low logic input which is used in conjunction with CS low to enable the data outputs. Ensure the WR pin is at logic high while performing a read operation.6WR Write Input. A rising edge on the WR input, with CS low and RD high, latches the logic state on DB0 to DB3 into the channel select register.7CLK IN/SL1Conversion Clock Input/Hardware Channel Select. The function of this pin depends upon the H /S SEL input. When the H /S SEL input is high (choosing software control of the channel selection sequence), this pin assumes its CLK IN function. CLK IN is an externally applied clock (that is only necessary when INT/EXT CLK is high) this allows the user to control the conversion rate of the AD7865. Each conversion needs 16 clock cycles in order for the conver-sion to be completed. The clock should have a duty cycle that is no greater than 60/40. See Using an External Clock.When the H /S SEL input is low (choosing hardware control of the channel conversion se-quence), this pin assumes its Hardware Channel Select function. The SL1 input determines whether Channel 1 is included in the channel conversion sequence. The selection is latched on the rising edge of CONVST . See Selecting a Conversion Sequence.8INT /EXT CLK/SL2Internal/External Clock/Hardware Channel Select. The function of this pin depends upon the H /S SEL input. When the H /S SEL input is high (choosing software control of the channel selection sequence), this pin assumes its INT /EXT CLK function. When INT /EXT CLK is at a Logic 0, the AD7865 uses its internally generated master clock. When INT /EXT CLK is at Logic 1, the master clock is generated externally to the device and applied to CLK IN.When the H /S SEL input is low (choosing hardware control of the channel conversion sequence),this pin assumes its Hardware Channel Select function. The SL2 input determines whether Channel 2 is included in the channel conversion sequence. The selection is latched on the rising edge of CONVST . When H /S is at Logic 1 these pins have no function and can be tied to Logic 1 or Logic 0. See Selecting a Conversion Sequence.9, 10SL3, SL4Hardware Channel Select. When the H /S SEL input is at Logic 0, the SL3 input determines whether Channel 3 is included in the channel conversion sequence while SL4 determines whether Channel 4 is included in the channel conversion sequence. When the pin is at Logic 1, the channel is included in the conversion sequence. When the pin is at Logic 0, the channel is excluded from the conversion sequence. The selection is latched on the rising edge of CONVST . See Selecting a Conversion Sequence.11H /S SELHardware/Software Select Input. When this pin is at a Logic 0, the AD7865 conversion sequence selection is controlled via the SL1–SL4 input pins and runs off an internal clock.When this pin is at Logic 1, the conversion sequence is controlled via the channel select regis-ter and allows the ADC to run with an internal or external clock. See Selecting a Conversion Sequence.12AGND Analog Ground. General Analog Ground. This AGND pin should be connected to the system ’s AGND plane.13–16V IN4x , V IN3x Analog Inputs. See Analog Input section.17AGND Analog Ground. Analog Ground reference for the attenuator circuitry. This AGND pin should be connected to the system ’s AGND plane.18–21V IN2x , V IN1x Analog Inputs. See Analog Input section.22STBY Standby Mode Input. This pin is used to put the device into the power save or standby mode.The STBY input is high for normal operation and low for standby operation.23AGNDAnalog Ground. General Analog Ground. This AGND pin should be connected to the system ’s AGND plane./REV. BAD7865–7–Pin Mnemonic Description24V REF Reference Input/Output. This pin provides access to the internal reference (2.5 V ± 20 mV)and also allows the internal reference to be overdriven by an external reference source (2.5 V± 5%). A 0.1 µF decoupling capacitor should be connected between this pin and AGND.25AV DD Analog Positive Supply Voltage, 5.0 V ± 5%. A 0.1 µF decoupling capacitor should be con-nected between this pin and AGND.26AGND Analog Ground. General Analog Ground. This AGND pin should be connected to the system’sAGND plane.27–34DB13–DB6Data Bit 13 is the MSB, followed by Data Bit 12 to Data Bit 6. Three-state TTL outputs.Output coding is twos complement for AD7865-1 and AD7865-3, and straight binary forAD7865-2.35DV DD Positive Supply Voltage for Digital section, 5.0 V ± 5%. A 0.1 µF decoupling capacitor shouldbe connected between this pin and AGND. Both DV DD and AV DD should be externally tiedtogether.36V DRIVE This pin provides the positive supply voltage for the output drivers (DB0 to DB13), BUSY,EOC and FRSTDATA. It is normally tied to DV DD. V DRIVE should be decoupled with a0.1 µF capacitor. It allows improved performance when reading during the conversionsequence. Also, the output data drivers may be powered by a 3 V ± 10% supply to facilitateinterfacing to 3 V processors and DSPs.37DGND Digital Ground. Ground reference for Digital circuitry. This DGND pin should be connectedto the system’s DGND plane. The system’s DGND and AGND planes should be connectedtogether at one point only, preferably at an AGND pin.38, 39DB5, DB4Data Bit 5 to Data Bit 4. Three-state TTL outputs.40–43DB3–DB0Data Bit 3 to Data Bit 0. Bidirectional data pins. When a read operation takes place, thesepins are three-state TTL outputs. The channel select register is programmed with the data onthe DB0–DB3 pins with standard CS and WR signals. DB0 represents Channel 1 and DB3represents Channel 4.44EOC End-of-Conversion. Active low logic output indicating conversion status. The end of eachconversion in a conversion sequence is indicated by a low going pulse on this line./REV. BAD7865–8–TERMINOLOGYSignal to (Noise + Distortion) RatioThis is the measured ratio of signal to (noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (f S /2), excluding dc.The ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quan-tization noise. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by:Signal to (Noise + Distortion ) = (6.02 N + 1.76) dB Thus for a 14-bit converter, this is 86.04dB.Total Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7865 it is defined as:THD dB V V V V V ()=++++2022324252621logV where V 1 is the rms amplitude of the fundamental and V 2, V 3,V 4 and V 5 are the rms amplitudes of the second through the fifth harmonics.Peak Harmonic or Spurious NoisePeak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to f S /2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is deter-mined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, it will be a noise peak.Intermodulation DistortionWith inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which neither m nor n are equal to zero. For example, the second order terms include (fa + fb) and (fa – fb), while the third order terms include (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (fa – 2 fb).The AD7865 is tested using two input frequencies. In this case,the second and third order terms are of different significance.The second order terms are usually distanced in frequency from the original sine waves, while the third order terms are usually at a frequency close to the input frequencies. As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dBs.Channel-to-Channel IsolationChannel-to-channel isolation is a measure of the level of crosstalk between channels. It is measured by applying a full-scale 10kHz sine wave signal to one channel and a 50 kHz signal to another channel and measuring how much of that signal is coupled onto the first channel. The figure given is the worst case across all four channels of the AD7865.Relative AccuracyRelative accuracy or endpoint nonlinearity is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function.Differential NonlinearityThis is the difference between the measured and the ideal 1LSB change between any two adjacent codes in the ADC.Positive Gain Error (AD7865-1, AD7865-3)This is the deviation of the last code transition (01...110 to 01...111) from the ideal 4 × V REF – 3/2 LSB (AD7865 at ±10 V), 2 × V REF – 3/2 LSB (AD7865 at ±5 V range) or V REF – 3/2 LSB (AD7865 at ±2.5 V range), after the Bipolar Offset Error has been adjusted out.Positive Gain Error (AD7865-2)This is the deviation of the last code transition (111...110 to 111...111) from the ideal 2 × V REF – 3/2 LSB (AD7865 at 0 V to 5 V), V REF – 3/2 LSB (AD7865 at 0 V to 2.5 V) after the Unipolar Offset Error has been adjusted out.Unipolar Offset Error (AD7865-2)This is the deviation of the first code transition (000...000 to 000...001) from the ideal AGND + 1/2 LSB.Bipolar Zero Error (AD7865-1, AD7865-3)This is the deviation of the midscale transition (all 0s to 1s)from the ideal AGND – 1/2 LSB.Negative Gain Error (AD7865-1, AD7865-3)This is the deviation of the first code transition (10...000 to 10...001) from the ideal –4 × V REF + 1/2 LSB (AD7865 at ±10 V), –2 × V REF + 1/2 LSB (AD7865 at ±5 V range) or –V REF + 1/2 LSB (AD7865 at ±2.5 V range), after Bipolar Zero Error has been adjusted out.Track/Hold Acquisition TimeTrack/Hold acquisition time is the time required for the out-put of the track/hold amplifier to reach its final value, within ±1/2 LSB, after the end of conversion (the point at which the track/hold returns to track mode). It also applies to situations where there is a step input change on the input voltage applied to the selected V INxA /V INxB input of the AD7865. It means that the user must wait for the duration of the track/hold acquisition time after the end of conversion or after a step input change to V INxA /V INxB before starting another conversion, to ensure that the part operates to specification./REV. BAD7865–9–CONVERTER DETAILSThe AD7865 is a high speed, low power, four-channel simulta-neous sampling 14-bit A/D converter that operates from a single 5V supply. The part contains a 2.4µs successive approximation ADC, four track/hold amplifiers, an internal 2.5V reference and a high speed parallel interface. There are four analog inputs which can be sampled simultaneously, thus preserving the relative phase information of the signals on all four analog inputs. Thereafter, conversions will be completed on the selected sub-set of the four channels. The part accepts an analog input range of ±10 V or ±5 V (AD7865-1), 0 V to 2.5 V or 0V to 5V (AD7865-2) and ±2.5 V (AD7865-3). Overvoltage protection on the analog inputs for the part allows the input voltage to go to ±18 V (AD7865-1 with ±10 V input range), ±9V (AD7865-1 with ±5V input range), –1V to +18 V (AD7865-2) and –4 V to +18 V (AD7865-3) without causing damage or effecting the con-version result of another channel. The AD7865 has two operating modes Reading Between Conversions and Reading after the Con-version Sequence. These modes are discussed in more detail in the Timing and Control section.A conversion is initiated on the AD7865 by pulsing the CONVST input. On the rising edge of CONVST, all four on-chip track/ holds are simultaneously placed into hold and the conversion sequence is started on all the selected channels. Channel selec-tion is made via the SL1–SL4 pins if H/S SEL is logic zero, or via the channel select register if H/S SEL is logic one—see Selecting a Conversion Sequence. The channel select register is programmed via the bidirectional data lines DB0–DB3 and a standard write operation. The selected conversion sequence is latched on the rising edge of CONVST so changing a selection will only take effect once a new conversion sequence is initi-ated. The BUSY output signal is triggered high on the rising edge of CONVST and will remain high for the duration of the conversion sequence. The conversion clock for the part is gen-erated internally using a laser-trimmed clock oscillator circuit. There is also the option of using an external clock, by tying the INT/EXT CLK pin logic high and applying an external clock to the CLKIN pin. However, the optimum throughput is obtained by using the internally generated clock— see Using an External Clock. The EOC signal indicates the end of each conversion in the conversion sequence. The BUSY signal indicates the end of the full conversion sequence and at this time all four Track and Holds return to tracking mode. The conversion results can either be read at the end of the full conversion sequence (indicated by BUSY going low) or as each result becomes available (indicated by EOC going low). Data is read from the part via a 14-bit parallel data bus with standard CS and RD signals—see Timing and Control. Conversion time for each channel of the AD7865 is 2.4 µs and the track/hold acquisition time is 0.35µs. To obtain optimum performance from the part, the read operation should not occur during a channel conversion or during the 100 ns prior to the next CONVST rising edge. This allows the part to operate at throughput rates up to 100 kHz for all four channels and achieve data sheet specifications.Track/Hold SectionThe track/hold amplifiers on the AD7865 allows the ADCs to accurately convert an input sine wave of full-scale amplitude to 14-bit accuracy. The input bandwidth of the track/hold is greater than the Nyquist rate of the ADC even when the ADC is oper-ated at its maximum throughput rate of 350 kSPS (i.e., the track/hold can handle input frequencies in excess of 175 kHz). The track/hold amplifiers acquire input signals to 14-bit accu-racy in less than 350 ns. The operation of the track/holds are essentially transparent to the user. The four track/hold amplifi-ers sample their respective input channels simultaneously, on the rising edge of CONVST. The aperture time for the track/ holds (i.e., the delay time between the external CONVST signal and the track/hold actually going into hold) are typically 15ns and, more importantly, is well matched across the four track/ holds on one device and also well matched from device to device. This allows the relative phase information between different input channels to be accurately preserved. It also allows multiple AD7865s to sample more than four channels simultaneously. At the end of a conversion sequence, the part returns to its tracking mode. The acquisition time of the track/hold amplifiers begins at this point.The autozero section of the track/hold circuit is designed to work with input slew rates of up to 4 × π × (Full-Scale Span). This corresponds to a full-scale sine wave of up to 4 MHz for any input range. Slew rates above this level within the acquisi-tion time may cause an incorrect conversion result to be returned from the AD7865.Reference SectionThe AD7865 contains a single reference pin, labelled V REF, which either provides access to the part’s own 2.5V reference or allows an external 2.5V reference to be connected to provide the reference source for the part. The part is specified with a 2.5V reference voltage.The AD7865 contains an on-chip 2.5V reference. To use this reference as the reference source for the AD7865, simply con-nect a 0.1µF disc ceramic capacitor from the V REF pin to AGND. The voltage that appears at this pin is internally buffered before being applied to the ADC. If this reference is required for use external to the AD7865, it should be buffered as the part has a FET switch in series with the reference output, resulting in a source impedance for this output of 6 kΩ nominal. The toler-ance on the internal reference is ±10mV at 25°C with a typical temperature coefficient of 25ppm/°C and a maximum error over temperature of ±20 mV.If the application requires a reference with a tighter tolerance or the AD7865 needs to be used with a system reference, the user has the option of connecting an external reference to this V REF pin. The external reference will effectively overdrive the internal reference and thus provide the reference source for the ADC. The reference input is buffered before being applied to the ADC with the maximum input current of ±100µA. Suitable reference sources for the AD7865 include the AD680, AD780, REF192 and REF43 precision 2.5V references./。
SK电动转辙机电路原理
（4）、分动外锁闭道岔电路结构
分动外锁闭道岔电路主要分为三个部分：室 内控制电路、道岔动作电路、道岔表示电 路。电路制式为五线制电路，分别命名为 X1线至X5线。
二、电源系统及断相保护
1、分动外锁闭道岔转换设备的动作电源采用三相 交流380V独立电源，故对有三相交流转换设备 的车站专设三相交流电源屏，供三相交流转换 设备使用，提供稳定可靠的三相交流电。分动 外锁闭道岔表示电源和24V交、直流电源均采用 原电源屏所供的电源。
断相保护器DBQ图示
断相保护器内部电路：
断相保护器内部电路原理：三个电流互感器 的一次侧分别窜入三相电路中的ABC相，二 次侧首尾相连经桥式整流电路整流供出直流 电源经电子时间开关到BHJ线圈1-4。平时道 岔不动作，电流互感器一次侧无电流通过， 二次侧线圈无感应电压，BHJ1-4线圈无电 落下。道岔动作时，电源及负载均正常，三个电流互感器一 次侧都有相同电流通过，二次侧感应电压叠加。 需说明的是，三相交流电基波各相位差120°基波电压叠加 后为零。但互感器恶齿村感应电压除基波外还存在有三次谐 波。三相交流电基波相差120°，其三次谐波相位相差 360°，经叠加后相当三个感应电压幅值相加，经桥式整流 后BHJ↑。不论电源还是负载发生断相，断相处感应器一次 侧相当于开路。另两相相位发生变化，电流减小。对应互感 器二次侧感应电压幅值减小，相位相反，互相抵消。BHJ14线圈电压近似为零，BHJ↓，电机电源被断开。 当道岔动作完毕，速动开关组接点断开电机电路，一次侧无 电流，二次侧无感应电压，BHJ↓。
1QDJ电路图
3、2QDJ原理
2QDJ的原理同1QDJ，而2QDJ作用用于心 轨部分所有转辙机全部开始转换和全部转 换到底的监督，以及本台转辙机1DQJ自闭 电路的切断
清华大学电路原理课件电路原理skja
1. 电路特点: (a) 各电阻顺序连接，流过同一电流 (KCL)； (b) 总电压等于各串联电阻的电压之和 (KVL)。
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2024/3/26
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电路原理
串联电路的总电阻 等于各分电阻之和。
2. 电压的分配公式
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R2
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电路原理
三、电阻的串并联
例1
4
2 3
R
6
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40 例2
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2024/3/26
电路原理
Y-变换的等效条件
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电路原理skja24
1 2
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补偿容量也可以用功率三角形确定：
C IC 375μF
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解 P I2R
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并求此最大功率。
解：用戴维南定理等效。
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精品课件！
精品课件！
求Zi(加压求流) 20W 10W -
cos =0.45~0.6
提高感性负载功率因数办法: 并联电容
I
IC
+
R
I L
1 2 I
U
SK电动转辙机电路
第26页/共61页
电动转辙机转换完，无电流流经DBQ，BHJ落下，断开1DQJ电路，随之断开1DQJF电路。
第27页/共61页
⑸．FBJ励磁电路：
FBJ励磁电路在电源正半周接通。
正半周：
BDII-3→R1→1DQJ23→2DQJ133→DBJ1-4线圈→X5→转辙机接点41-42→电机线圈C→电机线圈A→X1→1DQJ13→BDII-4。
3．对道岔尖轨采用两点牵引。
4．以三相交流电动机作为动力，控制电路基本原理相同。
第2页/共61页
(二)提速道岔组合
交流转辙机需设专用的提速单动道岔组合TDD及提速双动道岔组合TSD，每组固定心轨道岔增加一个提速道岔辅助组合TDF，每组可动心轨道岔增加两个提速道岔辅助组合，双动道岔算两组。 组合类型见表3－1。
①.A相→RD1→DBQ11-21→1DQJ12-11→X1→电动机A线
圈；
②.B相→RD2→DBQ31-41→1DQJF12-11→2DQJ111-113→X4
→转辙机接点11-12→电动机C线圈；
③.C相→RD3→DBQ51-61→1DQJF22-21→2DQJ121-123→X3
二次侧两互感器电压相反，桥式整流无输出，使BHJ落下而断
开1DQJ电路和三相交流电动机电路，防止因断相运行而烧坏电
动机。
第9页/共61页
（四）、道岔工作原理：
提速道岔启动电路如图3－7，该电路为S700K型交流转辙
机控制电路，用于转换道岔尖机C线圈。
第43页/共61页
第44页/共61页
三相交流电动机相序为A、B、C，电动机正转。电动机转动时三相电流经DBQ，使BHJ吸起，接通1DQJ自闭电路。
齐纳二极管工作原理
齐纳二极管工作原理齐纳二极管是一种半导体器件，常用于电子电路中的整流、开关、放大和保护等功能。
它由一个P型半导体和一个N型半导体组成，两者之间形成一个PN结。
在正常工作状态下，P区域的电子浓度较低，而N区域的电子浓度较高。
当给齐纳二极管的P区施加正向电压时，即使电压很小，也会使得P区的空穴和N区的电子向PN结区域挪移。
在PN结区域，空穴和电子会发生复合，形成一个电流，这个电流被称为漏电流。
当正向电压增加到一定程度时，PN结内的势垒会逐渐被克服，导致电流迅速增加。
相反，当给齐纳二极管的P区施加反向电压时，即使电压很小，也会使得PN结区域的势垒增加。
这个势垒会妨碍空穴和电子的挪移，从而减少漏电流。
当反向电压增加到一定程度时，PN结内的势垒会达到峰值，这时齐纳二极管处于截止状态，惟独极小的反向漏电流。
总结起来，齐纳二极管的工作原理可以归纳为以下几点：1. 正向偏置：当施加正向电压时，PN结内的势垒减小，电流迅速增加。
2. 反向偏置：当施加反向电压时，PN结内的势垒增加，电流几乎不流动。
齐纳二极管的工作原理使得它在电子电路中具有多种应用。
其中最常见的是作为整流器使用。
在正向偏置时，齐纳二极管可以将交流信号转换为直流信号，实现电流的单向流动。
这在电源电路中非常重要，因为电子设备需要稳定的直流电源来工作。
此外，齐纳二极管还可以用作开关。
在正向偏置时，齐纳二极管处于导通状态，可以允许电流通过。
而在反向偏置时，齐纳二极管处于截止状态，电流无法通过。
这种开关特性使得齐纳二极管在数字电路和摹拟电路中广泛应用。
齐纳二极管还可以用作放大器。
当施加正向电压时，齐纳二极管的电流与电压之间存在一定的关系，可以将输入信号的小变化放大为输出信号的大变化。
这种放大特性使得齐纳二极管在放大电路中起到关键作用。
此外，齐纳二极管还可以用作保护器件。
由于其特殊的电流-电压特性，当电路中浮现过电压或者过电流时，齐纳二极管可以迅速截止，防止电路中其他元件受到损坏。
电路原理实物图
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备注：此原理可用于 流水线正反转
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QJ45说明书(1)
QJ45携带式线路故障测试器使用说明书一 用 途本携带式线路故障测试议，主要以电桥测量原理组成各类回（线测试线路。
用以检测通讯电缆或通讯架空线等线路中的接地，混线，错接，断线等故障，并且也适宜作一般电阻的精密测量。
由于仪器内附有工作电源和灵敏指示仪表，便于在现场作线路检测维修用。
二 主要技术规格测量范围：阻值测量-------------1～1011000Ω （基本量程：10 ～10 欧）回线测试--------------可变比例臂式和固定比例臂式。
电容量测试------------（供断线和错接故障测量）接地绝缘阻值---------约10～10Ω准确度等级-------0.1级保证准确度的温度-------＋15℃～25℃ （相对湿度＜80%）。
使用温度范围--------＋10℃～35 （附加误差≤±0.1%）使用允许湿度-------＜85%比例臂倍率数----10001，1001，101，91，41 ，11， 110，1100，M1000 ，M100 ，，M10 。
比较臂指示值----10（1+10+100）Ω+（9×1000）Ω～检流计灵敏度----＜1μA/每分度（内阻-＜200Ω）工作电源-------3伏（1.5伏1号干电池2节串联）外形尺寸-----约270×230×145毫米重量-------约2.6公斤三 线路和结构仪器结构主要由比例臂，比较臂，检流计，量程变换电键，检流计分流系数按钮，外接指示器和外接电源线端以及“入”和 “断开”开关等组成。
仪器的正面排例如下图所示：（图1） 正 面外接指示器接线端（G ）：外接电源接线端 （B ）：比例臂旋钮：比交臂旋钮：被测线路接线端：检流计分流系数按钮（G 按钮）：S 开关：比较臂引出端：接地接线端：检流计：量程变换电键：检流计调零旋钮：电源按键：仪器的整体和各种量程交换的原理线路图列下：（图2）按实际排列的线路图G------检流计：B------工作电源：K-------量程变换电键.（图3）原理线路图（图4）接地绝缘电阻测量原理线路图（图5）电阻测量原理线路图（图6）固定比例臂法测量原理线路图（图7）可变比例法测量原理线路图四 使用方法（一）未知电阻测量法：（图8） A/B------比例臂指示值R---------比较臂指示值：X--------未知电阻的阻值： X ＝R BA 被测电阻接在仪器的21X X 和接线端上，开关扳向“接入”，电键扳向R 调节检流计零位调节钮指针指零。
电路原理解说
1.第二节总体方案的确定一．系统的运动方试与伺服系统的选择由于改造后的经济型数控车床具有定位、直线插补、圆弧插补、暂停、循环加工、螺纹加工等功能，所以应该选用连续控制系统。
考虑到经济型数控机床加工精度要求不高，为了简化结构、降低成本，采用步进电机开环控制系统。
二．计算机系统根据机床要求，采用8位机。
由于MCS—51系列单片机的特点之一是硬件设计简单，系统结构紧凑。
对于简单的应用场合，MCS—51系统的最小系统用一片8031外扩一片EPROM就能满足功能的要求，对于复杂的应用场合，可以利用MCS—51的扩展功能，构成功能强、规模较大的系统。
所以应选用8031单片机。
三．机床传动方式2.为了实现机床所要求的分辨率，采用步进电机经齿轮减速再传动丝杠。
为了保证一定的传动精度和平稳性，尽量减小摩擦力，选用滚珠丝杠螺母副。
同时，为了提高传动刚度和消除间隙，采用有预加负载荷的结构。
传动齿轮也要采用消除齿侧间隙的结构。
由于改造后的经济型数控车床具有定位、直线插补、圆弧插补、暂停、循环加工、等功能，所以应该选用连续控制系统。
考虑到经济型数控车床3.加工精度要求不高，为了简化结构、降低成本，采用步进电机开环控制系统。
4.选择芯片原则在选择程序存储器芯片时，首先满足程序容量，其次在价格合理情况下尽量选用容量大的芯片。
选用8051单片机，扩展2片8KB数据存储器6264和2片8KB的程序存储器2764芯片，共扩展4片芯片，选用线选法5.数据线的连接：存储器的8位数据线D0～D7接P0口（P0.0～P0.7）。
单片机规定指令码和数据都由P0口读入，数位对应相连即可。
地址锁存器地址锁存器就是一个暂存器，它根据控制信号的状态，将总线上地址代码暂存起来。
首先由CPU发出存储器地址，同时发出允许锁存信号ALE给锁存器，当锁存器接到该信号后将地址/数据总线上的地址锁存在总线上，随后才能传输数据，以74LS373为例，共有8个输入端D1—D8及8个输出端Q1—Q8。
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t
τ
(1) Ψu =0o, 即合闸 时Ψu = i L = I Lm sin(ωt +Ψ u ) A=0 无暂态分量 合闸后，电路直接进入稳态，不产生过渡过程。 合闸后，电路直接进入稳态，不产生过渡过程。 (2) Ψ u = ±π/2 即Ψ u = ±π/2
A = I Lm
' i L' = I Lm e
' ' i L = i L + i L' = I Lm sin(ωt + Ψ u ) + Ae
t
τ
定常数
i L (0 + ) = 0 = I Lm sin(Ψ u ) + A
A = I Lm sin(Ψ u )
解答为 讨论： 讨论：
i L = I Lm sin(ωt +Ψu ) I Lm sin(Ψu )e
一阶电路
第三讲 总第四十五讲） （总第四十五讲）
一阶电路的零输入响应 一阶电路的零状态响应
一阶电路的零输入响应
零输入响应(Zeroinput response )：激励 电源 为零，由初 电源)为零 零输入响应 ：激励(电源 为零， 始储能引起的响应。 始储能引起的响应。 放电) 一、 RC电路的零输入响应 (C对R放电 电路的零输入响应 对 放电 S(t=0) i duC i = C + dt + du duC R uR uC C uC + RC =0 – dt – uC (0)=U0 解答形式
|
|
充电效率为50% 充电效率为
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解法1: 解法
2 u 2i 1 u + = iC 1 1 du C u=C + uC dt
' u C = Ae t
' " 解答形式为： 解答形式为： uC = uC + uC
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特解
通解
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∞
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0
∫
∞
0
t U 0 RC 2 1 2 ( e ) Rdt = CU 0 R 2
二、RL电路的零输入响应 电路的零输入响应 R iL R1
US i L (0 ) = i L (0 ) = = I0 R1 + R L US S di L (t=0) uL = L – dt di L di L R L + Ri = 0 + i=0 ( t > 0) dt dt L
R t di L uL (t ) = L = RI 0 e L ( t > 0) dt
O uL O
t
(1) iL, uL 以同一指数规律衰减到零； 以同一指数规律衰减到零； (2)衰减快慢取决于 / 。 (2)衰减快慢取决于L/R。 衰减快慢取决于 电路的时间常数 令τ =L/R RL电路的时间常数 电路的 3τ 5τ 过渡过程结束。 过渡过程结束。
i L = I 0e
R t L
uV = RV i L = RV I 0e
R t L
= 875e
R t L
kV
( t > 0)
uV (0+)= 875 kV
!
现象： 现象：电压表烧坏 !
预防措施： 预防措施：
S(t=0)
iL R=0.2
35V
D L=0.4H
小结： 小结： 1. 一阶电路的零输入响应是由储能元件的初值引起的响应 都是一个指数衰减函数。 都是一个指数衰减函数。 2. 衰减快慢取决于时间常数τ . RC电路 ： τ = RC, 电路 RL电路： τ = L/R 电路： 电路 3. 同一电路中所有响应具有相同的时间常数。 同一电路中所有响应具有相同的时间常数。 4. 一阶电路的零输入响应和初值成正比。 一阶电路的零输入响应和初值成正比。
du C 4 + 4 uC = 6 dt
4 p + 4 = 0 → p = 1
uC (V) 1.5
u = 6 / 4 = 1.5V
" C
uC = 1.5 + Ae t uC = 1.5 1.5e t V ( t > 0)
O t
d uC 2 (C + uC ) dt t i1 ( 0 + ) ≠ i1 ( 0 ) i1 = = 0.5 + 0.3e A ( t > 0) 1
(t > 0)
I0 O t
时间常数. 令τ =RC, τ 具有时间的量纲 , 称τ 为时间常数 (欧×法=欧×库/伏=欧×安×秒/伏=秒) 欧 欧 伏 欧 伏 秒
1 τ = p
→∞时 电路才能达到稳态 电路才能达到稳态. 从理论上讲 t →∞时,电路才能达到稳态 但实际上一般认 经过3 的时间, 过渡过程结束,电路已达到新的稳态 电路已达到新的稳态. 为经过 τ 5τ 的时间 过渡过程结束 电路已达到新的稳态 t 0
2. RL电路的零状态响应 电路的零状态响应 iL S (t=0) R + – + US
uR
L
uL
–
di L L + Ri L = U S dt R t US iL = (1 e L )ε ( t ) R
uL = U S e
R t L
i
(0)=0 L
ε (t )
3. 正弦电源激励下的零状态响应 以RL电路为例 电路为例) 正弦电源激励下的零状态响应(以 电路为例 零状态响应 S (t=0) R + uS – +
u = Ae
'' C
t RC
(4) 求全解 (5) 定常数
' '' u C = u C + u C = U S + Ae
t RC
uC (0+)=A+US= 0
t RC
∴ A= US
t RC
uC = U S U S e
= U S (1 e
)
( t > 0)
强制分量(稳态 自由分量(暂态 强制分量 稳态) 自由分量 暂态) 稳态 暂态 uC uC' US O US uC" t
+ uL
+
其解答形式为： 其解答形式为：
i(t) = Aept
R 由特征方程 Lp+R=0 得 p = L 由初值 i(0+)=i(0)= I0 得 i(0+)=A= I0
解答
i L (t ) = I 0e
R t L
( t ≥ 0)
i L (t ) = I 0e
R t L
I0
( t ≥ 0)
iL
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一阶电路的零状态响应
零状态响应(Zerostate response)：储能元件初始能量为零， 零状态响应 ：储能元件初始能量为零， 在激励(电源 作用下产生的过渡过程。 电源)作用下产生的过渡过程 在激励 电源 作用下产生的过渡过程。 1. RC电路的零状态响应 电路的零状态响应 S(t=0) + US R (1) 列方程： 列方程： duC RC + uC = U S dt dt 非齐次线性常微分方程
uC(t)=uC"=Aept
uC = Ae
1 t RC
(特解 uC'=0)
1 RC
特征方程 RCp+1=0
∴p=
初始值
uC (0+)=uC(0)=U0
1 t RC
t RC
U 0 = Ae
t =0
→ A=U0
U0
uC
uC = U 0 e
(t ≥ 0)
t RC
O
t iC
du C U 0 e i C = C = dt R
t
τ
2τ τ
3τ τ
4τ τ
5τ τ
uc = U 0 e
τ
U0 0.368U0 0.135U0 0.05U0 0.02U0 0.007 U0 (实验测τ 的方法 实验测 的方法) 能量关系： 能量关系： C的能量不断释放 被R消耗 直到 的能量不断释放, 消耗, 的能量不断释放 消耗 全部储能消耗完毕. 全部储能消耗完毕
t duC U S RC e i=C = dt R
US i R
O
t
能量关系： 能量关系： R US
∞
电源提供的能量一部分被电阻消耗掉， 电源提供的能量一部分被电阻消耗掉， C
∞
一部分储存在电容中，且WC=WR 一部分储存在电容中，
∞
t 2 US τ 2 WR = ∫ pRdt = ∫ i 2Rdt = ∫ ( e ) Rdt 0 0 0 R 2t 2t ∞ 2 ∞ 1 US τ τ 1 2 2 ( )e = = CU S e τ 0 = CU S = WC 0 R 2 2 2
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t
RI0
量纲： 欧 韦 安 欧 韦 伏 伏 秒 伏 秒 量纲：亨/欧=韦/安*欧=韦/伏=伏*秒/伏=秒
例.