AT24C02中文资料
AT24C02SC中文资料
1Features•Low-voltage and Standard-voltage Operation, VCC = 2.7V–5.5V •Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K),1024 x 8 (8K), or 2048 x 8 (16K)•Two-wire Serial Interface•Schmitt Trigger, Filtered Inputs for Noise Suppression •Bidirectional Data Transfer Protocol •400 kHz Compatibility•8-byte Page (1K, 2K), 16-byte Page (4K, 8K, 16K) Write Modes •Partial Page Writes Allowed•Self-timed Write Cycle (5 ms max)•High Reliability–Endurance: One Million Write Cycles –Data Retention: 100 Years –ESD Protection: >3000VDescriptionThe AT24C01A/02SC/04SC/08SC/16SC provide 1024/2048/4096/8192/16384 bits of serial, electrically-erasable, and programmable read-only memory (EEPROM) orga-nized as 128/256/512/1024/2048 words of 8 bits each. The devices are optimized for use in smart card applications where low-power and low-voltage operation may be essential. The devices are available in several standard ISO 7816 smart card modules (see Ordering Information, pages 12–13). All devices are functionally equivalent to Atmel serial EEPROM products offered in standard IC packages (PDIP , SOIC, TSSOP ,MAP), with the exception of the slave address and write protect functions, which are not required for smart card applications.Figure 1. Card Module Contact2AT24C01ASC/02SC/04SC/08SC/16SC1610B –SEEPR –04/04Figure 2. Block DiagramPin DescriptionSERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open-collector devices.Memory OrganizationAT24C01ASC, 1K SERIAL EEPROM: Internally organized with 16 pages of 8 bytes each, the 1K requires a 7-bit data word address for random word addressing.AT24C02SC, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each, the 2K requires an 8-bit data word address for random word addressing.Absolute Maximum Ratings*NOTICE:Stresses beyond those listed under “Absolute Maximum Ratings ” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.3AT24C01ASC/02SC/04SC/08SC/16SC1610B –SEEPR –04/04AT24C04SC, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each, the 4K requires a 9-bit data word address for random word addressing.AT24C08SC, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each, the 8K requires a 10-bit data word address random word addressing.AT24C16SC, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes each, the 16K requires an 11-bit data word address random word addressing.Pin CapacitanceDC CharacteristicsAC CC 2.V IL min and V IH max are reference only and are not tested.AC CharacteristicsTable 2. Pin Capacitance (1)Applicable over recommended operating range from T = 25°C, f = 1.0 MHz, V = +2.7VTable 3. DC Characteristics (1)(1)4AT24C01ASC/02SC/04SC/08SC/16SC1610B –SEEPR –04/04A CC (unless otherwise noted)2.This parameter is characterized and is not 100% tested.Device OperationCLOCK AND DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-nal device. Data on the SDA pin may change only during SCL-low time periods (see Figure 3 on page 5). Data changes during SCL-high periods will indicate a start or stop condition as defined below.START CONDITION: A high-to-low transition of SDA with SCL high is a start condition that must precede any other command (see Figure 4 on page 6).STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.After a read sequence, the Stop command will place the EEPROM in a standby power mode (see Figure 4 on page 6).ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. Each word requires the receiver to acknowledge that it has received a valid command or data byte. During the transmission of commands from the host to the EEPROM, the EEPROM will send a zero to the host to acknowledge that it has received a valid command byte. This occurs on the ninth clock cycle of the com-mand byte. During read operations, the host will send a zero to the EEPROM to acknowledge that it has received a valid data byte and that it requests the next sequen-tial data byte to be transmitted during the subsequent eight clock cycles. This occurs on the ninth clock cycle of the data byte. If the host does not transmit this acknowledge bit,the EEPROM will disable the read operation and return to standby mode.STANDBY MODE: The AT24C01ASC/02SC/04SC/08SC/16SC feature a low-power standby mode that is enabled upon power-up and after the receipt of the stop bit and the completion of any internal operations.MEMORY RESET: After an interruption in protocol, power loss, or system reset, any two-wire part can be reset by following these steps:1.Clock up to 9 cycles.2.Look for SDA high in each cycle while SCL is high.3.Create a start condition as SDA is high.Table 4. AC Characteristics (1) (Continued)5AT24C01ASC/02SC/04SC/08SC/16SC1610B –SEEPR –04/04Timing DiagramsBus TimingFigure 1. Bus TimingNote:SCL: Serial Clock, SDA: Serial Data I/OWrite Cycle TimingFigure 2. Write Cycle TimingNotes:1.The write cycle time t WR is the time from a valid stop condition of a write sequence tothe end of the internal clear/write cycle.2.SCL: Serial Clock, SDA: Serial Data I/OData ValidityFigure 3.Data Validity6AT24C01ASC/02SC/04SC/08SC/16SC1610B –SEEPR –04/04Start and Stop DefinitionFigure 4. Start and Stop DefinitionOutput AcknowledgeFigure 5.Output Acknowledge7AT24C01ASC/02SC/04SC/08SC/16SC1610B –SEEPR –04/04Device AddressingThe 1K, 2K, 4K, 8K, and 16K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation (see Figure 6on page 7).The device address word consists of a mandatory “1”, “0”, “1”, “0” sequence for the first four most significant bits as shown. This is common to all the serial EEPROM devices.The next three bits of the device address word are the most significant data word address bits for the AT24C16SC (16K), which requires a total of 11 address bits. The AT24C08SC (8K) requires only 10 total word address bits. The most significant two bits are included in the device address word. The unused bit of the device address word should be set to “0”. The AT24C04SC (4K) requires only nine total data word address bits. The most significant bit is included in the device address word. The two unused bits of the device address word should be set to “0”. The AT24C02SC (2K) and AT24C01ASC (1K) do not require any address bits in the device address word. The three unused bits of the device address word should be set to “0”.The eighth bit of the device address is the read/write operation select bit. A read opera-tion is initiated if this bit is high, and a write operation is initiated if this bit is low.Upon a compare of the device address, the EEPROM will output a “0” (ACK). If a suc-cessful compare is not made, the chip will return to a standby state (NO ACK).Figure 6. Device AddressNote:P0, P1, P2 = Data word address bits8AT24C01ASC/02SC/04SC/08SC/16SC1610B –SEEPR –04/04Write OperationsBYTE WRITE: A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a “0” (ACK) and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a “0” (ACK) and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condi-tion. At this time the EEPROM enters an internally-timed write cycle, t WR , to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (refer to Figure 7).Figure 7. Byte WritePAGE WRITE: The 1K/2K EEPROM is capable of an 8-byte page write, and the 4K, 8K,and 16K devices are capable of 16-byte page writes.A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 7(1K/2K) or 15 (4K, 8K, 16K) more data words. The EEPROM will respond with a “0”(ACK) after each data word received. The microcontroller must terminate the page write sequence with a stop condition (refer to Figure 8).Figure 8. Page WriteNote:* = DON ’T CARE bit for 1KThe data word address lower three (1K/2K) or four (4K, 8K, 16K) bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address,internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than eight (1K/2K) or 16 (4K, 8K, 16K) data words are transmitted to the EEPROM, the data word address will “roll over ” and previous data will be overwritten.ACKNOWLEGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send-ing a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed9AT24C01ASC/02SC/04SC/08SC/16SC1610B –SEEPR –04/04will the EEPROM respond with a “0” (ACK), allowing the read or write sequence to continue.Read OperationsRead operations are initiated the same way as write operations, with the exception that the read/write select bit in the device address word is set to “1”. There are three read operations: current address read, random address read, and sequential read.CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “rollover ” during read is from the last byte of the last memory page to the first byte of the first page. The address “rollover ” during write is from the last byte of the cur-rent page to the first byte of the same page.Once the device address with the read/write select bit set to “1” is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out.The microcontroller does not respond with an input “0” but does generate a following stop condition (refer to Figure 9)Figure 9. Current Address Read.RANDOM READ: A random read requires a “dummy ” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a “0” (NO ACK) but does generate a following stop condition (refer to Figure 10).Figure 10. Random ReadNote:* = DON ’T CARE bit for 1K)10AT24C01ASC/02SC/04SC/08SC/16SC1610B –SEEPR –04/04SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “rollover ” and the sequen-tial read will continue. The sequential read operation is terminated when the microcontroller does not respond with a “0” (NO ACK) but does generate a following stop condition (refer to Figure 11).Figure 11.Sequential Read11AT24C01ASC/02SC/04SC/08SC/16SC1610B –SEEPR –04/04AT24C01ASC Ordering InformationAT24C02SC Ordering InformationAT24C04SC Ordering InformationAT24C08SC Ordering InformationAT24C16SC Ordering Information12AT24C01ASC/02SC/04SC/08SC/16SC1610B–SEEPR–04/0413AT24C01ASC/02SC/04SC/08SC/16SC1610B –SEEPR –04/04Smart Card ModulesDisclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company ’s standard warranty which is detailed in Atmel ’s Terms and Conditions located on the Company ’s web site. The Company assumes no responsibil ity for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time wit h out notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel ’s products are not auth orized for use as critical components in life support devices or systems.Atmel CorporationAtmel Operations2325 Orchard Parkway San Jose, CA 95131Tel: 1(408) 441-0311Fax: 1(408) 487-2600Regional HeadquartersEuropeAtmel SarlRoute des Arsenaux 41Case Postale 80CH-1705 Fribourg SwitzerlandTel: (41) 26-426-5555Fax: (41) 26-426-5500AsiaRoom 1219Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong KongTel: (852) 2721-9778Fax: (852) 2722-1369Japan9F, Tonetsu Shinkawa Bldg.1-24-8 ShinkawaChuo-ku, Tokyo 104-0033JapanTel: (81) 3-3523-3551Fax: (81) 3-3523-7581Memory2325 Orchard Parkway San Jose, CA 95131Tel: 1(408) 441-0311Fax: 1(408) 436-4314Microcontrollers2325 Orchard Parkway San Jose, CA 95131Tel: 1(408) 441-0311Fax: 1(408) 436-4314La Chantrerie BP 7060244306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18Fax: (33) 2-40-18-19-60ASIC/ASSP/Smart CardsZone Industrielle13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00Fax: (33) 4-42-53-60-011150 East Cheyenne Mtn. Blvd.Colorado Springs, CO 80906Tel: 1(719) 576-3300Fax: 1(719) 540-1759Scottish Enterprise Technology Park Maxwell BuildingEast Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000Fax: (44) 1355-242-743RF/AutomotiveTheresienstrasse 2Postfach 353574025 Heilbronn, Germany Tel: (49) 71-31-67-0Fax: (49) 71-31-67-23401150 East Cheyenne Mtn. Blvd.Colorado Springs, CO 80906Tel: 1(719) 576-3300Fax: 1(719) 540-1759Biometrics/Imaging/Hi-Rel MPU/High Speed Converters/RF DatacomAvenue de Rochepleine BP 12338521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00Fax: (33) 4-76-58-34-80e-mailliterature@Web Site1610B –SEEPR –04/04© Atmel Corporation 2003. All rights reserved. Atmel ® and combinations thereof are registered trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be the trademarks of others.。
I2C总线AT24C02芯片运用
I2C总线AT24C02芯片运用1，I2C总线介绍：I2C总线（Inter IC Bus）由飞利浦公司推出，是近年来微电子控制领域广泛采用的一宗新型总线标准，它使同步通信的一种特殊形式，具有接口少、控制简单、器件封装形体小、通信速率较高等优点（可达400Kbps）。
在主从通信中，可以有多个I2C 总线器件同时接到I2C总线上，所有与I2C总线兼容的器件都具有标准的接口，通过地址来识别通信对象，是她可以经由I2C总线相互直接通信。
I2C总线由数据线和时钟线SDA和SCL两条线构成，可发送数据可接收数据。
于CPU 及被控IC间、IC与IC间均可双向传送，各器件均并于总线上，各自有唯一地址。
信息传输中，I2C总线上的各器件既是被控又是控制器件，既是发送器又是接收器。
CPU 发出的控制信号分为地址码和数据码两部分；地址码选址；数据码送数。
故而各IC虽同并于总线上但却各自独立。
I2C总线硬件结构图图中：ACL时钟，SDA数据接上拉电阻，故总线空闲是高电平，任一器件变低均将拉低电平故曰：各器件的时钟线及数据线乃“与”关系。
通信格式为时钟高时下跳开始寻地址发送一字节 8位中低位为数据方向 0为我党要向下面发指令形象的为“O”，俗称为蛋，如川蛋：“川O001”，陕蛋：“陕O001”都是当官的向下发指令，发飙的，当然，单片机哎平方C系统呢有点民主成分，从机可以向主机传信息，既发1，形象的成为“1”：咦你们小麻虾小老百信还要上方发信息呀？？！！事实上是的 0为下蛋-----下传数据；1为上访-----上传数据。
记住了吧！时钟为高SCL=1时数据那得稳定俗称维稳期间当然时钟撤了 SCL=0时随便你虾子变化数据。
发送启动信号那得我们主机发了党外人士没这个权利在时钟为高警察在的时候主机发一个下跳沿信号表示开会了开始了既：SCL=1时 SDA 你们老百姓就等着查户口吧！当官的在警察在时下跳了于是衙门发令查户口高七位为你我家庭住址，最低一位为数据方向上面已表在此老子不说了。
AT24C02
Features•Low Voltage and Standard Voltage Operation5.0 (V CC = 4.5V to 5.5V)2.7 (V CC = 2.7V to 5.5V)2.5 (V CC = 2.5V to 5.5V)1.8 (V CC = 1.8V to 5.5V)•Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K),1024 x 8 (8K) or 2048 x 8 (16K)•2-Wire Serial Interface•Bidirectional Data Transfer Protocol•100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Compatibility •Write Protect Pin for Hardware Data Protection•8-Byte Page (1K, 2K), 16-Byte Page (4K, 8K, 16K) Write Modes •Partial Page Writes Are Allowed •Self-Timed Write Cycle (10 ms max)•High ReliabilityEndurance: 1 Million Cycles Data Retention: 100 Years•Automotive Grade and Extended Temperature Devices Available •8-Pin and 14-Pin JEDEC SOIC and 8-Pin PDIP PackagesDescriptionThe AT24C01A/02/04/08/16 provides 1024/2048/4096/8192/16384 bits of serial elec-trically erasable and programmable read only memory (EEPROM) organized as 128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The AT24C01A/02/04/08/16 is available in space saving 8-pin PDIP, 8-pin and 14-pin SOIC packages and is accessed via a 2-wire serial interface. In addition,the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V), 2.5V (2.5V to5.5V) and 1.8V (1.8V to 5.5V) versions.Pin Configurations8-Pin PDIP8-Pin SOIC14-Pin SOICAT24C01A/02/04/08/16Block Diagram*NOTICE: Stresses beyond those listed under “Absolute Maxi-mum Ratings” may cause permanent damage to the device.This is a stress rating only and functional operation of thedevice at these or any other conditions beyond those indi-cated in the operational sections of this specification is notimplied. Exposure to absolute maximum rating conditionsfor extended periods may affect device reliability. Absolute Maximum Ratings*Pin DescriptionSERIAL CLOCK (SCL): The SCL input is used to positiveedge clock data into each E2PROM device and negativeedge clock data out of each device.SERIAL DATA (SDA): The SDA pin is bidirectional for se-rial data transfer. This pin is open-drain driven and may bewire-ORed with any number of other open-drain or opencollector devices.DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1and A0 pins are device address inputs that are hard wiredfor the AT24C01A and the AT24C02. As many as eight1K/2K devices may be addressed on a single bus system(device addressing is discussed in detail under the DeviceAddressing section).The AT24C04 uses the A2 and A1 inputs for hard wireaddressing and a total of four 4K devices may be ad-dressed on a single bus system. The A0 pin is a no con-nect.The AT24C08 only uses the A2 input for hardwire ad-dressing and a total of two 8K devices may be addressedon a single bus system. The A0 and A1 pins are no con-nects.The AT24C16 does not use the device address pins whichlimits the number of devices on a single bus to one. TheA0, A1 and A2 pins are no connects.(continued)Applicable over recommended operating range from: T AI = -40°C to +85°C, V CC = +1.8V to +5.5V, T AC = 0°C to +70°C,Note:1.V IL min and V IH max are reference only and are not tested.DC CharacteristicsWRITE PROTECT (WP): The AT24C01A/02/04/16 has a Write Protect pin that provides hardware data protection.The Write Protect pin allows normal read/write operations when connected to ground (GND). When the Write Protectpin is connected to V CC , the write protection feature is en-abled and operates as shown in the following table.Pin Description (Continued)Memory OrganizationAT24C01A, 1K SERIAL E 2PROM: Internally organized with 128 pages of 1-byte each, the 1K requires a 7 bit data word address for random word addressing.AT24C02, 2K SERIAL E 2PROM: Internally organized with 256 pages of 1-byte each, the 2K requires an 8 bit data word address for random word addressing.AT24C04, 4K SERIAL E 2PROM: The 4K is internally or-ganized with 256 pages of 2-bytes each. Random word addressing requires a 9 bit data word address.AT24C08, 8K SERIAL E 2PROM:The 8K is internally or-ganized with 4 blocks of 256 pages of 4-bytes each. Ran-dom word addressing requires a 10 bit data word address.AT24C16, 16K SERIAL E 2PROM: The 16K is internally organized with 8 blocks of 256 pages of 8-bytes each.Random word addressing requires an 11 bit data word ad-dress.Pin Capacitance (1)Note:1. This parameter is characterized and is not 100% tested.AT24C01A/02/04/08/16Note:1. This parameter is characterized and is not 100% tested.Applicable over recommended operating range from T A = -40°C to +85°C, V CC = +1.8V to +5.5V, CL = 1 TTL Gate and100 pF (unless otherwise noted).AC CharacteristicsDevice OperationCLOCK and DATA TRANSITIONS: The SDA pin is nor-mally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (refer to Data Validity timing diagram). Data changes during SCL high periods will indicate a start or stop condition as de-fined below.START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition timing diagram).STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the E 2PROM in a standby power mode (refer to Start and Stop Definition timing diagram).ACKNOWLEDGE: All addresses and data words are se-rially transmitted to and from the E 2PROM in 8 bit words.The E 2PROM sends a zero to acknowledge that it has re-ceived each word. This happens during the ninth clock cy-cle.STANDBY MODE: The AT24C01A/02/04/08/16 features a low power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and thecompletion of any internal operations.Bus Timing SCL: Serial ClockSDA: Serial Data I/OWrite Cycle Timing SCL: Serial Clock SDA: Serial Data I/ONote: 1.The write cycle time t WR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.AT24C01A/02/04/08/16Data ValidityStart and Stop DefinitionOutput AcknowledgeDevice AddressingThe 1K, 2K, 4K, 8K and 16K E2PROM devices all require an 8 bit device address word following a start condition to enable the chip for a read or write operation (refer to Fig-ure 1).The device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. This is common to all the E2PROM devices.The next 3 bits are the A2, A1 and A0 device address bits for the 1K/2K E2PROM. These 3 bits must compare to their corresponding hard-wired input pins.The 4K E2PROM only uses the A2 and A1 device address bits with the third bit being a memory page address bit. The two device address bits must compare to their corre-sponding hard-wired input pins. The A0 pin is no connect. The 8K E2PROM only uses the A2 device address bit with the next 2 bits being for memory page addressing. The A2 bit must compare to its corresponding hard-wired input pin. The A1 and A0 pins are no connect.The 16K does not use any device address bits but instead the 3 bits are used for memory page addressing. These page addressing bits on the 4K, 8K, and 16K devices should be considered the most significant bits of the data word address which follows. The A0, A1 and A2 pins are no connect.The eighth bit of the device address is the read/write op-eration select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the E2PROM will output a zero. If a compare is not made, the chip will return to a standby state.Write OperationsBYTE WRITE: A write operation requires an 8 bit data word address following the device address word and ac-knowledgement. Upon receipt of this address, the E2PROM will again respond with a zero and then clock in the first 8 bit data word. Following receipt of the 8 bit data word, the E2PROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the E2PROM enters an internally-timed write cycle to the nonvolatile memory. All inputs are disabled during this write cycle and the E2PROM will not respond until the write is complete (refer to Figure 2).PAGE WRITE: The 1K/2K E2PROM is capable of an 8-byte page write, and the 4K, 8K and 16K devices are ca-pable of 16-byte page writes.A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the E2PROM acknowledges receipt of the first data word, the microcon-troller can transmit up to seven (1K/2K) or fifteen (4K, 8K, 16K) more data words. The E2PROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop con-dition (refer to Figure 3).The data word address lower three (1K/2K) or four (4K, 8K, 16K) bits are internally incremented following the re-ceipt of each data word. The higher data word address bits are not incremented, retaining the memory page row loca-tion. If more than eight (1K/2K) or sixteen (4K, 8K, 16K) data words are transmitted to the E2PROM, the data word address will “roll over” and previous data will be overwrit-ten.ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the E2PROM inputs are dis-abled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the E2PROM respond with a zero allowing the read or write sequence to continue.Read OperationsRead operations are initiated the same way as write op-erations with the exception that the read/write select bit in the device address word is set to one. There are three read operations: current address read, random address read and sequential read.CURRENT ADDRESS READ: The internal data word ad-dress counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “roll over” during read is from the last byte of the last memory page to the first byte of the first page. The address “roll over” during write is from the last byte of the current page to the first byte of the same page.Once the device address with the read/write select bit set to one is clocked in and acknowledged by the E2PROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but does generate a following stop condition (refer to Figure 4).RANDOM READ: A random read requires a “dummy”byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the E2PROM, the micro-(continued) AT24C01A/02/04/08/16Figure 1.Device AddressFigure 2.Byte WriteFigure 3. Page Write(* = DON’T CARE bit for 1K)controller must generate another start condition. The mi-crocontroller now initiates a current address read by send-ing a device address with the read/write select bit high.The E 2PROM acknowledges the device address and seri-ally clocks out the data word. The microcontroller does not respond with a zero but does generate a following stop condition (refer to Figure 5).SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read.After the microcontroller receives a data word, it responds with an acknowledge. As long as the E 2PROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words.When the memory address limit is reached, the data word address will “roll over” and the sequential read will con-tinue. The sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition (refer to Figure 6).Read Operations(Continued)Figure 5. Random Read(*= DON’T CARE bit for 1K)Figure 4.Current Address ReadFigure 6. Sequential ReadAT24C01A/02/04/08/16Ordering InformationOrdering InformationOrdering Information。
24c02中文资料
24c02中文资料1. 简介24c02是Microchip公司推出的一种串行电子可擦写可编程读写存储器，属于EEPROM（Electrically Erasable Programmable Read-Only Memory）系列。
它采用2-wire串行总线（I2C）接口，具有体积小、功耗低、可靠性高等特点。
本文档将详细介绍24c02的硬件特性、接口规范、存储容量和使用方法。
2. 硬件特性24c02的主要硬件特性如下：•存储容量：24c02有256个字节，每个字节有8位，总计拥有2Kb的存储空间。
•工作电源：24c02需要使用3.3V到5V的供电电压，支持广泛的电源电压范围。
•通信接口：24c02使用I2C串行总线进行通信，具有两根信号线：串行数据线（SDA）和串行时钟线（SCL）。
•封装类型：24c02有多种封装类型可供选择，如DIP（双列直插式封装）、SOP（小型轻负载封装）等。
3. 接口规范24c02采用I2C串行总线接口，其接口规范如下：•数据传输方式：24c02支持字节读写操作和页写操作。
字节读写操作是指每次读写一个字节的数据；页写操作是指每次可以写入8个连续字节的数据。
•起始信号和停止信号：在I2C总线上进行通信时，需要发送起始信号（Start）和停止信号（Stop）以标识数据传输的开始和结束。
•从器件地址：24c02有多个从器件地址可供选择，通过设置硬件地址引脚，可以实现多个24c02器件的级联。
4. 存储容量24c02的存储容量为2Kb，相当于256个字节。
每个字节有8位，可存储0x00到0xFF的数据。
这些存储空间可以被分为多个页，每页包含8个字节。
5. 使用方法以下是24c02的基本使用方法，供参考：•初始化：将24c02与主控芯片（如单片机）连接，并提供正常的供电电源。
同时，设置24c02的硬件地址引脚，确保能正确寻址。
•写入数据：选择要写入数据的存储地址，发送起始信号和器件地址，然后发送数据字节。
I2C总线at24c02芯片使用说明
response(); //应答信号
stop(); //停止信号
uchar at24_read(uchar address)
{uchar date;
}
void main()
{uchar tt, i ,r
sda=1;
scl=1;
at24_write(8,9);//向at24c02的地址8写入数据9
}}nopp(5);
scl=0;
nopp(5);
sda=1;
nopp(5);
uchar read_byte() //读一个字节
{uint i,j;
}
void at24_write(uchar address,uchar date)
{ start(); //初始信号
write_bscl=1;
nopp(5);
sda=0;
nopp(5);
for(n=0;n<s;n++)
_nop_();
{sda=0;
}
void response() //应答信号
{uchar i;
}
void write_byte(uchar date) //写一个字节
{uchar i,temp;
temp=date;
uchar i,date;
password [6];
uchar code deposit []={3,2,5,8,9,2};
sbit sda=P3^4;
sbit scl=P3^5;
void nopp(uchar s)
{uchar n;
}
void start() //开始信号
at24c02中文资料_数据手册_参数
AT24C02,AT24C04,AT24C16产品规格书
S P E C I F I C A T I O N24C02/24C04/24C08/24C16Version 1.0Two-wire Serial EEPROM2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8)▉FeaturesThe 24C02/24C04/24C08/24C16 provides 2048/4096/8192/16384 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 256/512/1024/2048 words of 8 bits each. The device is optimized for use in many industrial and commercial applications wherelow-power and low-voltage operation are essential. The 24C02/24C04/24C08/24C16 is available in space-saving 8-lead PDIP, 8-lead SOP, and 8-lead TSSOP packages and is accessed via a two-wire serial interface.▉Pin ConfigurationTwo-wire Serial EEPROM2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8)▉Pin DescriptionsTwo-wire Serial EEPROM2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8)▉Pin Descriptions24C02, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each, the 2K requires an 8-bit data word address for random word addressing.24C04, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each, the 4K requires a 9-bit data word address for random word addressing.24C08, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each, the 8K requires a 10-bit data word address for random word addressing.24C16, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes each, the 16K requires an 11-bit data word address for random word addressing.▉Device OperationTwo-wire Serial EEPROM 2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8)Two-wire Serial EEPROM2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8) The 2K, 4K, 8K and 16K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation (see to Figure 4 on page 7).The device address word consists of a mandatory "1", "0" sequence for the first four most significant bits as shown. This is common to all the Serial EEPROM devices.The next 3 bits are the A2, A1 and A0 device address bits for the 2K EEPROM. These 3 bits must compare to their corresponding hardwired input pins.The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a memory page address bit. The two device address bits must compare to their corresponding hardwired input pins. The A0 pin is no connect.The 8K EEPROM only uses the A2 device address bit with the next 2 bits being for memory page addressing. The A2 bit must compare to its corresponding hard-wired input pin. The A1 and A0 pins are no connect.The 16K does not use any device address bits but instead the 3 bits are used for memory page addressing. These page addressing bits on the 4K, 8K and 16K devices should be considered the most significant bits of the data word address which follows. The A0, A1 and A2 pins are no connect.The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low.Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the chip will return to a standby state.▉Write OperationsTwo-wire Serial EEPROM2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8) Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to "1". There are three read operations: current address read,random address read and sequential read.CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address "roll over" during read is from the last byte of the last memory page to the first byte of the first page. The address "roll over" during write is from the last byte of the current page to the first byte of the same page.Once the device address with the read/write select bit set to "1" is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input "0" but does generate a following stop condition (see Figure 7 on page 8).RANDOM READ: A random read requires a "dummy" byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a "0" but does generate a following stop condition (see Figure 8 on page 8). SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a randomTwo-wire Serial EEPROM 2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8)Two-wire Serial EEPROM2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8)l Absolute Maximum Stress RatingsDC Supply Voltage . . . . . . . . . . . . . . . . .-0.3V to +6.5V Input / Output Voltage . . . . . . . .GND-0.3V to V CC+0.3V Operating Ambient Temperature . . . . . -40℃to +85℃Storage Temperature . . . . . . . . . . . . -65℃to +150℃l CommentsStresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.Two-wire Serial EEPROM2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8)▉DC Electrical CharacteristicsApplicable over recommended operating range from TA = 25 ℃, f = 1.0 MHz, VCC = +1.8V Parameter Symbol Min. Typ. Max. Unit ConditionCI/O - - 8 pF VI/O = 0V Input/Output Capacitance(SDA)Input Capacitance (A0, A1,CIN - - 8 pF VIN = 0V A2, SCL)▉AC Electrical CharacteristicsTwo-wire Serial EEPROM2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8) Figure 10: SCL: Serial Clock, SDA: Serial Data I/OTwo-wire Serial EEPROM2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8)▉Write Cycle Timing。
AT24C02中文手册
概述与特点
� 24C01/02/04/08/16 是低工作电压的 1K/2K/4K/8K/16K 位串行电可擦除只读存储器，内部组织为 128/256/512/1024/2048 个字节，每个字节 8 位，该芯片被广泛应用于低电压及低功耗的工商业领域。
主要特性
� � � 工作电压：1.8V～5.5V 输入/输出引脚兼容 5V 应用在内部结构： 128x8(1K),256x8(2K),512x8(4K),1024x8(8K),2048x8(16K) � � � � � � 二线串行接口 输入引脚经施密特触发器滤波抑制噪声 双向数据传输协议 兼容 400KHz（1.8V,2.5V,2.7V,3.6V ） 支持硬件写保护 高可靠性：读写次数：1,000,000 次 – 数据保存：100 年
(WP) 引脚： 24C01/02/04/08/16 具有用于硬件数据写保护功能的引脚。当该引脚接 GND 时,允许正常 写保护 写保护(WP) (WP)引脚： 引脚：24C01/02/04/08/16 的读/写操作。当该引脚接 VCC 时,芯片启动写保护功能。
器件操作
时钟及数据传输：SDA 引脚通常被外围器件拉高。SDA 引脚的数据应在 SCL 为低时变化；当数据在 SCL 为高 时变化，将视为下文所述的一个起始或停止命令。 起始命令：当 SCL 为高，SDA 由高到低的变化被视为起始命令，必须以起始命令作为任何一次读/写操作命令 的开始(参见图 5)。 停止命令：当 SCL 为高，SDA 由低到高的变化被视为停止命令，在一个读操作后，停止命令会使 EEPROM 进 入等待态低功耗模式(参见图 5)。 应答：所有的地址和数据字节都是以 8 位为一组串行输入和输出的。每收到一组 8 位的数据后，EEPROM 都 会在第 9 个时钟周期时返回应答信号。每当主控器件接收到一组 8 位的数据后，应当在第 9 个时钟周期向 EEPROM 返回一个应答信号。收到该应答信号后，EEPROM 会继续输出下一组 8 位的数据。若此时没有得到主 控器件的应答信号，EEPROM 会停止读出数据，直到主控器件返回一个停止命令来结束读周期。 24C01/02/04/08/16 特有一个低功耗的等待模式。可以通过以下方法进入该模式：(a)上电 ()收 等待模式： 等待模式：24C01/02/04/08/16 到停止位并且结束所有的内部操作后。 在 器件复位：在协议中断、下电或系统复位后，器件可通过以下步骤复位：（1）连续输入 9 个时钟；（2） 每个时钟周期中确保当 SCL 为高时 SDA 也为高；（3）建立一个起始条件。
AT24C02芯片使用介绍
AT24C02芯片使用介绍AT24C02简介AT24C02是一个2K 位串行CMOS E2PROM ，内部含有256个8位字节，有一个16字节页写缓冲器。
该器件通过IIC 总线接口进行操作，有专门的写保护功能。
应用于AT24C02制造过程的先进CMOS 技术实质上减少了器件的功耗。
AT24C02特性1、采用I 2C 总线传输数据。
2、工作电压范围：1.8V ～6.0V 。
3、采用低功耗CMOS 技术制造。
4、当WP 为高电平时，AT24C02进入写保护状态。
5、页写缓冲器。
6、自定时擦写周期。
7、1,000,000 编程/擦除周期。
8、寿命长，可保存数据100 年。
9、2种封装：8脚DIP SOIC 或TSSOP 封装。
10、温度范围：商业级、工业级和汽车级。
AT24C02管脚描述1、SCL 串行时钟管脚AT24C02串行时钟输入管脚用于产生该器件所有数据发送或接收的时钟，SCL 串行时钟管脚是一个输入管脚。
2、SDA 串行数据AT24C02的双向串行数据管脚SDA，用于该器件所有数据的发送或接收。
SDA 管脚是一个开漏输出管脚。
3、A0、A1、A2 器件地址输入端这3个输入管脚用于多个器件级联时设置器件地址，当这些管脚悬空时默认值为0。
AT24C02 最大可级联8个器件。
如果只有一个AT24C02被总线寻址，这三个地址输入脚（A0、A1、A2 ）可悬空或连接到Vss 或 GND。
4、WP 写保护如果WP管脚连接到Vcc，AT24C02中所有的内容都被写保护只能读。
当WP管脚连接到Vss 或 GND 或悬空时，允许AT24C02器件进行正常的读/写操作。
5、V管脚CC管脚接+1.8V～+6.0V 工作电压的正极。
AT24C02的VCC6、V SS 管脚AT24C02的V SS 管脚接+1.8V ～+6.0V 工作电压的负极（即GND ）。
AT24C02的器件寻址AT24C02的芯片地址为1010，其地址控制字格式为1010A2A1A0R/W 。
AT24C02简介
AT24C02简介AT24C02简介AT24C02是美国Atmel 公司的低功耗CMOS 型E2PROM ，内含256*8位存储空间，具有⼯作电压宽(2.5V~5.5V)，擦写次数多(⼤于10000次)，写⼊速度快(⼩于10ms)，抗⼲扰能⼒强，数据不易丢失，体积⼩等特点。
并且它是采⽤I2C 总线式进⾏数据读写的串⾏操作，只占⽤很少的资源和I/O 线。
A T24C02有⼀个16字节页写缓冲器，该器件通过I2C 总线接⼝进⾏操作，还有⼀个专门的写保护功能。
AT24C02的引脚如图3-9，各引脚功能如下：SCL ：串⾏时钟输⼊管脚，⽤于产⽣器件所有数据发送或接收的时钟。
SDA ：双向串⾏数据/地址管脚，⽤于器件所有数据的发送或接收。
A0、A1、A2：器件地址输⼊端。
这些输⼊脚⽤于多个器件级联时设置器件地址，当这些脚悬空时默认值为0。
使⽤AT24C02最⼤可级联8个器件，如果只有⼀个24C02被总线寻址，这三个地址输⼊脚A0、A1、A2可悬空或连接到VSS 。
WP ：写保护。
如果WP 管脚连接到Vcc ，所有的内容都被写保护，只能读。
当WP 管脚连接到Vss 或悬空，允许器件进⾏正常的读/写操作。
VSS ：电源地(GND)。
VCC ：电源电压(5V)。
AT24C02⽀持I2C 总线数据传送协议，I2C 总线协议规定：任何将数据传送到总线的器件作为发送器，任何从总线接收数据的器件为接收器。
数据传送是由产⽣串⾏时钟和所有起始停⽌信号的主器件控制的，主器件和从器件都可以作为发送器或接收器，但由主器件控制传送数据发送或接收的模式。
I2C 总线协议定义如下：●只有在总线空闲时才允许启动数据传送。
●在数据传送过程中，当时钟线为⾼电平时，数据线必须保持稳定状态，不允许有跳变，时钟线为⾼电平时，数据线的任何电平变化将被看作总线的起始或停⽌信号。
图3-9 AT24C02引脚图图3-10 AT24C02起始/停⽌时序如图3-10所⽰，时钟线保持⾼电平期间，数据线电平从⾼到低的跳变作为I2C总线的起始信号。
AT24c02最全的中文资料
CA T24C 161/162(16K)，CAT24C081 /082(8K) CAT24C041/042(4K)，CAT24C021/022(2K)I2C串行CMOS E2PROM,精确的复位控制器和看门狗定时器控制电路特性•数据线上的看门狗定时器(仅对CA T24Cxxl)籲可编程复位门槛电平籲高数据传送速率为400KHz和I2C总线兼容• 2.7V至6V的工作电压•低功耗CMOS工艺籲16字节页写缓冲区籲片内防误擦除写保护籲高低电平复位信号输出——精确的电源电压监视器——可选择5V、3.3V和3V的复位门槛电平•100万次擦写周期•数据保存可长达100年•8脚DIP或SOIC封装•商业级、工业级和汽车温度范围概述CA T24Cxxx是集E2PROM存储器，复位微控制器和看门狗定时器三种流行功能与一体的芯片。
CAT24C161/162 (16K)，CAT24C081/082 (8K)，CA T24C041/042 (4K)和CAT24C021/022 (2K)以I2C是串行CMOS E2PROM器件。
釆用CMOS工艺大降低了器件的功耗。
CA T24Cxxx 另一特点是16字节的页写缓冲区，提供8脚DIP和SOIC 封装。
CA T24Cxxx的复位功能和看门狗定时器功能保证系统出现故障的时候能给CPU —个复位信号。
CA T24Cxxx 的2脚输出低电平复位信号，7脚输出高电平复位信号。
CAT24Cxxl看狗溢出信号从SDA脚输出。
CAT24Cxx2不具备看门狗功能。
绝对最大参数工作温度：-55°C〜125°C贮存温度：-65°C〜15°C各管脚承受对地电压：-2.0V〜Vcc+2.0V VCC对地电压范围：-2.0V〜7.0V 最大功耗： 1.0W管脚焊接温度(10S): 300 °C输出短路电流：100mA管脚配置]V C C ]RESET方框图表一直流操作特性表二上电时序管脚介绍WP：写保护将该管脚接Vcc，E2PRON就实现写保护（只读)。
24c02读写--相关资料
24c02读写—相关资料AT24C02是美国Atmel公司的低功耗CMOS型E2PROM，内含256×8位存储空间，具有工作电压宽(2.5～5.5 V)、擦写次数多(大于10 000次)、写入速度快(小于10 ms)、抗干扰能力强、数据不易丢失、体积小等特点。
而且他是采用了I2C总线式进行数据读写的串行器件，占用很少的资源和I／O线，并且支持在线编程，进行数据实时的存取十分方便。
1 AT24C02的引脚功能AT24C02引脚如图1所示。
他的的1、2、3脚是3根地址线，用于确定芯片的硬件地址。
第8脚和第4脚分别为正、负电源。
第5脚SDA为串行数据输入／输出，数据通过这根双向I2C总线串行传送。
第6脚SCL为串行时钟，SDA和SCL为漏极开路端，在实际的应用当中都需要和正电源间各接一个5.1 kΩ的电阻上拉。
第7脚为WP写保护端，接地时允许芯片执行一般的读写操作；接正电源时只允许对器件进行读操作。
2 AT24C02的内部结构图2为AT24C02的内部结构图。
启动、停止逻辑单元 接收数据引脚SDA上的电平信号，判断是否进行启动和停止操作串行控制逻辑单元 根据SCL，SDA电平信号以及“启动、停止逻辑”部件发出的各种信号进行区分，并排列出有关的“寻址”、“读数据”和“写数据”等逻辑，将他们传送到相应的操作单元。
例如：当操作命令为“寻址”时候，他将通知地址计数器加1，并启动“地址比较”器进行工作。
在“读数据”时，他控制“Dout／确认逻辑”单元；在“写数据”时候，他控制“高压泵／定时”电路，以便向E2PROM电路提供编程所需要的高电压。
地址／计数器单元 产生访问E2PROM所需要的存储单元的地址，并将其分别送到X译码器进行字选，送到Y译码器进行位选。
高压泵／定时单元 由于E2PROM数据写入时候需要向电路施加编程高电压，为了解决单一电源电压的供电问题，芯片生产厂家采用了电压的片内提升电路。
电压的提升范围一般可以达12～21.5 V。
24c02中文资料
24C02中文资料1. 介绍24C02是一种串行电子可擦除可编程只读存储器（EEPROM），由美国Microchip Technology公司生产。
它具有2K位存储容量，可用于存储数据。
24C02具有低功耗、高可靠性和可编程性等特点，因此在许多电子设备中得到广泛应用。
2. 24C02的功能特点•存储容量：24C02具有2K位的存储容量，相当于256个字节，每个字节包含8位二进制数据。
•串行接口：24C02采用串行接口进行数据的读写操作，使得它能够与各种微处理器和其他外围设备进行通信。
•可擦除、可编程：24C02采用电子擦除可编程技术，可以对存储的数据进行擦除和编程的操作。
•低功耗：24C02在工作状态下的功耗非常低，使得它适合应用于移动设备和电池供电的设备。
•高可靠性：24C02采用了自动页写技术，具有高可靠性和稳定性，适用于各种工业和消费类电子产品。
3. 24C02的引脚图和功能说明24C02具有8个引脚，每个引脚的功能如下：•VCC：供电引脚，将其连接到供电电源即可。
•GND：地引脚，连接到系统的地线。
•SDA：串行数据输入/输出引脚，与微处理器或其他设备进行数据传输。
•SCL：串行时钟引脚，用于同步传输数据。
•WC：写控制引脚，用于控制写入和擦除操作。
•A0、A1、A2：地址选择引脚，用于选择设备的地址，使得多个设备可以同时使用。
4. 24C02的工作原理24C02采用了I2C总线协议进行数据通信，它的工作原理如下：•开始信号：主设备发出一个开始信号，通知24C02开始进行工作。
•地址传输：主设备发送一个设备地址和操作位（读或写）到24C02。
•对应设备响应：24C02将自己的设备地址进行识别，并发出一个应答信号。
•数据传输：主设备发送要读取或写入的数据到24C02。
•应答信号：24C02接收到数据后，会发出应答信号。
•停止信号：传输完成后，主设备发送一个停止信号，通知24C02本次操作结束。
AT24C02A_中文资料(翻译的)
求一个10位数据字的地址。 AT24C016A，16K串行EEPROM：16K是指内部由128页组成，每页含16个字节，随机字寻 址要求一个11位数据字的地址。
引脚电容
推荐工作范围内适用，从TA= 25°C，F =1.0MHzIN 测试条件 输入输出电容（SDA） 输入电容 （A0,A1， A2,SCl） 最大 8 6 表3 单位 pF pF 状态 VI/O=0V VIN=0V
描述：
AT24C02A/04A/08A/16A 提供了串行电气可擦写， 可编程的只读存储器 （EEPROM） 的 2048/4096/8192/16384 位， 由每 8 位 256/512/1024/2048 字组成。 为了在许多要求必须是低功耗和低电压的那些工业和商业应用中 使用，最优化了这个器件。AT24C02A/04A/08A/16A 可用于保存 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead MAP and 8-lead TSSOP 的空间，也可经过一个 2-wire 串行接口存取 AT24C02A/04A/08A/16A。此外，整个 系列可用 2.7V (2.7V to 5.5V)和 1.8V (1.8V to 5.5V) 描述。 引脚配置 表1 引脚名 A0-A2 SDA SCL WP NC 功能 地址输入 串行数据 穿行时钟输入 写保护 未连接
图a
图b
图c
图d
绝对最大范围
操作温度 55℃到+125 贮存温度℃到+150℃ 引脚对地电压 -1.0V 到+7.0V 最大操作电压 6.25V 直流输出电流 5.0mA
注意：强调超出上面“绝对最大范围”列出那些可能促使永 久损毁器件设备。 这只是一个强调范围， 同样在这些情况或 任何别的超出说明书的操作指示下， 设备器件的功能操作不 被限制。 为扩展周期揭露绝对最大范围条件， 这样可能影响 设备的可靠性
CAT24C02CWA中文资料
© 2003 by Catalyst Semiconductor, Inc. Characteristics subject to change without noticeDoc. No. 1042, Rev. A1CAT24C02C2Doc. No. 1042, Rev. AABSOLUTE MAXIMUM RATINGS*Temperature Under Bias .................–55°C to +125°C Storage Temperature.......................–65°C to +150°C Voltage on Any Pin withRespect to V SS (1).................–2.0V to +V CC + 2.0V V CC with Respect to V SS ................................–2.0V to +7.0V Package Power DissipationCapability (Ta = 25°C)...................................1.0W Lead Soldering Temperature (10 secs)............300°C Output Short Circuit Current (2)........................100mA *COMMENTStresses above those listed under “Absolute Maximum Ratings ” may cause permanent damage to the device.These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.RELIABILITY CHARACTERISTICS Symbol Parameter Min.Max.Units Reference Test Method N END (3)Endurance 1,000,000Cycles/Byte MIL-STD-883, Test Method 1033T DR (3)Data Retention 100Years MIL-STD-883, Test Method 1008V ZAP (3)ESD Susceptibility 4000Volts MIL-STD-883, Test Method 3015I LTH (3)(4)Latch-up100mAJEDEC Standard 17D.C. OPERATING CHARACTERISTICSV CC = +1.8V to +6.0V, unless otherwise specified.Limits Symbol ParameterMin.Typ.Max.Units Test Conditions I CC Power Supply Current 3mA f SCL = 100 KHz I SB (5)Standby Current (V CC = 5.0V)0µA V IN = GND or V CC I LI Input Leakage Current 10µA V IN = GND to V CC I LO Output Leakage Current 10µA V OUT = GND to V CCV IL Input Low Voltage –1V CC x 0.3V V IH Input High VoltageV CC x 0.7V CC + 0.5V V OL1Output Low Voltage (V CC = 3.0V)0.4V I OL = 3 mA V OL2Output Low Voltage (V CC = 1.8V)0.5VI OL = 1.5 mA Note:(1)The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DCvoltage on output pins is V CC +0.5V, which may overshoot to V CC + 2.0V for periods of less than 20ns.(2)Output shorted for no more than one second. No more than one output shorted at a time.(3)This parameter is tested initially and after a design or process change that affects the parameter.(4)Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V CC +1V.(5)Standby Current (I SB ) = 0µA (<900nA).CAPACITANCE T A = 25°C, f = 1.0 MHz, V CC = 5V Symbol TestMax.Units Conditions C I/O (3)Input/Output Capacitance (SDA)8pF V I/O = 0V C IN (3)Input Capacitance (SCL)6pFV IN = 0VCAT24C02C3Doc. No. 1042, Rev. AA.C. CHARACTERISTICSV CC = +1.8V to +6.0V, unless otherwise specified.Read & Write Cycle LimitsNote:(1)This parameter is tested initially and after a design or process change that affects the parameter.(2)t PUR and t PUW are the delays required from the time V CC is stable until the specified operation can be initiated.The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.元器件交易网CAT24C02C4Doc. No. 1042, Rev. AFUNCTIONAL DESCRIPTIONThe CAT24C02C supports the I 2C Bus data transmis-sion protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a re-ceiver. Data transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT24C02C operates as a Slave device. Both the Master and Slave devices can operate as either transmitter or receiver, but the Master device controls which mode is activated.PIN DESCRIPTIONSSCL: Serial ClockThe CAT24C02C serial clock input pin is used to clock all data transfers into or out of the device. This is an input pin.SDA: Serial Data/AddressThe CAT24C02C bidirectional serial data/address pin is used to transfer data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs.I 2C BUS PROTOCOLThe following defines the features of the I 2C bus proto-col:(1)Data transfer may be initiated only when the bus isnot busy.(2)During a data transfer, the data line must remainstable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition.Figure 3. Start/Stop Timing5020 FHD F055020 FHD F03SCLSDA INSDA OUTSTART BITSDASTOP BITSCL元器件交易网CAT24C02C5Doc. No. 1042, Rev. ASTART ConditionThe START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT24C02C monitor the SDA and SCL lines and will not respond until this condition is met.STOP ConditionA LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition.DEVICE ADDRESSINGThe bus Master begins a transmission by sending a START condition. The Master then sends the address of the particular slave device it is requesting. The four most significant bits of the 8-bit slave address are fixed as 1010 for the CAT24C02C (see Fig. 5). The next three significant bits are all zeros. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write opera-tion is selected.After the Master sends a START condition and the slave address byte, the CAT24C02C monitors the bus and responds with an acknowledge (on the SDA line). The CAT24C02C then performs a Read or Write operation depending on the state of the R/W bit.AcknowledgeAfter a successful data transfer, each receiving device is required to generate an acknowledge. The acknowledg-ing device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data.The CAT24C02C responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation,it responds with an acknowledge after receiving each 8-bit byte.When the CAT24C02C is in a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowl-edge, the CAT24C02C will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition.WRITE OPERATIONSByte WriteIn the Byte Write mode, the Master device sends the START condition and the slave address information (with the R/W bit set to zero) to the Slave device. After the Slave generates an acknowledge, the Master sends the byte address that is to be written into the address pointer of the CAT24C02C. After receiving another acknowledge from the Slave, the Master device trans-mits the data byte to be written into the addressed memory location. The CAT24C02C acknowledge once more and the Master generates the STOP condition, at which time the device begins its internal programming cycle to nonvolatile memory. While this internal cycle is in progress, the device will not respond to any request from the Master device.Page WriteThe CAT24C02C writes up to 16 bytes of data in a single write cycle, using the Page Write operation. The Page Write operation is initiated in the same manner as counter will ‘wrap around ’ to address 0 and continue toFigure 4. Acknowledge Timing5020 FHD F06ACKNOWLEDGESTARTSCL FROM MASTERDATA OUTPUTFROM TRANSMITTERDATA OUTPUT FROM RECEIVER元器件交易网CAT24C02C6Doc. No. 1042, Rev. Athe Byte Write operation, however instead of terminating after the initial word is transmitted, the Master is allowed to send up to 15 additional bytes. After each byte has been transmitted the CAT24C02C will respond with an acknowledge, and internally increment the low order address bits by one. The high order bits remain un-changed.If the Master transmits more than 16 bytes prior to sending the STOP condition, the address counter ‘wraps around ’, and previously transmitted data will be overwrit-ten.Once all 16 bytes are received and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point all received data is written to the CAT24C02C in a single write cycle.Acknowledge PollingThe disabling of the inputs can be used to take advan-tage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host ’s write operation, the CAT24C02C initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the CAT24C02C is still busy with the write operation, no ACK will be returned.If the CAT24C02C has completed the write operation,an ACK will be returned and the host can then proceed with thenext read or write operation.Selective ReadSelective READ operations allow the Master device to select at random any memory location for a READ operation. The Master device first performs a ‘dummy ’write operation by sending the START condition, slave address and byte address of the location it wishes to read. After the CAT24C02C acknowledge the word address, the Master device resends the START condi-tion and the slave address, this time with the R/W bit set to one. The CAT24C02C then responds with its ac-knowledge and sends the 8-bit byte requested. The master device does not send an acknowledge but will generate a STOP condition.Sequential ReadThe Sequential READ operation can be initiated by either the immediate Address READ or Selective READ operations. After the 24C02C sends initial 8-bit byte requested, the Master will respond with an acknowledge which tells the device it requires more data. The CAT24C02C will continue to output an 8-bit byte for each acknowledge sent by the Master. The operation is terminated when the Master fails to respond with an acknowledge, thus sending the STOP condition.The data being transmitted from the CAT24C02C is outputted sequentially with data from address N fol-lowed by data from address N+1. The READ operation address counter increments all of the CAT24C02C address bits so that the entire memory array can be read during one operation. If more than 255 bytes are read out, the counter will “wrap around ” and continue to clock out data bytes.Figure 5. Slave Address BitsREAD OPERATIONSThe READ operation for the CAT24C02C is initiated in the same manner as the write operation with the one exception that the R/W bit is set to a one. Three different READ operations are possible: Immediate Address READ, Selective READ and Sequential READ.Immediate Address ReadThe CAT24C02C ’s address counter contains the ad-dress of the last byte accessed, incremented by one. In other words, if the last READ or WRITE access was to address N, the READ immediately following would ac-cess data from address N+1. If N=E (where E = 255 for 24WC02), then the clock out data. After the CAT24C02C receives its slave address information (with the R/W bit set to one), it issues an acknowledge, then transmits the 8-bit byte requested. The master device does not send an acknowledge but will generate a STOP condition.1010000R/W24C02C元器件交易网CAT24C02C7Doc. No. 1042, Rev. AFigure 7. Page Write Timing5020 FHD F08Figure 6. Byte Write TimingBUS ACTIVITY:MASTERSDA LINEDATA n+PBYTE ADDRESS (n)C KC K DATA n C K S T O C KDATA n+1C K S T A R SLAVE ADDRESSNOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0BYTE ADDRESSSLAVE ADDRESS SA C KA C KDATAA C KS T O P PBUS ACTIVITY:MASTERSDA LINES T A R T 5020 FHD F10Figure 8. Immediate Address Read TimingSCL SDA 8TH BIT STOPNO ACKDATA OUT89SLAVE ADDRESSSA C KDATAN O A C KS T O P PBUS ACTIVITY:MASTERSDA LINES T A R T 元器件交易网CAT24C02C8Doc. No. 1042, Rev. AORDERING INFORMATIONFigure 9. Selective Read TimingSLAVE ADDRESSSA C KN O A C K S T O P PBUS ACTIVITY:MASTERSDA LINES T A R T BYTE ADDRESS (n)S A C KDATA nSLAVE ADDRESSA C KS T A R T *Prefix Device #Suffix 元器件交易网Catalyst Semiconductor, Inc.Corporate Headquarters Copyrights, Trademarks and PatentsTrademarks and registered trademarks of Catalyst Semiconductor include each of the following:DPP ™AE 2 ™Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur.Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete.。
AT24C02-官方资料
1Features•Write Protect Pin for Hardware Data Protection –Utilizes Different Array Protection Compared to the AT24C02/04/08/16•Medium-voltage and Standard-voltage Operation –5.0 (V CC = 4.5V to 5.5V)–2.7 (V CC = 2.7V to 5.5V)•Internally Organized 256 x 8 (2K), 512 x 8 (4K), 1024 x 8 (8K) or 2048 x 8 (16K)•Two-wire Serial Interface•Schmitt Trigger, Filtered Inputs for Noise Suppression •Bidirectional Data Transfer Protocol •400 kHz (2.7V, 5V) Clock Rate•8-byte Page (2K), 16-byte Page (4K, 8K, 16K) Write Modes •Partial Page Writes Allowed•Self-timed Write Cycle (5 ms Max)•High Reliability–Endurance: One Million Write Cycles –Data Retention: 100 Years•Automotive Grade, Extended Temperature, and Lead-Free/Halogen-Free Devices Available•8-lead PDIP , 8-lead JEDEC SOIC, and 8-lead TSSOP PackagesDescriptionThe AT24C02A/04A/08A/16A provides 2048/4096/8192/16384 bits of serial electri-cally erasable and programmable read-only memory (EEPROM) organized as 256/512/1024/2048 words of 8 bits each. The device is optimized for use in many automotive applications where low-power and low-voltage operation are essential.The A T24C02A/04A/08A/16A is available in space-saving 8-lead PDIP , 8-lead JEDEC SOIC, and 8-lead TSSOP packages and is accessed via a two-wire serial interface. In addition, the entire family is available in 2.7V (2.7V to 5.5V) version.Table 1. Pin Configurations2AT24C02A/04A/08A/16A5083A–SEEPR–9/04Figure 1. Block DiagramPin DescriptionSERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open-collector devices.DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device address inputs that must be hardwired for the AT24C02A. As many as eight 2K devices may be addressed on a single bus system. (Device addressing is discussed in detail under Device Addressing, page 9).The AT24C04A uses the A2 and A1 inputs for hardwire addressing, and a total of four 4K devices may be addressed on a single bus system. The A0 pin is a no-connect.Absolute Maximum Ratings**NOTICE:Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.3AT24C02A/04A/08A/16A5083A–SEEPR–9/04The AT24C08A only uses the A2 input for hardwire addressing, and a total of two 8K devices may be addressed on a single bus system. The A0 and A1 pins are no-connects.The AT24C16A does not use the device address pins, which limits the number of devices on a single bus to one. The A0, A1, and A2 pins are no-connects.WRITE PROTECT (WP): The AT24C02A/04A/08A/16A have a WP pin that provides hardware data protection. The WP pin allows normal read/write operations when con-nected to ground (GND). When the WP pin is connected to V CC , the write protection feature is enabled and operates as shown. (See Table 1.)Table 1. Write ProtectMemory OrganizationAT24C02A, 2K SERIAL EEPROM: The 2K is internally organized with 32 pages of 8bytes each. Random word addressing requires an 8-bit data word address.AT24C04A, 4K SERIAL EEPROM: The 4K is internally organized with 32 pages of 16bytes each. Random word addressing requires a 9-bit data word address.AT24C08A, 8K SERIAL EEPROM: The 8K is internally organized with 64 pages of 16bytes each. Random word addressing requires a 10-bit data word address.AT24C16A, 16K SERIAL EEPROM: The 16K is internally organized with 128 pages of 16 bytes each. Random word addressing requires an 11-bit data word address.Note:This parameter is characterized and is not 100% tested.Table 2. Pin Capacitance4AT24C02A/04A/08A/16A5083A–SEEPR–9/04Note:1.V IL min and V IH max are reference only and are not tested.Table 3. DC CharacteristicsApplicable over recommended operating range from: T AE = −40°C to +125°C, V CC = +2.7V to +5.5V5AT24C02A/04A/08A/16A5083A–SEEPR–9/04Note:1.This parameter is characterized and is not 100% tested (T A = 25°C).2.This parameter is characterized and is not 100% tested.Table 4. AC CharacteristicsApplicable over recommended operating range from T AE = −40°C to +125°C, V CC = +2.7V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted).6AT24C02A/04A/08A/16A5083A–SEEPR–9/04Device OperationCLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-nal device. Data on the SDA pin may change only during SCL low time periods (see Figure 2). Data changes during SCL high periods will indicate a start or stop condition as defined in Figure 2.Figure 2. Data ValiditySTART CONDITION: A high-to-low transition of SDA with SCL high is a start condition that must precede any other command (see Figure 3).Figure 3. Start and Stop DefinitionSTOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 3).ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a “0” to acknowledge that it has received each word. This happens during the ninth clock cycle.STANDBY MODE: The AT24C02A/04A/08A/16A features a low-power standby mode that is enabled (a) upon power-up and (b) after the receipt of the STOP bit and the com-pletion of any internal operations.7AT24C02A/04A/08A/16A5083A–SEEPR–9/04MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps:1.Clock up to 9 cycles.2.Look for SDA high in each cycle while SCL is high.3.Create a start condition as SDA is high.Figure 4. Bus TimingFigure 5. Write Cycle TimingNote:The write cycle time t WRis the time from a valid stop condition of a write sequence to the end of the interval clear/write cycle.8AT24C02A/04A/08A/16A5083A–SEEPR–9/04Figure 6.Output Acknowledge9AT24C02A/04A/08A/16A5083A–SEEPR–9/04Device AddressingThe 2K, 4K, and 8K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation, as shown in Figure 7.Figure 7. Device AddressThe device address word consists of a mandatory “1”, “0” sequence for the first four most significant bits as shown. This is common to all the EEPROM devices.The next three bits are the A2, A1, and A0 device address bits for the 2K EEPROM.These three bits must compare to their corresponding hardwired input pins.The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a memory page address bit. The two device address bits must compare to their corre-sponding hardwired input pins. The A0 pin is no-connect.The 8K EEPROM only uses the A2 device address bit with the next two bits being for memory page addressing. The A2 bit must compare to its corresponding hardwired input pin. The A1 and A0 pins are no-connect.The 16K EEPROM does not use the device address pins, which limits the number of devices on a single bus to one. The A0, A1, and A2 pins are no-connects.The eighth bit of the device address is the read/write operation select bit. A read opera-tion is initiated if this bit is high, and a write operation is initiated if this bit is low.Upon a compare of the device address, the EEPROM will output a “0”. If a compare is not made, the chip will return to a standby state.Write OperationsBYTE WRITE: A write operation requires an 8-bit data word address following the device address word and acknowledgement. Upon receipt of this address, the EEPROM will again respond with a “0” and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a “0” and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time,the EEPROM enters an internally-timed write cycle, t WR , to the nonvolatile memory. All inputs are disabled during this write cycle, and the EEPROM will not respond until the write is complete, as shown in Figure 8.10AT24C02A/04A/08A/16A5083A–SEEPR–9/04Figure 8. Byte WritePAGE WRITE: The 2K EEPROM is capable of an 8-byte page write, and the 4K, 8K,and 16K devices are capable of 16-byte page writes.A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to seven (2K) or fifteen (4K, 8K, 16K) more data words. The EEPROM will respond with a “0”after each data word received. The microcontroller must terminate the page write sequence with a stop condition, as shown in Figure 9.Figure 9. Page WriteThe data word address lower three (2K) or four (4K, 8K, 16K) bits are internally incre-mented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address,internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than eight (2K) or sixteen (4K, 8K, 16K) data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten.ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send-ing a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a “0” allowing the read or write sequence to continue.11AT24C02A/04A/08A/16A5083A–SEEPR–9/04Read OperationsRead operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to “1”. There are three read operations: current address read, random address read and sequential read.CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “roll over” during read is from the last byte of the last memory page to the first byte of the first page. The address “roll over” during write is from the last byte of the cur-rent page to the first byte of the same page.Once the device address with the read/write select bit set to “1” is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out.The microcontroller does not respond with an input “0” but does generate a following stop condition, as shown in Figure 10.Figure 10. Current Address ReadRANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a “0” but does generate a following stop condition, as shown in Figure 11.Figure 11. Random ReadSEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequen-tial read will continue. The sequential read operation is terminated when the12AT24C02A/04A/08A/16A5083A–SEEPR–9/04microcontroller does not respond with a “0” but does generate a following stop condition,as shown in Figure 12.Figure 12.Sequential Read13AT24C02A/04A/08A/16A5083A–SEEPR–9/04Note:For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics tables (Table 3 on page 4 and Table 4 on page 5).AT24C02A Ordering Information14AT24C02A/04A/08A/16A5083A–SEEPR–9/04Note:For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics tables (Table 3 on page 4 and Table 4 on page 5).AT24C04A Ordering Information15AT24C02A/04A/08A/16A5083A–SEEPR–9/04Note:For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics tables (Table 3 on page 4 and Table 4 on page 5).AT24C08A Ordering Information16AT24C02A/04A/08A/16A5083A–SEEPR–9/04Note:For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table (Table 3 on page 4 and Table 4 on page 5).AT24C16A Ordering Information17AT24C02A/04A/08A/16A5083A–SEEPR–9/04Packaging Information8P3 – PDIP18AT24C02A/04A/08A/16A5083A–SEEPR–9/048S1 – JEDEC SOIC19AT24C02A/04A/08A/16A5083A–SEEPR–9/048A2 – TSSOP5083A–SEEPR–9/04Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise,to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL ’S TERMS AND CONDI-TIONS OF SALE LOCATED ON ATMEL ’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. 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AT24C02-官方资料
1Features•Write Protect Pin for Hardware Data Protection –Utilizes Different Array Protection Compared to the AT24C02/04/08/16•Medium-voltage and Standard-voltage Operation –5.0 (V CC = 4.5V to 5.5V)–2.7 (V CC = 2.7V to 5.5V)•Internally Organized 256 x 8 (2K), 512 x 8 (4K), 1024 x 8 (8K) or 2048 x 8 (16K)•Two-wire Serial Interface•Schmitt Trigger, Filtered Inputs for Noise Suppression •Bidirectional Data Transfer Protocol •400 kHz (2.7V, 5V) Clock Rate•8-byte Page (2K), 16-byte Page (4K, 8K, 16K) Write Modes •Partial Page Writes Allowed•Self-timed Write Cycle (5 ms Max)•High Reliability–Endurance: One Million Write Cycles –Data Retention: 100 Years•Automotive Grade, Extended Temperature, and Lead-Free/Halogen-Free Devices Available•8-lead PDIP , 8-lead JEDEC SOIC, and 8-lead TSSOP PackagesDescriptionThe AT24C02A/04A/08A/16A provides 2048/4096/8192/16384 bits of serial electri-cally erasable and programmable read-only memory (EEPROM) organized as 256/512/1024/2048 words of 8 bits each. The device is optimized for use in many automotive applications where low-power and low-voltage operation are essential.The A T24C02A/04A/08A/16A is available in space-saving 8-lead PDIP , 8-lead JEDEC SOIC, and 8-lead TSSOP packages and is accessed via a two-wire serial interface. In addition, the entire family is available in 2.7V (2.7V to 5.5V) version.Table 1. Pin Configurations2AT24C02A/04A/08A/16A5083A–SEEPR–9/04Figure 1. Block DiagramPin DescriptionSERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open-collector devices.DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device address inputs that must be hardwired for the AT24C02A. As many as eight 2K devices may be addressed on a single bus system. (Device addressing is discussed in detail under Device Addressing, page 9).The AT24C04A uses the A2 and A1 inputs for hardwire addressing, and a total of four 4K devices may be addressed on a single bus system. The A0 pin is a no-connect.Absolute Maximum Ratings**NOTICE:Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.3AT24C02A/04A/08A/16A5083A–SEEPR–9/04The AT24C08A only uses the A2 input for hardwire addressing, and a total of two 8K devices may be addressed on a single bus system. The A0 and A1 pins are no-connects.The AT24C16A does not use the device address pins, which limits the number of devices on a single bus to one. The A0, A1, and A2 pins are no-connects.WRITE PROTECT (WP): The AT24C02A/04A/08A/16A have a WP pin that provides hardware data protection. The WP pin allows normal read/write operations when con-nected to ground (GND). When the WP pin is connected to V CC , the write protection feature is enabled and operates as shown. (See Table 1.)Table 1. Write ProtectMemory OrganizationAT24C02A, 2K SERIAL EEPROM: The 2K is internally organized with 32 pages of 8bytes each. Random word addressing requires an 8-bit data word address.AT24C04A, 4K SERIAL EEPROM: The 4K is internally organized with 32 pages of 16bytes each. Random word addressing requires a 9-bit data word address.AT24C08A, 8K SERIAL EEPROM: The 8K is internally organized with 64 pages of 16bytes each. Random word addressing requires a 10-bit data word address.AT24C16A, 16K SERIAL EEPROM: The 16K is internally organized with 128 pages of 16 bytes each. Random word addressing requires an 11-bit data word address.Note:This parameter is characterized and is not 100% tested.Table 2. Pin Capacitance4AT24C02A/04A/08A/16A5083A–SEEPR–9/04Note:1.V IL min and V IH max are reference only and are not tested.Table 3. DC CharacteristicsApplicable over recommended operating range from: T AE = −40°C to +125°C, V CC = +2.7V to +5.5V5AT24C02A/04A/08A/16A5083A–SEEPR–9/04Note:1.This parameter is characterized and is not 100% tested (T A = 25°C).2.This parameter is characterized and is not 100% tested.Table 4. AC CharacteristicsApplicable over recommended operating range from T AE = −40°C to +125°C, V CC = +2.7V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted).6AT24C02A/04A/08A/16A5083A–SEEPR–9/04Device OperationCLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-nal device. Data on the SDA pin may change only during SCL low time periods (see Figure 2). Data changes during SCL high periods will indicate a start or stop condition as defined in Figure 2.Figure 2. Data ValiditySTART CONDITION: A high-to-low transition of SDA with SCL high is a start condition that must precede any other command (see Figure 3).Figure 3. Start and Stop DefinitionSTOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 3).ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a “0” to acknowledge that it has received each word. This happens during the ninth clock cycle.STANDBY MODE: The AT24C02A/04A/08A/16A features a low-power standby mode that is enabled (a) upon power-up and (b) after the receipt of the STOP bit and the com-pletion of any internal operations.7AT24C02A/04A/08A/16A5083A–SEEPR–9/04MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps:1.Clock up to 9 cycles.2.Look for SDA high in each cycle while SCL is high.3.Create a start condition as SDA is high.Figure 4. Bus TimingFigure 5. Write Cycle TimingNote:The write cycle time t WRis the time from a valid stop condition of a write sequence to the end of the interval clear/write cycle.8AT24C02A/04A/08A/16A5083A–SEEPR–9/04Figure 6.Output Acknowledge9AT24C02A/04A/08A/16A5083A–SEEPR–9/04Device AddressingThe 2K, 4K, and 8K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation, as shown in Figure 7.Figure 7. Device AddressThe device address word consists of a mandatory “1”, “0” sequence for the first four most significant bits as shown. This is common to all the EEPROM devices.The next three bits are the A2, A1, and A0 device address bits for the 2K EEPROM.These three bits must compare to their corresponding hardwired input pins.The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a memory page address bit. The two device address bits must compare to their corre-sponding hardwired input pins. The A0 pin is no-connect.The 8K EEPROM only uses the A2 device address bit with the next two bits being for memory page addressing. The A2 bit must compare to its corresponding hardwired input pin. The A1 and A0 pins are no-connect.The 16K EEPROM does not use the device address pins, which limits the number of devices on a single bus to one. The A0, A1, and A2 pins are no-connects.The eighth bit of the device address is the read/write operation select bit. A read opera-tion is initiated if this bit is high, and a write operation is initiated if this bit is low.Upon a compare of the device address, the EEPROM will output a “0”. If a compare is not made, the chip will return to a standby state.Write OperationsBYTE WRITE: A write operation requires an 8-bit data word address following the device address word and acknowledgement. Upon receipt of this address, the EEPROM will again respond with a “0” and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a “0” and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time,the EEPROM enters an internally-timed write cycle, t WR , to the nonvolatile memory. All inputs are disabled during this write cycle, and the EEPROM will not respond until the write is complete, as shown in Figure 8.10AT24C02A/04A/08A/16A5083A–SEEPR–9/04Figure 8. Byte WritePAGE WRITE: The 2K EEPROM is capable of an 8-byte page write, and the 4K, 8K,and 16K devices are capable of 16-byte page writes.A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to seven (2K) or fifteen (4K, 8K, 16K) more data words. The EEPROM will respond with a “0”after each data word received. The microcontroller must terminate the page write sequence with a stop condition, as shown in Figure 9.Figure 9. Page WriteThe data word address lower three (2K) or four (4K, 8K, 16K) bits are internally incre-mented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address,internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than eight (2K) or sixteen (4K, 8K, 16K) data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten.ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send-ing a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a “0” allowing the read or write sequence to continue.11AT24C02A/04A/08A/16A5083A–SEEPR–9/04Read OperationsRead operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to “1”. There are three read operations: current address read, random address read and sequential read.CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “roll over” during read is from the last byte of the last memory page to the first byte of the first page. The address “roll over” during write is from the last byte of the cur-rent page to the first byte of the same page.Once the device address with the read/write select bit set to “1” is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out.The microcontroller does not respond with an input “0” but does generate a following stop condition, as shown in Figure 10.Figure 10. Current Address ReadRANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a “0” but does generate a following stop condition, as shown in Figure 11.Figure 11. Random ReadSEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequen-tial read will continue. The sequential read operation is terminated when the12AT24C02A/04A/08A/16A5083A–SEEPR–9/04microcontroller does not respond with a “0” but does generate a following stop condition,as shown in Figure 12.Figure 12.Sequential Read13AT24C02A/04A/08A/16A5083A–SEEPR–9/04Note:For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics tables (Table 3 on page 4 and Table 4 on page 5).AT24C02A Ordering Information14AT24C02A/04A/08A/16A5083A–SEEPR–9/04Note:For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics tables (Table 3 on page 4 and Table 4 on page 5).AT24C04A Ordering Information15AT24C02A/04A/08A/16A5083A–SEEPR–9/04Note:For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics tables (Table 3 on page 4 and Table 4 on page 5).AT24C08A Ordering Information16AT24C02A/04A/08A/16A5083A–SEEPR–9/04Note:For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table (Table 3 on page 4 and Table 4 on page 5).AT24C16A Ordering Information17AT24C02A/04A/08A/16A5083A–SEEPR–9/04Packaging Information8P3 – PDIP18AT24C02A/04A/08A/16A5083A–SEEPR–9/048S1 – JEDEC SOIC19AT24C02A/04A/08A/16A5083A–SEEPR–9/048A2 – TSSOP5083A–SEEPR–9/04Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise,to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL ’S TERMS AND CONDI-TIONS OF SALE LOCATED ON ATMEL ’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. 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IIC总线读写 AT24C02
/*IIC总线读写A T24C02文章发表于：2010-04-19 12:04IIC总线由飞利浦推出的一种新型标准，它是同步通信的一种特殊形式，具有接口线少，控制简单，器件封装形式小，通信速度较高的优点。
在主从通信中，可以有很多的IIC总线器件同时接到IIC总线上，所有与IIC兼容的器件都具有标准的接口，通过地址来识别通信对象，使他们经过IIC总线直接通信。
总线SDA和SCL个器件上都采用漏极开路结构和总线相连，因此SDA和SCL 均要加上拉电阻，总线在空闲状态下均保持高电平，连到总线上任意器件输出的低电平都将使总线的信号变低，即各器件的SDA和SCL 都是线“与”关系。
IIC总线读写A T24C02例程：*/#include<reg52.h>#include<intrins.h>#define uchar unsigned char#define sda P2_0#define scl P2_1void delay(){;;}void delay1(uchar x){uchar a,b;for(a=x;a>0;a--)for(b=100;b>0;b--);}void init() //初始化，数据总线释放{sda=1;delay();scl="1";delay();}void start() //开始（scl 为高时，sda 上跳变）{sda="1";delay();scl="1";delay();sda=0;delay();} void stop() //停止（scl 为高时，sda 下跳变）{sda=0;delay();scl="1";delay();sda="1";delay();}void respons() scl 为高，sda=0，为应答；长时间无应答则跳出{uchar i;scl=1;delay();while((sda==1)&&(i<250))i++;scl="0";delay();}void write_byte(uchar date) scl="1",数据总线上数据保持稳定，等待读写操作，scl 变化过程中数据可以变化。
实战24C02读写
实战24C02读写AT24C02是美国ATMEL公司的低功耗CMOS串行EEPROM，它是内含256×8位存储空间，具有工作电压宽（2.5～5.5V）、擦写次数多（大于10000次）、写入速度快（小于10ms）等特点。
24C02与单片机的联接参见原理图 ,读写程序如下，运行此程序，可以看到其中之一数码管循环显示0,1,2,3,4,5,6,7,8,9的效果。
其根本是，先往24C02中写数据，然后，读出数据，在数码管中显示，这样直观明了，详细说明，请看程序中注解。
此程序是针对24c02的，其实，可以扩展来其他i2c的eeprom.这由你们来完成吧。
#include <at89x51.h>#include <intrins.h> //此文件中有_nop_()空操作函数#define uchar unsigned char#define uint unsigned int#define OP_READ 0xa1 // 器件地址以及读取操作#define OP_WRITE 0xa0 // 器件地址以及写入操作uchar code display[10]={0x28,0xEB,0x32,0xA2,0xE1,0xA4,0x24,0xEA,0x20,0xA0};//数码管0,1,2,3,4,5,6,7,8,9的编码sbit SDA = P2^0; //位定义sbit SCL = P2^1; //位定义void LED_display(uchar i);//数码管显示编码获取函数，例如，i=0,则P0=display[0],即显示数字“0”void start();//开始位void stop();//停止位uchar shin();//从AT24C02移入数据到MCUbit shout(uchar write_data);//从MCU移出数据到AT24C02void write_byte( uchar addr, uchar write_data); //在指定地址addr处写入数据write_datavoid fill_byte(uchar fill_size,uchar fill_data);//填充数据fill_data到EEPROM内fill_size字节void delayms(uchar ms); // 延时子程序uchar read_current(); // 在当前地址读取uchar read_random(uchar random_addr);// 在指定地址读取void LED_display(uchar i){P0 = display[i];}main(void){uchar i;uint j;SDA = 1;SCL = 1;fill_byte(11,0xff); // 将前10字节填充0xfffor(i = 0 ; i < 10; i++) //写入显示代码到AT24C02{write_byte(i, i);P2_7 = 0; //打开数码管1的显示for(i =0 ;i <10 ; i++){LED_display(read_random(i));for (j = 0; j<35000;j++);//延时}}void start()//开始位{SDA = 1;SCL = 1;_nop_();_nop_();SDA = 0;_nop_();_nop_();_nop_();_nop_();SCL = 0;}void stop()// 停止位{SDA = 0;_nop_();_nop_();SCL = 1;_nop_();_nop_();_nop_();_nop_();SDA = 1;}uchar shin()// 从AT24C02移入数据到MCU {uchar i,read_data;for(i = 0; i < 8; i++){SCL = 1;read_data <<= 1;read_data |= (uchar)SDA;SCL = 0;return(read_data);}bit shout(uchar write_data)// 从MCU移出数据到AT24C02{uchar i;bit ack_bit;for(i = 0; i < 8; i++) // 循环移入8个位{SDA = (bit)(write_data & 0x80);_nop_();SCL = 1;_nop_();_nop_();SCL = 0;write_data <<= 1;}SDA = 1; // 读取应答_nop_();_nop_();SCL = 1;_nop_();_nop_();_nop_();_nop_();ack_bit = SDA;SCL = 0;return ack_bit; // 返回AT24C02应答位}void write_byte(uchar addr, uchar write_data)// 在指定地址addr处写入数据write_data{start();shout(OP_WRITE);shout(addr);shout(write_data);stop();delayms(10); // 写入周期}void fill_byte(uchar fill_size,uchar fill_data)// 填充数据fill_data到EEPROM内fill_size字节{uchar i;for(i = 0; i < fill_size; i++){write_byte(i, fill_data);}}uchar read_current()// 在当前地址读取{uchar read_data;start();shout(OP_READ);read_data = shin();stop();return read_data;}uchar read_random(uchar random_addr) // 在指定地址读取{start();shout(OP_WRITE);shout(random_addr);return(read_current());}void delayms(uchar ms)// 延时子程序{uchar i;while(ms--){for(i = 0; i < 120; i++);}}。
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总线时序
深圳市联拓辉电子有限公司
深圳市联拓辉电子有限公司
封装信息 DIP-8
深圳市联拓辉电子有限公司
SOP-8
深圳市联拓辉电子有限公司
TSOT23-5L
深圳市联拓辉电子有限公司
(WP) 引脚： 24C01/02/04/08/16 具有用于硬件数据写保护功能的引脚。当该引脚接 GND 时,允许正常 写保护 写保护(WP) (WP)引脚： 引脚：24C01/02/04/08/16 的读/写操作。当该引脚接 VCC 时,芯片启动写保护功能。
器件操作
时钟及数据传输：SDA 引脚通常被外围器件拉高。SDA 引脚的数据应在 SCL 为低时变化；当数据在 SCL 为高 时变化，将视为下文所述的一个起始或停止命令。 起始命令：当 SCL 为高，SDA 由高到低的变化被视为起始命令，必须以起始命令作为任何一次读/写操作命令 的开始(参见图 5)。 停止命令：当 SCL 为高，SDA 由低到高的变化被视为停止命令，在一个读操作后，停止命令会使 EEPROM 进 入等待态低功耗模式(参见图 5)。 应答：所有的地址和数据字节都是以 8 位为一组串行输入和输出的。每收到一组 8 位的数据后，EEPROM 都 会在第 9 个时钟周期时返回应答信号。每当主控器件接收到一组 8 位的数据后，应当在第 9 个时钟周期向 EEPROM 返回一个应答信号。收到该应答信号后，EEPROM 会继续输出下一组 8 位的数据。若此时没有得到主 控器件的应答信号，EEPROM 会停止读出数据，直到主控器件返回一个停止命令来结束读周期。 24C01/02/04/08/16 特有一个低功耗的等待模式。可以通过以下方法进入该模式：(a)上电 ()收 等待模式： 等待模式：24C01/02/04/08/16 到停止位并且结束所有的内部操作后。 器件复位：在协议中断、下电或系统复位后，器件可通过以下步骤复位：（1）连续输入 9 个时钟；（2） 在 每个时钟周期中确保当 SCL 为高时 SDA 也为� � 工作电压：1.8V～5.5V 输入/输出引脚兼容 5V 应用在内部结构： 128x8(1K),256x8(2K),512x8(4K),1024x8(8K),2048x8(16K) � � � � � � 二线串行接口 输入引脚经施密特触发器滤波抑制噪声 双向数据传输协议 兼容 400KHz（1.8V,2.5V,2.7V,3.6V ） 支持硬件写保护 高可靠性：读写次数：1,000,000 次 – 数据保存：100 年
深圳市联拓辉电子有限公司
结构框图
引脚说明
(SCL)：在 SCL 输入时钟信号的上升沿将数据送入 EEPROM 器件,并在时钟的下降沿将数据 串行时钟信号引脚 行时钟信号引脚(SCL) 读出。 /输出引脚 (SDA)：SDA 引脚可实现双向串行数据传输。该引脚为开漏输出，可与其它多个开漏 串行数据输入 串行数据输入/ 输出引脚(SDA) 输出器件或开集电极器件线或连接。 /页 地址脚 (A2,A1,A0)： 器件 器件/ 地址脚(A2,A1,A0) A2、 A1 和 A0 引脚为 24C01 与 24C02 的硬件连接的器件地址输入引脚。 24C01 在一个总线上最多可寻址八个 1K 器件， 24C02 在一个总线上最多可寻址八个 2K 器件，A2、A1 和 A0 内 部必须连接。 24C04 仅使用 A2、A1 作为硬件连接的器件地址输入引脚，在一个总线上最多可寻址四个 4K 器件。A0 引脚 内部未连接。 24C08 仅使用 A2 作为硬件连接的器件地址输入引脚，在一个总线上最多可寻址两个 8K 器件。A0 和 A1 引脚 内部未连接。 24C16 未使用作为硬件连接的器件地址输入引脚，在一个总线上最多可连接一个 16K 器件。A0、A1 和 A2 引 脚内部未连接。
深圳市联拓辉电子有限公司
二线制串行 EEPROM—24C01/02/04/08/16
概述与特点
� 24C01/02/04/08/16 是低工作电压的 1K/2K/4K/8K/16K 位串行电可擦除只读存储器，内部组织为 128/256/512/1024/2048 个字节，每个字节 8 位，该芯片被广泛应用于低电压及低功耗的工商业领域。