大正VOD解码模块FPGA2说明文档

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V8A02解决方案用户手册V2.1

V8A02解决方案用户手册V2.1目录1. 文档说明 (6)1.1版本说明 (6)1.2专有名词 (6)2. 方案简介 (8)2.1方案概述 (8)2.2 功能特点 (8)2.2.1 支持DVI数据源输入 (8)2.2.2 支持宽屏等多种DVI输入分辨率 (8)2.2.3 发送卡超大带载 (8)2.2.4 功能强大的配套软件 (8)2.2.5 智能在线检测 (8)2.2.6 高刷新频率 (8)2.2.7 高灰度等级 (9)2.2.8 支持各种像素类型 (9)2.2.9 灵活支持各种模组 (9)2.2.10 多样的端口设置功能 (9)2.2.11箱体色度调整 (9)2.2.12 逐点校正功能 (9)2.2.13 集成测试功能 (9)2.2.14 联机配置数据 (9)2.2.15 智能维修 (10)2.2.16 环路备份功能 (10)2.2.17 在线升级固件安全可靠 (10)2.2.18 支持低电压输入 (10)2.2.19 配备指示灯及控制面板接口 (10)2.2.20 支持远距离传输 (10)2.2.21 支持音频传输及电源控制 (10)2.2.22 提供完整的二次开发接口 (10)2.2.24 支持内建PWM恒流 (10)2.2.25 支持低亮度高保真 (10)2.3产品清单 (11)3. 应用概述 (12)3.1 典型应用 (12)3.2 环路备份 (13)3.3 多发送卡 (14)4. 功能详解 (15)4.1 模组支持能力 (15)4.1.1 模组行、列数1～128以内任意 (16)4.1.2 模组数据类型 (16)4.1.3 模组内每扫描串移长度 (17)4.1.4 虚拟模组LED灯点位置多种排列方式 (17)4.2 箱体连接设置 (17)4.2.1 箱体内模组级联方式 (17)4.2.2 端口扩展 (18)4.2.3 端口对开 (19)4.2.4 端口逆序 (20)4.2.5 端口偏移 (20)4.2.6 箱体带载高度、宽度 (20)4.2.7 箱体显示起始的行、列位置 (21)4.2.8 箱体无信号输入时显示内容设置 (21)4.2.9 箱体级联数量 (21)4.2.10 箱体色度调整 (21)4.2.11 箱体逐点色度校正 (22)4.2.12 箱体测试功能 (22)4.3 屏体参数调节 (23)4.3.1 多个LED屏设置 (23)4.3.3 虚拟LED屏的实效果 (24)4.3.4 LED屏亮度调节 (25)4.3.5 LED屏对比度调节 (26)4.3.6 LED屏色温调节 (26)4.3.7 关闭LED屏显示 (27)4.3.8 锁定LED屏内容 (27)4.3.9 LED屏环境监控 (27)4.4 显示性能参数说明 (30)4.4.1 灰度等级 (30)4.4.2 刷新频率 (31)4.4.3 亮度效率 (31)4.4.4 最小OE (31)4.5 发送卡带载 (31)4.6 在线检测 (34)4.7 系统升级 (34)4.8 智能维修 (36)4.8.1 接收卡更换 (36)4.8.2模组替换 (37)5. 使用说明 (39)5.1 连接硬件 (39)5.1.1 发送卡安装方法 (39)5.1.2 接收卡安装方法 (39)5.1.3 多功能卡安装方法 (39)5.2 安装软件 (40)5.2.1 配置要求 (40)5.2.2 安装步骤 (40)5.3 系统设置 (40)5.3.1 显卡设置 (40)5.3.2系统设置 (43)6. 附录 (55)6.1 设备推荐型号 (55)6.1.1 DVI复制器 (55)6.2 选用线缆清单 (55)6.2.1 HDMI转DVI线缆 (55)6.2.2 音频线 (56)6.2.3 双绞线 (56)6.2.4 光纤 (56)1. 文档说明1.1版本说明版本日期说明V2.0 2013-01-09 升级自1.71版本V2.1 2013-07-15 新增接收卡产品1.2专有名词以下是本文中使用的专用术语及解释，便于读者更好的理解文章内容｡●软件一系列按照特定顺序组织的计算机数据和指令的集合，本文中特指在计算机上运行的应用软件。

基于FPGA的MPEG2视频硬件解码器的实现ppt课件

D4
微结构
D6
>>1
Hale Waihona Puke 'hA424 'h9292 'h817E 'h25A4 'hA05E 'h3668 'hC880 'h0000
Width Ecxtend
Output DFF
15bits
CLK
14
解码链模块分析与设计
[三] 二维反离散余弦变换(IDCT)
一维运算单元微结构频域到时域
共消耗90T
方式2：图1 、（图2-图1）、 [ 图3-（图2-图1）]
图1’ 、图2 ’ 、图3 ’
5
MPEG2视频编解码原理
时频域转换（离散余弦变换DCT）+ 量化
均匀
x
DCT 非0
u
量化
非0
u
分布
很多0
0
y
v
v
变长量编化码：：用一个数代表一个范围的数：
用较0短~1的0 二进0 制1串1~表25示经15常出26现~1的00图像30数…据模式，用较长的二进制串表示不经常出现的数据模式。
q_scale 译码
MUX
Load_Q_M
5级规范流水
缺省权值矩阵 ROM
RAM 用户权值矩阵
12
解码链模块分析与设计
[三] 二维反离散余弦变换(IDCT)模块频域到时域
1> 8X8二维IDCT表示为公式：
f (x, y) 1 7 7 C(u)C(v)F(u,v) cos (2x 1)u cos (2 y 1)v
4 u0 v0
16
16
可以将二维IDCT看作一维IDCT的串、并行运算

解码板说明书

通用型解码板安装使用说明书特别提醒球形云台适用如有任何疑问，请及时来电咨询在您开始使用产品前，请仔细阅读本说明书本产品工作电压为交流24V，千万不能直接接入220V市电第 1 页一、产品概述：本产品经过软件及硬件的优化设计，抗干扰性极强，专业设计的控制软件，使本产品从不死机。

极好的协议适应性：对国内大多数常用协议，均能自动识别。

优异的模块电源设计，可对摄像机提供最大1000mA 的连续12V 稳压无干扰输出。

超小内置板尺寸，能满足大多数球形云台。

具备云台、镜头输出超时保护功能：解码器在执行云台、镜头命令后，限定时间内（云台60秒，镜头10秒）未收到相应的停止命令，云台、镜头输出自动关断。

具有自检功能，可对云台及摄像机镜头进行检测，方便安装调试二、接线说明：①. JP1：485通信及AC24V输入：1脚：485 A+；2脚：485 B-；3、4脚：24V交流输入。

②. JP2：120Ω 485终端电阻跳线：485通信需在通信线路最远端的A、B之间接通一个120Ω负载电阻，以提高通信可靠性。

将短插头插在标有120一侧，即可接通120Ω负载电阻。

③. JP3：解码板云台控制输出引脚定义：④． JP4：摄像机电源及镜头输出引脚定义⑤． JP5：DIP开关：向上为ON，用1表示，向下为OFF，用0表示。

第1—2位表示波特率及特殊协议选择，详见表1；第3—9位表示解码板地址，详见表2。

三、技术参数：外部供电电压：AC24V±10%工作电流：AC200mA（不含云台工作电流）DC12V摄像机电源输出：DC12V/700mA(最大1000mA)第 2 页镜头驱动电压：DC12V/200mA云台驱动电压：AC 24V环境温度： -30℃ - +70℃自身温度：≤45℃（24小时后恒定温度）工作寿命：继电器20万次元器件八年镜头电压： DC 10-12V通讯接口： RS485四、设置说明：1．自检按钮：按“自检”开关将对云台、镜头功能进行自检控制，自检时，将对每一项进行为时一秒钟的动作，通过自检，您可以听到解码板内继电器动作的声音，看到云台镜头的动作，从而方便检测解码板的好坏，及云台、镜头接线是否正确等等。

解码板说明书

解码板说明书一、产品概述解码板是一种专用电子设备，用于将数字信号转化为可识别的模拟信号。

它广泛应用于电子产品、通信系统等领域，为数字信号处理提供了便利和灵活性。

本说明书将详细介绍解码板的功能、特点、使用方法以及注意事项，帮助用户更好地理解和操作解码板。

二、功能特点1. 多种接口支持：解码板配备有多种常用接口，可以与其他设备进行连接，包括HDMI接口、VGA接口、USB接口等，以满足不同场景的需求。

2. 高清信号输出：解码板支持高清信号输出，最高可达1080p分辨率，保证用户在使用过程中获得清晰、稳定的图像和视频输出。

3. 强大的信号解码能力：解码板能够解码多种编码格式的信号，包括H.264、MPEG等常见的编码方式，使用户可以轻松处理和播放各种数字信号。

4. 灵活的信号切换：解码板可通过简单的操作切换信号源，方便用户在多个输入信号之间切换，实现灵活性和便利性。

5. 可编程控制：解码板具备可编程控制的功能，用户可根据需要进行编程设置，实现个性化的操作与控制。

三、使用方法1. 接口连接：将解码板与显示设备（如电视、投影仪等）以及信号源（如电脑、DVD播放器等）通过适配器或线缆连接，确保连接稳固。

2. 电源接入：将解码板的电源线插入电源插座，确保供电正常。

3. 信号切换：根据需要使用遥控器或面板上的切换按钮，选择所需的输入信号源，确保正确选择。

4. 参数设置：如有需要，可以通过解码板上的操作按钮或遥控器进行参数设置，例如调节亮度、对比度、音量等参数。

5. 操作指南：根据解码板的使用说明书，了解各个功能按钮的具体作用和操作方法，并按需操作即可。

四、注意事项1. 请严格遵守使用说明书中的操作规范，避免不必要的损坏和故障。

2. 使用时请确保电源接地良好，保证工作环境干燥、通风良好。

3. 避免解码板长时间过热，应保持良好的散热环境。

4. 避免将水或其他液体溅入解码板内部，以免导致设备损坏。

5. 不要在有磁场或静电的环境下使用解码板，以免影响正常工作。

IGLOO2 FPGA 设备家族之间的设计迁移指南说明书

Application Note AC416February 20141© 2014 Microsemi CorporationMigrating Designs Between IGLOO2 M2GL025 and M2GL050 in VF400 PackageTable of ContentsIntroductionThis document describes how to migrate designs within the IGLOO ®2 field programmable gate array (FPGA) device family between the M2GL025 and M2GL050 devices within the VF400 package. It addresses restrictions and specifications that need to be considered while moving a design between the M2GL025 and M2GL050 devices. This includes pin compatibility between the devices, design and device resources evaluation, I/O banks, standards, and so on. This document also describes the software flow behavior during the migration.Design MigrationIGLOO2 family devices are architecturally compatible with each other. However, attention must be paid to some key areas while migrating a design from one device to another. The following specific points are discussed in this document:•Design and Device Evaluation •I/O Banks and Standards •Pin Migration and Compatibility•Power Supply and Board-Level Considerations •Software FlowDesign and Device EvaluationOne of the initial and main tasks while migrating a design should be to compare the available resources between the two devices. The device resources can be grouped into three different categories:•High Performance Memory Subsystem •Fabric Resources •On-Chip OscillatorsIn addition, necessary design timing analysis and simulations should be performed while migrating designs from one device to another.Each of the following sections focuses on the different aspects of the design and device evaluation categories.Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Design Migration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Design and Device Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1I/O Banks and Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Pin Migration and Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Power Supply and Board-Level Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Software Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Migrating Designs Between IGLOO2 M2GL025 and M2GL050 in VF400 Package2High Performance Memory SubsystemTable1 provides a high-level summary of the differences between the M2GL025 and M2GL050 high performance memory subsystem (HPMS) blocks. Based on the different HPMS resources and features, migration from one device to another can be planned to avoid any resource conflicts or issues. Fabric ResourcesTable2 gives a high-level summary of the differences between M2GL025 and M2GL050 fabric resources. Based on the differences, effective logic count, RAM size, and number of I/Os, migration can be evaluated and planned from one device to another without any resource conflicts or issues.On-Chip OscillatorsTable3 shows the summary of IGLOO2 on-chip oscillators that are the primary sources for generating free-running clocks.Table 1 • HPMS Features Per Package or DeviceFeatureVF400 PackageM2GL025 and M2GL025T M2GL050 and M2GL050T Fabric interfaces (FIC) 1 (FIC_0) 2 (FIC_0 and FIC_1) Memory subsytem DDR (MDDR)1X181X182eNVM (Kbytes) 256256eSRAM (Kbytes)6464eSRAM (non-SECDED) (Kbytes)8080SPI, HPDMA, PDMA22SDRAM through SMC_FIC Yes YesNotes:1.DDR supports x18, x16, x9, and x8 modes2.DDR supports x18 and x16 modesTable 2 • Summary of the Fabric Features Supported Per DeviceFabric Features (Logic, DSP, and Memory)VF400 PackageM2GL025 andM2GL025TM2GL050 andM2GL050T Logic/DSP Logic Modules (4-Input LUT)27,69656,340 Mathblocks3472PLLs and CCCs66Fabric Memory LSRAM 18 K blocks3169uSRAM 1K blocks3472User I/Os MSIO (3.3 V max)11187MSIOD (2.5 V max)3232DDRIO (2.5 V max)6488Total user I/Os per package207207Table 3 • On-Chip Oscillator Support Per DeviceFeatureVF400 PackageM2GL025M2GL0501 MHz RC oscillator1150 MHz RC oscillator11Design Migration3Refer to the IGLOO2 Clocking Resources User Guide for more information.I/O Banks and StandardsIGLOO2 I/Os are partitioned into multiple I/O voltage banks. The number of banks depends on the device. There are seven(7) I/O banks in M2GL025 and eight(8) I/O banks in the M2GL050 device.Table 4 shows a summary of organization of the I/O banks between M2GL025 and M2GL050 FPGA devices.Main crystal oscillator (32 KHz - 20 MHz)11Auxiliary crystal oscillator (32 KHz - 20 MHz)1-Table 4 • Organization of the I/O Banks in IGLOO2 DevicesI/O Banks VF400 PackageM2GL025TM2GL050TBank 0DDRIO: MDDR or fabricDDRIO: MDDR or fabricBank 1MSIO: fabric MSIO: fabric Bank 2MSIO: fabric –Bank 3MSIO: JTAG MSIO: fabric Bank 4MSIO: fabricMSIO: JTAG Bank 5MSIOD: SERDES_0 or fabric DDRIO: fabricBank 6MSIOD: fabric MSIOD: SERDES_0 or fabric Bank 7MSIO: fabric MSIOD: fabric Bank 8–MSIO: fabricTable 3 • On-Chip Oscillator Support Per DeviceFeatureVF400 PackageM2GL025M2GL050Migrating Designs Between IGLOO2 M2GL025 and M2GL050 in VF400 Package4Package pins VDDIx are the bank power supplies where x indicates the bank number. For example,VDDI0 is bank0 power supply. Figure 1 and Figure 2 show the different I/O bank locations and numbers per device in the VF400 package.An MSIO bank supports 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V voltage standards. MSIOD or DDRIO bank supports 1.2 V, 1.5 V, 1.8 V, or 2.5 V voltage standards. The 3.3 V voltage standard is not supported for MSIOD or DDRIO I/Os. For more details on user I/O pins (MSIO, MSIOD, and DDRIO) and supported voltage standards, refer to the "Supported Voltage Standards" table in the IGLOO2 FPGA Fabric Architecture User Guide .Figure 1 • IGLOO2 M2GL050T VF400 I/O Bank LocationsFigure 2 • IGLOO2 M2GL025T VF400 I/O Bank LocationsDesign Migration5Pin Migration and CompatibilityAlthough the IGLOO2 devices and packaging have been designed to allow footprint compatibility for smoother migration, some of the pins have a reduced compatibility feature set between M2GL025 and M2GL050 devices in the VF400 package. This section addresses the different aspects of pin compatibility. The differences can be grouped into three categories:•Global Versus Regular Pins •Available versus No Connect Pins•I/Os Technology Compatibility Per Pin or Bank •Probe PinsGlobal Versus Regular PinsWhen migrating designs between IGLOO2 devices, it is important to evaluate the different types of pins that are available per device. The functionality of the same pin can be different between devices. This section focuses on highlighting and comparing the global pins in one device against the other devices.Therefore, migration can be evaluated and planned from one device to another without any resource conflicts or issues.•Moving from a device, where the I/O is a global pin to a device where the same I/O is a regular pin. In this case, replace the global clock (for example, CLKBUF) with a regular input buffer (for example, INBUF) and then internally promote the signal to a global resource using a CLKINT or synthesis options.•Moving from a device, where the I/O is a regular pin to a device where the same I/O is a global pin. In this case, replace the INBUF with a CLKBUF or keep the INBUF and internally promote the signal to a global using a CLKINT or synthesis options.Table 5 provides a comparison between the global pins available in M2GL025 and M2GL050 devices.The unused global pins are configured as inputs with pull-up resistors by Libero ® System-on-Chip (SoC)software.For more information, refer to the "FPGA Fabric Global Network Architecture" chapter of the IGLOO2Clocking Resources User Guide .Table 5 • Non-Equivalent Global Pins Comparison Per DevicePackage Pin VF400 Pin NamesM2GL025Bank No M2GL050Bank No A3DDRIO62PB0/MDDR_DQ_ECC10DDRIO87PB0/CCC_NW1_CLKI3/MDDR_DQ_ECC10E6DDRIO61PB0/CCC_NW1_CLKI30DDRIO88PB00R13MSIO 134PB4/VCCC_SE1_CLKI 4DDRIO 164PB5/VCCC_SE1_CLKI 5U11MSIO 125NB4/GB7/CCC_SW1_CLKI24DDRIO 152NB5/GB7/CCC_SW1_CLKI25U13MSIO 133PB4/GB15/VCCC_SE1_CLKI 4DDRIO 163PB5/GB15/VCCC_SE1_CLKI 5V11MSIO 125PB4/GB3/CCC_SW0_CLKI34DDRIO 152PB5/GB3/CCC_SW0_CLKI35V12MSIO 130PB4/VCCC_SE0_CLKI 4DDRIO 160PB5/VCCC_SE0_CLKI 5W10MSIO 120NB4/CCC_SW0_CLKI24DDRIO 147NB5/CCC_SW0_CLKI25W13MSIO 131PB4/GB11/VCCC_SE0_CLKI 4DDRIO 161PB5/GB11/VCCC_SE0_CLKI 5Y12MSIO 129PB4/CCC_SW1_CLKI34DDRIO 159PB5/CCC_SW1_CLKI35Migrating Designs Between IGLOO2 M2GL025 and M2GL050 in VF400 Package6Table6 shows the list of global pins that are similar between the two devices.Refer to the "Dedicated Global I/O Naming Conventions" section in the IGLOO2 Pin Descriptions. Table 6 • Equivalent Global Pins Per DevicePackagePinVF400 Pin NamesM2GL025BankNo M2GL050BankNo A1DDRIO65PB0/GB0/CCC_NW0_CLKI30DDRIO91PB0/GB0/CCC_NW0_CLKI3A11DDRIO49PB0/CCC_NE1_CLKI3/MDDR_DQ140DDRIO75PB0/CCC_NE1_CLKI3/MDDR_DQ14B1DDRIO65NB0/GB4/CCC_NW1_CLKI20DDRIO91NB0/GB4/CCC_NW1_CLKI2C9DDRIO52PB0/GB8/CCC_NE0_CLKI3/MDDR_DQS10DDRIO78PB0/GB8/CCC_NE0_CLKI3/MDDR_DQS1D10DDRIO50PB0/GB12/CCC_NE1_CLKI2/MDDR_DQ120DDRIO76PB0/GB12/CCC_NE1_CLKI2/MDDR_DQ12D3DDRIO66NB0/CCC_NW0_CLKI20DDRIO92NB0/CCC_NW0_CLKI20D9DDRIO53PB0/CCC_NE0_CLKI2/MDDR_DQ100DDRIO79PB0/CCC_NE0_CLKI2/MDDR_DQ10E18MSIO28PB1/GB14/VCCC_SE1_CLKI1MSIO42PB1/GB14/VCCC_SE1_CLKI1F19MSIO26PB1/CCC_NE1_CLKI11MSIO40PB1/CCC_NE1_CLKI11G1MSIO97PB7/GB2/CCC_NW0_CLKI17MSIO115PB8/GB2/CCC_NW0_CLKI18G14MSIO25PB1/CCC_NE0_CLKI11MSIO39PB1/CCC_NE0_CLKI11G17MSIO27PB1/GB10/VCCC_SE0_CLKI1MSIO41PB1/GB10/VCCC_SE0_CLKI1G2MSIO96PB7/GB6/CCC_NW1_CLKI17MSIO114PB8/GB6/CCC_NW1_CLKI18H1MSIOD100PB6/GB5/CCC_SW1_CLKI16MSIOD118PB7/GB5/CCC_SW1_CLKI17H20MSIO20NB2/GB13/VCCC_SE1_CLKI2MSIO20NB3/GB13/VCCC_SE1_CLKI3H5MSIO98PB7/CCC_NW1_CLKI07MSIO116PB8/CCC_NW1_CLKI08J19MSIO20PB2/GB9/VCCC_SE0_CLKI2MSIO20PB3/GB9/VCCC_SE0_CLKI3J2MSIOD102PB6/CCC_SW1_CLKI06MSIOD120PB7/CCC_SW1_CLKI07J4MSIOD101PB6/GB1/CCC_SW0_CLKI16MSIOD119PB7/GB1/CCC_SW0_CLKI17J7MSIO99PB7/CCC_NW0_CLKI07MSIO117PB8/CCC_NW0_CLKI08K7MSIOD103PB6/CCC_SW0_CLKI06MSIOD121PB7/CCC_SW0_CLKI07M17MSIO11NB2/CCC_NE1_CLKI02MSIO11NB3/CCC_NE1_CLKI03N16MSIO11PB2/CCC_NE0_CLKI02MSIO11PB3/CCC_NE0_CLKI03Design Migration7Available versus No Connect PinsThere are pins that have one specific function in one device while those same pins are "no connect" (NC)in the other device. Table 7 lists the summary of these pins. For example, pin Y17 functions as the VPP pin in the M2GL025 while it is an NC in the M2GL050 device.Similarly, P13 pin is an NC in the M2GL025 but it is a VREF5 pin in the M2GL050 device.When moving from a device, where the I/O is an NC pin to a device where the I/O has a defined functionality and it is not used, follow the recommended methods for connecting the unused I/Os depending on the functionality of that I/O. Refer to "Unused Pin Configurations" in the Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGA Application Note .When moving from a device, where the I/O has a defined functionality to a device where the I/O is an NC,then the NC pins can be driven to any voltage or can be left floating with no effect on the operation of the device. NC indicates that the pin is not connected to circuitry within the device.I/Os Technology Compatibility Per Pin or BankTable 8 shows the list of I/Os that would lead to incompatibility with the different technology support while migrating between M2GL025 and M2GL050 within the VF400 package. The difference is the type of I/O technology (MSIO versus DDRIO) that is supported on those regular I/Os. Table 7 • Available versus NC PinsPackage Pin VF400 Pin NamesM2GL025M2GL050Y17VPP NC W17VPP NC P13NC VREF5R11NCVREF5Table 8 • I/O Standards Compatibility Per Device or Package Pins Package Pin VF400 Pin NamesM2GL025Bank NoM2GL050Bank NoR12MSIO 134NB44DDRIO 164NB55R13MSIO 134PB4/VCCC_SE1_C LKI4DDRIO 164PB5/VCCC_SE1_C LKI5T13MSIO 133NB44DDRIO 163NB55T14MSIO 144PB44DDRIO 184PB55T15MSIO 144NB44DDRIO 184NB55U11MSIO 125NB4/GB7/CCC_SW 1_CLKI24DDRIO 152NB5/GB7/CCC_SW 1_CLKI25U12MSIO 130NB44DDRIO 160NB55U13MSIO 133PB4/GB15/VCCC_SE1_CLKI 4DDRIO 163PB5/GB15/VCCC_S E1_CLKI 5U14MSIO 142NB44DDRIO 181NB55V11MSIO 125PB4/GB3/CCC_SW 0_CLKI34DDRIO 152PB5/GB3/CCC_SW 0_CLKI35V12MSIO 130PB4/VCCC_SE0_C LKI4DDRIO 160PB5/VCCC_SE0_C LKI5V14MSIO 142PB44DDRIO 181PB55V15MSIO 146NB44DDRIO 190NB55W10MSIO 120NB4/CCC_SW0_CL KI24DDRIO 147NB5/CCC_SW0_CL KI25Migrating Designs Between IGLOO2 M2GL025 and M2GL050 in VF400 Package8The DDRIOs do not support single ended 3.3 V I/O standards and differential LVPECL, LVDS 3.3 V, LVDS 2.5 V, RSDS BLVDS, MLVDS, and Mini-LVDS I/O standards, as shown in Table9. To migrate from M2GL025 to M2GL050 successfully, ensure that the correct VDDI power supply is used to power the equivalent banks. Only I/Os with compatible standards can be assigned to the same bank.W12MSIO121NB4/PROBE_B4DDRIO148NB5/PROBE_B5W13MSIO131PB4/GB11/VCCC_SE0_CLKI4DDRIO161PB5/GB11/VCCC_SE0_CLKI5W14MSIO131NB44DDRIO161NB55W15MSIO146PB44DDRIO190PB55Y10MSIO120PB44DDRIO147PB55Y11MSIO121PB4/PROBE_A4DDRIO148PB5/PROBE_A5Y12MSIO129PB4/CCC_SW1_CLKI34DDRIO159PB5/CCC_SW1_CLKI35Y13MSIO129NB44DDRIO159NB55Y15MSIO145PB44DDRIO187PB55Y16MSIO145NB44DDRIO187NB55Table 9 • Technology Support Difference Between Different I/O TypesI/O StandardsI/O TypesMSIO DDRIOSingle-Ended I/OLVTTL 3.3V Yes–LVCMOS 3.3V Yes–PCI Yes–LVCMOS 1.2V Yes YesLVCMOS 1.5V Yes YesLVCMOS 1.8V Yes YesLVCMOS 2.5V Yes YesVoltage-Referenced I/OHSTL 1.5V Yes YesSSTL 1.8Yes YesSSTL 2.5Yes YesSSTL 2.5 V(DDR1)Yes YesSSTL 1.8 V(DDR2)Yes YesSSTL 1.5 V (DDR3)Yes YesDifferential I/OLVPECL (input only)Yes–LVDS 3.3 V Yes–LVDS 2.5 V Yes–RSDS Yes–BLVDS Yes–Table 8 • I/O Standards Compatibility Per Device or Package Pins (continued)PackagePinVF400 Pin NamesM2GL025Bank No M2GL050Bank NoDesign Migration9Note:Even though the VDDI might be the same (for example, MSIO 2.5 V and DDRIO 2.5 V), theattributes and features supported might be different between different I/O types (MSIO versus DDRIO). Refer to the "I/O Programmable Features" section in the IGLOO2 FPGA Fabric Architecture User Guide for more information on the list of features supported per I/O type.Probe PinsProbe pins locations are compatible between the two devices. Table 10 shows the different probe I/Os location per device within the VF400 package. By default, probe pins are reserved for the probe functionality. Unreserve these pins by clearing the Reserve Pins for Probes check box in the "Device I/O Settings" under Project Setting in Libero SoC software. When the pins are not reserved, the probe I/Os can be used as regular I/Os.Note:Different I/O technologies are supported on these pins (MSIO versus DDRIO). Refer to "I/OsTechnology Compatibility Per Pin or Bank" on page 7 for more information.Power Supply and Board-Level ConsiderationsI/O power supply requirements are one of the key aspects to consider for design migrations. Since the migration is within the IGLOO2 family, there is no issue regarding the core voltage (VDD), charge pumps voltage (VPP), and analog sense circuit supply of the eNVM voltage (VPPNVM). The ground pins (VSS)are also equivalent between M2GL025 and M2GL050 devices. Refer to the IGLOO2 Pin Descriptions for more details. The bank supply voltages VDDI pins must be connected appropriately. Refer to the "Recommendation for Unused Bank Supplies" connections table in the Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGA Application Note for more information in case where the specific banks are not used. An MSIO bank supports 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V voltages and an MSIOD and DDRIO bank supports 1.2 V, 1.5 V, 1.8 V, or 2.5 V voltages. For more details on user I/O pins (MSIO,MSIOD, and DDRIO) and supported voltage standards, refer to the "Supported Voltage Standards" table in the IGLOO2 FPGA Fabric Architecture User Guide .The banks have dedicated supplies. Therefore, only I/Os with compatible voltage standards can be assigned to the same I/O voltage bank. The correct bank supply must be used when migrating between the different devices per the appropriate voltages (I/O Standards) selected for the bank. Table 11 shows the different banks power supply compatibility per device in the VF400 package.MLVDS Yes –Mini-LVDSYes–Table 10 • Probe Pins Per DevicePackage Pin VF400 Pin NamesM2GL025Bank No M2GL050Bank No W12MSIO 121NB4/PROBE_B 4DDRIO 148NB5/PROBE_B 5Y11MSIO 121PB4/PROBE_A4DDRIO 148PB5/PROBE_A5Table 11 • Power Supply Compatibility Per DevicePackage PinVF400 Pin NamesM2GL025M2GL050F2VDDI7VDDI8G5VDDI7VDDI8H18VDDI2VDDI3J1VDDI6VDDI7 J8VDDI7VDDI8Table 9 • Technology Support Difference Between Different I/O Types (continued)I/O Standards I/O TypesMSIO DDRIOMigrating Designs Between IGLOO2 M2GL025 and M2GL050 in VF400 Package10For the other bank supplies that are equivalent, refer to the provided recommendations in the IGLOO2 Pin Descriptions.Any other board-level considerations are common among the three devices. Refer to the Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGA Application Note for more details.Software FlowThe Libero® SoC Software provides the option of reserving pins for moving between different devices within the IGLOO2 family where pins within the current device that are not bonded in the destination device can be automatically reserved. This option is available in I/O Constraints Editor which can be accessed from the Design Flow window as shown in Figure3. This is done in the early stages of the design cycle.Follow the procedure given below to reserve pins:K4VDDI6VDDI7L17VDDI2VDDI3L8VDDI6VDDI7M20VDDI2VDDI3N14VDDI2VDDI3N3VDDI6VDDI7P16VDDI2VDDI3R14VDDI3VDDI4R19VDDI2VDDI3R3VDDI5VDDI6T12VDDI4VDDI5U15VDDI4VDDI5V18VDDI2VDDI3W11VDDI4VDDI5Y14VDDI4VDDI5Table 11 • Power Supply Compatibility Per Device (continued)Package PinVF400 Pin NamesM2GL025M2GL050Design Migration111.After finishing the Compile process, select the I/O Constraints option from the Design Flowwindow as shown in Figure 3.2.Select the Reserve Pins for Device Migration option from the Tools menu. The window shownbelow in Figure 4 is displayed.Figure 3 • I/O Constraint Editor Option part of the Design FlowMigrating Designs Between IGLOO2 M2GL025 and M2GL050 in VF400 Package12The first option shows the device that is currently being used in the Libero SoC project. From thedrop-down list, select the device that eventually will be migrated to as the target device. Refer to the Libero Soc software online help for more details on this window and other options.The Libero SoC software provides the option of moving between different devices within the IGLOO2family by changing the device selection using the Project Settings option in the Libero SoC software.Upon changing the device, Libero SoC software validates the features that are used within the design against the supported features within the new targeted device and package. Feedback messages are provided as part of the Libero SoC software flow listing the different actions taken by Libero SoC and the action required.The first step that Libero SoC performs upon changing the device is to invalidate the original design components and the design flows. The message is displayed as shown in Figure 5.Figure 4 • Reserve Pins for Device MigrationFigure 5 • Invalidating Component and Design Flow MessageConclusion 13As part of re-running the design flow, Libero SoC checks the different steps needed to be performed for completing and updating the design flow. Furthermore, Libero SoC converts the HPMS configurations to be compatible with the selected device and package combination.As part of the HPMS conversion, any changes that were made automatically to be compatible with the device and package selected will be printed to the log window. Libero SoC disables or defaults to different options if the current selected options are not supported in the new targeted device and package.After the HPMS configuration conversion is done, HPMS must be regenerated. To regenerate the HPMS component, open the HPMS component from Libero SoC Design Hierarchy Flow window and proceed through the different HPMS pages to complete the generation.ConclusionThis application note describes the design migration among IGLOO2 family devices focusing on migration between M2GL025 and M2GL050 within the VF400 package. IGLOO2 family devices share many common architectural features. During design migration, architecture differences between devices should be kept in mind to ensure seamless migration flow. Additionally, a key requirement is to run the functional simulation and timing analysis before and after the migration using Microsemi tools.List of ChangesThe following table lists critical changes that were made in the current version of the document. RevisionChanges PageRevision 1(February 2014)First version51900284-1/02.14© 2014 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor solutions for: aerospace, defense and security; enterprise and communications; and industrial and alternative energy markets. Products include high-performance, high-reliability analog and RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at .Microsemi Corporate HeadquartersOne Enterprise, Aliso Viejo CA 92656 USAWithin the USA: +1 (949) 380-6100Sales: +1 (949) 380-6136Fax: +1 (949) 215-4996。

智能融合2系列SoC FPGA开发板使用指南说明书

Application Note AC401January 20141© 2014 Microsemi Corporation SmartFusion2 SoC FPGA - SPI Master ProgrammingTable of ContentsPurposeThis application note describes how to use the serial peripheral interface (SPI) Master Programming mode on SmartFusion ®2 system-on-chip (SoC) field programmable gate array (FPGA) Development Kit board DVP-102-000400-001 Rev C.Note:Rev A and Rev B Development Kit Board are not supported.Two software utilities, SPI_Memory.exe and SetMuxes.exe, are described in this document. The SPI_Memory.exe is used to program Atmel ® AT25DF641 and SetMuxes.exe is used to configure the multiplexers on the Development Kit board to either perform SPI Memory Programming or initiate SPI Master Programming.IntroductionSPI Master Programming mode, also known as auto-update or reflash is one of the programming methods available to program SmartFusion2 devices. Refer to the SmartFusion2 Programming User's Guide for more information on the available programming modes. On power-up or resetting the device with FLASH_GOLDEN_N pin asserted (driven low), the SmartFusion2 device configures the dedicated SPI port to operate in Master mode. It also reads the attached external SPI memory device from address zero. Auto programming is executed if a valid programming image is found. Figure 1 shows a high level system design to execute auto programming.Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Development Kit Board Programming Circuit Design Description . . . . . . . . . . . . . . . . . . . . 2Programming the SPI Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Appendix A - SPI Memory Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Appendix B - SetMuxes Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7SmartFusion2 SoC FPGA - SPI Master Programming2Development Kit Board Programming Circuit Design DescriptionThe Development Kit board programming circuitry has an on board FT4232H module from Future Technology Devices International (FTDI). This module is a universal serial bus (USB)-to-serial interface converter. For more information on FT432H module, see FTDI website at /Products/Modules/DevelopmentModules.htm. This module is connected to the M2S dedicated SPI port and the SPI memory device using the multiplexers. The multiplexers can then be configured either manually or through SetMuxes.exe utility described below to program the Atmel SPI memory device or to initiate an auto-programming operation. The Development Kit board is designed in this fashion to program the SPI memory device on board through the FTDI chip. Figure 2 shows how the multiplexers are connected.Figure 1 • Auto Programming (SPI- Master) ModeDevelopment Kit Board Programming Circuit Design Description3Figure 2 • Connection of MultiplexersFigure 3 • Development Kit Board Programming Circuit - Auto Programming ModuleSmartFusion2 SoC FPGA - SPI Master Programming4Note:Some of the FT4232H I/O pins control the enable and select signals of the multiplexers.SetMuxes.exe configures these pins to either perform the SPI memory programming manually or initiate auto-programming.Programming the SPI MasterThe following steps describe how to program the SPI master.1.Set the jumpers on the Development Kit board as:–J43 (Pin 1 - Pin 2)–J55 (Pin 1 - Pin 2)–J70 (Pin 2 - Pin 3)2.Install the FTDI drivers based on the operating system as described in the FTDI driver installationguide available at: /Support/Documents/InstallGuides.htm.3.Copy the following files into a local directory on your PC.–FTCJTAG.dll: Used for interfacing FT2232 to devices using the JTAG protocol.Note:Click the file name to download a ZIP file containing the library.–libMPSSE.dll : This library has been created to aid the implementation of I2C designs using FTDI devices which incorporate the FTDI MPSSE.–SetMuxes.exe: Refer "Appendix B - SetMuxes Utility"for more information.–SPI_Memory.exe: Refer "Appendix A - SPI Memory Utility"for more information.–Click here to download a sample demo project containing both the exe files.4.Copy the programming file (.spi) to a local directory on the PC. Use one of the .spi files included inthis demo package or generate a design and export it through Libero ® System-on-Chip (SoC)software. For more information on how to use Libero software, refer /download/software/liberosoc/default.aspx.5.Open the Command Prompt and navigate to the directory where the files are saved.6.Connect the Development Kit board mini USB (J24) to the PC.7.Power-up the Development Kit board.Figure 4 • Development Kit Board Programming Circuit - FT4232H ModuleProgramming the SPI Master58.In the command prompt, type:SetMuxes MEMThis application sets the multiplexers for the FTDI chip to access the Atmel memory device on the board. Figure 4 shows an example message on successful setting-up of the multiplexers.9.In the command prompt, type:SPI_Memory -aprogram <file name>.spiThis updates the Atmel spi memory device, as shown in Figure 6.10.In the command prompt type the following:SetMuxes REFFigure 5 • SetMuxes MEMFigure 6 • aprogram <file name>.spiSmartFusion2 SoC FPGA - SPI Master Programming6This command sets the multiplexers for the M2S chip to access the Atmel memory device on the board and initiates reflash, as shown in Figure 7. The M2S device functions with a delay of approximately a minute. The functioning is based on the design that you programmed.Note:With this configuration, any subsequent resets to the device or board power cycle initiate thereflash operation again.11.In the command prompt type the following:SetMuxes SPIThis application sets the multiplexers for the FTDI chip to access the M2S device, as shown in Figure 8.List of ChangesThe following table lists critical changes that were made in the current version of the document.Figure 7 • SetMuxes REFFigure 8 • SetMuxes SPIRevisionChanges in Current Version (51900145-2/2.08*)Page Revision 1January 2014Updated the section "Programming the SPI Master"(SAR 53223).4Appendix A - SPI Memory Utility7Appendix A - SPI Memory UtilitySPI_Memory.exe is a standalone command line utility that uses the FTDI chip to program the SPI file into the Atmel AT25DF641 memory device used in the Development Kit board. This supports the following platforms:•Windows XP •Windows Vista •Windows 7Usage: spi_memory [options] <filename> Available options:•-h : show help message •-a<action>: Specify action name as follows:–read_id: Read device ID.–Blank: Checks to see if device is in erased state.–Erase: Erases the entire device.–Program: Programs the content of the file into the device starting at address 0.–Verify: Verifies the content of the device against the file.–Read: Reads the content of the device and saves it in ReadBuffer.bin.Appendix B - SetMuxes UtilitySetMuxes.exe configures the multiplexers on the Development Kit board based on the desired operation.This supports the following platforms:•Windows XP •Windows Vista •Windows 7Usage: SetMuxes [options]MEM: Configures the multiplexers to enable FTDI connection to the SPI memory device on the dedicated SPI port.REF: Configures the multiplexers to connect the M2S device to the SPI memory device and initiate reflash.SPI: Configures the multiplexers to connect the M2S device to FTDI for SPI- Slave programming.51900269-1/01-14© 2013 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor solutions for: aerospace, defense and security; enterprise and communications; and industrial and alternative energy markets. Products include high-performance, high-reliability analog and RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at .Microsemi Corporate HeadquartersOne Enterprise, Aliso Viejo CA 92656 USAWithin the USA: +1 (949) 380-6100Sales: +1 (949) 380-6136Fax: +1 (949) 215-4996。

8通道2U高密度安装音频放大器说明书

▸▸Eight channels in 2U –▸Extremely▸high▸channel▸density▸reduces▸space▸requirements▸and▸installation▸time▸▸High continuous output power of 250 W per channelat 70 V, 4 ohms, 8 ohms, and 16 ohms*▸▸All channels individually selectable for lo-Z or hi-Z Loudspeakers▸(2▸ohm▸–▸16▸ohm)▸and▸distributed▸systems▸can▸be▸connected▸to▸the▸same▸unit▸▸Bridged operation – Channel▸pairs▸bridgeable▸for▸increased▸output▸or▸for▸driving▸100▸V▸systems▸▸▸Patented output stage based on Class D topology▸▸High efficiency for lower thermal stress ▸▸General Purpose Input/Output (GPIO) – Compatible▸with▸third-party▸control▸systems▸▸NomadLink® network ready▸▸Universal Power Factor Corrected PSU with IEC inlet▸▸Efficient cooling – Dual▸variable▸speed,▸intelligent▸fans▸and▸parallel▸airflow▸over▸output▸devices▸provide▸uniform▸cooling ▸▸Comprehensive circuit protection and fault indication ▸▸Phoenix-style input connectors and barrier strip output connectorsAn Installation Amplifier without CompromiseLab.gruppen▸amplifiers▸have▸earned▸an▸enviable▸worldwide▸reputa-tion▸for▸sonic▸excellence▸and▸rock-solid▸durability▸in▸touring▸sound▸applications.▸These▸same▸qualities▸are▸now▸available▸for▸a▸broad▸range▸of▸installed▸sound▸applications▸in▸the▸C▸20:8X▸amplifier.▸By▸offering▸an▸unmatched▸combination▸of▸channel▸density,▸operating▸ef-ficiency▸and▸configuration▸flexibility,▸the▸C▸20:8X▸presents▸convincing▸performance▸and▸cost-saving▸advantages.▸Applications▸include▸pri-mary▸systems▸for▸theme▸parks,▸shopping▸malls,▸airports,▸hotels▸and▸▸restaurants▸as▸well▸as▸auxiliary▸systems▸for▸performance▸venues,▸houses▸of▸worship▸and▸numerous▸other▸installed▸sound▸applications. To▸achieve▸higher▸channel▸density▸without▸compromising▸per-formance,▸Lab.gruppen▸engineers▸developed▸a▸new▸output▸stage▸design.▸Based▸on▸a▸patented▸Class▸D▸circuit▸topology,▸these▸output▸stages▸produce▸sustained▸high▸power▸levels▸with▸very▸low▸distortion▸while▸maintaining▸efficiency▸levels▸of▸near▸90%.▸A▸new▸universal▸switching▸power▸supply▸employs▸Power▸Factor▸Correction▸(PFC)▸▸to▸stabilize▸current▸draw,▸and▸it▸accepts▸any▸mains▸voltage▸from▸▸65▸–▸265▸V▸(+/-▸10%)▸@▸50▸Hz▸or▸60▸Hz▸through▸the▸appropriate▸▸IEC▸cord.The▸C▸20:8X▸includes▸unique▸features▸which▸enable▸each▸unit▸–▸or▸even▸each▸channel▸–▸to▸be▸configured▸for▸a▸specific▸application▸or▸load▸condition.▸Input▸gain▸is▸selectable▸in▸four-channel▸groups,▸and▸a▸35▸Hz▸high▸pass▸filter▸may▸be▸inserted.▸All▸channels▸are▸bridgeable▸in▸pairs,▸and▸Lab.gruppen’s▸exclusive▸Voltage▸Peak▸Limiter▸(VPL)▸fea-ture▸allows▸each▸channel▸to▸be▸individually▸optimized▸for▸the▸reactive▸characteristics▸of▸the▸connected▸load.For▸comprehensive▸remote▸monitoring▸and▸control,▸the▸C▸20:8X▸includes▸NomadLink®▸network▸ports▸for▸connecting▸to▸an▸optional▸NLB▸60E▸NomadLink®▸Bridge▸&▸Network▸Controller▸and▸an▸Ethernet-linked▸PC.▸With▸NomadLink®,▸key▸amplifier▸parameters▸are▸displayed▸via▸DeviceControl▸software,▸and▸remote▸control▸of▸channel▸mute▸and▸power▸on/off▸is▸under▸network▸control.▸Alternatively,▸the▸GPIO▸▸facilities▸allow▸access▸to▸key▸amplifier▸functions▸via▸third-party▸▸remote▸control▸systems.▸To▸ensure▸a▸long▸and▸trouble-free▸service▸life,▸the▸C▸20:8X▸▸incorporates▸extensive▸features▸to▸safeguard▸internal▸circuits▸and▸connected▸loads.▸Protection▸and▸warning▸circuits▸prevent▸damage▸or▸service▸interruptions▸due▸to▸excessive▸current,▸DC▸at▸output,▸▸over-temperature,▸non-musical▸VHF▸(very▸high▸frequencies),▸and▸open▸load▸conditions.▸In▸addition,▸soft-start▸and▸PSU▸current▸limit-ing▸protect▸the▸mains▸supply▸from▸interruptions▸due▸to▸tripped▸circuit▸breakers▸or▸blown▸mains▸fuses.*▸Maximum▸continuous▸output▸power,▸all▸channels▸▸▸▸▸▸driven,▸VPL▸set▸at▸100▸V▸and▸Gain▸set▸at▸32▸dB ▸Auditoriums▸Performing Arts Centers▸Convention Centers▸Stadiums and Arenas▸Theme Parks▸Hotels▸Houses of Worship▸Restaurants▸Clubs▸Educational Establishments▸Boardrooms▸Museums▸Offices▸Shopping Malls▸Transportation Facilities ApplicationsC 20:8XItem no. TDS-C208X_V6GeneralNumber▸of▸channels8Peak▸total▸output▸all▸channels▸driven 2000▸WPeak▸output▸voltage▸per▸channel 100▸V▸/▸70▸Vrms Max.▸output▸current▸per▸channel 8▸Arms Max. Output Power 16 ohms 8 ohms 4 ohms 2 ohms Hi-ZPer▸ch.▸(all▸ch.’s▸driven)250▸W 250▸W 250▸W 125▸W 250▸W▸(70▸Vrms▸/▸100▸V▸peak)Bridged▸per▸ch.500▸W500▸W250▸Wn.r.500▸W▸(140▸Vrms▸/▸200▸V▸peak)Performance with Gain: 32 dB and VPL: 100 V THD▸20▸Hz▸-▸20▸kHz▸for▸1▸W<0.1%THD▸at▸1▸kHz▸and▸1▸dB▸below▸clipping <0.05%Signal▸To▸Noise▸Ratio>112▸dBA Channel▸separation▸(Crosstalk)▸at▸1▸kHz>70▸dBFrequency▸response▸(1▸W▸into▸8▸ohms)▸+0/-3▸dB 6.8▸Hz▸-▸34▸kHz Input▸impedance20▸kOhm Input▸Common▸Mode▸Rejection,▸CMR 50▸dB Output▸impedance▸@▸100▸Hz48▸mOhmVoltage Peak Limiter (VPL), max. peak output VPL,▸selectable▸per▸ch.▸(V)▸3)100,▸63,▸45,▸32▸V VPL,▸selectable▸when▸bridged▸(V)▸3)▸1)200,▸126,▸90,▸64▸V Voltage▸Peak▸Limiter▸mode▸(per▸ch.)Hard▸/▸SoftGain and LevelAmplifier▸gain▸selectable▸(all▸channels)▸1)▸–▸rear-panel▸switches 29,▸32,▸35,▸38▸dBDefault▸gain32▸dBLevel▸adjustment▸(per▸ch.)Front-panel▸potentiometer,▸21▸position▸detented▸from▸-inf▸to▸0▸dB,▸hidden▸behind▸security▸panel/dust▸filter▸grilleConnectors and switches Input▸connectors▸(per▸ch.)3-pin▸Phoenix,▸electronically▸balanced Output▸connectors▸(per▸ch.)Barrier▸strip▸2-pole▸screw▸terminals Output▸bridge▸mode A+B,▸C+D,▸E+F ,▸G+H,▸inputs▸A,▸C,▸E,▸G▸are▸signal▸source High▸pass▸filterFixed▸at▸35▸Hz,▸switchable▸per▸channelNomadLink ®▸network On▸board,▸2▸x▸RJ45▸connectors,▸IN▸and▸OUT Intelligent▸fans▸(on/off)Y es,▸depending▸on▸presence▸of▸output▸signal Power▸on/off▸and▸Remote▸enable▸on/off Individual▸switches▸on▸front-panelCoolingTwo▸fans,▸front-to-rear▸airflow,▸temperature▸controlled▸speed General▸Purpose▸Outputs▸(GPO)Contact▸Closure▸types,▸2-pole▸Phoenix General▸Purpose▸Inputs▸(GPI)Contact▸Closure▸types,▸2-pole▸PhoenixFront-panel indicators Common NomadLink ®▸Network;▸Power▸Average▸Limiter▸(PAL)▸2);▸Power▸on▸Per▸channelSignal▸present▸/▸High-impedance;▸Voltage▸Peak▸Limiter▸(VPL);▸Current▸Peak▸Limiter▸(CPL):▸Very▸High▸Frequency▸(VHF);▸High▸temperature;▸Fault;▸MutePowerOperating▸voltage,▸230▸V▸/▸115▸V▸nominal 65-265▸V Minimum▸power-up▸voltage,▸230▸V▸/▸115▸V 80▸V Power▸Average▸Limiter▸(PAL)▸2)YesSoft▸start▸/▸Inrush▸current▸draw Yes▸/▸max.▸5▸A Mains▸connector IEC▸InletDimensions (W/H/D)W:▸483▸mm▸(19”),▸H:▸88▸mm▸(2▸U),▸D:▸343▸mm▸(13.5”)Weight 8.5▸kg▸(18.75▸lbs.)FinishBlack▸painted▸steel▸chassis▸with▸gray▸painted▸steel▸front ApprovalsCE,▸ANSI/UL▸60065▸(ETL),▸CSA▸C22.2▸NO.▸60065,▸FCC▸▸Note 1):▸Automatic▸-6▸dB▸gain▸compensation▸when▸bridging▸channels.▸Ch.’s▸A+B▸and/or▸C+D,▸E+F,▸G+H,▸can▸be▸bridged▸individually.▸Note 2):▸PAL▸can▸reduce▸the▸maximum▸output▸power▸to▸keep▸the▸power▸supply▸operating▸safely,▸and/or▸to▸prevent▸excessive▸current▸draw▸tripping▸the▸mains▸breaker.▸▸▸▸▸Refer▸to▸Operation▸Manual.▸Note 3):▸For▸sine▸waves,▸peak▸voltage▸output▸values▸translate▸to▸Vrms▸with▸the▸formula▸V/1.41▸=▸Vrms.▸E.g.▸100▸V▸peak▸equals▸app.▸70▸Vrms.▸▸Hence,▸outputs▸can▸be▸set▸for▸high-impedance▸loads▸without▸requiring▸a▸transformer. All specifications are subject to change without notice.L a b .g r u p p e n a b ▸ S w e d e ni n t e r n a t i o n a L c o n t a c t ▸ i n f o @L a b g r u p p e n .c o m | u S & c a n a d a c o n t a c t ▸ i n f o @t c g -a m e r i c a S .c o mw w w .l a b g r u p p e n .c o mSpecifications C 20:8X。

Microsemi IGLOO2 FPGA 评估板说明书

IGLOO2 FPGA Evaluation KitQuickstart CardKit Contents—M2GL-EVAL-KITQuantity Description1IGLOO2 FPGA 12K LE M2GL010T-1FGG484 Evaluation Board 112 V, 2 A AC power adapter1FlashPro4 JTAG programmer1USB 2.0 A-Male to Mini-B cable1Quickstart cardOverviewThe Microsemi IGLOO®2 FPGA Evaluation Kit makes it easier to develop embedded applications that involve motor control, system management, industrial automation, and high-speed serial I/O applications such as PCIe, SGMII, and user-customizable serial interfaces. The kit offers best-in-class feature integration coupled with the lowest power, proven security, and exceptional reliability. The board is also small form-factor PCIe-compliant, which allows quick prototyping and evaluation using any desktop PC or laptop with a PCIe slot.The kit enables you to:• Develop and test PCI Express Gen2 x1 lane designs• Test signal quality of the FPGA transceiver using the full-duplex SerDes SMA pairs• Measure the low power consumption of the IGLOO2 FPGA• Quickly create a working PCIe link with the included PCIe Control Plane DemoHardware Features• 12K LE IGLOO2 FPGA in the FGG484 package (M2GL010T-1FGG484)• 64 Mb SPI flash memory• 512 Mb LPDDR• PCI Express Gen2 x1 interface• Four SMA connectors for testing the full-duplex SerDes channel • RJ45 interface for 10/100/1000 Ethernet • JTAG/SPI programming interface• Headers for I2C, SPI, and GPIOs• Push-button switches and LEDs for demo purposes• Current measurement test pointsRunning the DemoThe IGLOO2 FPGA Evaluation Kit is shipped with the PCI Express Control Plane demo preloaded. Instructions on running the demo design are available in the IGLOO2 FPGA Evaluation Kit PCIe Control Plane Demo user guide. See the Documentation Resources section for more information. ProgrammingThe IGLOO2 FPGA Evaluation Kit comes with a FlashPro4 programmer. Embedded programming with the IGLOO2 FPGA Evaluation Kit is also available, and it is supported by the Libero SoC v11.4 SP1 or later.Jumper SettingsJumper Development Kit Function Pins Factory DefaultJ23Selects switch-side MUX inputsof A or B to the line side 1–2 (input A to the line side) thatis on board 125 MHz differentialclock oscillator output will berouted to line sideClosed2–3 (input B to the line side)that is external clock requiredto source through SMAconnectors to the line sideOpenJ22Selects the output enablecontrol for the line side outputs 1–2 (line-side output enabled)Closed 2–3 (line-side output disabled)OpenJ24Provides the VBUS supply toUSB when using in Host mode OpenJ8Selects between RVI headeror FP4 header for applicationdebug1–2 FP4 for SoftConsole/FlashPro Closed2–3 RVI for Keil ULINK/IARJ-Link Open2–4 for toggling JTAG_SELsignal remotely using the GPIOcapability of the FT4232 chipOpenJ3Selects either the SW2 inputor the ENABLE_FT4232 signalfrom the FT4232H chip1–2 for manual power switchingusing the SW7 switch Closed2–3 for remote power switchusing the GPIO capability of theFT4232 chipOpenJ31Selects between FTDI JTAGprogramming and FTDI slaveprogramming1–2 for FlashPro FTDI JTAGprogramming Closed2–3 for SPI slave programming OpenJ32Selects between FTDI SPI andSC_SCI header 1–2 for programming throughFTDI SPI Closed 2–3 for programming throughSC_SPI header OpenJ35Selects between FP4 headerand FTDI JTAG 1–2 for programming throughFP4 header Closed 2–3 for programming throughFTDI JTAG Open©2016–2017 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are registered trademarks of Microsemi Corporation. Microsemi Corporate Headquarters One Enterprise, Aliso Viejo, CA 92656 USA Within the USA: +1 (800) 713-4113 Outside the USA: +1 (949) 380-6100 Fax: +1 (949) 215-4996Email:***************************Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer’s responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided “as is, where is” and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself Software and LicensingLibero ® SoC Design Suite offers high productivity with its comprehensive, easy-to-learn, easy-to-adopt development tools for designing with Microsemi’s low power Flash FPGAs and SoC. The suite integrates industry standard Synopsys Synplify Pro ® synthesis and Mentor Graphics ModelSim ® simulation with best-in-class constraints management and debug capabilities.Download the latest Libero SoC release/products/fpga-soc/design-resources/design-software/libero-soc#downloads Generate a Libero Silver license for your kit/products/fpga-soc/design-resources/licensingDocumentation ResourcesFor more information about the IGLOO2 FPGA Evaluation Kit, including user’s guides, tutorials, and design examples, see the documentation at /products/fpga-soc/design-resources/dev-kits/igloo2/igloo2-evaluation-kit#documentation .SupportTechnical support is available online at /soc/support and by email at **********************Microsemi sales offices, including representatives and distributors, are located worldwide. To find your local representative, go to /salescontacts。

IGLOO2 FPGAs商品说明书

IGLOO®2 FPGAsThe Industry’s Lowest-Power FPGAs/FPGA2IGLOO ®2 FPGAsIGLOO ®2 FPGAs Offer More Resources in Low-Density Devices With the Lowest Power, Proven Security and Exceptional ReliabilityIGLOO2 FPGAs are ideal for general-purpose functions such as Gigabit Ethernet or dual-PCI Express control planes, bridgingfunctions, (I/O) expansion and conversion, video/image processing, system management and secure connectivity. FPGAs are used in communications, industrial, medical, defense and aviation markets.IGLOO2 FeaturesMore Resources in Low-Density Devices• PCIe ® Gen 2 support in 10K LE• High-performance memory subsystem • Highest I/O densityWith Clear Advantages• Lowest power• Reduces total power by up to 50% • 70 mW per 5G SERDES (PCIe Gen 2) • Proven security• Protection from overbuilding and cloning • Secure boot for FPGA and processors • Exceptional reliability• SEU immune zero FIT Flash FPGA configuration •Reliable safety-critical and mission-critical systemsIGLOO2 FPGA ArchitectureIGLOO2 FPGAs offer 5K–150K LEs with a high-performance memory subsystem, up to 512 KB embedded Flash, 2 × 32 KB embedded SRAM, two Direct Memory Access (DMA) engines and two Double Data Rate (DDR) memory controllers. Architecture highlights include:• Up to 16× transceiver lanes • PCIe Gen 2, XAUI/XGXS+, generic ePCS mode at 3.2G • Up to 150K LEs, 5 Mbits SRAM, 4 Mbits eNVM• Hard 667 Mbps DDR2/3 controllers• Integrated DSP processing blocks• Power as low as 7 mW standby, typical• DPA-hardened, AES256, SHA256, on-demand NVM dataintegrity check • SEU-protected/tolerant memories: eSRAMs, DDR bridgesPCI ExpressDDR3 ControllerSecure FlashIGLOO2 FPGAs3PCIe 1G Control Plane• PCIe Gen 2 in 10K LE devices With I/O expansionMulti-Axis Motor Control• Deterministic and secure multi-axis/high-RPM solutions • Motor control IP and development kitAudio Processing, Storage, and Retrieval• I 2S-to-SPI bridge allows multiple audio recordings and playbacks/FPGA4Bridging and Co-Processing• SERDES to bridge CPRI, ADC/DACSecure Connectivity• Best-in-class security data communications and anti-tamper • Ultra-low static power for portabilityBoard Initialization• PMBus, instant-onIGLOO2 FPGAs5IGLOO2 FPGA FeaturesHigh-Performance Memory Subsystem• 64 KB embedded SRAM (eSRAM)• Up to 512 KB embedded nonvola -tile memory (eNVM)• One SPI/COMM_BLK• DDR bridge (2 port) with 64-bit AXI interface• Non-blocking, multi-layer AHB bus matrix allowing multi-master scheme supporting 4 masters and 8 slaves• Two AHB/APB interfaces to FPGA fabric (master/slave capable)• Two DMA controllers to offload data transactions• 8-channel peripheral DMA (PDMA) for data transfer between softperipherals in fabric and embedded eSRAMs, as well as support for memory-to-memory transfers• eSRAM and external DDR memory for efficient data movement between embedded real-time memoriesIGLOO2 FPGA SERDES• Up to 16 lanes at up to 5 Gbps • Dual-based reference clocks with single-lane rate granularity• Tx and Rx PLLs programmable for each lane• Reference clock is shared by groups of two lanes• Transmitter features• Programmable pre/post-emphasis • Programmable impedance • Programmable amplitude• Receiver features • Programmable termination• Programmable linear equalization• Built-in system debug features• PRBS gen/chk • Constant patterns • LoopbacksIGLOO2 FPGA Math Block• High-performance and power-optimized multiplication operations • Supports 18 × 18-signed multiplica -tion (natively)• Supports 17×17 unsigned multiplication• Supports dot product: the multi-plier computes (A[8:0] × B[17:9] + A[17:9] × B[8:0]) × 29 independent third input C with data width 44-bits completely registered• Supports both registered and unregistered inputs and outputs• Internal cascade signals(44-bit CDIN and CDOUT)enable cascading of the Math Blocks to supportlarger accumulator, adder,and subtractor withoutextra logic • Supports loopback capability• Adder support: (A×B) + C or (A×B) +D or (A×B) + C + D • Clock-gated inputand output registers for poweroptimizationsSUBA [17:0]B [17:0]C [43:0]CARRYIN ARSHFT17CDSELFDBKSELIGLOO2 FPGA Logic Element• A fully permutable 4-input LUT • A dedicated carry chain based on the carry look-ahead technique• A separate flip-flop that can be used independently from the LUT • Clock-gated input and output registers for power optimizationsA B C D CINLUT_BYPENSYNC_SRCLK RSTCO LORO/FPGA6Design ResourcesLibero ® SoC Design SoftwareLibero SoC Design Suite offers high productivity with its comprehensive, easy-to-learn, easy-to-adopt development tools that are used for designing with Microchip’s power-efficient Flash-based IGLOO2 devices. The suite integrates industry-standard Synopsys Synplify Pro synthesis and Mentor Graphics ModelSim simulation with best-in-class constraints management, debug capabilities, timing analysis, power analysis, secure production programming and push button design flow.This comprehensive suite features an intuitive design flow with GUI wizards to guide the design process. Its easy-to-adopt single-click synthesis to programming flow integrates industry-standard third-party tools, a rich IP library of DirectCores and Companion -Cores and supports complete reference designs and development kits.https:///product-directory/design-resources/1750-libero-socIGLOO2 Evaluation Kit• Gives designers access to IGLOO2 FPGAs that offer leadership in I/O density, security, reliability and low power for mainstream applications • Supports industry-standard interfaces including Gigabit Ethernet, USB 2.0 OTG, SPI, I 2C and UART• Can be powered by a 12V power supply or the PCIe connector and includes a FlashPro4 programmerBoard features• IGLOO2 FPGA in the FGG484 package (M2GL010T -1FGG484)• JTAG/SPI programming interface• Gigabit Ethernet PHY and RJ45 connector • USB 2.0 OTG interface connector • 1 GB LPDDR, 64 MB SPI Flash • Headers for I 2C, UART, SPI, GPIOs • ×1 Gen2 PCIe edge connector •Tx/Rx/Clk SMP pairs/existing-parts/parts/143976Intellectual PropertyMicrochip enhances your design productivity by providing an extensive suite of proven and optimized IP cores for use with FPGAs. Our extensive suite of IP cores covers all key markets and applications. Our cores are organized as either Microchip-developed DirectCores or third-party-developed CompanionCores. Most DirectCores are available for free within our Libero tool suite and include common communications interfaces, peripherals, and processing elements.Below are a few key DirectCores and CompanionCores. Click the below link for more details on IP Cores./product-directory/design-resources/5092-ip-coresIGLOO2 FPGA Product Family*Feature availablility is package dependent.Highlighted devices can migrate vertically in the same packageIGLOO2 FPGAs7SupportMicrochip is committed to supporting its customers in de-veloping products faster and more efficiently. We maintain a worldwide network of field applications engineers and technical support ready to provide product and system assistance. For more information, please visit :• Technical Support: /support • Evaluation samples of any Microchip device: /sample • Knowledge base and peer help: /forums• Sales and Global Distribution: /salesTrainingIf additional training interests you, Microchip offers several resources including in-depth technical training and reference material, self-paced tutorials and significant online resources.• Overview of Technical Training Resources: /training • MASTERs Conferences: /masters • Developer Help Website:/developerhelp • Technical Training Centers: /seminarsMicrochip Technology Inc. | 2355 W. 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All other trademarks mentioned herein are property of their respective companies.© 2019, Microchip Technology Incorporated. All Rights Reserved. 11/19 DS00003294A。

AELTA DVP06XA-E2 说明书

2010-04-22 5011687001-E2X1DVP-1130430-02………………………………………………………………… ENGLISH …………………………………………………………………Thank you for choosing Delta’s DVP series PLC. DVP06XA-E2 mixed analoginput/output module receives external 4 points of analog input signals (voltage or current) and converts them into 16-bit digital signals. For the analog signal output, DVP06XA-E2 receives 2 groups of 16-bit digital data coming from the PLC MPU and converts the digital data into 2 points of analog output signals (voltage or current). In addition, you can access the data in the module by applying FROM/TO instructions or read the average value or write the output value of channels directly by using MOV instruction (Please refer to allocation of special registers D9900 ~ D9999).a This instruction sheet provides only information on the electrical specification,general functions, installation and wiring. For detailed program design and applicable instructions, please refer to “DVP-ES2 Operation Manual: Modules”. For details of the optional peripheral, please refer to the instruction sheet enclosed in it.a This is an OPEN TYPE I/O module and therefore should be installed in an enclosurefree of airborne dust, humidity, electric shock and vibration. The enclosure should prevent non-maintenance staff from operating the device (e.g. key or specific tools are required for operating the enclosure) in case danger and damage on the device may occur.a DO NOT connect the input AC power supply to any of the I/O terminals; otherwiseserious damage may occur. Check all the wiring again before switching on the power.Make sure the ground terminal is correctly grounded in order to preventelectromagnetic interference.Product Profile & DimensionholeExternal Wiringyyy Outputrecorder,scale valve...Terminal of recorder, scale valve...*1: When performing analog input, please isolate other power wirings.*2: When the XA module is connected to current signals, make sure you short-circuit "V+” and “I+”terminals.*3: If the ripples at the loaded input terminal are too significant that causes noise interference on thewiring, connect the wiring to 0.1 ~ 0.47μF 25V capacitor.*4: When performing analog output, please isolate other power wirings.*5: If the ripples at the loaded output terminal are too significant that causes noise interference on thewiring, connect the wiring to 0.1 ~ 0.47μF 25V capacitor.*6: Please connect the terminal on both the power module and XA module to the system earth pointand ground the system contact or connect it to the cover of power distribution cabinet.I /O Terminal LayoutElectrical SpecificationsDVP06XA-E2Power supply voltage 24VDC (20.4VDC ~ 28.8VDC) (-15% ~ +20%) Max. rated power consumption 2.5W, supplied by external power sourceConnectorEuropean standard removable terminal block (Pin pitch: 5mm)DVP06XA-E2Operation/storage Operation: 0°C~55°C (temp.), 50~95% (humidity), Pollution degree2 Storage: -25°C~70°C (temp.), 5~95% (humidity)Vibration/shock immunity International standards: IEC61131-2, IEC 68-2-6 (TEST Fc)/ IEC61131-2 & IEC 68-2-27 (TEST Ea)Series connection to DVP-PLC MPU The modules are numbered from 0 to 7 automatically by their distance from MPU. Max. 8 modules are allowed to connect to MPU and will not occupy any digital I/O points.Functions SpecificationsCommon specifications Digital data format 2’s complement of 16 bits Response time 400μs / each channelOverall accuracy ±0.5% when in full scale within the range of (25°C, 77°F);±1% when in full scale within the range of (0 ~ 55°C, 32 ~ 131°F)Isolation Optical coupler isolation between digital circuits and analog circuits. No isolation among analog channels.500VDC between digital circuits and Ground. 500VDC between analog circuits and Ground. 500VDC between analog circuits and digital circuits. 500VDC between 24VDC and GroundAnalog / DigitalVoltage input Current inputAnalog input channel 4 channels / each moduleRange of analog input ±10V ±5V ±20mA 0 ~ 20mA 4 ~ 20mA Range of digitalconversion±32,000 ±32,000 ±32,000 0 ~ 32,000 0 ~ 32,000Max./Min. output range of digital data ±32,384 ±32,384 ±32,384 -384~+32,384-384~+32,384Hardware Resolution 14 bits 14 bits 14 bits 13 bits 13 bits Input impedance ≧1MΩ 250ΩRange of absolute input±15V ±32mAAverage Function Supported. Available for setting up sampling range in CR#8 ~ CR#11. Range: K1 ~ K100.Self-diagnosis Upper and lower bound detection in all channelsDigital / AnalogVoltage output Current outputAnalog output channel 2 channels / each moduleRange of analog output-10V ~ 10V 0 ~ 20mA 4mA ~ 20mA Range of digitalconversion-32,000 ~ +32,000 0 ~ +32,000 0 ~ +32,000 Max./Min. input range ofdigital data-32,768 ~ +32,767 0 ~ +32,767 -6,400 ~ +32,767 Hardware Resolution 14 bits 14 bits 14 bitsMax. output current 5mA －Tolerance loadimpedance1KΩ ~ 2MΩ0 ~ 500ΩOutput impedance 0.5Ω or lowerProtection Voltage output is protected by short circuit. Short circuit lasting for too long may cause damage on internal circuits. Current output can be open circuit.Control RegisterCR# Attrib. Register name Explanation#0 O R Model name Set up by the system:DVP06XA-E2 model code = H’00C4#1 O R Firmware version Display the current firmware version in hex.#2 O R/W CH1 Input mode setting #3 O R/W CH2 Input mode setting #4 O R/W CH3 Input mode setting #5 O R/W CH4 Input mode setting Input mode: Default = H’0000. Take CH1 for example:Mode 0 (H’0000):Voltage input (±10V) Mode 1 (H’0001):Voltage input (±5V)Mode 2 (H’0002):Voltage input (0 ~+10V) Mode 3 (H’0003):Voltage input (0 ~+5V) Mode 4 (H’0004):Current input (±20mA) Mode 5 (H’0005):Current input (0 ~+20mA) Mode 6 (H’0006):Current input (4 ~+20mA) Mode -1 (H’FFFF):Channel 1 unavailable#6 O R/W CH5 output mode setting #7 O R/W CH6 output mode setting Output mode: Default = H’0000. Take CH5 for example:Mode 0 (H’0000):Voltage output (±10V) Mode 1 (H’0001):Current output (0~+20mA) Mode 2 (H’0002):Current output (4~+20mA) Mode -1 (H’FFFF):Channel 5 unavailable#8 O R/W CH1 sampling range #9 O R/W CH2 sampling range #10 O R/W CH3 sampling range #11 O R/W CH4 sampling range Set sampling range in CH1 ~ CH4: Range = K1 ~ K100Default = K10#12 X R CH1 average input value#13 X R CH2 average input value #14 X R CH3 average input value #15 X R CH4 average input value Average value of input signals at CH1 ~ CH4#16 X R/W CH5 output signal value #17 X R/W CH6 output signal value Voltage output range: K-32,000~K32,000. Current output range: K0~K32,000. Default: K0.#20 X R CH1 present input value#21 X R CH2 present input value#22 X R CH3 present input value#23 X R CH4 present input valuePresent value of input signals at CH1 ~ CH4 #28 O R/W Adjusted Offset value of CH1#29 O R/W Adjusted Offset value of CH2 #30 O R/W Adjusted Offset value of CH3 #31 O R/W Adjusted Offset value of CH4 #32 O R/W Adjusted Offset value of CH5 #33 O R/W Adjusted Offset value of CH6 Set the adjusted Offset value of CH1 ~ CH6 Default = K0.Definition of Offset in DVP06XA -E2:The corresponding voltage (current) input value when the digital output value = 0#34 O R/W Adjusted Gain value of CH1#35 O R/W Adjusted Gain value of CH2 #36 O R/W Adjusted Gain value of CH3 #37 O R/W Adjusted Gain value of CH4 #38 O R/W Adjusted Gain value of CH5 #39 O R/W Adjusted Gain value of CH6 Set the adjusted Gain value in CH1 ~ CH6 Default = K16,000. Definition of Gain in DVP06XA-E2: The corresponding voltage (current) input value when the digital output value = 16,000.#40 O R/W Set value changing prohibited Prohibit set value changing in CH1 ~ CH4 Default= H’0000.#41 X R/W Save all the set values Save all the set values, Default =H’0000CR# Attrib. Register name Explanation#42 X R/W Return to default setting Set all values to default setting, Default = H’0000#43 X R Error statusRegister for storing all error status. Refer to table of error status for more information. #100 O R/W Enable/Disable limit detection Enable/Disable the upper and lower bound detection function. Default= H’0000. #101 X R/W Upper and lower bound status Display the upper and lower bound value, Default =H’0000#102 O R/W Set value of CH1 upper bound #103 O R/W Set value of CH2 upper bound #104 O R/W Set value of CH3 upper bound #105 O R/W Set value of CH4 upper bound #106 OR/W Set value of CH5 upper bound #107 OR/W Set value of CH6 upper bound Set value of CH1~CH6 upper bound. Default = K32000.#108 O R/W Set value of CH1 lower bound #109 O R/W Set value of CH2 lower bound #110 O R/W Set value of CH3 lower bound #111 O R/W Set value of CH4 lower bound #112 O R/W Set value of CH5 lower bound #113 O R/W Set value of CH6 lower bound Set value of CH1~CH6 lower bound. Default = K-32000.#114 O R/W Output update time of CH5 #115 O R/W Output update time of CH6 Set output update time of CH5 ~ CH6#118 O R/WLV output mode setting of Ch5~ Ch6Set the output mode of CH5~CH6 when thepower is at LV (low voltage) condition.Default=0Symbols: O: When CR#41 is set to H’5678, the set value of CR will be saved.X: set value will not be saved.R: able to read data by using FROM instruction. W: able to write data by using TO instruction.Explanation on Special Registers D9900~D9999When DVP-ES2 MPU is connected with modules, registers D9900~D9999 will be reserved for storing values from modules. You can apply MOV instruction to operate values in D9900~D9999.When DVP-ES2 MPU is connected with DVP06XA-E2, the configuration of special registers is as below:Module #0 Module #1 Module #2 Module #3 Module #4 Module #5 Module #6 Module #7 DescriptionD1320 D1321 D1322D1323D1324D1325D1326D1327 Model Code D9900 D9910 D9920D9930D9940D9950D9960D9970CH1 averageinput value D9901 D9911 D9921D9931D9941D9951D9961D9971CH2 averageinput value D9902 D9912 D9922D9932D9942D9952D9962D9972CH3 averageinput value D9903 D9913 D9923D9933D9943D9953D9963D9973CH4 averageinput value D9904 D9914 D9924D9934D9944D9954D9964D9974 CH5 output value D9905 D9915 D9925D9935D9945D9955D9965D9975 CH6 output valueNote 1: D9900 ~ D9999 are average input values of CH1 ~ CH4 and the sampling range is K1 ~ K100.When the sampling range is set to K1, the values displayed in D9900 ~ D9999 are current values. You can use: 1. ES_AIO Configuration Function of WPLSoft or 2. FROM/TO instructions (CR#8~CR#11) to set the sampling range as K1.Adjust A/D Conversion CurveUsers can adjust the conversion curves according to the actual needs by changing the Offset value (CR#28 ~ CR#31) and Gain value (CR#34 ~ CR#37).y Equation for voltage input Mode0 / Mode2: 0.3125mV = 20V/64,000 = 10V/32,000()Offset Gain Offset V V X Y −⎟⎟⎠⎞⎜⎜⎝⎛−××=320001016000)()(Y=Digital output, X=Voltage inputy Equation for voltage input Mode1 / Mode3: 0.15625mV = 10V/64,000 = 5V/32,000()Offset Gain Offset V V X Y −⎟⎟⎠⎞⎜⎜⎝⎛−××=32000516000)()(Y=Digital output, X=Voltage inputy Equation for current input Mode4 / Mode5: 0.625μA = 40mA/64,000 = 20mA/32,000()Offset Gain Offset mA mA X Y −⎟⎟⎠⎞⎜⎜⎝⎛−××=320002016000)()(Y=Digital output, X=Current inputy Equation for current input Mode6: 0.5μA = 16mA/32,000Adopt the equation of current input mode4/mode5, substitute Gain for 19,200 (12mA) and Offset for 6,400 (4mA)()6400192006400320002016000−⎟⎟⎠⎞⎜⎜⎝⎛−××=)()(mA mA X YY=Digital output, X=Current input y Mode 0:y Mode 1:Mode 0 of CR#2 ~ CR#5 ±10V ，Gain = 5V (16,000)，Offset = 0V (0) Mode 1 of CR#2 ~ CR#5±5V ，Gain = 2.5V (16,000), Offset = 0V (0)Range of digital conversion (Max./Min.) ±32,000 (±32,384)y Mode 2:y Mode 3:Digital outputDigital outputMode 2 of CR#2 ~ CR#5 0 ~ +10V, Gain = 5V (16,000), Offset = 0V (0) Mode 3 of CR#2 ~ CR#50 ~ +5V, Gain = 2.5V (16,000), Offset = 0V (0)Range of digital conversion (Max./Min.) 0 ~ +32,000 (-384 ~ +32,384)y Mode 4:Mode 4 of CR#2 ~ CR#5±20mA, Gain = 10mA (16,000), Offset = 0mA (0)Range of digital conversion (Max./Min.) ±32,000 (±32,384)y Mode 5:y Mode 6:Mode 5 of CR#2 ~ CR#5 0 ~ +20mA, Gain = 10mA (16,000), Offset = 0mA (0)Mode 6 of CR#2 ~ CR#5+4 ~ +20mA, Gain = 12mA (19,200), Offset = 4mA (6,400)Range of digital conversion (Max./Min.) 0 ~ +32,000 (-384 ~ +32,384)Adjust D/A Conversion CurveUsers can adjust the conversion curves according to the actual needs by changing the Offset value (CR#32 ~ CR#33) and Gain value (CR#38 ~ CR#39). y Equation for voltage output Mode0: 0.3125mV = 20V/64,000()()⎟⎠⎞⎜⎝⎛×⎥⎦⎤⎢⎣⎡+−×=32000)(1016000V Offset Offset Gain X V YY=Voltage output, X=Digital inputy Equation for current output Mode1: 0.625μA = 20mA/32,000()()⎟⎠⎞⎜⎝⎛×⎥⎦⎤⎢⎣⎡+−×=32000)(2016000mA Offset Offset Gain X mA YY=Current output, X=Digital input y Equation for current output Mode2: 0.5μA = 16mA/32,000Adopt the equation of current output Mode 1, substitute Gain for 19,200(12mA) andOffset for 6,400(4mA)()()⎟⎠⎞⎜⎝⎛×⎥⎦⎤⎢⎣⎡+−×=32000)(20640016000640019200mA X mA YY=Current output, X=Digital inputy mode 0:Mode 0 (CR#2 ~ CR#5)±10V, Gain = 5V (16,000), Offset = 0V (0)Range of digital conversion (Max./Min.) ±32,000 (-32,768 ~ +32,767)y mode 1:Mode 1 (CR#2 ~ CR#5)0 ~ +20mA ，Gain = 10mA (16,000), Offset = 0mA (0)Range of digital conversion (Max./Min.) 0 ~ +32,000 (0 ~ +32,767)y mode 2:Mode 2 (CR#2 ~ CR#5)4 ~ +20mA ，Gain = 12mA (19,200), Offset = 4mA (6,400)Range of digital conversion (Max./Min.) 0 ~ +32,000 (-6400 ~ +32,767)……………………………………………………………… 繁體中文 …………………………………………………………………………感謝您採用台達DVP系列產品。

解码板产品说明书

故障 3：近距离可控制，远距离不能控制。分析： A、 RS485 转换器输出驱动能力不够。 B、控制线长度是否超过 1200 米，要是信号线过长应加 RS485 中继器或 RS485 分配器。
输入电源：AC24V(交流) 功率输出：20-36W (直流：12V 、电流最大为：2A) 云台电压：AC24V（交流）镜头电源电压：12DCV / 500MA 信号通讯方式：RS-485 双芯屏蔽绞线连接地址码范围：0-63，64-127，128-191，192-255 可选择支持协议：多种协议环境指标：温度：0-60 0C 湿度 90%RH
摄像机编码
0/64/128/192 1/65/129/193 2/以下编码 3 4 5 6 7 8 9 10 11 12
地址编码开关与摄像机编号对照表
地址编码开关 123456
摄像机编码
000000
32
100000
33
010000
34
110000
35
001000
36
101000
37
011000
38
111000
3、协议、波特率、地址码可现场设定利于安装调试，通过设置可直接将系统扩充到 255 个地址。
4、波特率是否拨至与主机所要求的波特率一致。 5、地址码是否按要求准确设置好。 6、协议是否设置为主机所要求的协议 7、为了有效的防止雷击及其它干扰，建议架设屏蔽双绞线，应尽可能的避开高压线路
或其它可能的干扰源，同时要将屏蔽线在主机端良好的接地（RS485 S 端子）。控制线不能与电源线同管布线以免电源线产生干扰而影响控制。
二、各接线端子连线示意图
注意：本解码板及云台工作电源电压为 AC24V（交流），请特别注意。（使用电压过高，会造成解码板和云台烧坏）

FPGA模块说明书

FPGA模块1 概述1.1模块结构框图和功能描述该模块具有在线下载和在系统可编程功能,模块可采用总线供电和外部供电两种供电方式；模块中采用的FPGA为altera公司的CycloneⅡEP2C5Q208C8N 的FPGA，具有4608个逻辑单元，119808个比特的嵌入RAM，两个锁相环（PLL），142个用户I/O管脚，可使用Altera的Nios软核和丰富的IP库，快速实现完整的可编程单芯片系统（SOPC）,完全满足复杂的设计要求。

1.2模块系统资源分配：计算机可以通过JATG向FPGA下载程序；FPGA通过本模块提供的丰富I/O口与片外资源发生进行数据交换，从而达到与片外资源进行有效的通信；本模块向用户提供了十分丰富的I/O口，用户可以通过编程对这些Ｉ/O口进行各种操作。

提供了4*4的键盘，8个发光二极管，4个单独的按键。

AS方式与JATＧ方式AS为FPGA主动下载方式，在FPGA主动下载方式中，由目标FPGA来输出控制和同步信号（包括配置时钟）给Altera专用的一种串行配置芯片（EPCS1）,在配置芯片收到命令后，就把配置数据发到FPGA，完成配置过程。

在系统上电后，FPAG和配置器件都进入到上电复位关态（POR）。

这时,FPGA驱动nSTATUS为低，指示其处于“忙”态；同时驱动CONF_DONE为低，表示器件未被配置。

当POR过程完成以后,FPGA随即释放nSTA TUS信号，这个开漏信号被外部的上拉电阻拉为高电平后，FPGA就进入了配置模式。

在AS配置中所有操作均由FPGA发起，它在配置过程中完全处于主动状态。

在该配置模式下，FPGA输出有效配置时钟信号DCLK，它是由FPGA将驱动nCSO信号为低，这就使能了串行配置器件。

FPGA使用ASDO到ASDI的信号控制配置芯片，配置数据由DA TA管脚读出，配置到FPGA中。

从而完成整个配置过程。

AS下载方式如图：图中串行时钟输入(DCLK)；AS控制信号输入（ASDI）；片选信号（nCS）;串行数据输出（DA TA）；JA TG是IEEE 1149.1边界扫描测试的标准接口。

fpga开发板DE2实验讲义

2.1 DE2 板上资源及硬件布局 ........................................................................................4 2.2 DE2 原理 ....................................................................................................................5 2.3 DE2 平台的开发环境 ................................................................................................7 2.4 DE2 开发板测试说明 ...............................................................................................7 三 FPGA 设计流程 .............................................................................................................10 3.1 QuartusⅡ设计流程概述 ..........................................................................................10 3.2 用 QuartusⅡ完成 FPGA 设计的实例 ....................................................................12 四嵌入式系统设计...............................................................................................................17 4.1 NiosII 简介 ...............................................................................................................17 4.2 NiosII 系统的基本开发流程....................................................................................18 五实验内容...........................................................................................................................20 实验一多路数据选择器...........................................................................................20 实验二七段数码管显示译码器.................................................................................21 实验三嵌入式 LED 实验 ..........................................................................................22 六附录表 DE2 平台的引脚分配表 ....................................................................................27

FPGA可编程逻辑器件芯片XC2VP30-2FF896C中文规格书

Chapter 5:Tile FeaturesDescriptionThe GTX_DUAL tile offers different levels of power control. Each channel in each directioncan be powered down separately using TXPOWERDOWN and RXPOWERDOWN.Additionally, the part of the reference clock circuit between the differential clock input pairpin and dedicated clock routing circuit can be powered down. The PLLPOWERDOWNport directly affects the shared PMA PLL and therefore both channels of the GTX_DUALtile.Generic GTX Power-Down CapabilitiesThe GTX_DUAL tile provides several power-down features that can be used in a widevariety of applications. Table5-12 summarizes these capabilities.Table 5-12:Basic Power-Down Functions SummaryFunction Controlled By AffectsREFCLK Power Down REFCLKPWRDNB The GTX_DUAL tile (TX and RX forboth transceivers) when using anexternal oscillator to drive thededicated clock routing, and alldownstream GTX_DUAL tiles sharingthat REFCLK.PLL Power Down PLLPOWERDOWN TX and RX for both transceivers in aGTX_DUAL tile. Powers down theshared PMA PLL as well as the RX andTX PMA circuits.TX Power Down TXPOWERDOWN[1:0]TX in a single transceiver.RX Power Down RXPOWERDOWN[1:0]RX in a single transceiver.REFCLK Power DownTo activate the REFCLK power-down mode, the active-Low REFCLKPWRDNB signal isasserted. When REFCLKPWRDNB is asserted, toggling of all circuitry between thedifferential clock pair input pins and the dedicated clock routing circuitry is suppressed.As long as power is applied to a GTX_DUAL tile, all other circuitry including thededicated clock routing and shared PMA PLL continue to toggle even whenREFCLKPWRDNB is asserted. This is a different implementation from the GTP_DUAL tilewhere when REFCLKPWRDNB is asserted, the dedicated clocking routing circuity isdisabled and all circuitry clocked by the REFCLK input is suppressed, including the sharedPMA PLL and all clocks derived from it. If the GTX_DUAL tiles share a common reference,REFCLK is suppressed to tiles that are downstream in the clock routing chain. Figure5-3,page97 illustrates how the dedicated clock routing blocks forward REFCLKs betweenGTX_DUAL tiles.Deactivation of the REFCLK power-down mode is indicated by the PLLLKDET signal,which is asserted on the tiles sourcing the affected reference clocks.PLL Power DownTo activate the PLL power-down mode, the active-High PLLPOWERDOWN signal isasserted. When PLLPOWERDOWN is asserted, the shared PMA PLL and both the PMATX and PMA RX circuits are powered down. As a result, all clocks derived from the PMAPLL are stopped. This is a different implementation than for the GTP_DUAL tile wherewhen PLLPOWERDOWN is asserted, only the shared PMA PLL and all clocks derived from it are stopped.Recovery from this power state is indicated by the assertion of the PLLLKDET signal on the tile whose REFCLKPWRDNB signal is asserted .TX and RX Power DownWhen the TX and RX power-down signals are used in non PCI Express implementations, TXPOWERDOWN and RXPOWERDOWN can be used independently. However, when these interfaces are used in non PCI Express applications, only two power states are supported, as shown in Table 5-13. When using this power-down mechanism, the following must be True:•TXPOWERDOWN[1] and TXPOWERDOWN[0] are connected together.•RXPOWERDOWN[1] and RXPOWERDOWN[0] are connected together.•TXDETECTRX must be strapped Low.•TXELECIDLE must be strapped to TXPOWERDOWN[1] and TXPOWERDOWN[0].Power Control Features for PCI Express OperationThe GTX_DUAL tile implements all of the functions needed for power control states compatible with those defined in the PCI Express and PIPE specifications. Whenimplementing PCI Express compatible power control, the following conditions must be met:•The TXPOWERDOWN and RXPOWERDOWN signals on each GTX transceiver must be connected together to ensure that they are in the same state at all times.•The REFCLKPWRDNB and PLLPOWERDOWN signals must be held in inactive states.Table 5-13:TX and RX Power States for Non PCI Express OperationTXPOWERDOWN[1:0] or RXPOWERDOWN[1:0]Description00P0 mode. Transceiver TX or RX is active sending or receiving data.11P2 mode. Transceiver TX or RX is idle.Table 5-14:TX and RX Power States for PCI Express OperationTXPOWERDOWN[1:0]and RXPOWERDOWN[1:0]TXDETECTRXTXELECIDLEDescription00 (P0 state)0The PHY is transmitting data. The MAC provides data bytes to be sent every clock cycle.01The PHY is not transmitting and is in the electrical idle state.10The PHY goes into loopback mode.11Not permitted.Chapter 5:Tile FeaturesFPGA TX InterfaceTXCHARDISPVAL0[3:0] TXCHARDISPVAL1[3:0]In TXUSRCLK2TXCHARDISPVAL and TXCHARDISPMODE allow controlof the 8B/10B outgoing data disparity when 8B/10Bencoding is enabled.When 8B/10B encoding is disabled, TXCHARDISPVAL isused to extend the data bus for 10- and 20-bit TX interfaces.See “FPGA TX Interface,” page 120.TXCHARDISPVAL[3] corresponds to TXDATA[31:24]TXCHARDISPVAL[2] corresponds to TXDATA[23:16]TXCHARDISPVAL[1] corresponds to TXDATA[15:8]TXCHARDISPVAL[0] corresponds to TXDATA[7:0]Table6-5, page133 shows how to use TXCHARDISPVAL tocontrol the disparity of outgoing data when 8B/10Bencoding is enabled.TXDATA0[31:0] TXDATA1[31:0]In TXUSRCLK2The bus for transmitting data. The width of this port dependson TXDATAWIDTH:•TXDATAWIDTH = 0: TXDATA[7:0] = 8 bits wide•TXDATAWIDTH = 1: TXDATA[15:0] = 16 bits wide•TXDATAWIDTH = 2: TXDATA[31:0] = 32 bits wideWhen a 10-bit, 20-bit, or 40-bit bus is required, theTXCHARDISPVAL and TXCHARDISPMODE ports from the8B/10B encoder are concatenated with the TXDATA port. SeeFigure6-3, page123.TXDATAWIDTH0[1:0] TXDATAWIDTH1[1:0]In TXUSRCLK2Selects the width of the TXDATA port.•0: TXDATA is 8 bits or 10 bits wide•1: TXDATA is 16 bits or 20 bits wide•2: TXDATA is 32 bits or 40 bits wide•3: ReservedTXENC8B10BUSE0 TXENC8B10BUSE1In TXUSRCLK2TXENC8B10BUSE is set High to enable the 8B/10B encoder.INTDATAWIDTH must also be High.0: 8B/10B encoder bypassed. This option reduces latency.1: 8B/10B encoder enabled. INTDATAWIDTH must beHigh.TXOUTCLK0 TXOUTCLK1Out N/AThis port provides a parallel clock generated by the GTXtransceiver. This clock can be used to drive TXUSRCLK forone or more GTX transceivers. The rate of the clock dependson INTDATAWIDTH:•INTDATAWIDTH is Low: F TXOUTCLK = Line Rate/16•INTDATAWIDTH is High: F TXOUTCLK = Line Rate/20Note:•When INTDATAWIDTH is High, the duty cycle is 60/40instead of 50/50.•When oversampling is enabled, the line rate in thecalculation of F TXOUTCLK is equal to the oversampled linerate, not the PMA line rate.Table 6-1:FPGA TX Interface Ports (Cont’d)Port Direction Clock Domain Description。

A-V 双通道音频视频转换器说明书

Maximum Distance*2500 feet Bandwidth 20 Hz to 20 kHz Impedance600 ohms, balanced Isolation 500 VNominal Level 1.0 volts Insertion Loss1 dBCommon Mode Rejection Greater than 40 dBUnshielded Twisted Pair Maximum capacitance: 20 pf/foot Cabling Specifications Impedance: 100 ohms @ 1 MHz(24 gauge or lower solidAttenuation: 6.6 dB/1000 ft. @ 1 MHzcopper)Cat 3, Cat 5, Cat 5e, Cat 6, Cat 7 compatible Connectors Two (2) female RCA to one (1) RJ45RJ45 Pinout Channel 1 (R): 1 & 2, pair 2Channel 2 (L): 3 & 6, pair 3TemperatureOperating: 32 to 131 F (0 to 55 C)Storage: -4 to 185 F (-20 to 85 C)Humidity: up to 95%Enclosure Black plastic Dimensions 4.3” x 2.5” x 1”Weight0.2 lbs (3.2 oz.)Ordering Information AVO-A2: single A VO-A2 balun in bulk packagingAVO-A2-PAC : two A V0-A2 baluns in retail-ready packagingWarranty2 years*Distances and picture quality may be affected by cable grade, cable quality, source anddestination equipment, RF and electrical interference, and cable patches. Intelix specifications are based on straight-through cabling with standard-grade Cat 5.Intelix2222 Pleasant View Road Middleton, WI 53562Toll-free: 866-4-MA TMIX Phone: 608-831-0880Fax: The Intelix A VO-A2 balun passively transmits twomono or one stereo analog audio signal via Cat 5unshielded twisted pair (UTP) cable, such as Cat ed in pairs, the AVO-A2 transmits analog audio in either direction up to 2500 feet, providing a low-cost,versatile cabling solution which uses a building’s existing structured cabling systemThe AVO-A2 is ideal for corporate AV , houses of worship, schools, auditoriums, and virtually any other situation involving structured audio distributionTo install an AVO-A2 balun, perform the following steps:1.Turn off power and disconnect the audio equipment by following the manufacturer’s instructions.2.Make certain that outlets and cross connects to which you will connect the A VO-A2are configured properly and labeled appropriately to identify the circuit.3.Verify the desired twisted pairs are not being used for other LAN or telephony equipment.4.Connect the RCA inputs from the source equipment to one of the two baluns. Two A VO-A2’s are needed—one at each end of the run—and are interchangeable.5.Connect a 4-pair Cat 5 cable from the RJ45 8-position modular jack of the A VO-A2to a structured cable, such as Cat 5.6.Connect the second balun’s RCA inputs to the destination equipment.7.Connect the 4-pair Cat 5 cable from the RJ45 8-position modular jack of another A VO-A2 to the structured cable attached to the first balun.8.Power on the source and destination equipment and test for correct operation.Caution:Do not attempt to open the balun housing. There are no user-serviceable parts inside the A VO-A2. Opening the unit will void your warranty.Caution:Do not connect the A VO-A2 to a telecommunication outlet wired to unrelated equipment. Making such a connection may damage the equipment and/or balun. Please ensure all wiring is “straight-through.”Caution:Do not mount the balun over equipment ventilation openings. Covering the openings may cause the equipment to overheat.If your equipment malfunctions with A VO-A2 baluns in place, follow the troubleshooting procedures below:1.Perform diagnostics on your audio equipment by following the manufacturer’sinstructions.2.Check all the connections and the structured cabling system. Verify the RJ45 crimppattern conforms to either EIA/TIA 568A or 568B standards.3.Check the pin configuration on the structured cable.4.The maximum operational distances over which the A VO-A2 can be transmitted isdependant on the equipment used and cable. Ensure that the maximum recommended operational distances have not been exceeded.5.Check that only twisted pair patch cords are being used.6.Replace the A VO-A2 balun with another A VO-A2 that is known to be working.7.If you still cannot diagnose the problem, contact Intelix for support.How do I expose the individual pairs in Cat 5 cabling?There is no single method when exposing the fourindividual pairs in twisted pair cabling, such as Cat 5and Cat 6; however, it does help to have a cablestripping tool designed to strip the cable jacket/insulation.Begin by stripping back the cable’s outer jacket/insulation about an inch (or more depending onwhether multiple baluns will be connected to the pairsof a single cable) so that the internal wires are exposed.Be careful not to cut the internal wires when strippingthe insulation/jacket. Eight twisted wires and a stringshould now be visible; the string is unnecessary andmay be removed. These eight wires, which whencombined form four pairs, connect directly to thebaluns. Typical protocol pairs similar colors; theimportant thing is to verify the same color-coded pairsare used on each end.How do I crimp an unshielded RJ45 connector onto Cat 5?Crimping an RJ45 connector onto Cat 5 is a fairly straight forward task, assuming you have the proper tools. Keep in mind that baluns require either the EIA/TIA 568A or 568B crimp pattern, which are the industry standards for networking.1.First, strip a portion of the insulation about 3/4" to expose the four twisted pairs.2.Next, untwist the wires and fan them out so that they match either EIA/TIA 568A or568B pattern.3.Evenly trim the wires to about 1/2". Most RJ45 crimp tools feature a built-in wiretrimmer.4.Insert the trimmed wires into the RJ45 connector so that each wire is in its individualslot. V erify each wire is completely inserted.5.Finally, insert the RJ45 connector into the crimp tool and squeeze firmly.6.Repeat the above steps on the other end of the Cat 5 cable and verify pinout is iden-tical on each end.。

GW2A GW2AR系列FPGA产品原理图手册说明书

GW2A/GW2AR series of FPGA ProductsSchematic ManualIntroductionUsers should follow a series of rules during circuit board design when using the GW2A/GW2AR series of FPGA products. This manual describesthe characteristics and special features of GW2A/GW2AR series FPGAproducts and provides a comprehensive checklist to guide designprocesses. The main contents of this guide are as follows:●Power Supply●JTAG download●MSPI download●Clock pin●Difference pin●READY, RECONFIG_N, DONE●MODE●JTAGSEL_N●FASTRD_N●EXTR●Pin Multiplexing●Reference for the external crystal oscillator circuit●GW2AR Bank voltage●Supported configuration modes●Pin DistributionPower Supply1. OverviewVoltage types of the GW2A/GW2AR series of FPGA products include core voltage (V CC), PLL voltage (V CCPLL), auxiliary voltage (V CCX) and Bankvoltage (V CCIO).V CCX is an auxiliary power supply that is used to connect the internal part of the chip, with a 2.5V or 3.3V power supply. If no V CCX exists, I/O,OSC, and BSRAM circuits will be impacted and the chip will not befunctional.2. Power IndexUsers should ensure GOWINSEMI products are always used withinrecommended operating conditions and range. Data beyond the working conditions and range are for reference only. GOWINSEMI does notguarantee that all devices will operate as expected beyond the standard operating conditions and range.Table 1 lists the recommended working range for each power voltage.3. Total PowerFor specific density, packages, and resource utilization, GPA tools can be used to evaluate and analyze the power consumption.4. Power-on timeReference range of power-on time: 0.2 ms ~ 2 ms.Note!● If the power-on time is more than 2ms, you need to ensure that the power-on in sequence is V CC , and then V CCX /V CCIO ;●If the power-on time is less than 0.2ms, it is recommended to increase the capacitance to prolong the power-on time.5. Power FilterEach FPGA power input pin is connected to the ground with a 0.1uF ceramic capacitor.The input end of the V CC core voltage should primarily conduct the noise processing. Specific reference is as shown in Figure 1:Figure 1 Noise Processing of the Input End of the V CC Core VoltageGW2A/GW2AR series of FPGA products isolate and filter the V CCPLL . Specific reference is as shown in Figure 2:Figure 2 Isolate and Filter the V CCPLLFB is a magnetic bead, reference model mh2029-221Y , ceramic capacitance 4.7uF, 100nF and 10nF . It offers an accuracy of more than ±10%.JTAG Download1. OverviewJTAG download is used for downloading the bitstream data into the SRAM, on-chip flash or off-chip flash of the FPGA. 2. Signal Definition3. JTAG Circuit ReferenceFigure 3 JTAG Circuit ReferenceNote!● The resistance accuracy is not less than 5%;●The power supply of the 6th pin in the JTAG socket can be adjusted to VCC1P2, VCC1P5, VCC1P8 and VCC2P5 as required.MSPI Download1. OverviewAs a master device, the MSPI configuration mode reads theconfiguration data automatically from the off-chip flash and sends it to theFPGA SRAM.2. Signal Definition3. MSPI Circuit ReferenceFigure 4 MSPI Circuit ReferenceNote!The serial flash chip model is for reference only. Alternatively, serial flash storage with thesame index can be used. The resistance accuracy is not less than 5%.Clock Pin1. OverviewThe clock pins include GCLK global clock pins and PLL clock pins.GCLK: The GCLK pins in the GW2A/GW2AR series of FPGA products distribute in four quadrants. Each quadrant provides eight GCLK networks.The optional clock resources of the GCLK can be pins or CRU. Selectingthe clock from the dedicated I/Os can result in better timing.PLL: Frequency (multiply and division), phase, and duty cycle can be adjusted by configuring the parameters.2. Signal Definition3. Clock Input SelectionIf the external clock inputs as a PLL clock, the user is advised to input from the PLL dedicated pin. And the PLL_T end is selected if the externalclock inputs from the single-end.GCLK is the global clock and is directly connected to all resources in the device. The GCLK_T end is advised if the GCLK inputs from thesingle-end.Difference Pin1. OverviewDifferential transmission is a form of signal transmission technology that operates according to differences between the signal line and theground line. The differential transmit signals on these two lines, theamplitude of the two signals are equal and have the same phase butdemonstrate opposite polarity.2. LVDSLVDS is a low-voltage differential signal that offers low powerconsumption, low bit error rate, low crosstalk, and low radiation. Itfacilitates the transmission of data using a low-voltage swing high-speeddifferential. Different packages employ different signals. Please refer to theTrue LVDS section of the Package Pinout Manual for further details.Note！●All BANKs in the GW2A/GW2AR series of FPGA products support True LVDS output;●BANK0/1 in the GW2A/GW2AR series of FPGA products support 100 ohm differentialinput resistance;●If the BANK is used as the differential input, 100-ohm terminal resistance is needed；●The different line impedance of PCB is controlled at about 100 ohms. READY, RECONFIG_N, DONE1. OverviewRECONFIG_N is a reset function within the FPGA programming configuration. FPGA can't configure if RECONFIG_N is low.As a configuration pin, a low level signal with pulse width no less than 25ns is required to start GowinCONFIG to reload bitstream data accordingto the MODE setting value. You can control the pin via the write logic andtrigger the device to reconfigure.READY, the FPGA can configure only when the READY signal is high. The device should be restored by using the power on or triggering RECONFIG_N when the READY signal is low.As an output configuration pin, FPGA can be indicated for the current configuration state. If the device meets the configuration condition, READY signal is high. If the device fails to configure, the READY signal changes to low. As an input configuration pin, you can reduce the READY signal via its own logic or manually operate outside the device to delay configuration.DONE, the DONE signal indicates that the FPGA is configured successfully. The signal is high after successful configuration.As an output configuration pin, FPGA can be indicated whether the current configuration is successful. If configured successfully, DONE is high, and the device enters into a working state. If the device failed to configure, the DONE signal remains low. For the input type, the user can reduce the READY signal via its own internal logic or manually operate outside the device to delay progression to user mode.When the RECONFIG_N or READY signals is low. The DONE signal is low. DONE has no influence when SRAM is configuried through the JTAG circuit.2. Signal Definition3. Reference CircuitFigure 5 Reference CircuitNote!●The upper pull power supply is the bank voltage value of the corresponding pin;●The resistance accuracy is not less than ± 5%.MODE1. OverviewMODE spans the MODE0, MODE1, MODE2, and GowinCONFIG configuration MODE modes. When the FPGA powers on or a low pulsetriggers the RECONFIG_N mode, the device enters the correspondingGowinCONFIG state according to the MODE value. As the number of pinsfor each package is different, some MODE pins are not all packaged, andthe unpacked MODE pins are grounded inside. Please refer to thecorresponding PINOUT manual for further details.2. Signal Definition3. Mode SelectionJTAGSEL_N1. OverviewSelect the signal in JTAG mode. If the JTAG pin is set as GPIO in Gowin software, the JTAG pin is changed to GPIO pin after being poweredon and successfully configured. The JTAG pin can be recovered byreducing the JTAGSEL_N. The JTAG configuration functions are alwaysavailable if no JTAG pin multiplexing is set.2. Signal DefinitionNote!As GPIO, the JTAGSEL_N pin and the four pins (TCK, TMS, TDI, and TDO) configuredwith JTAG are mutual exclusive;●If JTAGSEL_N is set to GPIO, the JTAG pin can only be used as a configuration pin;●If JTAG is set to GPIO, the JTAGSEL_N pin can only be used as a configuration pin.FASTRD_N1. OverviewIn MSPI configuration mode, signals are selected via reading the SPI flash speed rate. FASTRD_N is normal read mode if high level; FASTRD_Nis high speed read mode if low level. Each manufacturer's flash high speedread instruction is different. Please refer to the corresponding flash datamanual.2. Signal DefinitionNote!In the high-speed flash access mode: the clock frequency is greater than 30MHz. EXTREXTR is a dedicated pin that needs to be connected to the ground with 10K resistance. The resistance precision is 1%.Specific reference is as shown in:Figure 6 EXTR Pin ConfigurationThe resistance accuracy is ±1%.Pin Multiplexing1. OverviewConfigure pin multiplexing refers to configuring during power-on, which is used as a normal I/O after downloading the bitstream file.Configure pin multiplex via the Gowin software:a). Open the corresponding project in Gowin software;b). Select “Project > Configuration > Dual Purpose Pin” from the menuoptions, as shown in Figure 7;c). Check the corresponding option to set the pin multiplex.Figure 8 Pin Multiplex2. Pin Multiplexing● SSPI: As a GPIO, SSPI can be used as input or output type;●MSPI: As a GPIO, MSPI can be used as input or output type; ● RECONFIG_N GPIO can only be used as an output type. Forsmooth configuration, set the initial value of RECONFIG_N as high when multiplexing it.●READY: As a GPIO, READY can be used as an input or output. Asan input GPIO for READY, the initial value of READY should be 1before configuring. Otherwise, the FPGA will fail to configure;●DONE: As a GPIO, DONE can be used as an input or output type.If DONE is used as an input GPIO, the initial value of DONE shouldbe 1 before configuring. Otherwise, the FPGA will fail to enter theuser mode after configuring;●JTAG: As a GPIO, JTAG can be used as an input or output type;●JTAGSEL_N: As a GPIO, JTAGSEL_N can be used as an input oroutput type.●DONE: As a GPIO, JTAG can be used as an input or output type. Inorder to smoothly configure, the user multiplexes the MODE pin,the correct configuration mode value is needed to provided duringconfiguration (power-on or low-level pulse triggers RECONFIG_N).Less than three pins can be multiplexed in the MODE. Unpackagedproducts are grounded internally. Please refer to PINOUT manualof the corresponding device for details. For the MODE valuecorresponding to different configuration modes, please refer to thecorresponding device configuration and programming manual.Note!If the Number of I/O ports are sufficient, use non-multiplexed pins first. FPGA External Crystal Oscillator Circuit ReferenceFigure 9 FPGA External Crystal Oscillator Circuitthan ±5% resistance accuracy, and more than ±10% capacitance accuracy.GW2AR Bank VoltageDue to the SIP SDRAM is in the GW2AR, the BANK voltage connected with it will have a fixed value, which is as follows:1. GW2AR-18 QN88 Package2. GW2AR-18 LQ144 Package3. GW2AR-18 LQ176 PackageSupported Configuration Modes1. GW2A-182. GW2A-553. GW2AR-18Pin DistributionBefore designing circuits, users should take the overall FPGA pin distribution needs into consideration and make informed decisions relatedto the application of the device architecture features, including I/O LOGIC,global clock resources, PLL resources, etc.All banks of the GW2A/GW2AR bank support true LVDS output. When using true LVDS output, V CCO shall be configured to 2.5 V or 3.3 V, andrefer to GW2A/GW2AR series FPGA Product Pinout to ensure that thecorresponding pins support true LVDS output.To support SSTL, HSTL, etc., each bank also provides oneindependent voltage source (V REF) as the reference voltage. Users canchoose V REF from the internal reference voltage of the bank (0.5 x VCCO)or external reference voltage V REF using any I/O from the bank.Support and FeedbackGowin Semiconductor provides customers with comprehensivetechnical support. If you have any questions, comments, or suggestions,please feel free to contact us directly using the information provided below.Website: E-mail: *********************Tel: 00 86 0755 ********Copyright©2018 Guangdong Gowin Semiconductor Corporation. All Rights Reserved.No part of this document may be reproduced or transmitted in any form or by any denotes, electronic, mechanical, photocopying, recording or otherwise, without the prior written consent of GOWINSEMI.DisclaimerGOWINSEMI®, LittleBee®, Arora™, and the GOWINSEMI logos are trademarks of GOWINSEMI and are registered in China, the U.S. Patent and Trademark Office and other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders, as described at . GOWINSEMI assumes no liability and provides no warranty (either expressed or implied) and is not responsible for any damage incurred to your hardware, software, data, or property resulting from usage of the materials or intellectual property except as outlined in the GOWINSEMI Terms and Conditions of Sale. All information in this document should be treated as preliminary. GOWINSEMI may make changes to this document at any time without prior notice. Anyone relying on this documentation should contact GOWINSEMI for the current documentation and errata.Click to View Pricing, Inventory, Delivery & Lifecycle Information:G OWIN Semiconductor:GW2A-LV18LQ144C8/I7GW2A-LV18PG256C7/I6GW2A-LV18PG256C8/I7GW2A-LV18PG484C7/I6GW2A-LV18PG484C8/I7GW2A-LV18EQ144C8/I7GW2A-LV55PG484C8/I7GW2A-LV55PG484C9/I8GW2A-LV55UG324C8/I7GW2A-LV18PG484C9/I8GW2A-LV18QN88A6GW2A-LV18QN88C7/I6GW2A-LV18QN88C8/I7 GW2A-LV18UG324C9/I8GW2A-LV55PG484A6GW2A-LV18MG196C8/I7GW2A-LV18PG256C9/I8GW2A-LV18PG256CC8/I7GW2A-LV18PG256CC9/I8GW2A-LV18PG256SC7/I6GW2A-LV18PG256SC8/I7Click to View Pricing, Inventory, Delivery & Lifecycle Information:G OWIN Semiconductor:GW2AR-LV18EQ144PFC8/I7GW2AR-LV18PG256SC8/I7GW2AR-LV18QN88PFC8/I7。

Xilinx FPGA JTAG-SMT2-NC程序模块说明书

1300 Henley Court Pullman, WA 99163509.334.6306 JTAG-SMT2-NC ™ Programming Module for Xilinx ® FPGAsRevised February 25, 2021This manual applies to the JTAG-SMT2-NC rev. AOverviewThe Joint Test Action Group (JTAG)-SMT2-NC is a compact, complete, and fully self-contained surface-mountprogramming module for Xilinx field-programmable gate arrays (FPGAs). The module can be accessed directly from all Xilinx Tools, including iMPACT, Chi pScope™, eFuse, Vivado, and EDK. Users can load the module directly onto a target board and reflow it like any other component.The JTAG-SMT2-NC uses a 3.3V main power supply and a separate Vref supply to drive the JTAG signals. All JTAG signals use high speed 24mA three-state buffers that allow signal voltages from 1.8V to 5V and bus speeds up to 30MBit/sec. The JTAG bus can be shared with other devices as the SMT2-NC signals are held at high impedance, except when actively driven during programming. The SMT2-NC module is CE certified and fully compliant with EU RoHS and REACH directives. The module routes the USB D+ (DP) and D- (DM) signals out to pads, providing the system designer with the ability to choose the type of USB connector and its location on the system board.Users can connect JTAG signals directly to the corresponding FPGA signals, as shown in Fig. 1. For best results, mount the module over a ground plane on the host PCB. Although users may run signal traces on top of the host PCB beneath the SMT2-NC, Digilent recommends keeping the area immediately beneath the SMT2-NC clear. Note: Keep the impedance between the SMT2-NC and FPGA below 100 Ohms to operate the JTAG at maximum speed.123489567GND TCK TDI TMS GPIO1GPIO2GPIO0TDOVREF GNDVdd (3.3V)23D MD PThe JTAG-SMT2-NC• Small, complete, all-in-one JTAG programming/debuggingsolution for Xilinx FPGAs• Compatible with all Xilinx Tools• Compatible with IEEE 1149.7-2009 Class T0 – Class T4(includes 2-Wire JTAG)• GPIO pin allows debugging software to reset the processorcore of Xilinx’s Zynq ® platform • Single 3.3V supply• Separate Vref drives JTAG signal voltages; Vref can be anyvoltage between 1.8V and 5V.• High-Speed USB2 port that can drive JTAG/SPI bus at up to30Mbit/sec (frequency settable by user)• SPI programming solution (modes 0 and 2 up to 30Mbit/sec,modes 1 and 3 up to 2Mbit/sec)• Small form-factor surface-mount module can be directlyloaded on target boards• USB D+ and D- signals routed to pads, allowing USBconnector to be placed anywhere on the host PCBFeatures include:The SMT2-NC improves upon the SMT1 with the addition of three general purpose I/O pins (GPIO0 – GPIO2) and support for interfacing IEEE 1149.7-2009 JTAG targets in both 2 and 4-wire modes.In addition to supporting JTAG, the JTAG-SMT2-NC also features eight highly configurable Serial Peripheral Interface (SPI) ports that allow communication with virtually any SPI peripheral (see Fig. 2). All eight SPI ports share the same SCK, MOSI, and MISO pins, so users may enable only one port at any given time. Table 1 summarizes the features supported by each port. The SMT2-NC supports SPI modes 0, 1, 2, and 3.PortChip Select SignalPortNumberSPIModeShiftLSBFirstShiftMSB FirstSelectableSCKFrequencyMax SCKFrequencyMin SCKFrequencyInter-byteDelayTMS/CS0 00 Yes Yes Yes 30 MHz 8 KHz 0 – 1000 µS2 Yes Yes Yes 30 MHz 8 KHz 0 – 1000 µS 10 Yes Yes Yes 2.066 MHz 485 KHz 0 – 1000 µS1 Yes Yes Yes 2.066 MHz 485 KHz 0 – 1000 µS2 Yes Yes Yes 2.066 MHz 485 KHz 0 – 1000 µS3 Yes Yes Yes 2.066 MHz 485 KHz 0 – 1000 µSGPIO0/CS1 20 Yes Yes Yes 30 MHz 8 KHz 0 – 1000 µS2 Yes Yes Yes 30 MHz 8 KHz 0 – 1000 µS 30 Yes Yes Yes 2.066 MHz 485 KHz 0 – 1000 µS1 Yes Yes Yes 2.066 MHz 485 KHz 0 – 1000 µS2 Yes Yes Yes 2.066 MHz 485 KHz 0 – 1000 µS3 Yes Yes Yes 2.066 MHz 485 KHz 0 – 1000 µSGPIO1/CS2 40 Yes Yes Yes 30 MHz 8 KHz 0 – 1000 µS2 Yes Yes Yes 30 MHz 8 KHz 0 – 1000 µS 50 Yes Yes Yes 2.066 MHz 485 KHz 0 – 1000 µS1 Yes Yes Yes 2.066 MHz 485 KHz 0 – 1000 µS2 Yes Yes Yes 2.066 MHz 485 KHz 0 – 1000 µS3 Yes Yes Yes 2.066 MHz 485 KHz 0 – 1000 µSGPIO2/CS360 Yes Yes Yes 30 MHz 8 KHz 0 – 1000 µS2 Yes Yes Yes 30 MHz 8 KHz 0 – 1000 µS70 Yes Yes Yes 2.066 MHz 485 KHz 0 – 1000 µS1 Yes Yes Yes 2.066 MHz 485 KHz 0 – 1000 µS2 Yes Yes Yes 2.066 MHz 485 KHz 0 – 1000 µS3 Yes Yes Yes 2.066 MHz 485 KHz 0 – 1000 µSFigure 2. SMT2 SPI port connections.Figure 1. JTAG-SMT2 port connections.Table 1. Port features.Note: The Xilinx Tools expect GPIO2/CS3 to be connected to the SRST_B pin on a Zynq chip. As a result, SPI ports 6 and 7 may not be used for SPI communication if the Xilinx Tools are going to be used to communicate with the SMT2.1 Software SupportThe JTAG-SMT2-NC has been designed to work seamlessly with Xilinx’s ISE® (iMPACT, ChipScope, EDK, and eFuse) and Vivado tool suites. The most recent versions of ISE and Vivado include all of the drivers, libraries, and plugins necessary to communicate with the JTAG-SMT2-NC. At the time of writing, the following Xilinx software included support for the SMT2-NC: Vivado 2014.1+, Vivado 2013.1+, and ISE 14.1+.The SMT2-NC is also compatible with ISE 13.1 – 13.4; however, these versions of ISE do not include all of the libraries, drivers, and plugins necessary to communicate with the SMT2-NC. In order to use the JTAG-SMT2-NC with these versions of ISE, version 2.5.2 or higher of the Digilent Plugin for Xilinx Tools package must be downloaded from the Digilent website and the ISE13 plugin must be manually installed as described in the included documentation.In addition to working seamlessly with all Xilinx tools, Digilent’s Adept software and the Adept software development kit (SDK) support the SMT2-NC module. For added convenience, customers may freely download the SDK from Digilent’s website. This Ad ept software includes a full-featured programming environment and a set of public application programming interfaces (API) that allow user applications to directly drive the JTAG chain.With the Adept SDK, users can create custom applications that will drive JTAG ports on virtually any device. Users may utilize the APIs provided by the SDK to create applications that can drive any SPI device supporting those modes. Please see the Adept SDK reference manual for more information.2 IEEE 1149.7-2009 CompatibilityThe JTAG-SMT2-NC supports several scan formats, including the JScan0-JScan3, MScan, and OScan0 - OScan7. It is capable of communicating in 4-wire and 2-wire scan chains that consist of Class T0 – T4 JTAG Target Systems (TS) (see Figs. 3 & 4).Figure 3. 4-Wire series topology.The IEEE 1149.7-2009 specification requires any device that functions as a debug and test system (DTS) to provide a pull-up bias on the TMS and TDO pins. In order to meet this requirement, the JTAG-SMT2-NC features weak pull-ups (100K ohm) on the TMS, TDI, TDO, and TCK signals. Though not required in the specifications, the pull-ups on the TDI and TCK signals ensure that neither signal floats while another source is not driving them (see Fig. 5).VREF VREFUsers should place a current limiting resistor between the TMS pin of the SMT2-NC and the TMSC pin of the TS when using the JTAG-SMT2-NC to interface with a 1149.7 compatible TS. If a drive conflict occurs, this resistorshould prevent damage to components by limiting the amount of current flowing between the pins of each device. A 200 ohm resistor will limit the maximum current to 16.5mA when using a 3.3V reference (see Figs. 6 & 7). While this level of resistance should be sufficient for most applications, the value of the resistor may need to be adjusted to meet the requirements of the TS.In most cases, users can avoid a drive conflict by having applications that use the SMT2-NC communicate with the TS in two-wire mode. Use the applications to reconfigure the TS to use the JScan0, JScan1, JScan2, or JScan3 scan format prior to disabling the SMT2-NC ’s JTAG port.2-Wire Star Topology4-Wire Star TopologyFigure 4. 4-Wire and 2-Wire star topology.The Adept SDK provides an example application that demonstrates how to communicate with a Class T4 TAP controller using the MScan, OScan0, and OScan1 scan formats.3 GPIO PinsThe JTAG-SMT2-NC has three general purpose I/O pins that are useful for a variety of different applications (GPIO0, GPIO1, and GPIO2). Each pin features high speed three-state input and output buffers. At power up, the JTAG-SMT2-NC disables these output buffers and places the signals in a high-impedance state. Each signal remains in a high-impedance state until a host application enables DPIO port 0 and configures the applicable pin as an output. When the host application disables DPIO port 0, all GPIO pins revert to a high-impedance state. Weak pull-ups (100K ohm) ensure that the GPIO signals do not float while not being actively driven (see Fig. 8).OEGPIOxWhen customers use the JTAG-SMT2-NC to interface the scan chain of Xilinx’s Zynq platform, they should connect the GPIO2 pin of the SMT2-NC to the Zynq’s PS_SRST_B pin. This connection allows t he Xilinx Tools to reset theFigure 7. 200 Ohm resistor limiting current flow.Zynq’s processor core at various times during debugging operations. Please see the following “Application Examples” section for more information.Note: The Xilinx tools expect GPIO2 to be connected to the SRST_B pin on a Zynq chip. As a result, GPIO2 may not be used as a general purpose I/O if the Xilinx tools are going to be used to communicate with the SMT2.Note: DPIO port 0 can only be used while both JTAG and SPI are disabled.4 Application ExamplesExample 1: Interfacing a Zynq-7000 when VCCO_0 and VCCO_MIO1 use a common supplyFigure 9 demonstrates how to connect the JTAG-SMT2-NC to Xilinx’s Zynq-7000 silicon when the same voltage supplies both the VCCO_0 (Programmable Logic Bank 0 Power Supply) and the VCCO_MIO1 (Processor MIO Bank 1 Power Supply).In this case, the SMT2-NC has a 100K pull-up to VREF, which operates at the same voltage as VCCO_MIO1. This similar voltage makes it possible to eliminate the external pull-up that is normally required for the PS_SRST_B pin.Figure 9. Connecting the JTAG-SMT2-NC to Xilinx’s Zynq-7000.Example 2:Interfacing a Zynq-7000 that uses different voltages for VCCO_0 and VCCO_MIO1Figure 10 demonstrates how to connect the JTAG-SMT2-NC to Xilinx’s Zynq-7000 silicon when different voltages supply the VCCO_0 (Programmable Logic Bank 0 Power Supply) and VCCO_MIO1 (Processor MIO Bank 1 Power Supply). If the Zynq’s JTAG pins are operating at a different voltage than the PS_SRST_B, it requires an external buffer to adjust the level of the GPIO2 signal. The example in Fig. 10 demonstrates the use of an open drain buffer to allow for the possibility of adding a reset button.Figure 10. Use of an open drain buffer.Example 3:Interfacing a Zynq-7000 while retaining the Xilinx JTAG HeaderFigure 11 below demonstrates how to connect the JTAG-SMT2-NC to Xilinx’s Zynq-7000 silicon alongside Xilinx’s 14-pin JTAG header. In this example, the open drain buffers allow both the SMT2-NC and Xilinx JTAG Header to drive the PS_SRST_B pin, which may operate a different voltage than the Zynq’s JTAG pins.Figure 11. Open drain buffers allowing the SMT2-NC and JTAG Header to drive the PS_SRST_B pin.5 Supported Target DevicesThe JTAG-SMT2-NC is capable of targeting the following Xilinx devices:•Xilinx FPGAs, including UltraScale+•Xilinx SoCs, MPSoCs, and RFSoCs, including Xilinx Zynq-7000 and Zynq UltraScale+•Xilinx ACAPs, including Versal•Xilinx CoolRunner™/CoolRunner-II CPLDs•Xilinx Platform Flash ISP configuration PROMs•Select third-party SPI PROMs•Select third-party BPI PROMsThe following devices cannot be targeted by the JTAG-SMT2-NC:•Xilinx 9500/9500XL CPLDs•Xilinx 1700 and 18V00 ISP configuration PROMs•Xilinx FPGA eFUSE programmingRemote device configuration is not supported for the JTAG-SMT2-NC when used with Xilinx’s iMPACT software. Note: Please see the “Introduction to Indirect Programming –SPI or BPI Flash Memory” help topic iniMPACT for a list of supported FPGA/PROM combinations. Note: Please see the “Configuration Memory Support” section of Xilinx UG908 for a list of the FPGA/PROM combinations that Vivado supports.5.1 Programming Solutions Comparison ChartJTAG-SMT1 JTAG-SMT2 JTAG-SMT2-NCMax Speed 30 MHz 30 MHz 30 MHz VoltageRange1.8V – 5V 1.8V – 5V 1.8V – 5V Xilinx NativeSupportISE 13.2+Vivado 2012.1+ISE 14.1+Vivado 2013.1+ISE 14.1+Vivado 2013.1+ Xilinx Plug-inSupportISE 13.1+ ISE 13.1+ ISE 13.1+ DigilentAdeptSupportYES YES YESPC Interface USB USB USB Onboard USBConnectorYES YES NO Host BoardConnectorInterface8-pad SMT 11-pad SMT 13-pad SMT 4-Wire JTAG YES YES YES2-Wire JTAG NO YES YES Zynq-7000PS_SRSTSupportNO YES YESSPI Support NO YES YES6 Mechanical InformationNote: PCB dimensions have a tolerance of +/- 0.13mm.Note: All dimensions are shown in millimeters.7 General USB Signal Routing Guidelines•Maintain a differential impedance of 90 ohms between the DP and DM signals.•Keep DP and DM trace lengths within 50 mils of each other.•Minimize DP and DM signal trace length. Keeping the trace length below 3 inches is recommended.•When possible, route DP and DM on the plane closest to the ground plane.•When possible, avoid routing the DP and DM signals through vias. If vias cannot be avoided, then keep them small and place the DP and DM traces on the same layer.•When possible, avoid routing other traces near DP and DM.•When possible, minimize or avoid the use of bends in the DP and DM traces. If 90 degree bends are necessary, then use two 45 degree turns or an arc instead of a single 90 degree turn.•Do NOT route DP or DM near oscillators, crystals, switching regulators, clock generators, or inductors.7.1 Absolute Maximum RatingsSymbol Parameter Condition Min Max Unit Vdd Operating supply voltage -0.3 4.0 V Vref I/O reference/supply voltage -0.3 6 V VIO Signal Voltage -0.3 6 VI IK,I OK TMS, TCK, TDI, TDO, GPIO0,GPIO1, GPIO2DC Input/Output Diode CurrentVIO < -0.3V -50mAVIO > 6V +20I OUT DC Output Current ±50 mA T STG Storage Temperature -10 +60 ºCESD Human Body Model JESD22-A114 4000 V Charge Device Model JESD22-C101 2000 V7.2 DC Operating CharacteristicsSymbol Parameter Min Typ Max Unit Vdd Operating supply voltage 2.97 3.3 3.63 Volts Vref I/O reference/supply voltage 1.65 2.5/3.3 5.5 VoltsTDO, GPIO0, GPIO1, GPIO2 Input High Voltage (V IH) 1.62 5.5 Volts Input Low Voltage (V IL) 0 0.65 VoltsTMS, TCK, TDI, GPIO0, GPIO1, GPIO2 Output High (V OH) 0.85 x Vref 0.95 x Vref Vref Volts Output Low (V OL) 0 0.05 x Vref 0.15 x Vref VoltsT A Operating Temperature -40 85 ºC8 AC Operating CharacteristicsThe JTAG-SMT2-NC’s JTAG signals operate according to the timing diagram in Fig. 12. The SMT2-NC supports JTAG/TCK frequencies from 30 MHz to 8 KHz at integer divisions of 30 MHz from 1 to 3750. Common frequencies include 30 MHz, 15 MHz, 10 Mhz, 7.5 MHz, and 6 MHz (see Table 2). The JTAG/TCK operating frequency can be set within the Xilinx tools.Note: Please refer to Xilinx’s iMPACT documentation for more information.TDITCKTDOTMS9 Mounting to Host PCBsThe JTAG-SMT2-NC module has a moisture sensitivity level (MSL) of 6. Prior to reflow, the JTAG-SMT2-NC module must be dried by baking it at 125° C for 17 hours. Once this process has been completed, the module has a MSL of 3 and is suitable for reflow for up to 168 hours without additional drying.The factory finishes the JTAG-SMT2-NC signal pads with the ENIG process using 2u” gold over 150u” electroless nickel. This makes the SMT2-NC compatible with most mounting and reflow processes (see Fig. 13). The binding force of the solder is sufficient to hold the SMT2-NC firmly in place so mounting should require no additional adhesives.Figure 12. Timing diagram.Table 2. JTAG frequency support.Note: these parameters are specified for Vref = 3.3V.10 PackagingDigilent ships small quantities of less than 20 per order, individually packaged in antistatic bags. Digilent will pack and ship larger quantities in groups of 80 positioned in an antistatic bubble tray (see Fig. 14).Figure 13. JTAG-SMT2-NC reflow temperature over time.Figure 14. JTAG-SMT2-NC shipping arrangement.。

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４．主控模块在执行大正ＶＯＤ算法中所需要的参数信息命令和状态命令由通信接口模块从宿主机顶盒获得
二系统模块框图
Q 输入 A M
开关模块
PCR 寄存器
输出信号信号名称
[9:0] FB_ADDRA [9:0] FB_ADDRB [7:0] DO FB_CLKA FB_CLKB [15:0] FB_DIA FB_WEA FSYNCO I2C_C_O I2C_D_O ICO_EN IDO_EN [5:0] PIDT_Addr [7:0] PIDT_DATA [5:0] PIDT_RAddr PIDT_RD PIDT_WR [9:0] RT_AddrA [9:0] RT_AddrB RT_CLKA RT_CLKB
此模块是一种通用的模块传输码流符合ＤＶＢ－Ｃ标准可以方便地插入任何一款符合ＤＶＢ－Ｃ标准的机顶盒内扩充该机顶盒的功能使其具有大正ＶＯＤ的功能而又不影响它原有的所有功能
整个解码模块可以工作在２种状态大正ＶＯＤ解码状态和闲置状态
在闲置状态从ＱＡＭ解调器来的信号直接送往输出端口
在大正ＶＯＤ解码状态解码模块的信号流向控制过程如下
信息包的 PID 信息
ቤተ መጻሕፍቲ ባይዱ
PIDCTRL 的 RX_PID[12:0]
用于调试 , 若新 PID 的值为
13’h1FFF 则 Test 为 0 否则为 1
模块功能此模块为 FIFO 缓冲区包括两个 4 字节的缓冲区用于取出信息包的 PID 号将取
得的 PID 号送入 PID 表控制模块以便控制模块将其与三个选中的 PID 号相比较另外将缓冲区数据输出至主控模块根据情况以决定存储或丢弃
三 TOP 模块输入输出说明
输入信号信号名称
CLK90K CLKM [7:0] DI [15:0] FB_DOB FSYNCI I2C_C_IN I2C_D_IN [2:0] I2cAddr [1:0] Mem_Sel
[7:0] PIDT_DB [7:0] RT_DOA [7:0] RT_DOB ResetN VALIDI [7:0] sd_data_in1 [7:0] sd_data_in2 [7:0] sd_data_in3 [7:0] sd_data_in4
DATA[15:0]
FSYNCV
DEN
信号作用缓冲区数据输出其内容由 DMUX 决定帧同步信号
数据准备好信号表示缓冲区已满高有效
信号去向
RXINFOFR
CSM
FRBUFCTL 三个模块
RXINFOFR
CSM
FRBUFCTL 三个模块
RXINFOFR
CSM
FRBUFCTL 三个模块
RX_PID[12:0] Test
PID_TABLE 和 PIDCTL 模块 PID_TABLE 和 PIDCTL 模块 PID_TABLE 和 PIDCTL 模块
模块功能及原理 movereg EdgeDetect Counter m1 四个模块实现了 I2C 接口的基本时序下面分别
对这些子模块的功能加以说明有关 I2C 协议的内容请参见 I2C 协议规范 EdgeDetect 模块描述的是几个边沿检测器 I2C 协议规定通讯的开始结束以及通讯
实现该方案的核心是开发一种基于该数字模型播放的接收控制存贮的专用芯片即大正ＶＯＤ解码模块将该芯片加入机顶盒中完成节目的点播功能由于在信道上传输的节目流是经过排列组合后的段所以通用的机顶盒无法直接接收大正ＶＯＤ解码模块的基本原理就是将打散后的段重新排列使它恢复原来节目流的格式并通过适当的缓冲后以符合ＤＶＢ－Ｃ标准的形式输出
I2C 时钟输出使能 I2C 数据输出使能 PIDT 表的地址总线 PIDT 表的数据总线 PID 表模块的 B 端口读出地址 PID 表模块的 B 端口读信号 PID 表的 A 端口写信号高有效段注册表 A 端口的读写地址段注册表 B 端口的读写地址段注册表 A 端口写时钟段注册表 B 端口写时钟
过程中数据的读入写出都是以时钟线和数据线上出现的沿为标志的因此在本模块中应该监测时钟线和数据线上电平的变化
I2C 总线是一种串行总线总线上顺序传送的数据必须经过一个串并转换后得到并行数据 movereg 模块的功能就是完成串并转换
信号说明帧缓冲区 A 端口写入地址总线帧缓冲区 B 端口读出地址总线
系统的数据输出总线
帧缓冲区 A 端口时钟帧缓冲区 B 端口时钟帧缓冲区 A 端口写入数据总线帧缓冲区 A 端口写允许系统的帧同步输出
经过 3 态输出缓冲后输出到 I2C 总线的时钟线经过 3 态输出缓冲后输出到 I2C 总线的数据线
四模块说明
模块名称ＦＩＦＯ接收模块相关文件 RxModule.v
输入信号信号名称
RESETN CLKM MDI[7:0] VALIDI FSYNCI DMUX
信号作用复位信号低有效系统时钟 8 位输入数据数据有效信号帧同步信号用来选择 DATA 输出 DMUX 为高时 DATA 输出为缓冲区的低 16 位 DMUX 为低时 DATA 输出为缓冲区的高 16 位
[7:0] RT_DIA [7:0] RT_DIB RT_WEA RT_WEB VALIDO [11:0] sd_addx [1:0] sd_ba sd_cas_l sd_clk sd_data_ena [7:0] sd_data_out1 [7:0] sd_data_out2 [7:0] sd_data_out3 [7:0] sd_data_out4 sd_ras_l sd_wr_l [3:0] sdram_cs [3:0] sdram_dqm
一.系统总体说明
大正ＶＯＤ系统是上海大正公司开发的一种基于单向ＣＡＴＶ网实现视频随选点播的技术其基本思想是将一个节目流通过适当的算法拆分成若干个节目段将节目段加以合理的排列组合后进行发送利用电视信道的宽带特性就可以在接收端达到ＮＶＯＤ的效果它充分利用了现有ＣＡＴＶ网络的带宽资源用户可以访问当前正被提供的任何节目１个８ＭＨｚ的物理频道可点３个节目从节目选择到节目从头开始播放的等待时间小于４８秒用户的收看选择不受其他用户收看选择或数量的限制
段注册表 A 端口的数据输入段注册表 B 端口的数据输入段注册表 A 端口写允许段注册表 B 端口写允许系统的数据有效输出
SDRAM 地址总线 SDRAM 分区选择 SDRAM 列地址锁存 SDRAM 时钟 SDRAM 输出允许 SDRAM 数据输入总线 SDRAM 数据输入总线 SDRAM 数据输入总线 SDRAM 数据输入总线 SDRAM 行地址锁存 SDRAM 写信号 SDRAM 片选 SDRAM 数据字节选择
l 若是未被点播的大正ＶＯＤ节目的ＴＳ包将此ＴＳ包直接丢弃
l 若不是大正ＶＯＤ节目的ＴＳ包则将此ＴＳ包暂时存入输出缓冲区待输出模块空闲时将此ＴＳ包输出
３．在播放模式下主控模块根据大正ＶＯＤ的算法确定当前时刻是否需要输出ＴＳ包若到达输出时刻则通知存储器读写模块从ＳＤＲＡＭ读出相应的ＴＳ包送入输出模块输出在暂停模式无上述过程
信号来源
(FPGA 的 P49)&(!K) FPGA 的 P77 来自 QAM 解调器来自 QAM 解调器来自 QAM 解调器由 RxInfoFr 模块输出的 Rx_SelLW csm 模块输出的 RxDaMux 和 FrBufCtl 模块输出的 RxDaMux 相或得到
输出信号信号名称
l 对于大正ＶＯＤ信息包提取其中的ＰＩＤ信息如果为选中的ＰＩＤ则根据信息包中的信息初始化并配置段注册表控制是否存储该段所有有用信息取完后丢弃该信息包除了带初始化参数标志的大正VOD信息包
l 若是被点播的大正ＶＯＤ节目的ＴＳ包则根据算法决定是否存储并回放确定存储的ＴＳ包由存储器读写模块写入ＳＤＲＡＭ
１．从ＱＡＭ解调器来的信号ＴＳ包送入输入模块ＴＳ包的帧同步和字节同步信号均由ＱＡＭ解调器提供输入模块将数据送入输入缓冲区同时将ＴＳ包中的ＰＩＤ信息与ＰＩＤ表中的ＰＩＤ比较，看是否为被选中的大正节目
２．主控模块根据大正ＶＯＤ的算法结合１ＴＳ包中的ＰＩＤ信息以及大正ＶＯＤ信息包中的信息２由宿主机顶盒送来的信息命令和状态命令控制该ＴＳ包的信号流向
RTCTL 模块
输出信号信号名称
Ｉ２Ｃ＿Ｄ＿Ｏ
ＩＤＯ＿ＥＮＩ２Ｃ＿Ｃ＿Ｏ
ＩＣＯ＿ＥＮ K
Pause
信号说明
经过 3 态输出缓冲后输出到 I2C 总线的数据线
I2C 数据输出使能经过 3 态输出缓冲后输出到 I2C 总线的时钟线 I2C 时钟输出使能播放信号为 1 时系统处于 IDLE 状态为 0 为工作状态暂停信号在 FPGA 工作状态令 Pause 有效可暂停输出节目流
工作原理模块内有两个 4 字节缓冲区 DBUFF0 和 DBUFF1 交替用做输出数据 DBUFF
和 PID TEMPD 当帧同步信号有效时随后写入缓冲区的第 2 3 个字节中包含 PID 信息 RX_PID 将信息包的 PID 信息输出至 PIDCtl 模块当一个缓冲区写满后开始写另一个缓冲区已满的缓冲区用作输出数据这样可以保证输出的数据和 PID 信息都是有效的
信号说明 90K Hz 时钟信号系统时钟来自 QAM 解调器的 8 位输入数据帧缓冲区数据输出帧同步信号 I2C 总线时钟输入 I2C 总线数据输入用于设置 I2C 端口设备地址设备地址为 1011 I2Caddr 表示当前系统中 SDRAM 即内存的实际大小 00 32MB
01 64MB 10 128MB 11 256MB 读 PID 表得到的数据段注册表 A 端口输出的数据段注册表 B 端口输出的数据复位信号低有效数据有效信号 SDRAM 数据输出总线 SDRAM 数据输出总线 SDRAM 数据输出总线 SDRAM 数据输出总线