10_BQConf_Lever
HMC1094广域输入带宽1至23 GHz的对数检波器数据手册说明书
50 dB, Logarithmic Detector,1 GHz to 23 GHzData SheetHMC1094FEATURESWide input bandwidth: 1 to 23 GHzWide dynamic range: 50 dB up to 23 GHz Single positive supply: 3.3 VExcellent stability over temperature Fast rise/fall time: 12 ns/65 ns16-lead 3 mm × 3 mm SMT package: 9 mm²APPLICATIONSPoint-to-point microwave radio VSATWideband power monitoringReceiver signal strength indication (RSSI) Test and measurementFUNCTIONAL BLOCK DIAGRAMFigure 1.GENERAL DESCRIPTIONThe HMC1094 logarithmic detector converts RF signals at its input to a proportional dc voltage at its output. The HMC1094 employs successive compression topology that delivers high dynamic range over a wide input frequency range.As the input power is increased, successive amplifiers move into saturation one by one, creating an approximation of the logarithm function. The output of a series of detectors is summed, con-verted into the voltage domain, and buffered to drive the LOGOUT output.The HMC1094 provides a nominal logarithmic slope of 18 mV/dB and an intercept of −113 dBm at 23 GHz. Ideal as a log detector for high volume microwave radio and VSAT applications, the HMC1094 is housed in a compact 3 mm ×3 mm RoHS compliant SMT plastic package.GND RFIN GND RSV 6543V C CV C CV C CV C C12810-001Rev. ADocument Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners.O ne Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013–2014 Analog Devices, Inc. All rights reserved. Technical Support HMC1094 Data Sheet TABLE OF CONTENTSFeatures (1)Applications (1)Functional Block Diagram (1)General Description (1)Revision History (2)Specifications (3)Absolute Maximum Ratings (5)ESD Caution (5)Pin Configuration and Function Descriptions ............................. 6Interface Schematics.. (7)Typical Performance Characteristics (8)Application and Evaluation Printed Circuit Board (PCB) Schematic (11)Evaluation PCB (12)Bill of Materials for Evaluation PCB (12)Packaging and Ordering Information (13)Outline Dimensions (13)Ordering Guide (14)REVISION HISTORY11/14—Rev. 00.0813 to Rev. AThis Hittite Microwave Products data sheet has been reformattedto meet the styles and standards of Analog Devices, Inc.Updated Format .................................................................. U niversal Changes to Ordering Guide . (14)Rev. A | Page 2 of 14Data Sheet HMC1094 SPECIFICATIONSV CC = 3.3 V, T A = 25°C, unless otherwise noted.Table 1.Parameter Test Conditions/Comments Min Typ Max Unit OVERALL FUNCTIONInput Frequency Range1 1 23 GHzRF INPUT INTERFACE P IN = RFINNominal Input Impedance 50 Ω OUTPUT INTERFACEOutput Voltage Range 1 2.1 VRise Time f = 10 GHz, P IN = off to 0 dBm, 10% to 90% 12 nsFall Time f = 10 GHz, P IN = off to 0 dBm, 10% to 90% 65 nsf IN = 1 GHz±3 dB Dynamic Range 48 dB±3 dB Dynamic Range Center −20 dBm Deviation vs. Temperature Deviation from calculated ideal output at 25°C,±0.8 dB−40°C < T A < +85°CLogarithmic Slope Calibration at −38 dBm and −2 dBm 20 mV/dB Logarithmic Intercept Calibration at −38 dBm and −2 dBm (x-intercept) −96 dBmf IN = 5 GHz±3 dB Dynamic Range 48 dB±3 dB Dynamic Range Center −22 dBm Deviation vs. Temperature Deviation from calculated ideal output at 25°C,±0.7 dB−40°C < T A < +85°CLogarithmic Slope Calibration at −38 dBm and −2 dBm 21 mV/dB Logarithmic Intercept Calibration at −38 dBm and −2 dBm (x-intercept) −97 dBmf IN = 10 GHz±3 dB Dynamic Range 48 dB±3 dB Dynamic Range Center −23 dBm Deviation vs. Temperature Deviation from calculated ideal output at 25°C,±0.5 dB−40°C < T A < +85°CLogarithmic Slope Calibration at −38 dBm and −2 dBm 20 mV/dB Logarithmic Intercept Calibration at −38 dBm and −2 dBm (x-intercept) −100 dBmf IN = 14 GHz±3 dB Dynamic Range 50 dB±3 dB Dynamic Range Center −24 dBm Deviation vs. Temperature Deviation from calculated ideal output at 25°C,±1 dB−40°C < T A < +85°CLogarithmic Slope Calibration at −38 dBm and −2 dBm 19 mV/dB Logarithmic Intercept Calibration at −38 dBm and −2 dBm (x-intercept) −105 dBmf IN = 16 GHz±3 dB Dynamic Range 54 dB±3 dB Dynamic Range Center −25 dBm Deviation vs. Temperature Deviation from calculated ideal output at 25°C,±0.7 dB−40°C < T A < +85°CLogarithmic Slope Calibration at −38 dBm and −2 dBm 19 mV/dB Logarithmic Intercept Calibration at −38 dBm and −2 dBm (x-intercept) −108 dBmRev. A | Page 3 of 14HMC1094 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unitf IN = 18 GHz±3 dB Dynamic Range 54 dB±3 dB Dynamic Range Center −26 dBm Deviation vs. Temperature Deviation from calculated ideal output at 25°C,±0.7 dB−40°C < T A < +85°CLogarithmic Slope Calibration at −38 dBm and −2 dBm 18 mV/dB Logarithmic Intercept Calibration at −38 dBm and −2 dBm (x-intercept) −111 dBmf IN = 20 GHz±3 dB Dynamic Range 55 dB±3 dB Dynamic Range Center −27 dBm Deviation vs. Temperature Deviation from calculated ideal output at 25°C,±0.8 dB−40°C < T A < +85°CLogarithmic Slope Calibration at −38 dBm and −2 dBm 18 mV/dB Logarithmic Intercept Calibration at −38 dBm and −2 dBm (x-intercept) −113 dBmf IN = 23 GHz±3 dB Dynamic Range 57 dB±3 dB Dynamic Range Center −24 dBm Deviation vs. Temperature Deviation from calculated ideal output at 25°C,±1.1 dB−40°C < T A < +85°CLogarithmic Slope Calibration at −38 dBm and −2 dBm 18 mV/dB Logarithmic Intercept Calibration at −38 dBm and −2 dBm (x-intercept) −113 dBm POWER SUPPLY INTERFACESupply Voltage 3.15 3.30 3.45 V Supply Current 70 85 95 mA1 Video output load should be 1 kΩ or higher.Rev. A | Page 4 of 14Data Sheet HMC1094 ABSOLUTE MAXIMUM RATINGSTable 2.Parameter Rating Supply Voltage, V CC 3.6 VRF Input Power, RFIN 13 dBmRF DC Level 1.1 V Maximum Junction Temperature (T J) 125°C Continuous Power Dissipation (P DISS) at T A =85°C (Derate 65.4 mW/°C Above 85°C)2.62 WThermal Resistance (R TH) (Junction toGround Paddle)15.29°C/W Storage Temperature −65°C to +150°C Operating Temperature −40°C to +85°C ESD Sensitivity Level (HBM) Class 1B Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.Rev. A | Page 5 of 14HMC1094Data SheetPIN CONFIGURATION AND FUNCTION DESCRIPTIONSFigure 2. Pin ConfigurationTable 3. Pin Function DescriptionsPin No. Mnemonic Description1 GND Ground. This pin must be connected to a high quality RF/dc ground.2 RFIN RF Input. The dc voltage level of the RF input should be 0 V. If the RF input has a dc level different than 0 V, use a dc block capacitor.3 GND Ground. This pin must be connected to a high quality RF/dc ground.4 RSV Reserved. This pin is reserved for internal use; leave this pin floating.5 RSV Reserved. This pin is reserved for internal use; leave this pin floating.6 GND Ground. This pin must be connected to a high quality RF/dc ground.7 GND Ground. This pin must be connected to a high quality RF/dc ground.8 NC No Connect. No connection is necessary for this pin; this pin may be connected to RF/dc ground without affecting performance.9 RSV Reserved. This pin is reserved for internal use; leave this pin floating. 10 RSVReserved. This pin is reserved for internal use; leave this pin floating. 11 LOGOUT Log Out. The log out load should be at least 1 kΩ or higher.12 VTEMP Temperature Sensor Output. This pin requires a minimum 10 kΩ resistance or higher. 13V CC Bias Supply. Connect a supply voltage to this pin with appropriate filtering. 14 V CC Bias Supply. Connect a supply voltage to this pin with appropriate filtering. 15 V CC Bias Supply. Connect a supply voltage to this pin with appropriate filtering. 16 V CC Bias Supply. Connect a supply voltage to this pin with appropriate filtering.EPExposed Pad. Connect the exposed pad to a high quality RF/dc ground.12810-01712111096516151413GND RFIN GND RSV VTEMP V C CV C CV C CV C CLOGOUT RSV RSVR S V G N D G N D N C NOTES1.NO CONNECTION NECESSARY. THIS PIN MAY BE CONNECTED TO RF/DC GROUND WITHOUT AFFECTING PERFORMANCE.2.EXPOSED PAD. CONNECT THE EXPOSED PAD TO A HIGH QUALITY RF/DC GROUND.Rev. A | Page 6 of 14Data Sheet HMC1094INTERFACE SCHEMATICSFigure 3. GND InterfaceFigure 4. RFIN Interface Figure 5. LOGOUT Interface Figure 6. VTEMP InterfaceFigure 7. V CC Interface VLOGOUTVVTEMPV CCRev. A | Page 7 of 14HMC1094Data SheetTYPICAL PERFORMANCE CHARACTERISTICSV CC = 3.3 V , T A = 25°C, unless otherwise noted.Figure 8. LOGOUT and Error vs. Input Power, f IN = 1 GHzFigure 9. LOGOUT and Error vs. Input Power, f IN = 5 GHzFigure 10. LOGOUT and Error vs. Input Power, f IN = 10 GHzFigure 11. LOGOUT and Error vs. Input Power, f IN = 14 GHzFigure 12. LOGOUT and Error vs. Input Power, f IN = 16 GHzFigure 13. LOGOUT and Error vs. Input Power, f IN = 18 GHz2.250.751.001.251.501.752.003–3–2–1012–60–50–40–30–20–1010L O G O U T (V )E R R O R (d B )INPUT POWER (dBm)12810-0022.250.751.001.251.501.752.003–3–2–112–60–50–40–30–20–1010L O G O U T (V )E R R O R (d B )INPUT POWER (dBm)12810-0032.250.751.001.251.501.752.003–3–2–1012–60–50–40–30–20–1010L O G O U T (V )E R R O R (d B )INPUT POWER (dBm)12810-0042.250.751.001.251.501.752.003–3–2–112–60–50–40–30–20–1010L O G O U T (V )E R R O R (d B )INPUT POWER (dBm)12810-0052.250.751.001.251.501.752.003–3–2–112–60–50–40–30–20–1010L O G O U T (V )E R R O R (d B )INPUT POWER (dBm)12810-0062.250.751.001.251.501.752.003–3–2–112–60–50–40–30–20–1010L O G O U T (V )E R R O R (d B )INPUT POWER (dBm)12810-007Rev. A | Page 8 of 14Data SheetHMC1094Figure 14. LOGOUT and Error vs. Input Power, f IN = 20 GHzFigure 15. LOGOUT and Error vs. Input Power, f IN = 23 GHzFigure 16. LOGOUT vs. FrequencyFigure 17. Fall Time for Various Frequencies at P IN = 0 dBm2.250.751.001.251.501.752.003–3–2–1012–60–50–40–30–20–1010L O G O U T (V )E R R O R (d B )INPUT POWER (dBm)12810-0082.250.751.001.251.501.752.003–3–2–112–60–50–40–30–20–1010L O G O U T (V )E R R O R (d B )INPUT POWER (dBm)12810-0092.250.751.001.251.501.752.00–60–50–40–30–20–1010L O G O U T (V )INPUT POWER (dBm)12810-0102.11.01.11.21.31.41.51.61.71.81.92.0250225200175150125100755025L O G O U T (V )TIME (ns)12810-011Rev. A | Page 9 of 14HMC1094Data SheetFigure 18. Rise Time for Various Frequencies at P IN = 0 dBmFigure 19. Input Return Loss vs. FrequencyFigure 20. VTEMP vs. Temperature2.01.01.21.41.61.860555045403530252015105LO G O U T (V )TIME (ns)12810-012–25–20–15–10–5R E T U R N L O S S (d B )FREQUENCY (GHz)12810-0131.40.80.91.01.11.21.3–452595V T E M P (V )TEMPERATURE (°C)12810-014Rev. A | Page 10 of 14APPLICATION AND EVALUATION PRINTED CIRCUIT BOARD (PCB) SCHEMATICFigure 21. Application and Evaluation PCB SchematicTable 4.Component DescriptionDefault ValueR7 Bypass resistor; used to make the RFIN line connection on the board R7 = 0 Ω (Size 0402)C1 Power supply decoupling C1 = 4.7 μF (size tantalum) C2, C3Power supply decouplingC2 and C3 = 10 nF (Size 0402)12810-015V CCEVALUATION PCBFigure 22. Evaluation PCB Layout, Top SideBILL OF MATERIALS FOR EVALUATION PCBTable 5. Bill of MaterialsItem DescriptionJ2 K-type connector J5SMA connector TP1, TP2, TP3 DC pinC2, C3 10 nF capacitor, 0402 package C1 4.7 µF tantalum capacitor R7 0 Ω resistor, 0402 package U1 HMC1094 log detectorPCB 1600-00733-00 evaluation PCB1Circuit board material: Rogers 4350B or Arlon 25 FR.The circuit board used in the application uses RF circuit design techniques. Signal lines should have 50 Ω impedance whereas the package ground leads and exposed paddle should beconnected directly to the ground plane similar to that shown in Figure 21. Use a sufficient number of via holes to connect the top and bottom ground planes.12810-016PACKAGING AND ORDERING INFORMATIONOUTLINE DIMENSIONSFigure 23. 16-Lead Quad Flat No-Lead Package [QFN]3 mm × 3 mm Body, Very Thin Quad Dimensions shown in inches and [millimeters]Figure 24. Tape and Reel Outline DimensionsDimensions shown in millimeters11-03-2014-ANOTES:1.PACKAGE BODY MATERIAL:LOW STRESS INJECTION MOLDED PLASTIC SILICA AND SILICON IMPREGNATED.2.LEAD AND GROUND PADDLE MATERIAL:COPPER ALLOY.3.LEAD AND GROUND PADDLE PLATING:100%MATTE TIN.4.DIMENSIONS ARE IN INCHES [MILLIMETERS].5.LEAD SPACING TOLERANCE IS NON-CUMULATIVE.6.CHARACTERS TO BE HELVETICA MEDIUM,.018HIGH,WHITE INK,OR LASER MARK LOCATED APPROX.AS SHOWN.7.PAD BURR LENGTH SHALL BE 0.15mm MAX.PAD BURR HEIGHT SHALL BE 0.05mm.8.PACKAGE WARP SHALL NOT EXCEED 0.05mm.9.REFER TO HITTITE APPLICATION NOTE FOR SUGGESTED PCB LAND PATTERN.THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONSSECTION OF THIS DATA SHEET.11-03-2014-A1 E = RoHS Compliant Part.2 Maximum peak reflow temperature of 260°C for HMC1094LP3E and HMC1094LP3ETR.3 Four-digit lot number represented by XXXX.©2013–2014 Analog Devices, Inc. All rights reserved. Trademarks andregistered trademarks are the property of their respective owners./HMC1094D12810-0-11/14(A)。
Chirp Microsystems EV_MOD_CH101 评估模块用户指南 AN-000231
AN-000231Chirp Microsystems reserves the right to changeChirp Microsystems2560 Ninth Street, Ste 200, Berkeley, CA 94710 U.S.A Document Number: AN-000231EV_MOD_CH101 Evaluation Module User GuideTABLE OF CONTENTS1Scope and Purpose (3)2EV_MOD_CH101 Evaluation Module Board (4)2.1Pin Assignments (4)2.2Electrical Specifications (4)2.3Schematic (4)2.4Bill of Materials (5)3Configuration, Programming, and Operation (6)3.1Configuration and Programming (6)3.2Operation (6)4Mechanical Specifications (7)5Sensor Mounting and Beam Patterns (8)5.1Sensor Mounting (8)5.2Beam Patterns (8)6Revision History (10)LIST OF FIGURESFigure 1. View of EV_MOD_CH101 evaluation module with an omnidirectional acoustic housing (3)Figure 2. EV_MOD_CH101 Schematic (4)Figure 3. EV_MOD_CH101 Module Connection (EV_MOD_CH101 acoustic port is facing down) (5)Figure 4. Dimensions of the EV_MOD_CH101 assembly (7)Figure 5. Recommended EV_MOD_CH101 module mounting (8)Figure 6. Beam pattern measurements of module in 100 mm plate (raw linear LSB units left, normalized dB right) (8)Figure 7. Beam pattern measurements of an EV_MOD_CH101 (w/o a mounting plate) (9)LIST OF TABLESTable 1. EV_MOD_CH101 ZIF Connector Pin-Out (4)Table 2. Recommended Flat Flex Cable and Connector (5)Table 3. Bill of Material (5)Table 4. Geometric Dimensions for EV_MOD_CH101 (7)1SCOPE AND PURPOSEThis document details the specification, programming and operation of an EV_MOD_CH101-03-01 (referred to as the EV_MOD_CH101 in the remainder of this document) ultrasonic sensor evaluation module. The module board incorporates a CH101 Ultrasonic Sensor device with an omnidirectional acoustic housing assembly, a capacitor and an FPC/FFC connector. This evaluation module can perform pitch-catch and pulse-echo range-finding at distances from 4 cm to 1.2m. Several programming options are available for medium and short-range applications.Figure 1. View of EV_MOD_CH101 evaluation module with an omnidirectional acoustic housing2EV_MOD_CH101 EVALUATION MODULE BOARD2.1PIN ASSIGNMENTSPIN NAME DESCRIPTION1 INT Interrupt output. Can be switched to input for triggering and calibration functions2 SCL SCL Input. I2C clock input. This pin must be pulled up to VDD externally.3 SDA SDA Input/Output. I2C data I/O. This pin must be pulled up to VDD externally.4 PROG Program Enable. This pin must be pulled down to ground externally.5 RESET_N Active-low reset. This pin must be pulled up to VDD externally.6 VSS Power return.7 VSS Power return.8 VDD Power supply input. Connect to externally regulated 1.8V supplyTable 1. EV_MOD_CH101 ZIF Connector Pin-Out2.2ELECTRICAL SPECIFICATIONSPlease refer to DS-000331 CH101 Datasheet for information on the device’s electrical characteristics. Please note that the datasheet covers CH101 part numbers with different suffixes. Regardless, the electrical specifications in the datasheet still apply.2.3SCHEMATICElectrical connection to the EV_MOD_CH101 module is via an 8-pin 0.5 mm pitch flat flex cable (FFC) connector. Part numbers of the FFC connectors on the module PCB and the recommended FFC cables are shown in Table 2. The electrical schematic of the module, including the connector pinout and the connections to the EV_MOD_CH101 module, are shown in Figure 2. Note that the 0.1 μF decoupling capacitor, as recommended in the CH101 datasheet, is included in the module. Consult the CH101 datasheet and application notes for additional information on the electrical connections and operation.Figure 2. EV_MOD_CH101 SchematicEach EV_MOD_CH101 requires its own PROG and INT lines, the remaining connections can be shared. Refer to the CH101 datasheet for additional information.Module connections using a flat flex cable (FFC) are shown in Figure 3.Figure 3. EV_MOD_CH101 Module Connection (EV_MOD_CH101 acoustic port is facing down)FLAT CABLE CONNECTOR TYPE Molex 503480-0800RECOMMENDED FLAT CABLE Molex 151660073 (151660094)Table 2. Recommended Flat Flex Cable and Connector2.4BILL OF MATERIALSQUANTITY REFERENCE PART PCB FOOTPRINT MANUFACTURER MANUFACTURERPART NUMBER1 PCB PCB NA1 U1 CH101-03 Custom – 8 Pin TDK CH101-031 C1 100n 6.3V 20% X7R 0402 0402 TDK CGA2B1X7R1C104K050BC1 J1 Connector, FPC-FFC, 8-Pin 8Pin, 0.5 mm Pitch Molex 503480-0800Table 3. Bill of Material3CONFIGURATION, PROGRAMMING, AND OPERATION Please refer to DS-000379 CH101 Datasheet for information on the device’s electrical characteristics.3.1CONFIGURATION AND PROGRAMMINGPlease refer to the following documents for configuration and programming information:•AN-000154 SmartSonic Hello Chirp Hands-On Document•AN-000175 SonicLib Programmers Guide3.2OPERATIONPlease refer to the following documents for operating information:•AN-000155 CHx01 SonicLink Software Quick Start Guide•AN-000180 CH101 and CH201 SmartSonic Evaluation Kit Users Guide4MECHANICAL SPECIFICATIONSDIMENSION EV_MOD_CH101 UNITAcoustic port hole 0.7 mmMaximum width 8.15 mmModule height 3.57 mmTable 4. Geometric Dimensions for EV_MOD_CH101The outer dimensions of the EV_MOD_CH101 assembly are shown in Figure 4. The acoustic port hole has a diameter of 0.7 mm and is in the center of the front face. During transducer operation, the port cannot be occluded or covered.Figure 4. Dimensions of the EV_MOD_CH101 assembly5 SENSOR MOUNTING AND BEAM PATTERNS5.1 SENSOR MOUNTINGTo achieve the best acoustic performance, users are recommended to mount the EV_MOD_CH101 module in a flat mounting plate. An example mounting plate is shown in Figure 5, where the sensor has been inserted into a 5.3 mm diameter hole has been drilled in a 1 mm thick plastic plate measuring 135 mm x 175 mm.Figure 5. Recommended EV_MOD_CH101 module mounting5.2 BEAM PATTERNSPulse-echo beam-pattern plots of the EV_MOD_CH101 module are shown in Figure 6. This beam-pattern was measured by placing a 1m 2 target at a 30 cm distance from the EV_MOD_CH101 module and recording the ToF amplitude as the sensor is rotated 180°. The plots are shown in both raw LSB units and normalized dB units, where 0 dB corresponds to the peak amplitude (5000 LSB) recorded on-axis. Chirp defines the field-of-view (FoV) as the full-width at half-maximum (FWHM) of the beam pattern; in other words, the FoV is the range of angles over which the amplitude remains above half the peak amplitude (or -6 dB). When mounted in the recommended plate, the sensor’s FoV is approximately 180° and the pulse-echo amplitude diminishes relatively smoothly from 0° to ±80°.Figure 6. Beam pattern measurements of module in 100 mm plate (raw linear LSB units left, normalized dB right)CH101 sensor moduleFor comparison, the pulse-echo beam-pattern plot measured for an EV_MOD_CH101 when tested without a sensor mounting plate is shown in Figure 7. The beam pattern has three lobes: a main lobe and two side-lobes that are centered at ±45°. The sensor device will work well for detecting on-axis targets, but targets located at ±25° will have approximately 70% lower (-10 dB) amplitude, possibly resulting in poor range-finding performance.Figure 7. Beam pattern measurements of an EV_MOD_CH101 (w/o a mounting plate)(raw linear LSB units left, normalized dB right)6REVISION HISTORYREVISION DATE REVISION DESCRIPTION08/18/2020 1.0 Initial ReleaseThis information furnished by Chirp Microsystems, Inc. (“Chirp Microsystems”) is believed to be accurate and reliable. However, no responsibility is assumed by Chirp Microsystems for its use, or for any infringements of patents or other rights of third parties that may result from its use. Specifications are subject to change without notice. Chirp Microsystems reserves the right to make changes to this product, including its circuits and software, in order to improve its design and/or performance, without prior notice. Chirp Microsystems makes no warranties, neither expressed nor implied, regarding the information and specifications contained in this document. Chirp Microsystems assumes no responsibility for any claims or damages arising from information contained in this document, or from the use of products and services detailed therein. This includes, but is not limited to, claims or damages based on the infringement of patents, copyrights, mask work and/or other intellectual property rights.Certain intellectual property owned by Chirp Microsystems and described in this document is patent protected. No license is granted by implication or otherwise under any patent or patent rights of Chirp Microsystems. This publication supersedes and replaces all information previously supplied. Trademarks that are registered trademarks are the property of their respective companies. Chirp Microsystems sensors should not be used or sold in the development, storage, production or utilization of any conventional or mass-destructive weapons or for any other weapons or life threatening applications, as well as in any other life critical applications such as medical equipment, transportation, aerospace and nuclear instruments, undersea equipment, power plant equipment, disaster prevention and crime prevention equipment.©2020 Chirp Microsystems. All rights reserved. Chirp Microsystems and the Chirp Microsystems logo are trademarks of Chirp Microsystems, Inc. The TDK logo is a trademark of TDK Corporation. Other company and product names may be trademarks of the respective companies with which they are associated.©2020 Chirp Microsystems. All rights reserved.。
Autodesk Nastran 2023 参考手册说明书
FILESPEC ............................................................................................................................................................ 13
DISPFILE ............................................................................................................................................................. 11
File Management Directives – Output File Specifications: .............................................................................. 5
BULKDATAFILE .................................................................................................................................................... 7
National Instruments PCIe-5785 5775 FLEXRIO IF TRA
Manufacturer: National InstrumentsBoard Assembly Part Numbers (Refer to Procedure 1 for identification procedure):Part Number and Revision Description149945A-01L or later PCIE-5785, FLEXRIO IF TRANSCEIVER, 2X2 CH, 6.4 GS/S, KU035149945A-02L or later PCIE-5785, FLEXRIO IF TRANSCEIVER, 2X2 CH, 6.4 GS/S, KU040149945A-03L or later PCIE-5785, FLEXRIO IF TRANSCEIVER, 2X2 CH, 6.4 GS/S, KU060149945A-04L or later PCIE-5785, FLEXRIO IF TRANSCEIVER W/AO FLTR, 2X2 CH, 6.4 GS/S, KU035 149945A-05L or later PCIE-5785, FLEXRIO IF TRANSCEIVER W/AO FLTR, 2X2 CH, 6.4 GS/S, KU040 149945A-06L or later PCIE-5785, FLEXRIO IF TRANSCEIVER W/AO FLTR, 2X2 CH, 6.4 GS/S, KU060Part Number and Revision Description149946A-01L or later PCIE-5775, FLEXRIO DIGITIZER, 2 CH, 6.4 GS/S, 12-BIT, KU035149946A-02L or later PCIE-5775, FLEXRIO DIGITIZER, 2 CH, 6.4 GS/S, 12-BIT, KU040149946A-03L or later PCIE-5775, FLEXRIO DIGITIZER, 2 CH, 6.4 GS/S, 12-BIT, KU060Volatile MemoryTarget Data Type Size BatteryBackupUser1AccessibleSystemAccessibleSanitizationProcedureData storage DRAM 4 GB No Yes Yes Cycle power User FPGA bitstreamstorageSDRAM 32 MB No Yes Yes Cycle powerUser bitstream FPGA Xilinx KU035,KU040 orKU060No Yes Yes Cycle power Non-Volatile Memory (incl. Media Storage)Target Data Type Size BatteryBackupUserAccessibleSystemAccessibleSanitizationProcedureAdapter module ID EEPROM 32 KB No No Yes NoneFPGA configuration logic CPLD Altera10M04SAU169No No Yes NoneUser persistentFPGA imageFLASH 64 MB No No Yes NoneDefault persistentFPGA imageFLASH 64 MB No No Yes None Golden FPGA image FLASH 64 MB No No Yes None Calibration constants EEPROM 1 KB No Yes Yes Procedure 21 Refer to Terms and Definitions section for clarification of User and System AccessibleProceduresProcedure 1 – Board Assembly Part Number identification:To determine the Board Assembly Part Number and Revision, refer to the label applied to the surface of your product. The Assembly Part Number should be formatted as “P/N: 146652a-xxL” or “P/N: 149066a-xxL” where “a” is the letter revision of the assembly (e.g. A, B, C…) and “xx” describes the product version.Procedure 2 – Calibration Constants EEPROM:Requirements: LabVIEW 2018 or later and FlexRIO 18.7 or laterThe calibration constants EEPROM can be cleared by using the FlexRIO API to overwrite the memory space with arbitrary values. To clear the storage through LabVIEW, complete the following steps:1.Find and open the example LabVIEW Project “Read-Write Calibration Data”at “C:\<ProgramFiles>\National Instruments\<LabVIEW>\examples\FlexRIO\System Calibration\” (replace<LabVIEW> with version of LabVIEW running on system).a.Alternatively, create a new VI and drop the “Write Calibration Data” VI from the FlexRIO APIpalette.2.Select your FlexRIO device from FPGA Resource dropdown and set Calibration Operation to Write.3.Run VI with Calibration Data set to 0, or other arbitrary value, to clear values in flash memory.4.Repeat Step 3 for entire memory space to clear entire EEPROM memory. Set the Read option for theCalibration Operation to verify data has been cleared or to check sections of memory for otherunintended values.This memory space is also exposed to the C API. Use the following code as reference to clear it:// Open session to the resourceniFlexRIO_OpenSession(resource, bitfile, 0, &session)// Determine calibration storage sizeniFlexRIO_GetAttributeInt32(session, NULL, kFlexRIO_CalibrationStorageSize, &size)// Allocate byte buffer of zeroszeros = calloc(size, 1);// Write zeros to the deviceniFlexRIO_WriteCalibrationData(session, 0, zeros, size)Terms and DefinitionsCycle Power:The process of completely removing power from the device and its components and allowing for adequate discharge. This process includes a complete shutdown of the PC and/or chassis containing the device; a reboot is not sufficient for the completion of this process.Volatile Memory:Requires power to maintain the stored information. When power is removed from this memory, its contents are lost. This type of memory typically contains application specific data such as capture waveforms.Non-Volatile Memory:Power is not required to maintain the stored information. Device retains its contents when power is removed. This type of memory typically contains information necessary to boot, configure, or calibrate the product or may include device power up states.User Accessible:The component is read and/or write addressable such that a user can store arbitrary information to the component from the host using a publicly distributed NI tool, such as a Driver API, the System Configuration API, or MAX. System Accessible:The component is read and/or write addressable from the host without the need to physically alter the product. Clearing:Per NIST Special Publication 800-88 Revision 1, “clearing” is a logical technique to sanitize data in all User Accessible storage locations for protection against simple non-invasive data recovery techniques using the same interface available to the user; typically applied through the standard read and write commands to the storage device.Sanitization:Per NIST Special Publication 800-88 Revision 1, “sanitization” is a process to render access to “Target Data” on the media infeasible for a given level of effort. In this document, clearing is the degree of sanitization described.。
Conformal_Verification_Guide_8.1
I N VE N TI V ECONFIDENTIALFormal Verification GuidePrototype | Implement | VerifyAgenda• Equivalence Checking Refresh • Verification Guide– RTL Design – Verifiable Synthesis Flow – Abort Resolution• ECO Automation • Best Practice Recommendation2August 6, 2009Cadence ConfidentialEncounter Conformal Product FamilyVerifies 100% of design functionality without requiring test vectors Provides independent verification for lowest risk silicon Validates CPF LP Equivalence Checking Verifies Low Power design implementation Performs structural and functional checksEquivalence CheckingRTL or Gate RTL or GateDigital Custom Verification including Memories, Data Paths, and IO Orders of magnitude faster than simulationLow Power VerificationFunctional Checksv1v2ISOABFinds bugs earlier in the design cycle Verifies proper CDC synchronization to avoid clock related re-spins Creates safer EC environmentValidation, generation and analysis of constraints Uses industry proven formal engines Shorter design cycle with improved timing constraintsConstraint DesignECO Implementationo1 o2Provides automated RTL2GDS ECO solution Identifies and generates fix to implement ECO Interfaces with physical implementation tool flow3August 6, 2009Cadence ConfidentialEncounter Conformal & FED Product FamilyEquivalence CheckingRTL or Gate RTL or GateConstraint DesignLow Power VerificationFunctional ChecksAValidation, generation & analysis of constraints Shorter design cycles with improved timing constraintsv 1v2ISOB100% Independent vector-less verification of implementation RTL Gate Transistor CDC & Ext ChecksStructural and functional LP checks LP design implementation Verification LP Equivalence CheckingNew Products ECO Implementation RC-Physical Synthesis Chip Planning Systemso 1 o 2Automated RTL2GDS ECO solution Identifies and generates ECO fix Physical Correlation & Predictability with final backend Congestion Analysis & Opto (Congestion Relief) Architectural & Economic Forecasting Lower IC Cost & Expedite TTM4August 6, 2009Cadence ConfidentialI N VE N TI V ECONFIDENTIALCrash Course on Equivalency CheckingPrototype | Implement | VerifyEquivalence Checking FlowGolden Design Standard Library Revised DesignSpecify Constraints and Design ModelingSetup Mode LEC ModeSpecify Compare ParametersCompare DesignsMiscompare?yesDiagnosenoEquivalence Checking Complete6August 6, 2009Cadence ConfidentialMapping! What is that?Pairing corresponding golden and revised key points:G RPI PO DFF DLAT BBOX CUT Z EPI PO DFF DLAT BBOX CUT Z E Key points Combinatorial logicGolden RevisedE UExtra Points Unreachable Points Unmapped Points7August 6, 2009Cadence ConfidentialComparison– Only mapped points can be compared. – Comparison is an iterative process.• Conformal remembers points already compared. • Comparison can be interrupted with Control-c. • Enter compare to continue comparing.set log file logfile.$LEC_VERSION -replace add notranslate module *sram* -library -both read design cpu_rtl.v -verilog -golden read design -file verilog.vc -verilog -revised // Command:pin constraint 0 scan_en -revised add compare ================================================================================ set flatten model -latch_fold Compared points PO DFF DLAT BBOX Total add renaming rule rule0 "abc" "xyz" -map -revised -------------------------------------------------------------------------------Equivalent renaming rule rule1 "xyz" "C" -map -golden 2 146 2 1 151 add -------------------------------------------------------------------------------set system mode lec Non-equivalent 0 2 0 0 2 add compare points -all ================================================================================ compare ...8August 6, 2009Cadence ConfidentialUsing the Mapping Manager to Debug NEQsMain windowUnmapped pointsMapped pointsCompared points9August 6, 2009Cadence ConfidentialCategories of Comparison ResultsEquivalent: Key points proven to be equivalent (green-filledcircle)Inverted-Equivalent: Key points proven to be complementary (divided green-filled circle) Nonequivalent: Key points proven to be different (red-filled circle) Abort: Key points not yet proven equivalent or nonequivalent due to timeout or other system parameters (yellow-filled circle) Not-Compared: Key points not yet compared?10LEC> report compare data -class [...]August 6, 2009Cadence ConfidentialI NVENTIVE CONFIDENTIAL RTL DesignFor Ease of VerificationRTL Design For Ease of Verification•To highlight the impact of RTL design on verification –Useful for RTL designers to understand their impact of coding styles on verification–Useful guidelines for machine/script generated RTL codes •Factors in RTL designs that can affect the ease of verifications are–Don’t care conditions in RTL description–Structuring of logics–Partitioning of designsRTL Design For Ease of VerificationDon’t-Cares Conditions in RTL•Don’t-care conditions are created in RTL by–X assignments–Incomplete case–Out-of-range indexing–Range constraint (VHDL)• A don’t-care condition can be synthesized to– a constant (zero or one)–or any Boolean function•Designs with extensive don’t-care conditions can be difficult to verify •Use LEC “report design data”to report don’t cares•Use LEC “report rule checks”to report out-of-range indexingRTL Rule Checkers•LEC’s RTL rule checker provides an fast and easy way to detect RTL coding styles that can impact verification •For example, index out of range is reported as –// Warning: (RTL7.3) Array index in RHS might be out of range (occurrence:1)•Running LEC RTL rule checker early in the RTL design process can reduce many potential synthesis andverification issues later onRTL Rule CheckersSETUP> read design –golden rtl.vSETUP> read design –revised rtl.vSETUP> set system mode lecSETUP> report rule check –golden –design –verbose > lint.rptSETUP> report message –golden –model –verbose > model.rpt•Consider Synthesis and EC ramifications of design –Multiply-driven and floating nets–Combinational cycles–Assignment size mismatch–Ambiguities leading to simulation mismatches–EtcRTL Design For Ease of VerificationDon’t-Cares Due to Index Out of Range•Don’t care is created when index is out of range –When the index can address more locations thanwhat an array can hold•For examplereg[4:0] q; // q has 5 locationsReg[2:0] A; // A can index 8 locationsBAD -q[A];// (1) out-of-range conditionGOOD -q[(A> 4) ? 0: A)];// (2) No out-of-rangeLogic Structuring•Structural Similarity–How closely does RTL structure match the netlist •Designs with higher structural similarity between RTL and netlist are easier to verify•Synthesis can restructure code. For examples:–Resource sharing–Map unsigned operators to signed operators•Minimize structural differences between RTL and netlist by:–Using Verilog 2K to code signed arithmetics–Using explicit grouping (such as in additions) with parenthesis –Manually code resource sharingDesign Partitioning•Partitioning a complex block breaks it into smaller pieces for ease of verification•Guidelines–Keep high complexity design modules small in size–Avoid excessive logic cone depth–Separate datapath block (especially those requiring retiming) from control block–Partitioning may impact QOR so the tradeoffs should be explored early in the design cycle•Smaller blocks are easier to verify. Well partitioned designs can also make use of more techniques to ease verificationsI NVENTIVE CONFIDENTIAL Verifiable Synthesis FlowModule Data PathArchitecture & Advanced Synthesis Optimizations Create Verification Challenges DatapathArchitectureBoundary OptimizationPhase Inversion Resource Sharing• A synthesis flow with verification considerations can significantly reduce verification challenges–Enable the identification of synthesis bugs more easily–Allow use of more LEC features (e.g., module-based datapath analysis, hierarchical comparisons) to streamline the verification processL E CSynthesis Optimization on Datapath Modules•Synthesis tools like RC and DC can group several datapath operators into asingle datapath unit which called datapath module. These modules can be synthetic or they can be instantiated components such as DW modules•For Design Compiler, these modules are reported in the resource report with string DP_OP as naming convention•These modules boundary are not preserved if ungrouping and boundary optimization are applied, making them difficult to prove Synthesis Flow Needs To Be Verification-Friendly R T L D a t a p a t h D e si g n ungroup/boundary optimizationMulti-Stage Synthesis•The basic principle of ensuring ease of verification is to break difficult to verify synthesis optimizations intostages in the synthesis flow•Recommend synthesis stages–RTL to first mapped netlist•Enable: datapath synthesis•Disable: ungrouping, boundary optimizations, phase inversions –Mapped netlist to optimized mapped•Enable: Ungrouping, Incremental optimizations, boundaryoptimizationsEmbed Verification Requirements in Synthesis •To deploy an easy to verify synthesis flow, embed the verificationsinto the synthesis scripts–Instead of resynthesizing after running into verification challenges •Control synthesis options that impact verification, e.g.,–Range constraint–Datapath synthesis, resource sharing–Ungrouping, boundary optimizations•Allow for a range of verification requirements to allow for trade-offs in verifiability•This is default behavior for Encounter RTL Compiler (RC)LEC Feature Module Based Datapath (MDP) Analysis (DC Synthesis)•Datapath synthesis may cause aborts because of operator optimization.•This is handled in RTL Compiler with Netlist Verification (more later). DC netlists require MDP.•Module-Based Datapath (MDP) Analysis performs datapath abstraction at a module level•This analysis is performed in addition to and prior to the regular operator level analysis•The result goal is to improve the quality of the operator-level analysis•Requires the preservation of synthetic datapath modules during synthesisRTLRTLFinal GateDC Script LE C DC Script Original Flow New Flow RTL FinalGate DC + MDP Script Intermediate Gate L E C LE C •Include MDP Script •Output Intermediate &Final Netlist•Perform RTL2Gate•Perform Gate2Gate Improve Synthesis Script to Ensure Verification Success (MDP) Analysis (DC Synthesis)DC Synthesis Script to Enable MDP Analysis•To enable the successful verification of datapath design using Design Compiler synthesis, LEC provides a script to ensure that LEC’s Module-Based Datapath (MDP) Analysis can be effectively applied•The script can be embedded into the overall synthesis script as followssource <lec_release_path>/share/cfm/lec/scripts/mdp.tcl…compile_ultra_mdp<level> <design_module>compile_ultra……<continue original DC synthesis script commands>…•compile_ultra_mdp command is placed before the first compile_ultra command in the DC script•Design module is the name of the top module that is synthesizedDC Synthesis Script for Datapath Verification •MDP level can be 1, 2, 3, or 4, and affects the synthesis as followsMDP Level Preserve Hierarchy ofBoundaryOptimizationSequentialOutputInversion DP/DW Design1YES NO ALLOW ALLOW 2YES NO DISABLE ALLOW 3YES NO DISABLE DISABLE 4YES YES DISABLE DISABLECollecting DC Synthesis Data•During the synthesis process, the following information should be collected for verification–Datapath Resource File: This is required to ensure that datapath intensive design can be easily verified–Change Name File: This is required to ensure name-based mapping for ease of verification–VSDC File: This file contains information that can help to guide the setup of the verification–Synthesis log file: This can contain information to help guide the setup of the verificationLEC Feature Qualifying Your DC Synthesis Environments •New versions of synthesis tools may introduce new verificationrequirements–New optimization techniques (e.g., sequential constant groups)–New datapath structures (e.g., new multiplier architectures)–New technology mapping techniques (e.g., using multi-bit library cells)–Changes in naming conventions (e.g., in generate statements)–Changes in default synthesis option settings (e.g., having sequential merge optimizations ON by default)•LEC ships with IP-free designs that can be used as testcases in a new synthesis environment or tool–Enable users to provide early feedbacks to the Conformal team to ensure success of verifications in the latest synthesis environment –At $conformal_dir/share/cfm/lec/demo/*How to Determine QoR ImpactRTL RTLFinalGate DC ScriptL E CDCScriptOriginal FlowNew FlowRTLRTLFinalGateDC ScriptDC + MDPScriptIntermediateGate L ECL E CQoR ImpactRC Netlist Verification Flow• RC verification flow– Only one intermediate netlist between RTL code and the final netlist – Two LEC comparisons: RTL-to-Intermediate & Intermediate-toFinal – Better support of advanced (datapath) optimizations – LEC-friendly netlist by 'write_hdl –lec’• additional datapath info (as comments) about architecture changes31August 6, 2009Cadence ConfidentialRC Netlist Verification Flow•Synthesize with no ungrouping •Output Intermediate & Final Netlist •Perform RTL2Gate •Perform Gate2GateNew Flowwrite_hdl -lecRTLFinal GateEC LIntermediate GateEC LIntermediate netlist to Ensure Verification Success32August 6, 2009Cadence ConfidentialRC Netlist Verification Flow for Datapathread_hdl elaborate read_sdcFirst netlist generated with “-lec” optionsynthesize -to_mapped write_hdl -lec > intermediate.v write_do_lec -revised intermediate.v > rtl2map.do [ungroup in any way] <no more datapath architecture change> Do not ungroup before first netlistsynthesize -incr as many times as wished without “-lec” option; write_hdl > final.v write_do_lec -golden intermediate.v -revised final.v > map2final.do exit Every “write_hdl” followed by “write_do_lec”33August 6, 2009Cadence ConfidentialRC Netlist Verification Flow for Datapath• First LEC run (RTL-gate):read design <RTL_code> -golden read design intermediate.v -revised compare – write_do_lec generates a hierarchical dofile script (rtl2map.do) – Conformal dofile script will contain the following commands: analyze datapath –module –verbose analyze datapath -verbose• Second LEC run (gate-gate):read design intermediate.v -golden read design final.v -revised compare – write_do_lec generates a flat dofile script (map2final.do)34August 6, 2009Cadence ConfidentialSummary• When a design is complex and contains many datapath operators, with today’s advance synthesis optimizations, the datapath become structurally different between RTL and netlist, creating challenge to all verification tools • To effectively help Conformal datapath analysis quality and improve verification result, an integrated synthesis & verification flow is needed • DC MDP Analysis and the recommended synthesis script will help close the gap between datapath synthesis and verification • RC Netlist Verification flow reduces the chance of aborts for a more complete verification35August 6, 2009Cadence ConfidentialI N VE N TI V ECONFIDENTIALAbort ResolutionResolving Aborts• Abort is reported when formal (exhaustive) analysis cannot provide a complete proof of equivalence within a resource limit– The design has been partially verified since no input vector resulting in non-equivalence has been found either• Resource limit is adjusted by compare effort– SET COMPARE EFFORT <LOW|MED|HIGH|COMPLETE>• This section describes– Techniques to resolve aborts – Methods to isolate abort to better understand the aborted region and options for further verifications37August 6, 2009Cadence ConfidentialResolving AbortsReview Synthesis Flow• Abort can be avoided by following the guidelines given earlier • For datapath intensive design– Check that MDP level 4 has been used for DC synthesis – Use Netlist Verification Flow for RC synthesis• RTL design for ease of verification– Check for excessive don’t care conditions with LEC’s rule checker and design report• Partition the design well and use LEC’s hierarchical comparison– Check that all complex modules can be hierarchically compared38August 6, 2009Cadence ConfidentialResolving AbortsReview LEC Dofiles• Hierarchical Comparison– Check that hierarchical comparison is used – For module containing abort, check that it has no submodules that can be further hierarchically compared• For datapath intensive design– Check that MDP has been used (Analyze datapath –module) – Check that datapath analysis are successful• Abort Analysis– Check that LEC’s abort analysis has been used (analyze abort)• Multithreading– Check that multithreading is used for abort analysis39August 6, 2009Cadence ConfidentialResolving AbortsAdvanced LEC Techniques• Several advanced techniques are available to resolve aborts • Advanced options for ‘analyze datapath’– – – – -wordlevel -share -effort high -addertree• Advanced commands and techniques– run partition_compare (help run partition_compare –verbose) – add partition points – read design –norangeconstraint –vhdl40August 6, 2009Cadence ConfidentialRe-synthesis and RTL Recoding•Re-synthesis of problem blocks–Adjust effort level–Disable range constraints–Preserve key signals and boundaries •Pros–Makes verification easy for all future runs •Cons–Requires additional efforts, may impact qualityAbort Isolation•When aborts cannot be completely resolved, it is useful to identify the region where aborts occurred–Allow for a more targeted re-synthesis–Allow for a better understanding on the netlist that leads to abort –Allow for additional verification to these smaller regions •Techniques to isolate abort–Ensure that the modules are hierarchically compared•Easier if RTL is partitioned well–In MDP analysis flow, abstracted datapath cluster can be automatically isolatedAbort Isolation for Datapath Module •When using MDP analysis, LEC can isolate the datapathmodule that causes the abort so that the remaining non-aborting netlist can be verified–That is, if the remaining netlist is equivalent and the datapath module is also equivalent, then the entire netlist is equivalent •Provides more visibility into the region of abort –Instead of reporting all fanout keypoints from the datapath module as abort, only the datapath module is reported as abort(See next slide)•The is invoked as–ANALYZE DATAPATH –isolate_abort_module…Abort Isolation for Datapath Module •Results with abort:==============================================================Compared points PO Total--------------------------------------------------------------Abort 67 67==============================================================•Results with abort isolation:==============================================================Compared points PO Total--------------------------------------------------------------Equivalent 67 67==============================================================Compared results of isolated instances in Revised design (top)==============================================================Status Instance (Module)--------------------------------------------------------------Abort i5/add_123_S1_DP_OP_123_456(NV_GR_PE_STRI_core_add_123_S1_DP_OP_123_456) ==============================================================Multi-Threading•For machines with multi-core CPUs–No need to set up the parallel processing environment–Takes advantage of multi-core, multi-CPU machines •Parallel ComparisonLEC> compare –threads #•Best for large gate-to-gate comparisons, where the comparison canbe distributed to multiple comparison threadsLEC> analyze abort –compare –threads #•Best for RTL-to-gate comparison aborts, where a few keypoints canconsume a large portion of the runtime*Obsoletes the previous method of parallel comparisons using the command Run Parallel Compare•Support two new multiplier architectures •Improve divider architecture analysis•Support higher effort analysis for better datapath learning quality.Results from sample testcasesRadix-8Unsigned DividerHigh Effort AnalysisDatapath AnalysisI NVENTIVE CONFIDENTIAL ECO AutomationPrototype | Implement | VerifyECO ChallengesNomenclature•Engineering Change Order (ECO) is the process of making local changes to the design netlist without re-running the entire synthesis and P&R flow•ECO Types–Functional ECO•Changes the functionality of the design–Non-functional ECO•Fix timing, cross talk, DRV, routing violations with minimal effort•ECO Stages–Pre-Mask ( Pre tape-out) ECO•Uses normal logic gates to implement change–Post-Mask (Metal-only ECO)•Uses spare gates only to implement changeECO ChallengesManual Task•Current ECO flows are manual–Process is very time and resource consuming–Error Prone–Limited by ECO size•Very difficult to identify location of needed fix–Easy to modify RTL, yet difficult to transfer fix to gate netlist•Manual ECO changes do not easily incorporate use of –Spare gates, location, timing, routing access–Freed cells (used originally but not used in ECO patch)•Hard to manually optimize the eco patchECO ChallengesManual Flow Targeting Post Mask ECOSynthesisNew RTL (R2)Old RTL (R1)Old Netlist (G1)Final Netlist (New DEF)ECO Route/DRV/SIOld DEFP&RManual EditingTest InsertionNew Netlist(G2)ECECDelete/add connections Map to spare gatesDifficult to identify where to fix!Which logic cones are affected?P&RWhat type/many spare cells are available and how can I optimally map new gates to them?Use limited Metal Layers!How can I get the smallest possible change?Create ECO CmdWill this ECO meet timing, is it DRC clean?ORB a c k -e n d EC Or o n t -e n d E C ORepeat process for each ECO。
Nokia 7250 IXR-10 IXR-6 IXR-s 集成路由器说明书
Interconnect routers complement IP edge and core router platforms to deliver enhanced, cost-effective IP network architectures. The 7250 IXR delivers a comprehensive set of IP/MPLS, synchronization and quality of service (QoS) capabilities. Flexible traffic management includes big buffering, per-port queuing, shaping and policing.High-density aggregationThe 7250 IXR is optimized for high-density aggregation, supporting up to 57.6 Tb/s(7250 IXR-10), 28.8 Tb/s (7250 IXR-6) or 1.6 Tb/s (7250 IXR-s) of system capacity, and is equipped with high-performance 100GE (Gigabit Ethernet), 50GE 2, 40GE, 25GE, 10GE and GE interfaces to scale networks to meet evolving traffic demands.Differentiated service supportPer-service, hierarchical queuing features support differentiated QoS, which is ideal for any-Gaggregation and fixed-mobile network convergence. These features also help industrial enterprises attain IT/OT (informational technology/operational technology) convergence by simultaneously carrying both their business and operational traffic.Nokia 7250 IXR-10/IXR-6/IXR-s Interconnect RoutersRelease 20The Nokia 7250 Interconnect Router (IXR) family addresses evolving demands driven by the cloud, 5G and the Internet of Things. The IXR-10, IXR-6 and IXR-s1 routers enable high-scale interconnectivity in data centers and across WANs and aggregation networks in service provider, enterprise and webscale environments.7250 IXR-107250 IXR-s7250 IXR-61 The 7250 IXR-10, IXR-6 and IXR-s are part of the 7250 IXR product family. Additional data sheets are available for other models in this product family.The 7250 IXR10, IXR-6 and IXR-s are referred to collectively as the 7250 IXR throughout this data sheet.2 50GE is a future software deliverable.High availabilityThe 7250 IXR sets the benchmark for high availability. The 7250 IXR-10 and IXR-6 systems support a full suite of 1+1 control, 5+1 fabric,and redundant fan and power configurations.In addition to full hardware redundancy, the robust Nokia Service Router Operating System (SR OS) supports numerous features to maximize network stability, ensuring that IP/MPLS protocols and services run without interruption. These features include innovative nonstop routing, nonstop services and stateful failover. AutomationThe 7250 IXR uses the Nokia SR OS and is managed by the Nokia Network Services Platform (NSP). The Nokia NSP offers a rich set of service management features that automate new service delivery and reduce operating cost.Standards-based software-defined networking (SDN) interfaces enable best-path computation to be offloaded to path computation elements (PCEs) such as the Nokia NSP. The 7250 IXR operates as a path computation client (PCC), collecting and reporting per-link and per-service delay, jitter and loss metrics as well as port utilization levels, for efficient path computation. Software featuresThe 7250 IXR supports, but is not limited to,the following features.Services• Point-to-point Ethernet pseudowires/virtual leased line (VLL)• Ethernet Virtual Private Network (EVPN)–Virtual Private Wire Service (EVPN-VPWS)–Virtual Private LAN Services (EVPN-VPLS):IPv4 and IPv6 support, including VirtualRouter Redundancy Protocol (VRRP)–Multihoming with single active or active/active • Multipoint Ethernet VPN services with VPLS based on Targeted Label Distribution Protocol (T-LDP) and Border Gateway Protocol (BGP)• Routed VPLS with Internet Enhanced Service (IES) or IP-VPN, IPv4 and IPv6• Ingress and egress VLAN manipulation for Layer 2 services• IP VPN (VPRN), Inter-Autonomous System (Inter-AS) Option A, B and C• IPv6 VPN Provider Edge (6VPE)Network protocols• Segment routing–Intermediate System-to-Intermediate System(SR-ISIS) and Open Shortest Path First(SR-OSPF)–Traffic engineering (SR-TE)• MPLS label edge router (LER) and label switching router (LSR) functions–Label Distribution Protocol (LDP)–Resource Reservation Protocol with trafficengineering (RSVP-TE)• BGP - Labeled Unicast (BGP-LU) (IETF RFC 3107) route tunnels• IP routing–Dual-stack Interior Gateway Protocol (IGP)–Multi-topology, multi-instance IntermediateSystem to Intermediate System (IS-IS)–Multi-instance OSPF–Multiprotocol BGP (MP-BGP)–BGP-LU support in edge, area border router(ABR) and autonomous system boundaryrouter (ASBR) roles–Usage-triggered download of BGP labelroutes to Label - Forwarding Information Base(L-FIB)–Accumulated IGP (AIGP) metric for BGP–BGP route-reflector for EVPN and IP-VPNwith VPNv4 and VPNv6 address families (AFs) • Layer 3 Multicast – base routing–Internet Group Management Protocol (IGMP)–Protocol Independent Multicast – Sparse Mode(PIM-SM), Source Specific Multicast (SSM)–Multicast Listener Discovery (MLD)• Layer 3 Multicast - VPRN (7250-IXR-s)–Next-generation multicast VPNs (NG-MVPN)–SSM with multicast LSPv4 (mLDPv4)–IGMP/MLD–IGMP/MLD on Routed VPLS Interface• Layer 2 Multicast–IGMP/MLD snoopingSDN• SR-TE LSPs, RSVP-TE LSPs–PCC initialized, PCC controlled–PCC initialized, PCE computed (7250 IXR-s)–PCC initialized, PCE controlled (7250 IXR-s)• SR-TE LSPs: PCE initialized, PCE controlled(7250 IXR-s)• Topology discovery: BGP-Link State (BGP LS) IPv4 and IPv6• Telemetry: streaming interface, service delay and jitter statisticsLoad balancing and resiliency• Nonstop routing (IXR-10 and IXR-6)• Segment routing topology independent and remote loop-free alternate (TI-LFA and rLFA)• LDP LFA• IEEE 802.3.ad Link Aggregation Group (LAG) and multi-chassis (MC) LAG• Pseudowire and LSP redundancy• IP and MPLS load balancing by equal-cost multipath (ECMP)• VRRP• Configurable polynomial and hash seed shift • Entropy label (IETF RFC 6790)• RSVP-TE Fast Reroute (FRR)• BGP Edge and Core Prefix Independent Convergence (BGP PIC)Platform• Ethernet IEEE 802.1Q (VLAN) and 802.1ad (QinQ) with 9k jumbo frames• Detailed forwarded and discarded countersfor service access points (SAPs) and network interfaces in addition to port-based statistics: per Virtual Output Queue (VoQ) packet and byte counters (7250 IXR-s)• Dynamic Host Configuration Protocol (DHCP) server for IPv4 IES, VPNv4• DHCP relay, IPv4 and IPv6, IES, IP-VPN,EVPN-VPLS• Accounting recordsQoS and traffic management• Hierarchical QoS (7250 IXR-s)–Hierarchical egress schedulers and shapersper forwarding class, SAP, network interfaceor port–Port sub-rate• Intelligent packet classification, including MAC, IPv4, IPv6 match-criteria-based classification • Granular rate enforcement with up to 32 policers per SAP/VLAN, including broadcast, unicast, multicast and unknown policers• Hierarchical policing for aggregate rate enforcement• Strict priority, weighted fair queuing schedulers • Congestion management via weighted random early discard (WRED)• Egress marking or re-markingSystem management• Network Management Protocol (SNMP)• Model-driven (MD) management interfaces–Netconf–MD CLI–Remote Procedure Call (gRPC)• Comprehensive support through Nokia NSPOperations, administration and maintenance • IEEE 802.1ag, ITU-T Y.1731: Ethernet Connectivity Fault Management for both fault detection and performance monitoring, including delay, jitter and loss tests• Ethernet bandwidth notification with egress rate adjustment• IEEE 802.3ah: Ethernet in the First Mile• Bidirectional Forwarding Detection IPv4 and IPv6• Two-Way Active Measurement Protocol (TWAMP), TWAMP Light• A full suite of MPLS OAM tools, including LSP and virtual circuit connectivity verification ping • Service assurance agent• Mirroring with slicing support:–Port–VLAN–Filter output: Media Access Control (MAC),IPv4/IPv6 filters–Local/remote• Port loopback with MAC swap• Configuration rollback• Zero Touch Provisioning (ZTP) capable (7250 IXR-s) Security• Remote Authentication Dial-In User Service (RADIUS), Terminal Access ControllerAccess Control System Plus (TACACS+), and comprehensive control-plane protection capabilities• MAC-, IPv4- and IPv6-based access control lists and criteria-based classifiers• Secure Shell (SSH)Hardware overview7250 IXR-10 and IXR-6 platformsThe 7250 IXR-10 and IXR-6 share common integrated media module (IMM) cards, control processor modules (CPMs) and power supplyunits (PSUs).Each chassis uses an orthogonal direct cross-connect architecture, with IMMs connecting in front and switch fabrics and fans connecting at the rear. The lack of a backplane, midplane or midplane connector system provides a compact chassis design, optimal cooling and easy capacity upgrades. The 7250 IXR supports a 5+1 switch fabric design for full fabric redundancy with graceful degradation. Fans and switch fabrics are separate, ensuring a complete separation of cooling from the dataplane and enabling non-service-impacting fan replacement options. The system uses a complete Faraday Cage design to ensure EMI containment, a critical requirement for platform evolution that will support next-generation application-specific integrated circuits (ASICs).7250 IXR-10 and IXR-6 control plane Control-plane performance is a key requirementin networking. Multicore CPUs with support for symmetric multiprocessing (SMP) provide leading capabilities in task distribution and concurrent processing, leveraging the hardened capabilitiesof the SR OS. This is a capability common to all platforms in the 7250 IXR product series.The 7250 IXR-10/IXR-6 supports dual-redundant CPMs for hot-standby control-plane redundancy and supports a fully distributed control infrastructure with dedicated CPUs per line card. Compared to single monolithic control plane systems, this distributed architecture provides optimized control plane processing without any detrimental impacts to the central CPM during system maintenance, IMM commissioning and heavy data loads. The distributed architecture also improves system security.Power suppliesThe 7250 IXR-10/IXR-6 platforms support 12and 6 PSUs respectively, allowing for full N+M(N is active and M is the number of protecting power supplies) power supply redundancy and full power feed redundancy. In contrast to systems with fewer power supplies, the 7250 IXR provides added headroom for power growth for system enhancements with next-generation ASICs.On the IXR-10/IXR-6, two PSU variants are available: a low-voltage DC PSU (LVDC) and a combined high-voltage DC (HVDC) and AC PSU. The PSUs are fully interchangeable between the chassis variants. The HVDC PSU option enables OPEX and CAPEX savings as a result of the power-supply and infrastructure design.The 7250 IXR-s supports two PSUs with 1+1 redundancy with support for either AC or LVDC power options.Technical specificationsTable 1. 7250 IXR6-10/IXR-6/IXR-s specificationsSystem configuration Dual hot-standby CPMs Dual hot-standby CPMs Single integrated CPM System throughput:Half duplex (HD) IMIXtraffic57.6 Tb/s28.8 Tb/s 1.6 Tb/sSwitch fabric capacity per module: Full duplex (FD) • 5.76 Tb/s• Single-stage fabric with gracefuldegradation• Separate fan tray from switch fabric• 2.88 Tb/s• Single-stage fabric with gracefuldegradation• Separate fan tray from switch fabricIntegratedCard slot throughput:FD per slot3.6 Tb/s 3.6 Tb/s n/aCard slots84n/aService interfaces n/a n/a• 6 x QSFP28/QSFP+100/40GE• 48 x SFP+/SFP 10/1GEControl interfaces Console, management, Synchronous Ethernet (SyncE)/1588, OES, BITS,Bluetooth, USB*, 1PPS, SD slot Console, management, USB, SD slotTiming and synchronization • Built-in Stratum 3E clock• ITU-T Synchronous Ethernet (SyncE)• IEEE 1588v2–Boundary clock (BC), slave clock (SC)–Profiles: IEEE 1588v2 default, ITU-T G.8275.1• Nokia Bell Labs IEEE 1588v2 algorithm• IETF RFC 5905 Network Time Protocol (NTP)• Building Integrated Timing Supply (BITS) ports (T1, E1, 2M) and pulse-persecond (1PPS) timing• Built-in Stratum 3E clock• ITU-T SyncE• ITU-T G.8262.1 eEEC• IEEE 1588v2–BC–Profile: ITU-T G.8275.1• ITU-T G.8273.2 Class B, C**• IETF RFC 5905 NTP• Support for GNSS SFPMemory buffer size Per card (see T able 2)Per card (see T able 2)8 GBRedundant hardware• Dual redundant CPMs• Switch fabric redundancy (5+1)• Power redundancy (M+N)• Fan redundancy (N+1)• Power redundancy (1+1)• Fan redundancy (5+1)Dimensions• Height: 57.78 cm (22.75 in);13 RU• Width: 44.45 cm (17.5 in)• Depth: 81.28 cm (32.0 in)Fits in standard 19-in rack • Height: 31.15 cm (12.25 in);7 RU• Width: 44.45 cm (17.5 in)• Depth: 81.28 cm (32.0 in)Fits in standard 19-in rack• Height: 4.35 cm (1.75 in);1 RU• Width: 43.84 cm (17.26 in)• Depth: 51.5 cm (20.28 in)Fits in standard 19-in rack* Future software deliverable** Class C for noise generation. Future support for RS-FEC.Power• 12 PSUs with N+M redundancy• LVDC (single feed): -40 V DC to-72 V DC• HVDC: 240 V to 400 V• AC: 200 V AC to 240 V AC,50 Hz/60 Hz• Front-bottom mounted • 6 PSUs with N+M redundancy• LVDC (single feed): -40 V DC to-72 V DC• HVDC: 240 V to 400 V• AC: 200 V AC to 240 V AC,50 Hz/60 Hz• Front-bottom mounted• 2 PSUs with 1+1redundancy• LVDC (single feed):-40 V DC/-72 V• AC: 200 V AC to 240 V AC,50 Hz/60 Hz• Rear mountedCooling• 3 trays of 3 ultra-quiet fans• Fan trays separate from switchfabric• Safety electronic breaks on removal• Front-to-back airflow• Fan filter door kit (optional)• 3 trays of 2 ultra-quiet fans• Fan trays separate from switchfabric• Safety electronic breaks on removal• Front-to-back airflow• Fan filter door kit (optional)• 6 trays of 1 ultra-quietfan each• Fan trays separate fromswitch fabric• Safety electronic breakson removal• Front-to-back airflowNormal operatingtemperature range0°C to +40°C (32°F to +104°F) sustainedShipping and storagetemperature-40°C to 70°C (-40°F to 158°F) Normal humidity5% to 95%, non-condensing Note: Throughout this table, n/a = not applicable.Optical breakout solutions available on QSFP28/QSFP+ ports:• 7210 IXR-10, IXR-6: 4 x 10GE and 4 x 25GE• 7210 IXR-s: 4 x 10GETable 2. Nokia 7250 IXR-10 and IXR-6 IMM cards36-port 100GE• 36 x 100GE QSFP28/QSFP+ 100/40GE• MACsec on all ports*• 48 GB packet buffer2-port 100GE + 48-port 10GE • 2 x 100GE QSFP28/QSFP+ 100/40GE • 48 x SFP+/SFP 10/1GE• MACsec on all ports*• 8 GB packet bufferTable 3. Platform density7250 IXR-s• 288 x 100/40GE• 384 x 10/1 GE + 16 x 100/40GE • 144 x 100/40GE• 192 x 10/1GE + 8 x 100/40GE• 6 x 100/40GE•48 x 10/1GE* Future software deliverableStandards compliance3Environmental• ATIS-0600015.03• ATT-TP-76200• ETSI EN 300 019-2-1; Storage Tests, (Class 1.2)• ETSI EN 300 019-2-2; Transportation Tests,(Class 2.3)• ETSI EN 300 019-2-3; Operational Tests, (Class 3.2)• ETSI EN 300 753 Acoustic Noise (Class 3.2)• GR-63-CORE• GR-295-CORE• GR-3160-CORE• VZ.TPR.9205• VZ.TPR.9203 (CO)Safety• AS/NZS 60950.1• CSA/UL 62368-1 NRTL• EN 62368-1 CE Mark• IEC 60529 IP20• IEC/EN 60825-1• IEC/EN 60825-2• IEC 62368-1 CB Scheme Electromagnetic compatibility• AS/NZS CISPR 32 (Class A)• ATIS-600315.01.2015• BSMI CNS13438 Class A• BT GS-7• EN 300 386• EN 55024• EN 55032 (Class A)• ES 201 468• ETSI EN 300 132-3-1• ETSI EN 300 132-2 (LVDC)• ETSI EN 300 132-3 (AC)• FCC Part 15 (Class A)• GR-1089-CORE• ICES-003 (Class A)• IEC 61000-3-2• IEC 61000-3-3• IEC CISPR 24• IEC CISPR 32 (Class A)• IEC 61000-6-2• IEC 61000-6-4• IEC/EN 61000-4-2 ESD• IEC/EN 61000-4-3 Radiated Immunity• IEC/EN 61000-4-4 EFT• IEC/EN 61000-4-5 Surge• IEC/EN 61000-4-6 Conducted Immunity • IEC/EN 61000-4-11 Voltage Interruptions • ITU-T L.1200• KCC Korea-Emissions & Immunity(in accordance with KN32/35)• VCCI (Class A)Directives, regional approvals and certifications • DIRECTIVE 2011/65/EU RoHS• DIRECTIVE 2012/19/EU WEEE• DIRECTIVE 2014/30/EU EMC• DIRECTIVE 2014/35/EU LVD• MEF CE 3.0 compliant• NEBS Level 3–Australia: RCM Mark–China RoHS: CRoHS–Europe: CE Mark–Japan: VCCI Mark–South Korea: KC Mark–Taiwan: BSMI Mark3 System design intent is according to the listed standards. Refer to product documentation for detailed compliance status.7Data sheetAbout NokiaWe create the technology to connect the world. Powered by the research and innovation of Nokia Bell Labs, we serve communications service providers, governments, large enterprises and consumers, with the industry’s most complete, end-to-end portfolio of products, services and licensing.From the enabling infrastructure for 5G and the Internet of Things, to emerging applications in digital health, we are shaping the future of technology to transformthe human experience. Nokia operates a policy of ongoing development and has made all reasonable efforts to ensure that the content of this document is adequate and free of material errors and omissions. Nokia assumes no responsibility for any inaccuracies in this document and reserves the right to change, modify, transfer, or otherwise revise this publication without notice.Nokia is a registered trademark of Nokia Corporation. Other product and company names mentioned herein may be trademarks or trade names of their respective owners. © 2020 NokiaNokia OyjKaraportti 3FI-02610 Espoo, Finland。
ROHM BD71850MWV 应用说明书
12
UVLO Is it possible to modify the ULVO value? No, it is the fixed value.
© 2019 ROHM Co., Ltd.
No. 62AN087E Rev.004
2/4
Mar.2020
BD71850MWV FAQ
Application Note
will flow if 3.3V is directly supplied.
This leakage current can be suppressed to add the series resistor
to BUCK6_FB line.
The maximum value is up to 60kohm.
“shutdown” which will call several routines to store content and
finally power down the system.
One possibility for a power-down is to de-assert the
PMIC_ON_REQ line. This will cause the PMIC to power down the
Nano Reference Manual.
2. Terminologies
Term DCR DDR I2C LDO PMIC RTC SoC UVLO VR
Definition DC Resistance Double Data Rate Inter-Integrated Circuit Low Dropout Power Management Integrate Circuit Real-Time Clock System-on-Chip Under Voltage Lock Out Voltage Regulator
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MPLAB Code Configurator SMPS Library说明书
MPLAB® Code Configurator SMPS Library Release NotesWhat is the MPLAB Code Configurator SMPS LibraryThe MPLAB Code Configurator SMPS Library allows quick and easy configuration, and code generation for 8-bit PIC SMPS applications.System Requirements1.MPLAB® X IDE v5.40 or later2.MCC v4.0.1 or later3.MCC Core v5.0.0 or later4.MCC PIC10 / PIC12 / PIC16 / PIC18 MCU Library 1.81.6 or later5.XC8 compiler v2.20 or laterRelated Hardware and Documentation SupportMPLAB Code Configurator Switch Mode Power Supply Library User's GuideCIP Hybrid Power Starter KitInstalling the MPLAB Code Configurator SMPS Library1.To install the MPLAB® Code Configurator Plugin:1.1.In the MPLAB X IDE, select Plugins from the Tools menu1.2.Select the Available Plugins tab1.3.Check the box for the MPLAB® Code Configurator v4, and click on Install2.To install the SMPS Library:2.1.In the MPLAB X IDE, select Options from the Tools menu2.2.Select the MPLAB® Code Configurator 4.x tab from Plugins option2.3.Click on Install Library/Open Library Folder2.4.Add SMPSPowerLibrary_vX.X.X.jar2.5.Restart MPLAB X IDE (optional)3.To load different SMPS Library version:3.1.Open MPLAB® Code Configurator v4 from the Tools menu3.2.Expand the Versions tab under Software/SMPS Power Library (loaded version is indicated by thegreen mark)3.3.Right click on the desired version of the library and select Mark for load3.4.Click on the Load Selected Libraries button to load the libraryWhat’s New•v1.4.0–Compatibility update with MCC Plugin v4.0.1 and MCC Core v5.0.0–Various output pin fixes•v1.3.0–Added CIP Hybrid Starter Kit (PCMC/VMC) Demo modules–Added a CIP SEPIC LED Driver Demo module•v1.2.1–Removed local peripheral modules–Added dependency to the MCC 8bit PIC Library•v1.2.0–Added support for PIC16(L)F176x devices–Updated the Compensator Block module with an override setting–Updated the Fault Block module with CIN- pin options–Updated the PCMC Control Mode module with LED dimming options –Added the Pulse Modulator Block module–Added the SEPIC_LED Topology module–Added up to four instances of each SMPS Library module•v1.0.0–Initial release with support for a Synchronous Buck Topology moduleSupported Families•8-bit Families–PIC16(L)F177x–PIC16(L)F176xTable of ContentsWhat is the MPLAB Code Configurator SMPS Library (1)1.System Requirements (1)2.Related Hardware and Documentation Support (1)3.Installing the MPLAB Code Configurator SMPS Library (1)4.What’s New (1)5.Supported Families (2)The Microchip Website (4)Product Change Notification Service (4)Customer Support (4)Microchip Devices Code Protection Feature (4)Legal Notice (5)Trademarks (5)Quality Management System (6)Worldwide Sales and Service (7)The Microchip WebsiteMicrochip provides online support via our website at /. This website is used to make files and information easily available to customers. Some of the content available includes:•Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software•General Technical Support – Frequently Asked Questions (FAQs), technical support requests, online discussion groups, Microchip design partner program member listing•Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representativesProduct Change Notification ServiceMicrochip’s product change notification service helps keep customers current on Microchip products. Subscribers will receive email notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest.To register, go to /pcn and follow the registration instructions.Customer SupportUsers of Microchip products can receive assistance through several channels:•Distributor or Representative•Local Sales Office•Embedded Solutions Engineer (ESE)•Technical SupportCustomers should contact their distributor, representative or ESE for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in this document.Technical support is available through the website at: /supportMicrochip Devices Code Protection FeatureNote the following details of the code protection feature on Microchip devices:•Microchip products meet the specifications contained in their particular Microchip Data Sheet.•Microchip believes that its family of products is secure when used in the intended manner and under normal conditions.•There are dishonest and possibly illegal methods being used in attempts to breach the code protection features of the Microchip devices. We believe that these methods require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Attempts to breach these codeprotection features, most likely, cannot be accomplished without violating Microchip’s intellectual property rights.•Microchip is willing to work with any customer who is concerned about the integrity of its code.•Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not mean that we are guaranteeing the product is “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products.Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act.If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.Legal NoticeInformation contained in this publication is provided for the sole purpose of designing with and using Microchip products. Information regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications.THIS INFORMATION IS PROVIDED BY MICROCHIP “AS IS”. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE OR WARRANTIES RELATED TO ITS CONDITION, QUALITY, OR PERFORMANCE.IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE INFORMATION OR ITS USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THE INFORMATION. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated.TrademarksThe Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A.Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, , Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, , PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial QuadI/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries.GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries.All other trademarks mentioned herein are property of their respective companies.© 2020, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.ISBN:Quality Management SystemFor information regarding Microchip’s Quality Management Systems, please visit /quality.Worldwide Sales and Service。
MORNSUN LS08-13BxxSS系列AC DC电源说明书
8W,DIY AC/DC converterRoHSFEATURES●Ultra-wide 85-305VAC and 100-430VDC input voltage range ●Accepts AC or DC input (dual-use of same terminal)●Operating ambient temperature range:-40℃~+85℃●Multi-application available,flexible layout ●High power density,high reliability●Low power consumption,green power●Output short circuit,over-current protection●Designed to meet IEC/EN/UL62368safety standards (Pending)●Designed to meet IEC/EN/UL60335safety standardsLS08-13BxxSS series is one of Mornsun’s highly efficient green power AC-DC Converter series.They feature ultra-wide wide input rangeaccepting either AC or DC voltage,high efficiency,low power consumption and CLASS II reinforced insulation.All models are particularly suitable for industrial control,electric power,instrumentation and smart home applications which don’t have high requirement for dimension.A variety of EMC external circuits meet the needs of multiple industries.Input SpecificationsItemOperating Conditions Min.Typ.Max.Unit Input Voltage Range AC input 85--305V AC DC input100--430VDC Input Frequency 47--63HzInput Current 115V AC ----0.3A 277V AC ----0.15Inrush Current115V AC --15--277V AC--30--Recommended External Input Fuse 1A,slow-blow,requiredHot PlugUnavailableOutput SpecificationsItemOperating Conditions Min.Typ.Max.UnitOutput Voltage Accuracy 0%-100%load 3.3V output --±1.5±3%Other output--±1±2Line Regulation Rated load --±0.5±1Load Regulation 0%-100%load--±1±1.5Ripple &Noise *20MHz bandwidth (peak-to-peak value)--80150mV Temperature Coefficient --±0.02--%/°C Short Circuit Protection Hiccup,continuous,self-recoveryOver-current Protection ≥110%Io,self-recoveryMinimum Load----%Note:*The “parallel cable”method is used for ripple and noise test,please refer to AC-DC Converter Application Notes for specific information.Selection GuideCertificationPart No.Output PowerNominal Output Voltage and Current (Vo/Io)Efficiency at 230V AC(%)Typ.Capacitive Load(µF)Max.CE/UL/CB (Pending)LS08-13B03SS 5.28W3.3V/1600mA 701500LS08-13B05SS8W 5V/1600mA 741500LS08-13B09SS 9V/880mA 751000LS08-13B12SS 12V/670mA 76680LS08-13B15SS 15V/530mV 77470LS08-13B24SS24V/330mA79330General SpecificationsItem Operating Conditions Min.Typ.Max.UnitIsolation Test Input-output Electric Strength Test for1min.,(leakage current＜5mA)3000----VACOperating Temperature-40--+85℃Storage Temperature-40--+105Storage Humidity----95%RHPower Derating -40℃~-25℃ 2.67----%/℃+55℃~+85℃ 2.5----85V AC-100VAC1----277V AC-305V AC0.54----Safety Standard IEC/EN/UL62368,IEC/EN/UL60335 Safety Certification IEC/EN/UL62368(Pending) Safety CLASS CLASS IIMTBF MIL-HDBK-217F@25°C>300,000h Mechanical SpecificationsCase Material44.50x24.00x15.00mmWeight11g(Typ.)Cooling method Free air convectionElectromagnetic Compatibility(EMC)Emissions CECISPR32/EN55032CLASS A(Recommended circuit1,4)CISPR32/EN55032CLASS B(Recommended circuit2,3) RECISPR32/EN55032CLASS A(Recommended circuit1,4)CISPR32/EN55032CLASS B(Recommended circuit2,3)Immunity ESD IEC/EN61000-4-2Contact±6KV Perf.Criteria B RS IEC/EN61000-4-310V/m perf.Criteria AEFTIEC/EN61000-4-4±2KV(Recommended circuit1,2)perf.Criteria BIEC/EN61000-4-4±4KV(Recommended circuit3,4)perf.Criteria B SurgeIEC/EN61000-4-5line to line±1KV(Recommended circuit1,2)perf.Criteria BIEC/EN61000-4-5line to line±2KV(Recommended circuit3,4)IEC/EN61000-4-5line to line±4KV(Recommended circuit4)perf.Criteria B CS IEC/EN61000-4-610Vr.m.s perf.Criteria A Voltage dips,shortinterruptions and voltagevariations immunityIEC/EN61000-4-110%,70%perf.Criteria BProduct Characteristic CurveNote:①With an AC input between85-100VAC/277-305VAC and a DC input between100-120VDC/390-430VDC,the output power must be derated as per temperature derating curves;②This product is suitable for applications using natural air cooling;for applications in closed environment please consult factory or one of our FAE.Additional Circuits Design ReferenceLS series additional circuits design referenceLS08series additional components selection guidePart No.FUSE(required)C1required)C2(required)L1(required)C3（required ）C4CY1（required ）LS08-13B03SS 1A/300V22µF/450V470µF/16V(solid-state capacitor) 4.7µH 150µF/35V 0.1µF/50V1.0nF/400V ACLS08-13B05SS LS08-13B09SS 220µF/16V(solid-state capacitor)100µF/35V LS08-13B12SS LS08-13B15SS 470uF/35V 47µF/35VLS08-13B24SS220uF/35VNote:1.C1:input capacitors,C2:output storage capacitors,they must be connected externally.2.We recommend using an electrolytic capacitor with high frequency and low ESR rating for C3(refer to manufacture’s datasheet).Combined with C2,L1,they form a pi-type filter circuit.Choose a capacitor voltage rating with at least 20%margin,in other words not exceeding 80%.C4is a ceramic capacitor,used for filtering high frequency noise.A suppressor diode (TVS)is a recommended to protect the application in case of a converter failure and specification should be 1.2times of the output voltage.Immunity design circuits for referenceEmissions design circuits for referenceCLASS ⅢCLASS ⅣCLASS ACLASS BEnvironmental Application EMC SolutionLS series environmental application EMC solution selection tableRecommendedcircuit Application environmental Typical industryInput voltagerangeEnvironment temperature Emissions Immunity 1Basic applicationNone85～305V AC -40℃~+85℃CLASS A CLASS Ⅲ2Indoor civil environment Smart home/Home appliances(2Y)-25℃~+55℃CLASS BCLASS ⅢIndoor general environment Intelligent building/Intelligentagriculture 3Indoor industrial environment Manufacturing workshop -25℃~+55℃CLASS B CLASS Ⅳ4Outdoor general environmentITS/Video monitoring/Charging point/Communication/Securityand protection-40℃~+85℃CLASS ACLASS ⅣOutdoor harsh environmentOn-line power meter Communication base station-40℃~+85℃CLASS A>CLASS ⅣSurge:line to ground ±4KV EFT:CLASS ⅣElectromagnetic Compatibility Solution--Recommended Circuit1.Recommended circuit 1——Basic applicationrecommended circuit 1Application environmentalAmbient temperature rangeImmunity CLASSEmissions CLASSBasic application-40℃~+85℃CLASS ⅢCLASS AComponentRecommended valueR112Ω/3W LDM4.7mH2.Recommended circuit 2——Indoor civil /Universal system recommended circuits for general environmentRecommended circuit 2Application environmentalAmbient temperature rangeImmunity CLASSEmissions CLASS Indoor civil /general -25℃~+55℃CLASS ⅢCLASS BComponentRecommended valueR112Ω/3W CY1(CY2) 1.0nF/400V ACLCM 3.5mH LDM 0.33mH CX0.1µF/310VAC FUSE (required)1A/300V ,slow-blowNote:In the home appliance application environment,the two Y capacitors of the primary and secondary need to be externally connected (CY1/CY2,value at 2.2nF/400VAC),which can meet the EN60335certification.In other industries,only one Y capacitor is needed.3.Recommended circuit 3——Universal system recommended circuits for indoor industrial environmentRecommended circuit 3Application environmental Ambienttemperature rangeImmunity CLASSEmissions CLASSIndoor industrial-25℃~+55℃CLASS ⅣCLASS BComponentRecommended valueMOV S14K350C1450V/22uF CY1 2.2nF/400V AC CX 0.1µF/310V ACLCM 3.5mH LDM 0.33mH R112Ω/3WFUSE (required)2A/300V ,slow-blow4.Recommended circuit 4——Universal system recommended circuits for outdoor general/harsh environmentRecommended circuit 4Application environmental Ambienttemperature rangeImmunity CLASSEmissions CLASSOutdoor general environment-40℃~+85℃CLASS ⅣCLASS AComponentRecommended valueMOV S14K350C1450V/22uF LDM 4.7mH R112Ω/3WFUSE (required)2A/300V ,slow-blowApplication environmental Ambient temperaturerangeImmunity CLASS EmissionsCLASSOutdoor harsh environment -40℃~+85℃>CLASSⅣSurge:line to ground±4KVEFT:CLASSⅣCLASS AComponent Recommended valueMOV S20K350C1450V/33uF(Surge protection priority)LDM 4.7mHR133Ω/5WFUSE(required) 6.3A/300V,slow-blow5.For additional information please refer to application notes on . LS08-13BxxSS Dimensions and Recommended LayoutNote:1.For additional information on Product Packaging please refer to .Packaging bag number:58220032;2.External electrolytic capacitors are required to modules,more details refer to typical applications;3.This part is open frame,at least6.4mm safety distance between the primary and secondary external components of the module isneeded to meet the safety requirement;4.Unless otherwise specified,parameters in this datasheet were measured under the conditions of Ta=25℃,humidity<75%,nominal inputvoltage(115V and230V)and rated output load;5.In order to improve the efficiency at light load,there will be audible noise generated,but it does not affect product performance andreliability;6.Module required dispensing fixed after assembled;7.All index testing methods in this datasheet are based on our company corporate standards;8.We can provide product customization service,please contact our technicians directly for specific information;9.Products are related to laws and regulations:see"Features"and"EMC";10.Our products shall be classified according to ISO14001and related environmental laws and regulations,and shall be handled byqualified units.Mornsun Guangzhou Science&Technology Co.,Ltd.Address:No.5,Kehui St.1,Kehui Development Center,Science Ave.,Guangzhou Science City,Huangpu District,Guangzhou,P.R.China Tel:86-20-38601850Fax:86-20-38601272E-mail:***************。
Quick Reference Guide
Agilent supplies for Agilent instrumentsAgilent is committed to optimizing your laboratory’s productivity. Thisreference guide shows the most commonly ordered supplies and parts for the Agilent 240/280 and 50/55 series AA systems. Keep this list so you can quickly find the supplies you need and minimize instrument downtime.Agilent Atomic Absorption SuppliesDeuterium Background Corrector Deuterium UV background correction lamp, for AA instruments G8431-80000Burner, nitrous oxide-acetylene, Mark 7Spare probesSPS 4 probe, 0.8 mm id, green marker, inert, FEP-sleeved (standard probe for flame AA)G8410-80102* Includes:Replacement electrodes (2 pairs), spare shroud, omega platform tubes (5/pk of 10 tubes), 100 μL syringe, kit of capillary assemblies (5/pk) plastic beakers (5/pk), 2 mL polyethylene sample vials (2 pk of 1,000 vials)Agilent offers a comprehensive range of other single and multi-element standards, ionization buffers, metallo-organic and biodiesel standards, solvents, and environmental standards for atomic spectroscopy. With the assurance of NIST traceability, Agilent’s Certified Reference Materials and standard mixes offer accurate, reliable calibrations at great value.To place your order:/chem/wheretobuyThis information is subject to change without notice.© Agilent Technologies, Inc. 2019 Printed in the USA, May 1, 2019 5990-9476ENHollow Cathode LampsAgilent lamps are manufactured in ISO 9001 certified environment and use proven processing steps to guarantee quality and reliability.We offer a full range of coded or uncoded lamps with either single or multi-element combinations. This includes High Intensity UltrAA lamps, whichincrease sensitivity by up to 40%, providing lower detection limits for the most demanding flame, furnace, and vapor AA applications.For more information, visit us online at:/chem/hollow-cathode-lampsAgilent spectroscopy supplies - to help you get the results you needFor greater confidence in your spectroscopy results, optimize your total system with quality Agilent supplies.Our of supplies, kits, and accessories are designed, manufactured, and tested to rigorous Agilent specifications, under a quality system registered to ISO 9001.Why risk compromising your analytical results with anything less than genuine Agilent supplies?For a complete list of Agilent atomic spectroscopy supplies, including hollow cathode lamps and supplies for AA, ICP-OES, ICP-MS and MP-AES products, visit us online at: /chem/atomic。
Maxim DS2710 单节 NiMH 充电器 IC 评估套件 用户手册说明书
General DescriptionThe DS2710 evaluation kit (EV kit) demonstrates opera-tion of the DS2710 single-cell NiMH charger IC. The kit includes an assembled and tested PCB with a AA-size battery socket for easy connection to USB or other power source and a CD with documentation for the kit and device. The DS2710 EV kit fully charges a single NiMH chemistry cell and then provides a maintenance charge current to counteract self-discharging. Safety features include overvoltage protection, thermal protec-tion, charge timeout, and alkaline-cell rejection by impedance test. An L ED output displays the charging state.Features♦Convenient Power Source and Load Connections♦AA-Size NiMH Cell Socket ♦LED Outputs Charging Status ♦Compact PCB Layout ♦Fully AssembledEvaluates: DS2710DS2710 Evaluation Kit________________________________________________________________Maxim Integrated Products 119-4837; Rev 1; 8/09For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,or visit Maxim’s website at .Ordering Information+Denotes lead(Pb) free and RoHS compliant.E v a l u a t e s : D S 2710ConnectionsConnect a AA-size NiMH cell between the B- and B+tabs, observing proper polarity. Make sure the battery contacts the exposed thermistor (103AT-2 provided with the kit board). To charge the cell, connect a 5V charge source capable of supplying at least 2.5W at 4V to 5.5V between the CS pad and GND pad or connect directly to a powered USB port through the USB-B female connector. An optional load to the cell should be connected between the L OAD+ and L OAD- pads.The sense resistor is included in the discharge path through the load so the cell can be charged while under load. Figure 1 shows connections to the DS2710EV kit board.OperationRefer to the DS2710 IC data sheet for a full description of charge operation. After applying power to theDS2710 EV kit board, the DS2710 waits in presence state until a cell is inserted into the AA socket. When the DS2710 determines a cell has been inserted,charging begins as shown in Table 1.Time, temperature, overvoltage, or impedance faults can cause the DS2710 to terminate charge early and enter fault state. Refer to the DS2710 IC data sheet for a full description of possible faults while charging.While in fault state, the status LED blinks at a 4Hz rate.The DS2710 exits fault state and returns to presence state when the cell is removed from the socket.DS2710 Evaluation Kit 2_______________________________________________________________________________________Figure 1. Connections to DS2710 EV Kit Evaluation BoardEvaluates: DS2710DS2710 Evaluation Kit_______________________________________________________________________________________3Figure 2. NiMH Charge CycleE v a l u a t e s : D S 2710DS2710 Evaluation Kit 4_______________________________________________________________________________________Figure 3 shows the switching waveform for the DS2710 while actively charging the cell. The CS out-put pin toggles rail-to-rail to regulate the voltage across the sense resistor to 0.113V. This exampleuses a 15µH coil to create a switching frequency of approximately 110kHz to 150kHz during charge,depending on supply voltage.Figure 3. Switching WaveformDescription of Hardware Figure 4 shows the DS2710 EV kit schematic.Inductor Selection Proper selection of the output inductor achieves a tar-get output ripple current for a given set of input and output voltages and output current load. Trade-offs between package size and losses that affect overall efficiency are other considerations for selecting a par-ticular inductor model. The inductor selected for the DS2710 EV kit is SISCDRH74M-150RC from Elec & Eltek Magnetics. The inductance value is 15µH, which results in a switching frequency of approximately 120kHz for this evaluation board.PCB Layout The DS2710 EV kit is built on a two-layer board with 1oz copper. The artwork for the two component and two signal layers is shown in Figure 5. The loop formed by C2, D2, and Q1 is the most crucial part of the PCB lay-out. The loop area is kept as small as possible to mini-mize switching noise.An additional battery tab land pattern is included to allow the AA-size battery tabs to be replaced with AAA-size battery tabs if desired.Adjusting ChargingCharacteristicsCharge-Rate Adjustment The charge rate is determined by the external sense resistor connected between the VN1 and VN0 pins (R9). The DS2710 regulates the charge current to main-tain a voltage drop of 113mV typical across the sense resistor during fast-charge. The charge rate can there-fore be selected by:R9 = 113mV/Desired Fast-Charge CurrentThe default evaluation board sense resistor value is0.100Ω, giving a charge rate of approximately 1.13A during fast-charge. Note that the limiting factor for max-imum charge current on the DS2710 EV kit board is the15µH coil, which is rated to 1.4A maximum sustained current.Charge Time and Top-Off Time Adjustment Charge time and top-off time are controlled by the external resistor from the TMR pin to VSS (R7). Resistors can be selected to support fast-charge time-out periods of 0.5hr to 5hr and top-off charge timeout periods of 0.25hr to 2.5hr. The programmed chargetime approximately follows the equation:t = 1.5 x R TMR(Ω)/1000 (time in minutes)The default evaluation board value for R7 is 100kΩ, giv-ing a charge timeout of approximately 150min.Impedance Test-Threshold AdjustmentThe charge rate must be determined before the imped-ance threshold can be set. The resistor from the CTESTpin to VSS (R8) sets the voltage-level threshold used to prohibit charging of non-NiMH cells using the following formula:Impedance Threshold (mΩ) =(8000/(R CTEST(Ω) x Charge Rate (A))The default evaluation board value for R8 is 47kΩ,which sets the impedance threshold at approximately150mΩat a 1.13A charge rate. The resistance of thecell tabs must be considered when setting the imped-ance threshold level.Evaluates: DS2710 DS2710 Evaluation Kit_______________________________________________________________________________________5E v a l u a t e s : D S 2710DS2710 Evaluation Kit6_______________________________________________________________________________________Figure 4. DS2710 EV Kit SchematicEvaluates: DS2710DS2710 Evaluation Kit_______________________________________________________________________________________7Figure 5. DS2710 EV Kit PCB LayoutE v a l u a t e s : D S 2710DS2710 Evaluation KitMaxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.8_____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600©2009 Maxim Integrated ProductsMaxim is a registered trademark of Maxim Integrated Products, Inc.。
MCS-2110 CS-2110系列芯片控制器产品说明书
U O n/Off orProportional Control UC onvenient Receptacles for Input andOutput Connections U C ompact Benchtop Design U 15 A Maximum Output UJ , K Thermocouple or RTD Input U O n/Off Power SwitchThe MCS-2110 and CS-2110 seriesbenchtop controllers are ideal for laboratory use and applications requiring portable temperature control. Pre-wired input andoutput receptacles at the back of the case enable quick and easyconnections to power, thermocouple or RTD input and power output.Thermocouple models use universal female connector to accept either a miniature or standard male connector. RTD models use a 3-prong female connector to accept an OTP-U-M type connector. A 120 Vac, 15 A maximum output receptacle can be used to control heaters or other devices up to 1800 watts. TheMCS-2110 and CS-2110controllers operate in either on/off or proportional control modes, selectable by a simple front panel adjustment.Control ModesThe CN2110 provides precise, solid state proportion control with automatic reset (PI) that will control most heating applications. On/off control may be selected forapplications where maximum output life (load switching) is needed.All models operate on 120 Vac, 15 A and include a 1.5 m (5') power cord.MCS-2110 SeriesBenchtop Temperature ControllersMCS-2110J-R shownsmaller than actual size.Ordering Examples: MCS-2110J-R , benchtop controller, single 15 A relay output, Type J thermocouple input, -73 to 760°C (-100 to 1400°F) range.OCW-3, OMEGACARE SM extends standard 1-year warranty to a total of 4 years.SpecificationsControl Modes: On/off, PI-proportional with integralControl AdjustmentsProportional Band: sensor range Automatic Reset:0.0 to 99.9 repeats/minuteCycle Time: 0.1 to 60.0 seconds On/Off Deadband: 1° to 100°F or °C Setpoint Upper Limit: Sensor range °F or °C Setpoint Lower Limit: Sensor range °F or °C Output Limit: 0 to 100%Alarm Adjustments:Type: Absolute high or lowSetpoint: Sensor range °F or °CAlarm Dead Band: 0° to 100°F or °C Control/Alarm Outputs Relay: Form “A”, 120 Vacresistive loads at 30 seconds, cycle time; 15 A, 500,000 operations; 15 A, 1 million operations; 5 A, 5 million operationsSolid State Relay: Up to 10 A at 40°C Sensor Input: Switch selectable, J, K thermocouple or RTDInput Update Rate: 4 samples/s Readout Stability:J and K Thermocouple: ±1°F/10°F change in ambient temperature RTD: ±0.5 per 10°F change in ambient temperatureOpen Sensor and Out-of-Range Conditions: Displays “SENS”; control output 0%Instrument Power: 120 Vac <10 Va Operating Environment: 0° to 65°C (32°to 150°F)Enclosure Material: High-temperature ABS plastic rated for 0° to 175°F Front Panel: NEMA 4X construction Influence of Line Voltage Variation: ±0.1% of sensor span per 10% change in nominal line voltage Noise Rejection:Common Mode Noise: <2°F with 230 Vac, 60 Hz applied from sensor input to groundSeries Mode Noise: <2°F with 100 mV, peak-to-peak series mode noiseRFI: Typically <0.5% of sensor span at distance of 1 m (3.1’) from a transmitter of 4 W at 464 MHz Sensor Leadwire Effect:RTD: ±0.1% of sensor span per 20Ω balanced leadwire resistanceThe UPJ-K-F universal connector accepts eitherRear ViewMC OutputAC powerOMEGACARE SM extended warranty program isavailable for models shown on this page. Ask your sales representative for full details when placing an order. OMEGACARE SM covers parts, labor and equivalent loaners.。
MORNSUN A05_XT-1WR3 电源说明书
1W,Fixed input voltage,isolated &unregulated dual outputPatent Protection RoHSFEATURES●Continuous short-circuit protection ●No-load input current as low as 5mA●Operating temperature range:-40℃to +105℃●High efficiency up to 83%●Compact SMD package ●Isolation voltage:1.5K VDC ●International standard pin-out●Meets UL62368,EN62368standards （Pending ）A05_XT-1WR3series are specially designed for applications where an isolated voltage is required in a distributed power supply system.They are suitable for:pure digital circuits,low frequency analog circuits,relay-driven circuits and data switching circuits.Selection GuideCertificationPart No.Input Voltage (VDC)OutputEfficiency (%,Min./Typ.)@Full Load Max.CapacitiveLoad(µF)*Nominal (Range)Output Voltage(VDC)Output Current (mA)(Max./Min.)UL/CE (Pending)A0505XT-1WR35(4.5-5.5)±5±100/±1078/821200A0509XT-1WR3±9±56/±679/83470A0512XT-1WR3±12±42/±579/83220A0515XT-1WR3±15±34/±479/83220Note:*The capacitive loads of positive and negative outputs are identical.Input SpecificationsItemOperating ConditionsMin.Typ.Max.Unit Input Current(full load /no-load)5VDC input5VDC output--244/5257/10mA 9VDC/12VDC output --241/12254/2015VDC output--241/18254/30Reflected Ripple Current*--15--mA Surge Voltage (1sec.max.)5VDC input-0.7--9VDCInput Filter Filter capacitor Hot PlugUnavailableNote:*Reflected ripple current testing method please see DC-DC Converter Application Notes for specific operation.Output SpecificationsItemOperating ConditionsMin.Typ.Max.Unit Output Voltage Accuracy See tolerance envelope curve(Fig.1)Line RegulationInput voltage change:±1%---- 1.2%/%Load Regulation10%-100%load5VDC output--1015%9VDC output --81012VDC output --71015VDC output--610Ripple &Noise *20MHz bandwidth --3075mVp-p Temperature Coefficient Full load--±0.02--%/℃Short Circuit ProtectionContinuous,self-recoveryNote:*Ripple and noise are measured by “parallel cable”method,please see DC-DC Converter Application Notes for specific operation;General SpecificationsItemOperating ConditionsMin.Typ.Max.Unit Isolation Voltage Input-output,with the test time of 1minute and the leak current lower than 1mA1500----VDC Isolation Resistance Input-output,isolation voltage 500VDC 1000----M ΩIsolation Capacitance Input-output,100KHz/0.1V--20--pFOperating Temperature Derating when operating temperature up to 100℃,(see Fig.2)-40--105℃Storage Temperature -55--125Casing Temperature Rise Ta=25℃--15--Pin Welding Resistance Temperature Welding spot is 1.5mm away from the casing,10seconds ----300Storage HumidityNon-condensing ----95%RH Reflow Soldering Temperature*Peak temp.≤245℃,maximum duration time ≤60s at 217℃.Switching Frequency Full load,nominal input voltage --270--KHz MTBFMIL-HDBK-217F@25℃3500----K hoursMoisture Sensitivity Level (MSL)IPC/JEDEC J-STD-020D.1Level 2Note:*For actual application,please refer to IPC/JEDEC J-STD-020D.1.Physical SpecificationsCasing Material Black flame-retardant and heat-resistant plastic(UL94V-0)Dimensions 15.24*11.40*7.25mm Weight1.4g (Typ.)Cooling MethodFree air convectionEMC SpecificationsEMI CE CISPR32/EN55032CLASS B (see Fig.5for recommended circuit)RE CISPR32/EN55032CLASS B (see Fig.5for recommended circuit)EMSESDIEC/EN61000-4-2Air ±8kV ,Contact ±4kVperf.Criteria BProduct Characteristic Curve-10%-5%0+5%+10%+15%T y p .M i n .M a x .Output Current Percent (Nominal Input Voltage)O u t p u t V o l t a g e A c c u r a c yTolerance Envelope CurveFig.112080O u t p u t P o w e r P e r c e n t (%)Ambient Temp.()℃Safe Ope rating AreaFig.2Design ReferenceIf it is required to further reduce input and output ripple,a filter capacitor may be connected to the input and output terminals,see Fig.3.Moreover,choosing a suitable filter capacitor is very important,start-up problems may be caused if the capacitance is too large.Under the condition of safe and reliable operation,the recommended capacitive load values are shown in Table 1.The simplest device for output voltage regulation,over-voltage and over-current protection is a linear voltage regulator with overheat protection that is connected to the input or output end in series (see Fig.4).Vin +Vo 0V DCCinDC CoutCout -VoVin 0V +Vo DC DC-VoREGREGREGFig.4Recommended capacitive load value table (Table 1)Vin(VDC)Cin(µF)Vo (VDC)Cout(µF)54.7±54.7±9 2.2±121±1512.EMC solution-recommended circuitFig.5EMC recommended circuit value table (Table 2)Input voltage 5VDCOutput voltage(VDC)5/912/15EMIC1/C24.7µF /25V4.7µF /25VCY --1nF/2KVDCHEC C1206X102K202T JOHANSON 202R18W102KV4E C3Refer to the Cout in table 1LDM6.8µH 6.8µHNote:In the case of actual use,the requirements for EMI are high,it is subject to CY.3.For more information please find DC-DC converter application notes on Dimensions and Recommended LayoutNotes:1.Packing information please refer to Product Packing Information which can be downloaded from .TubePacking bag number:58210023,Roll Packing bag number:58210034;2.If the product is not operated within the required load range,the product performance cannot be guaranteed to comply with allparameters in the datasheet;3.The maximum capacitive load offered were tested at input voltage range and full load;4.Unless otherwise specified,parameters in this datasheet were measured under the conditions of Ta=25℃,humidity<75%RH with nominalinput voltage and rated output load;5.All index testing methods in this datasheet are based on our Company’s corporate standards;6.We can provide product customization service,please contact our technicians directly for specific information;7.Products are related to laws and regulations:see"Features"and"EMC";8.Our products shall be classified according to ISO14001and related environmental laws and regulations,and shall be handled byqualified units.MORNSUN Guangzhou Science&Technology Co.,Ltd.Address:No.5,Kehui St.1,Kehui Development Center,Science Ave.,Guangzhou Science City,Luogang District,Guangzhou,P.R.China Tel:86-20-38601850-8801Fax:86-20-38601272E-mail:***************。
PI2EQX502TZHE SMA EVB User Guide
For the customer use onlyPI2EQX502TZHE SMA EVB User Guide IntroductionPericom Semiconductor’s PI2EQX502T is a low power, high performance 5.0 Gbps signal ReDriver specifically for the USB 3.0 protocol.The device provides programmable equalization and De-Emphasis to optimize performance over a variety of physical mediums by reducing Inter-Symbol Interference.PI2EQX502T supports two 100Ω Differential CML data I/O’s between the Protocol ASIC to a switch fabric, over cable, or to extend the signals across other distant data pathways on the user’s platform.This user guide describes how to use PI2EQX502TZHE SMA EVB for evaluation.Figure1 shows top view and bottom view of PI2EQX502TZHE SMA EVB.Figure1a. TOP view of PI2EQX502TZHE SMA EVBPericom Semiconductor Corp.For the customer use onlyFigure1b. Bottom view of PI2EQX502TZHE SMA EVBBoard Operationz Logical Block DiagramFigure2 shows the logical block diagram of PI2EQX502TZHE.Figure2. Logical Block Diagram of PI2EQX502TZHEPericom Semiconductor Corp.For the customer use only z Board Setting and Operation1) Power SupplyOn the EV board, there is one way for the power supply below.Two 3-Pin headers are for this 3.3V power and ground input.Figure3. Power Input for PI2EQX502TZHE SMA board2) Configuration ControlPI2EQX502TZHE provides pin control for EQ_A/B, DE_A/B and OS_A/B on EVB like in dark blue below.Figure4. Pin control for PI2EQX502TZHE SMA boardOn PI2EQX502TZHE EVB, Below are description and configuration tables for equalization, de-emphasis and swing control setting.Equalization SettingEQ_A and EQ_B are the selection pins for the equalization selection for ChA and ChB in Table2 below. EQ_A or EQ_B can be selected by 3pin headers for 0, open and 1 option to separately 3dB, 6dB and 9dB. N ote for 12dB, the user needs to hand-solder one 48kohm resistor between EQ_A/B and ground like Figure5.Pericom Semiconductor Corp.For the customer use onlyPericom Semiconductor Corp.Table2. Equalizer Configuration Selection Table for PI2EQX502TZHEFigure5. 48Kohm Resistor hand-soldered for 12dB selection of EQ_A/B on PI2EQX502TZHE SMA boardDe-emphasis Setting:DE_A and DE_B are the selection pins for the equalization selection for ChA and ChB in Table3 below. DE_A orDE_B can be selected by 3pin headers for 0, open and 1 option to separately 0dB, -3.5dB and -6dB.Table3. De-emphasis Configuration Selection Table for PI2EQX502TZHER=48KohmR=48KohmFor the customer use onlyPericom Semiconductor Corp.Swing Setting:OS_A and OS_B are the selection pins for the equalization selection for ChA and ChB in Table4 below. OS_A or OS_B can be selected by 3pin headers for 0(GND) and 1(VDD) option to separately 700mV and 1000mV.Table4. Swing Configuration Selection Table for PI2EQX502TZHE3) EVB Test ConnectionFigure6 is the test connection example for AI signal input and AO signal output.Figure6. Test connection with PI2EQX502TZHE SMA boardPower Supply for3.3V Power and GNDFor the customer use onlyPericom Semiconductor Corp.Appendix A: PCB SchematicAppendix B: PCB Stack-upFor the customer use only HistoryVersion 1.0 Original Version 2014/1/27Pericom Semiconductor Corp.。
AlphaScreen Nickel Chelate Donor Beads产品说明书
Material ProvidedFormats:The number of assay points is based on an assay volume of 25 µL in 384-well assay plates using a final bead concentration of 20 µg/mL.Manufacturing Date :October 19, 2017Description: AlphaScreen Nickel Chelate Donor Beads at 5 mg/mL in 25 mM Hepes, pH 7.4, 100 mMNaCl supplemented with 0.05% Proclin-300 as a preservative.Storage:Store in the dark at 4˚C .Stability :This product is stable for at least 12 months from the manufacturing date when stored in its original packaging under recommended storage conditions.Product InformationIntended use: This product is intended for use in homogeneous AlphaScreen or AlphaLISA assays for the capture of 6XHis-tagged targets.RESEARCH USE ONLY. NOT FOR USE IN DIAGNOSTIC PROCEDURES.Quality ControlLot-to-lot consistency is confirmed by a Quality Control AlphaScreen ®titration assay read on an EnVision ®HTS Alpha instrument (see protocol below). We certify that the results meet our quality release criteria. Note: maximum counts will vary depending on assay conditions as well as between lots. This variation has no impact on assay quality.Maximum signal 194810 counts Minimum signal: 467 count2s EC 50: 61.68 nMResearch Use Only. Not for use in diagnostic procedures.Nickel Chelate Donor BeadsProduct No.: AS101D (1 mg)AS101M (5 mg)AS101R (25 mg)Lot No.: 2350145Titration Assay (Quality Control Protocol)This protocol provides a means to verify product performance.The following reagents and materials are recommended.Recommendations:∙AlphaScreen® Donor beads are light-sensitive. All Alpha assays using the Donor beads should be performed under subdued laboratory lighting (< 100 lux). Green filters (LEE 090 filters (preferred) or Roscolux filters #389 from Rosco) can be applied to light fixtures.∙Sodium azide should not be added to stock solutions or assay components. Final concentrations of sodium azide higher than 0.001 % will decrease the AlphaLISA signal.∙Spin down tubes briefly before use to improve recovery of content (2,000 x g, 10-15 sec). Resuspend all reagents by vortexing before use.∙Use Milli-Q® grade water (18 MΩ•cm) to dilute the 5X AlphaLISA Universal Buffer.∙1X AlphaLISA Universal Assay Buffer contains PBS, pH 7.5, 0.1% BSA, 0.01% Proclin-300. 1X AlphaLISA Universal Assay Buffer is used in the titration assay described below (Quality Control Protocol). Optimization of this assay buffer might be necessary in other assay types.∙Small volumes may be prone to evaporation. It is recommended to cover microplates with TopSeal-A Adhesive Sealing Film to reduce evaporation during incubation. Microplates are read with the TopSeal-A Film on the plate.∙Total signal varies with temperature and incubation time. For consistent results, identical incubation times and temperature should be used for all plates.∙The AlphaLISA signal is detected with an EnVision Multilabel Reader equipped with the ALPHA option using the AlphaScreen standard settings (e.g. Total Measurement Time: 550 ms, Excitation Time: 180 ms, Mirror: D640as, Emission Filter: M570w, Center Wavelength 570 nm, Bandwidth 100 nm, Transmittance 75%).Protocol:This protocol is recommended for generating one titration curve in a 25 µL final assay volume (12 concentrations, triplicate determinations with manual pipetting). If more assay points are needed, volumes should be adjusted accordingly.1) Preparation of 1X AlphaLISA Universal Assay Buffer:Add 1 mL of 5X AlphaLISA Universal Assay Buffer to 4 mL H2O.2) Preparation of 1.7X Biotin-rabbit IgG dilutions:Prepare 1.7X dilutions in 1X AlphaLISA Universal Assay Buffer as follows:TubeVolume ofGST, 6 His-taggedVolume ofbuffer (µL)[GST, 6 His-tagged](M) in 15 µL (1.7X)[GST, 6 His-tagged] (M)in final assay volume (25 µL)A 7 µL of 37 µM 145 1.7E-6 1.0E-6B 60 µL of tube A 140 5.1E-7 3.0E-7C 60 µL of tube B 120 1.7E-7 1.0E-7D 60 µL of tube C 140 5.1E-8 3.0E-8E 60 µL of tube D 120 1.7E-8 1.0E-8F 60 µL of tube E 140 5.1E-9 3.0E-9G 60 µL of tube F 120 1.7E-9 1.0E-9H 60 µL of tube G 140 5.1E-10 3.0E-10I 60 µL of tube H 120 1.7E-10 1.0E-10J 60 µL of tube I 140 5.1E-11 3.0E-11K 60 µL of tube J 120 1.7E-11 1.0E-11L 0 140 0 03) Preparation of 5X AlphaLISA Acceptor beads (100 µg/mL):Add 5 µL of 5 mg/mL AlphaLISA beads to 245 µL of 1X AlphaLISA Universal Assay Buffer.4) Preparation of 5X Streptavidin-coated Donor Beads (100 µg/mL):Keep the beads under subdued laboratory lighting.Add 5 µL of 5 mg/mL Nickel Chelate Donor Beads to 245 µL of 1X AlphaLISA Universal Assay Buffer.5) In an OptiPlate-384 microplate:Add 15 µL of 1.7X GST, 6 His-tagged dilutions (A to L)Add 5 µL of 5X AlphaLISA Glutathione Acceptor Beads(20 µg/mL final)Add 5 µL of 5X Nickel Chelate Donor Beads(20 µg/mL final)Read using EnVision-Alpha ReaderPerkinElmer, Inc. 940 Winter StreetWaltham, MA 02451 USATypical Product DataLog [GST, 6 His-tagged] (M)A l p h a L I S A S i g n a l (c o u n t s )* The EC 50 value was determined following a non-linear regression analysis using the sigmoidal dose-response curve model with variable slope. Only assay points up to the maximum signal were used for EC 50 determination (in this case, up to 300 nM).Suggested Materials and InstrumentationPlease visit our website/AlphaTechThis product is not for resale or distribution except by authorized distributors.LIMITED WARRANTY: PerkinElmer BioSignal Inc. warrants that, at the time of shipment, the products sold by it are free from defects in material and workmanship and conform to specifications which accompany the product. PerkinElmer BioSignal Inc. makes no other warranty, express or implied with respect to the products, including any warranty of merchantability or fitness for any particular purpose. Notification of any breach of warranty must be made within 60 days of receipt unless otherwise provided in writing by PerkinElmer BioSignal Inc. No claim shall be honored if the customer fails to notify PerkinElmer BioSignal Inc. within the period specified. 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