JESD79E DDR_SDRAM_Specification_Standard
DDR SDRAM：SoC低成本高复杂度片外存储器解决方案
DDR SDRAM：SoC低成本高复杂度片外存储器解决方案几乎所有人都知道，用于桌面计算机和便携计算机的DRAM存储器产品与本白皮书所讨论的片外DRAM完全相同。
事实上，全部DRAM产量中的约90%用在计算机上，其它10%当作了系统级芯片（SoC）的片外存储器来使用，这就象将方木钉打入圆孔一样地不适合。
随着要求配备与外部存储器接口的SoC设计方案的数量增加，现化化的DDRn SDRAM存储器接口（DDR、DDR2、DDR3）提供了可靠的供货能力、高存储容量、低成本和合理的通道带宽，但却存在使用不便的接口以及复杂控制器方面的问题。
面对内部DRAM阵列所导致的独特指令结构，且要求在设计方案内加入代表当前先进水平的DRAM接口时，SoC设计人员就会将这个任务视为畏途。
本白皮书对SDRAM的历史进行了简短介绍，并探讨了实施DDRn控制器和PHY的设计考虑要素，并描述了如何采用完整的IP解决方案来帮助加快产品上市周期和降低成本。
SDRAM历史简介尽管存储容量上也发生了令人惊奇的进步，但商品DRAM在过去15年来的演化让接口峰值带宽以远大于2000%的系数增加（请参见图1）。
虽然任何人都不能违背物理学的基本规律而对基本随机存取操作的延迟现象做出类似程度的提升，但通过增加引脚带宽以及在脉冲猝发下访问数据的能力，能够减少一部分存储器相对于典型处理器对于更高速存储器带宽永无止境的需求之间的差距。
在这段发展期内，被称为JC42的美国电子器件工程联合委员会（JEDEC）一直是商品DRAM的行业标准的制订机构。
在1993年下半年，JEDEC发布了最初的SDRAM标准，这个标准最终变成了后来称为“PC100 SDRAM”的标准。
通过将SDRAM的时序参数推到实际极限时，PC133 SDRAM出现了，它将通道频率增加到了133MHz，数据速率增加到了133Mbps。
图1 峰值带宽与DRAM类型对比Peak…峰值带宽在20世纪90年代末，JEDEC制订了一份内容扎实的DRAM发展路线图。
JESD79-4 第4章 SDRAM命令描述与操作(4.10)
JESD79-4 第4章SDRAM命令描述与操作（4.10）4.10 多功能寄存器（MPR）4.10.1 使用MPR的DQ训练DDR4 SDRAM包含了4个8bit的MPR寄存器用来存储DQ数据。
这些一次性编程的寄存器可通过MRS命令来激活。
在DQ总线连接性训练过程中可使用MPR所存储的数据位。
在MPR使能模式下，DDR4 SDRAM仅支持如下命令：MRS, RD, RDA WR, WRA, DES, REF与RESET。
需要注意的是在MPR模式下，RDA和WRA命令的功能与READ和WRITE命令的功能是相同的，也就是说，在MPR模式下RDA和WRA的自动充电部分是被忽略的。
在MPR模式下，RESET命令后的tRFC时间内仅允许1x Refrsh命令发送。
在MPR操作中，所有的读写命令都必须在Refresh命令之前完成。
4.10.2 MPR的定义MR3寄存器控制了训练过程中的MPR寄存器的使用。
MR3寄存器可通过将CS_n,RAS_n/A16,CAS_n/A15与WE_n/A14驱动至低电平, 将ACT_n, BA0与BA1驱动至高电平，以及将BG11和BG0驱动至低电平。
控制状态与地址引脚可参考下图。
4.10.3 MPR读DDR4 SDRAM支持BC4与BL8模式读取MPR寄存器的操作，且不支持BC4 OTF模式来读取MPR寄存器。
BC4读取MPR寄存器时，BA0与BA1表示了MPR的中选中页的地址，A10、BG0、BG1以及其他的地址总线都是不关心的。
使用BC4读MPR寄存器时，列地址的A2：A0仅能取“000”或“001”这两个值中间的一个。
在MPR读操作中，DBI功能是不可用的。
DDR4 MPR模式是通过将A2写为1来使能的，读返回的时间来自于MPR寄存器内的特殊位置。
MPR的位置是由Bank地址BA0与BA1来确定的。
每一个MPR位置都是8-bits宽的。
步骤：1.若MR1[A0=1]，DLL使能情况下，在进行MPR读操作之前DLL必须已经完成LOCK。
DDR_SDRAM_简介
Only a few years ago, "regular" SDRAM was introduced as a proposed replacement for the older FPM and EDO asynchronous DRAM technologies.
This was due to the limitations the older memory has when working with systems using higher bus speeds (over 75 MHz).
DDR2 Addresses these challenges by:
Special New Features:
DDR Evolution
DDR and DDR-II
DDR-II Architecture
4-bit Pre-fetch
Single Data SDRAM In most DRAMs, the core and the I/O logic are running at the same frequency.
This type of circuit provides excellent gain and bandwidth.
High Speed Memory Design Considerations
The Signal integrity is an challenging issue in High speed design. The following effects are more important in High Speed Design and can cause data corruption.
JESD79-4 第4章 SDRAM命令描述与操作(4.5-4.7)
JESD79-4 第4章SDRAM命令描述与操作（4.5-4.7）4.5 DLL-off模式DDR4 SDRAM的DLL-off模式是通过配置MR1寄存器的A0为0来进入的。
在此模式中，DLL将不会有任何操作，知道MR1寄存器的A0重新被配置为1。
DLL-off模式可在初始化过程中，或者是在初始化完成之后进入。
具体可参考4.6节“改变输入时钟频率”。
下面列表中的的DLL-off模式时DDR4 SDRAM的可选操作模式。
DLL-off模式中的可使用的最大时钟频率为参数tCKDLL_OFF所限定的。
且没有最低时钟频率要求，除了需要满足tREFI的要求（刷新时间间隔）。
由于延迟计数以及时序约束，仅支持MR0寄存器中一种CL值，以及MR2寄存器中一种CWL值，DLL-off模式仅支持CL=10与CWL=9。
且一旦进入DLL-off模式，CA奇偶检验功能将不可用。
DLL-off模式会影响读数据时钟与数据选通信号的时序关系tDQSCK。
但是不影响tDQSQ 与tQH。
特别需要注意的是需要将读数据按次序返回给控制时钟域。
对比DLL-on模式，从读命令后的AL+CL个时钟上升沿（）后开始计算时间tDQSCK，而DLL-off模式则是从读命令后的AL+CL-1时钟上升沿开始计算时间。
另一个区别在于DLL-off模式中，tDQSCK是不小于tCK的，而且tDQSCKmin与tDQSCKmax都会比DLL-on模式中的大很多。
tDQSCK（DLL-off）使用设备商来提供说明。
下图中是DLL-off模式中的读操作时序关系图（CL=10,BL=8,PL=0)4.6 改变输入时钟频率DDR4 SDRAM初始化完成之后，在进行大多数普通的操作时要求时钟的相对稳定的。
这就意味着一旦时钟频率设定好，就要一直保持着这种稳定状态，在此期间，时钟周期不允许改变，除了时钟的jitter与SSC（展频）。
在Self-refresh模式与Precharge Power Down模式下可以让输入时钟频率由当前的稳定状态改变的到另一个稳定状态。
jedec标准3200
jedec标准3200JEDEC标准3200。
JEDEC标准3200是一项关于半导体存储器的行业标准，它规定了DDR4 SDRAM的技术规范和参数。
DDR4 SDRAM是一种高速、低功耗的内存芯片，广泛应用于个人电脑、服务器、工作站等领域。
JEDEC标准3200的发布，标志着DDR4内存技术的进一步发展和成熟，为行业带来了更高的性能和更低的能耗。
JEDEC标准3200对DDR4 SDRAM的规范包括了内部结构、时序特性、电气特性、功能特性等方面的详细要求。
其中，内部结构包括了存储单元的组织方式、存储密度、排列方式等；时序特性包括了读写时序、预充电时序、刷新时序等；电气特性包括了供电电压、信号电平、功耗等；功能特性包括了自刷新、自检测、错误校正码等。
这些规范的制定和遵循，保证了DDR4 SDRAM的稳定性、可靠性和兼容性。
根据JEDEC标准3200的规范，DDR4 SDRAM的工作电压为1.2V，相比于DDR3 SDRAM的1.5V，功耗降低了20%。
同时，DDR4 SDRAM的频率也得到了显著提升，最高可达到3200MT/s，数据传输速度更快，响应更加迅速。
此外，DDR4 SDRAM还支持更大的单条内存容量，最高可达128GB，满足了大内存需求的应用场景。
除了提升性能和降低功耗外，JEDEC标准3200还规定了DDR4 SDRAM的物理尺寸和引脚排布，以确保其与主板插槽的兼容性。
同时，标准还规定了DDR4 SDRAM的温度范围、湿度范围、机械强度等环境要求，保证其在各种工作环境下的稳定运行。
这些规范的制定，为DDR4 SDRAM的设计、生产、测试和应用提供了统一的依据，有利于降低成本、提高效率。
总的来说，JEDEC标准3200的发布，推动了DDR4内存技术的发展和普及，为计算机系统的性能提升和能耗降低做出了重要贡献。
作为一项行业标准，它的制定和遵循，有利于提高产品质量、降低生产成本、促进技术创新，对整个半导体存储器行业具有重要意义。
美国半导体CM3202-02 DDR VDDQ和VTT终端电压调节器数据手册说明书
CM3202-02DDR VDDQ and VTT Termination Voltage RegulatorProduct DescriptionThe CM3202−02 is a dual−output low noise linear regulator designed to meet SSTL−2 and SSTL−3 specifications for DDR−SDRAM V DDQ supply and termination voltage V TT supply. With integrated power MOSFETs the CM3202−02 can source up to 2A of VDDQ continuous current, and source or sink up to 2 A VTT continuous current. The typical dropout voltage for VDDQ is 500 mV at 2 A load current.The CM3202−02 provides excellent full load regulation and fast response to transient load changes. It also has built−in over−current limits and thermal shutdown at 170°C.The CM3202−02 supports Suspend−To−RAM (STR) and ACPI compliance with Shutdown Mode which tri−states VTT to minimize quiescent system current.The CM3202−02 is available in a space saving WDFN8 surface mount packages. Low thermal resistance allows them to withstand high power dissipation at 85°C ambient. The CM3202−02 can operate over the industrial ambient temperature range of –40°C to 85°C. Features•Two Linear Regulators•Maximum 2 A Current from VDDQ•Source and Sink Up to 2 A VTT Current•1.7 V to 2.8 V Adjustable VDDQ Output V oltage•0.85 V to 1.4 V VTT Output V oltage (Tracking at 50% of VDDQ)•500 mV Typical VDDQ Dropout V oltage at 2 A •Excellent Load and Line Regulation, Low Noise•Meets JEDEC DDR−I and DDR−II Memory Power Spec •Linear Regulator Design Requires no Inductors and Has Low External Component Count•Integrated Power MOSFETs•Dual Purpose ADJ/Shutdown Pin•Built−In Over−Current Limit and Thermal Shutdown for V DDQ and V TT•Fast Transient Response•Low Quiescent Current•These Devices are Pb−Free and are RoHS CompliantApplications•DDR Memory and Active Termination Buses •Desktop Computers, Servers •Residential and Enterprise Gateways •DSL Modems •Routers and Switches•DVD Recorders•3D AGP Cards•LCD TV and STBMARKING DIAGRAMDevice Package Shipping†ORDERING INFORMATIONCM3202−02DE WDFN8(Pb−Free)3000/T ape & Reel†For information on tape and reel specifications,including part orientation and tape sizes, pleaserefer to our Tape and Reel Packaging SpecificationBrochure, BRD8011/D.CM320 202DE= CM3202−02DECM320202DEWDFN8DE SUFFIXCASE 511BHTYPICAL APPLICATIONV IN = 3.3 V to 3.6 VFUNCTIONAL BLOCK DIAGRAMVTTGNDPACKAGE / PINOUT DIAGRAMSTop View(Pins Down View)Thermal PadCM3202−02DETable 1. PIN DESCRIPTIONSPin(s)Name Description1VIN Input supply voltage pin. Bypass with a 220 m F capacitor to GND.2NC Not internally connected. For better heat flow, connect to GND (exposed pad).3VTT V TT regulator output pin, which is preset to 50% of V DDQ.4NC Not internally connected. For better heat flow, connect to GND (exposed pad).5GND Ground pin (analog).6GND Ground pin (power).7ADJSD This pin is for V DDQ output voltage adjustment. It is available as long as V DDQ is enabled.During Manual/Thermal shutdown, it is tightened to GND. The V DDQ output voltage is setusing an external resistor divider connected to ADJSD:V DDQ = 1.25 V ×((R1 + R2) / R2)Where R1 is the upper resistor and R2 is the ground−side resistor. In addition, the ADJSD pin functions as aShutdown pin. When ADJSD voltage is higher than 2.7 V (SHDN_H), the circuit is in Shutdown mode. WhenADJSD voltage is below 1.5 V (SHDN_L), both VDDQ and VTT are enabled. A low−leakage Schottky diode inseries with ADJSD pin is recommended to avoidinterference with the voltage adjustment setting.8VDDQ VDDQ regulator output voltage pin.EPad GND The backside exposed pad which serves as the package heatsink. Must be connected to GND.SPECIFICATIONSTable 2. ABSOLUTE MAXIMUM RATINGSParameter Rating Units VIN to GND[GND − 0.3] to +6.0VPin VoltagesV DDQ, V TT to GND ADJSD to GND [GND − 0.3] to +6.0[GND − 0.3] to +6.0VOutput CurrentVDDQ / VTT, continuous (Note 1) VDDQ / VTT, peakVDDQ Source + VTT Source 2.0 / ±2.02.8 / ±2.83ATemperature Operating Ambient Operating Junction Storage –40 to +85–40 to +170–40 to +150°CThermal Resistance, R JA (Note 2)55°C / W Continuous Power Dissipation (Note 2)WDFN8, T A = 25°C / 85°C 2.6 / 1.5WESD Protection (HBM)2000VLead Temperature (soldering, 10 sec)300°C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.1.Despite the fact that the device is designed to handle large continuous/peak output currents, it is not capable of handling these under allconditions. Limited by the package thermal resistance, the maximum output current of the device cannot exceed the limit imposed by the maximum power dissipation value.2.Measured with the package using a 4 in2 / 2 layers PCB with thermal vias.Table 3. STANDARD OPERATING CONDITIONSParameter Rating Units Ambient Operating Temperature Range–40 to +85°CVDDQ RegulatorSupply Voltage, VINLoad Current, Continuous Load Current, Peak (1 sec) C DDQ 3.0 to 3.60 to 22.5220VAAm FVTT RegulatorSupply Voltage, VINLoad Current, Continuous Load Current, Peak (1 sec) C TT 3.0 to 3.60 to ±2.0±2.50220VAAm FVIN Supply Voltage Range 3.0 to 3.6VVDDQ Source + VTT Source Load Current, Continuous Load Current, Peak (1 sec)2.53.5AJunction Operating Temperature Range–40 to +150°CSPECIFICATIONS (Cont’d)Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note 1)Symbol Parameter Conditions Min Typ Max Units GeneralVIN Supply Voltage Range 3.0 3.6VI Q Quiescent Current I DDQ = 0, I TT = 0715mA V ADJSD ADJSD Voltage 1.225 1.250 1.275VI SHDN Shutdown Current V ADJSD = 3.3 V (Shutdown) (Note 3)0.20.5mA SHDN_H ADJSD Logic High(Note 2) 2.7V SHDN_L ADJSD Logic Low 1.5V UVLO Under−Voltage Lockout Hysteresis = 100 mV 2.40 2.70 2.90VT OVER Thermal SHDN Threshold150170°C T HYS Thermal SHDN Hysteresis50°C TEMPCO V DDQ, V TT TEMPCO I OUT = 1 A80ppm/°C VDDQ RegulatorV DDQ DEF VDDQ Output Voltage I DDQ = 100 mA 2.450 2.500 2.550VV DDQ LOAD VDDQ Load Regulation10 mA ≤ I DDQ≤2 A (Note 3)1025mV V DDQ LINE VDDQ Line Regulation 3.0 V ≤ VIN ≤3.6 V, I DDQ= 0.1 A525mV V DROP VDDQ Dropout Voltage I DDQ= 2 A (Note 4)500mVI ADJ ADJSD Bias Current(Note 3)0.8 3.0m A I DDQ LIM VDDQ Current Limit 2.0 2.5A VTT RegulatorV TT DEF VTT Output Voltage I TT = 100 mA 1.225 1.250 1.275VV TT LOAD VTT Load Regulation Source, 10 mA ≤ I TT≤ 2 A (Note 3)Sink, −2A ≤ I TT≤ 10 mA (Note 3)–3010–1030mVmVV TT LINE VTT Line Regulation 3.0 V≤VIN≤3.6 V, I TT= 0.1 A515mVI TT LIM ITT Current Limit Source / Sink (Note 3)±2.0±2.5AI VTT OFF VTT Shutdown Leakage Current V ADJSD = 3.3 V (Shutdown)10m A1.VIN = 3.3 V, V DDQ=2.50 V, VTT = 1.25 V (default values), C DDQ= C TT= 47 m F, T A = 25°C unless otherwise specified.2.The ADJSD Logic High value is normally satisfied for full input voltage range by using a low leakage current (below 1 m A). Schottky diodeat ADJSD control pin.3.Load and line regulation are measured at constant junction temperature by using pulse testing with a low duty cycle. For high current tests,correlation method can be used. Changes in output voltage due to heating effects must be taken into account separately. Load and line regulation values are guaranteed by design up to the maximum power dissipation.4.Dropout voltage is the input to output voltage differential at which output voltage has dropped 100 mV from the nominal value obtained at3.3 V input. It depends on load current and junction temperature. Guaranteed by design.TYPICAL OPERATING CHARACTERISTICS0.750.850.951.051.151.251.351.451.551.651.5 1.75 2 2.25 2.5 2.75 3 3.252.4502.4752.5002.5252.550−40−20 0 20 40 60 80 100 120 1400.51.0 1.52.0 2.51.02.03.04.0010020030040050060000.51.01.52.02.53.00.51.01.52.02.5TEMPERATURE (5C)V D D Q (V )VDDQ vs. TemperatureVTT vs. VDDQVDDQ (V)V T T (V )VDDQ vs. Load CurrentIDDQ (A)V D D Q (V )VIN = 3.3 V T A = 25°CVDDQ Dropout vs. IDDQIDDQ (A)D r o p o u t V o l t a g e (m V )T A = 25°CVTT vs. Load CurrentITT (A)V T T (V )VIN = 3.3 VStartup into Full LoadTime (1 ms/div)UVLOVIN = 3.3 V2 V/divVTT 1 V/div Vin VDDQ 1 V/divTYPICAL OPERATING CHARACTERISTICS (Cont’d)V INI DDQ0.5A/divV DDQ 0.1V/divI TT0.5A/divV TT0.1V/divTIME (0.2ms/div)TIME (0.2ms/div)-0.75AVDDQ Transient Response VTT Transient ResponseV IN= 3.3VAPPLICATION INFORMATIONPowering DDR MemoryDouble−Data−Rate (DDR) memory has provided a huge step in performance for personal computers, servers and graphic systems. As is apparent in its name, DDR operates at double the data rate of earlier RAM, with two memory accesses per cycle versus one. DDR SDRAMs transmit data at both the rising and falling edges of the memory bus clock.DDR’s use of Stub Series Terminated Logic (SSTL) topology improves noise immunity and power−supply rejection, while reducing power dissipation. To achieve this performance improvement, DDR requires more complex power management architecture than previous RAM technology.Unlike the conventional DRAM technology, DDR SDRAM uses differential inputs and a reference voltage for all interface signals. This increases the data bus bandwidth, and lowers the system power consumption. Power consumption is reduced by lower operating voltage, a lower signal voltage swing associated with Stub Series Terminated Logic (SSTL_2), and by the use of a termination voltage, V TT. SSTL_2 is an industry standard defined in JEDEC document JESD8−9. SSTL_2 maintains high−speed data bus signal integrity by reducing transmission reflections. JEDEC further defines the DDR SDRAM specification in JESD79C.DDR memory requires three tightly regulated voltages: V DDQ, V TT, and V REF (see Typical DDR terminations, Class II). In a typical SSTL_2 receiver, the higher current V DDQ supply voltage is normally 2.5 V with a tolerance of ±200mV. The active bus termination voltage, V TT, is half of V DDQ. V REF is a reference voltage that tracks half of V DDQ±1%, and is compared with the V TT terminated signal at the receiver. V TT must be within ±40 mV of V REFFigure 1. Typical DDR Terminations, Class IIThe VTT power requirement is proportional to the number of data lines and the resistance of the termination resistor, but does not vary with memory size.In a typical DDR data bus system each data line termination may momentarily consume 16.2mA to achieve the 405 mV minimum over V TT needed at the receiver:I terminaton+405 mVRt(25 W)+16.2 mAA typical 64 Mbyte SSTL−2 memory system, with 128 terminated lines, has a worst−case maximum V TT supply current up to ±2.07 A. However, a DDR memory system is dynamic, and the theoretical peak currents only occur for short durations, if they ever occur at all. These high current peaks can be handled by the V TT external capacitor. In a real memory system, the continuous average V TT current level in normal operation is less than ±200 mA.The VDDQ power supply, in addition to supplying current to the memory banks, could also supply current to controllers and other circuitry. The current level typically stays within a range of 0.5 A to 1 A, with peaks up to 2 A or more, depending on memory size and the computing operations being performed.The tight tracking requirements and the need for V TT to sink, as well as source, current provide unique challenges for powering DDR SDRAM.CM3202−02 RegulatorThe CM3202−02 dual output linear regulator provides all of the power requirements of DDR memory by combining two linear regulators into a single TDFN−8 package. VDDQ regulator can supply up to 2 A current, and the two−quadrant V TT termination regulator has current sink and source capability to ±2 A. The VDDQ linear regulator uses a PMOS pass element for a very low dropout voltage, typically 500 mV at a 2 A output. The output voltage of V DDQ can be set by an external voltage divider. The use of regulators for both the upper and lower side of the VDDQ output allows a fast transient response to any change of the load, from high current to low current or inversely. The second output, V TT, is regulated at V DDQ/2 by an internal resistor divider. Same as VDDQ, VTT has the same fast transient response to load change in both directions. The V TT regulator can source, as well as sink, up to 2 A current. The CM3202−02 is designed for optimal operation from a nominal 3.3 VDC bus, but can work with VIN up to 5 V. When operating at higher VIN voltages, attention must be given to the increased package power dissipation and proportionally increased heat generation. Limited by the package thermal resistance, the maximum output current of the device at higher VIN cannot exceed the limit imposed by the maximum power dissipation value.V REF is typically routed to inputs with high impedance, such as a comparator, with little current draw. An adequate V REF can be created with a simple voltage divider of precision, matched resistors from V DDQ to ground. A small ceramic bypass capacitor can also be added for improved noise performance.Input and Output CapacitorsThe CM3202−02 requires that at least a 220 m F electrolytic capacitor be located near the VIN pin for stability and to maintain the input bus voltage during load transients. An additional 4.7 m F ceramic capacitor between the VIN and GND, located as close as possible to those pins, is recommended to ensure stability.At a minimum, a 220 m F electrolytic capacitor is recommended for the V DDQ output. An additional 4.7 m F ceramic capacitor between the V DDQ and GND, located very close to those pins, is recommended.At a minimum, a 220 m F electrolytic capacitor is recommended for the V TT output. This capacitor should have low ESR to achieve best output transient response. SP or OSCON capacitors provide low ESR at high frequency, and thus are a good choice. In addition, place a 4.7 m F ceramic capacitor between the V TT pin and GND, located very close to those pins. The total ESR must be low enough to keep the transient within the V TT window of 40 m V during the transition for source to sink. An average current step of ±0.5 A requires:ESR t 40 mV1 A+40 m WBoth outputs will remain stable and in regulation even during light or no load conditions. The general recommendation for circuit stability for the CM3202−02 requires the following:1.C IN = C DDQ = C TT = 220 m F/4.7 m F for the full temperature range of –40 to +85°C.2.C IN = C DDQ = C TT = 100 m F/2.2 m F for the temperature range of –25 to +85°C.Adjusting VDDQ Output VoltageThe CM3202−02 internal bandgap reference is set at 1.25 V. The V DDQ voltage is adjustable by using a resistor divider, R1 and R2:V DDQ+V ADJ R1)R2R2where V ADJ = 1.25 V. The recommended divider value is R1= R2= 10 k W for DDR−1 application, and R1 = 4.42 k W, R2=10k W for DDR−2 application (V DDQ= 1.8 V, V TT= 0.9 V).ShutdownADJSD also serves as a shutdown pin. When this is pulled high (SHDN_H), both the VDDQ and the VTT outputs tri−state and could sink/source less than 10 m A. During shutdown, the quiescent current is reduced to less than 0.5 mA, independent of output load.It is recommended that a low leakage Schottky diode be placed between the ADJSD Pin and an external shutdown signal to prevent interference with the ADJ pin’s normal operation. When the diode anode is pulled low, or left open, the CM3202−02 is again enabled.Current Limit and Over−temperature ProtectionThe CM3202−02 features internal current limiting with thermal protection. During normal operation, V DDQ limits the output current to approximately 2 A and V TT limits the output current to approximately ±2 A. When V TT is current limiting into a hard short circuit, the output current folds back to a lower level (~1 A) until the over−current condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the junction temperature of the device exceeds 170°C (typical), the thermal protection circuitry triggers and tri−states both VDDQ and VTT outputs. Once the junction temperature has cooled to below about 120°C the CM3202−02 returns to normal operation.Typical Thermal CharacteristicsThe overall junction to ambient thermal resistance (q JA) for device power dissipation (P D) primarily consists of two paths in the series. The first path is the junction to the case (q JC) which is defined by the package style and the second path is case to ambient (q CA) thermal resistance which is dependent on board layout. The final operating junction temperature for any condition can be estimated by the following thermal equation:T JUNC+T AMB)P D(q JC))P D(q CA) +T AMB)P D(q CA)When a CM3202−02 using WDFN8 package is mounted on a double−sided printed circuit board with four square inches of copper allocated for “heat spreading,” the q JA is approximately 55°C/W. Based on the over temperature limit of 170°C with an ambient temperature of 85°C, the available power of the package will be:+1.5WP D+170°C*85°C55°CńWPCB Layout ConsiderationsThe CM3202−02 has a heat spreader (exposed pad) attached to the bottom of the WDFN8 package in order for the heat to be transferred more easily from the package to the PCB. The heat spreader is a copper pad with slightly smaller dimensions than the package itself. By positioning the matching pad on the PCB top layer to connect to the spreader during manufacturing, the heat will be transferred between the two pads. Thermal Layout for WDFN8 package shows the CM3202−02 recommended PCB layout. Please note there are four vias to allow the heat to dissipate into the ground and power planes on the inner layers of the PCB. Vias must be placed underneath the chip but this can result in solder blockage. The ground and power planes need to be at least 2 square inches of copper by the vias. It also helps dissipation if the chip is positioned away from the edge of the PCB, and away from other heat−dissipating devices. A good thermal link from the PCB pad to the rest of the PCB will assure the best heat transfer from the CM3202−02 to ambient temperature.Top ViewBottom LayerGround PlaneFigure 2. Thermal Layout for WDFN8 PackageWDFN8 3x3, 0.65P CASE 511BH −01ISSUE ODATE 21 JUL 2010SCALE 2:1NOTES:1.DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.2.CONTROLLING DIMENSION: MILLIMETERS.3.DIMENSION b APPLIES TO PLATEDTERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM TERMINAL TIP .4.COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.DIM MIN MAX MILLIMETERS A 0.700.80A10.000.05b 0.250.35D 3.00 BSC D2 2.20 2.40E 3.00 BSC E2 1.40 1.60e 0.65 BSC L 0.200.40*For additional information on our Pb −Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.SOLDERING FOOTPRINT*DIMENSIONS: MILLIMETERSA30.20 REF L1−−−0.15RECOMMENDEDK 0.45 REF MECHANICAL CASE OUTLINEPACKAGE DIMENSIONSON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others.© Semiconductor Components Industries, LLC, 2019PUBLICATION ORDERING INFORMATIONTECHNICAL SUPPORTNorth American Technical Support:Voice Mail: 1 800−282−9855 Toll Free USA/Canada Phone: 011 421 33 790 2910LITERATURE FULFILLMENT :Email Requests to:*******************onsemi Website: Europe, Middle East and Africa Technical Support:Phone: 00421 33 790 2910For additional information, please contact your local Sales Representative◊。
JE第章DDRSDRAM引脚描述
Input
Bank组输入：BG0-BG1可以选择当前的ACT、RD、WRT或是PRE命令是对哪一个Bank组进行操作。在MRS命令中，BG0也参与模式寄存器的选择。在x4、x8系统中，有BG0与BG1，而x16系统中，仅有BG0。
A0-A17
Input
地址总线：在ACT命令中作为行地址，在读写命令中作为列地址，从而可定位到存储阵列中的确定位置。(A10/AP, A12/BC_n, RAS_n/A16, CAS_n/A15 与 WE_n/A14可作为额外的地址总线使用。在MRS命令中，地址总线还作为操作码使用，即写入模式寄存器的值。A17仅在x4系统中可用。
A10/AP
Input
自动刷新：此位可控制在完成读写操作好是否进行自动刷新操作，高电平为开启自动刷新，低电平为关闭自动刷新。在PRE命令中，A10为还可作为是否进行全bank操作的开关。如果仅有一个bank进行刷新，则由bank地址来确定哪个bank来进行操作。
A12/BC_n
Input
Burst选择：在选择On-The-Fly时，此位作为Burst长度的选择信号。具体细节参考命令真值表。
TDQS_t,TDQS_c
Output
终端数据选通：TDQS_t\TDQS_c仅在x8系统中应用。当MR1寄存器中的A11为高电平时，DRAM就会使能相似终端阻抗（same termination resistance）功能，同时TDQS_c与TDQS_t将会应用与DQS_t\DQS_c。当MR1寄存器中的A11为低电平时，DM\DBI\TDQS将会作为数据掩码或数据总线翻转功能使用，且A11、A12、A10与TDQS_c都不会使用。在x4与x16 DRAM中TDQS必须是禁止的，也就是MR1寄存器中的A11为永远为低电平。
JESD79-4 第4章 SDRAM命令描述与操作
JESD79-4 第4章SDRAM命令描述与操作（4.1-4.4）4 DDR4 SDRAM命令描述与操作4.1 命令真值表Note 1,2,3 and 4 适用于真值表中所有命令Note 5 适用于读写命令[BG=Bank组地址, BA=Bank地址, RA=Row地址, CA=Column地址, BC_n=Burst长度, X=不关心, V=需有效].∙NOTE 1 所有DDR4 SDRAM命令都是由在ck时钟上升沿的时刻CS_n,ACT_n,RAS_n/A16,CAS_n/A15,WE_n/A14以及CKE的状态确定的。
BG,BA,RA与CA的有效位是由设备密度以及配置确定的。
当ACT_n为高电平时，RAS_n/A16, CAS_n/A15与WE_n/A14是分别用作命令控制信号RAS_n, CAS_n与WE_n的；当ACT_n为低电平时，RAS_n/A16, CAS_n/A15与WE_n/A14是分别用作地址信号A16, A15与A14的。
∙NOTE 2 RESET_n是低电平有效的，异步复位信号，在任何其他命令中此信号都必须为高电平∙NOTE 3 BANK组地址（BG）与BANK地址（BA）可确定是哪一个bank被操作。
在MRS命令中，BG与BA用来定位模式寄存器。
∙NOTE 4 “V”表示此信号此时需要一个“0”或者“1”，“X”表示此信号此时不需要任何逻辑值，可以为悬空信号。
∙NOTE 5 读请求或者写请求的burst类型，仅在模式寄存器中被定义，且不可在访问过程中被打断。
∙NOTE 6 Power Down模式中，不发送任何Refresh命令。
∙NOTE 7 ODT的状态并不影响此真值表中的任何状态，且在Self-refresh模式中ODT功能不可用。
∙NOTE 8 由控制器来保证退出Self-refresh命令的同步。
∙NOTE 9 在Self-refresh模式中必须保持VREF（VrefCA）的状态，且在Self-refresh 结束后的TBD个ck时钟周期内都不能出现write leveling的触发命令∙NOTE 10 无操作命令可用在DDR4 SDRAM的Gear Down模式与退出最大低功耗模式时。
DDR 存储器概述 (应用指南)
存储器 控制器
时钟、地址、控制
选通、数据 DDR DRAM
选通、数据
DDR DRAM
选通、数据
DDR DRAM
选通、数据
请参阅教程 5990-3317CHCN《仿真器件 和互连验证》，了解更多信息。
探测物理层并进行 功能测试
JEDEC 定义了 DRAM 细间距球栅阵列 （FBGA）封装的球输出 DDR 规范。球输 出位于 FBGA 封装的下面，这让您很难探 测其信号，实现真正的一致性。工程师 们通常会在过孔或端接电阻器处探测信 号，但这通常会影响测量结果。信号反 射、失真和偏移等问题会产生一些不良 影响。您如何选择一种恰当的方式进行 探测，确保您能够精确观察到信号的特 性？
07 | 是德科技 | DDR 存储器概述、开发周期和挑战 — 应用指南
是德科技示波器
从 20 MHz 至 > 90 GHz 的多种型号 | 业界领先的技术指标 | 功能强大的应用软件
08 | 是德科技 | DDR 存储器概述、开发周期和挑战 — 应用指南
演进
我们独有的硬件、软件和技术人员资源组合能够帮助您实现下一次突破。 我们正在开启技术的未来。
细间距球栅 阵列（FBGA）/ POP x16、x32
细间距球栅 阵列（FBGA）
x4、x8、x16
POP x16、x32
细间距球栅 阵列（FBGA）
x4、x8、x16
有，兼容 DDR2 无
无
无
表 1. JEDEC 定义了 DDR 规范，但它将是否遵从该标准的责任交由设计师或采纳者自行决定，而非强制实施该规范。
JESD79-4 第4章 SDRAM命令描述与操作(4.8-4.9)
JESD79-4 第4章SDRAM命令描述与操作（4.8-4.9）4.8 温控的刷新模式此模式是由MR4中的A3位来进行关闭与打开，两种可支持的模式则是由MR4中的A2位来选择。
4.8.1 普通温度模式当MR4寄存器中的A3=1且A2=0时，即可进入此模式。
发送给DRAM的refresh命令间隔需要等于或小于普通温度模式（0℃-85℃）中的tREFI时间。
在此模式中，系统必须保证DRAM的温度不超过85℃。
当低于45℃时，DRAM会以一定的比例屏蔽外部的refresh命令，来增加内部refresh间隔时间tREFI。
此动作是由DRAM内部完成，不需要用户额外控制命令发送策略。
4.8.2 扩展温度模式当MR4寄存器中的A3=1且A2=1时，即可进入此模式。
发送给DRAM的refresh命令间隔需要等于或小于扩展温度模式（85℃-95℃）中的tREFI时间。
4.9 精细粒度的刷新模式4.9.1 模式寄存器与真值表可使用MRS命令来配置DDR4 SDRAM的刷新命令时间tRFC与刷新命令间隔时间tREFI。
通过配置MR4相关的控制位，可选择固定刷新模式或动态刷新模式。
固定刷新模式为固定一套tRFC与tREFI，动态刷新模式可在两套tRFC与tREFI中间动态选择。
在向DRAM发送动态刷新命令之前，必须首先配置MR4寄存器为动态刷新模式，具体配置如下图所示。
通过配置MR寄存器可选择两种动态刷新模式，分别是1x/2x模式与1x/4x模式。
当MR4寄存器的A8=1时，即选择了动态刷新模式。
然后在向DRAM发送refresh命令时，DDR4 SDRAM通过检测BG0的值，来确定具体的刷新模式是1x/2x模式还是1x/4x模式，从而执行相一致的刷新操作。
具体的真值表如下表所示。
4.9.2 tRFC与tREFI参数在默认情况下，刷新速率的模式为x1模式，此时发送给DRAM的刷新命令应该按照普通的速率来进行，比如说tREFI1=tREFI(base)（在小于85℃时），以及每次刷新命令的时长为普通的刷新时间tRFC1。
DDR内存介绍
DDR内存介绍DDR SDRAM最早是由三星公司于1996年提出，由日本电气、三菱、富士通、东芝、日立、德州仪器、三星及现代等八家公司协议订立的内存规格，并得到了AMD、VIA与SiS等主要芯片组厂商的支持。
它是SDRAM 的升级版本，因此也称为「SDRAM II」。
其最重要的改变是在界面数据传输上，他在时钟信号的上升沿与下降沿均可进行数据处理，使数据传输率达到SDR(Single Data Rate)SDRAM 的2倍。
至于寻址与控制信号则与SDRAM相同，仅在时钟上升沿传送。
DDR SDRAM模块部份与SDRAM模块相比，改为采用184针(pin)，4～6 层印刷电路板，电气接口则由「LVTTL」改变为「SSTL2」。
在其它组件或封装上则与SDRAM模块相同。
DDR SDRAM模块一共有184个接脚，且只有一个缺槽，与SDRAM的模块并不兼容。
DDR SDRAM在命名原则上也与SDRAM不同。
SDRAM的命名是按照时钟频率来命名的，例如PC100与PC133。
而DDR SDRAM 则是以数据传输量作为命名原则，例如PC1600以及PC2100，单位 MB/s。
所以 DDR SDRAM中的DDR200 其实与 PC1600 是相同的规格，数据传输量为1600MB/s(64bit×100MHz×2÷8＝1600MBytes/s)，而 DDR266与PC2100 也是一样的情形(64bit×133MHz×2÷8＝2128MBytes/s)。
DDR SDRAM 在规格上按信号延迟时间(CL；CAS Latency，CL是指内存在收到讯号后，要等待多少个系统时钟周期后才进行读取的动作。
一般而言是越短越好，不过这还要看内存颗粒的原始设定值，否则会造成系统的不稳定)也有所区别。
按照电子工程设计发展联合协会（JEDEC）的定义(规格书编号为JESD79)：DDR SDRAM一共有两种CAS延迟，分为2ns以及2.5ns(ns为十亿分之一秒)。
JEDEC_DDR3_SPD_Specification_Rev1.0
Annex K: Serial Presence Detect (SPD) for DDR3 SDRAM ModulesSPD Revision 1.01.0 IntroductionThis annex describes the serial presence detect (SPD) values for all DDR3 modules. Differences between module types are encapsulated in subsections of this annex. These presence detect values are those referenced in the SPD standard document for ‘Specific Features’. The following SPD fields will be documented in the order presented in section 1.1 with the exception of bytes 60 ~ 116 which are documented in separate annexes, one for each family of module types. Fur-ther description of Byte 2 is found in Annex A of the SPD standard. All unused entries will be coded as 0x00. All unused bits in defined bytes will be coded as 0 except where noted.To allow for maximum flexibility as devices evolve, SPD fields described in this document may support device configura-tion and timing options that are not included in the JEDEC DDR3 SDRAM data sheet (JESD79-3). Please refer to DRAM supplier data sheets or JESD79-3 to determine the compatibility of components.1.1 Address mapThe following is the SPD address map for all DDR3 modules. It describes where the individual lookup table entries will be held in the serial EEPROM.Byte Number Function Described Notes0Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage1, 21SPD Revision2Key Byte / DRAM Device Type3Key Byte / Module Type4SDRAM Density and Banks35SDRAM Addressing36Module Nominal Voltage, VDD7Module Organization38Module Memory Bus Width9Fine Timebase (FTB) Dividend / Divisor10Medium Timebase (MTB)Dividend11Medium Timebase (MTB) Divisor12SDRAM Minimum Cycle Time (tCKmin)313Reserved14CAS Latencies Supported, Least Significant Byte315CAS Latencies Supported, Most Significant Byte316Minimum CAS Latency Time (tAAmin)317Minimum Write Recovery Time (tWRmin)318Minimum RAS# to CAS# Delay Time (tRCDmin)319Minimum Row Active to Row Active Delay Time (tRRDmin)320Minimum Row Precharge Delay Time (tRPmin)321Upper Nibbles for tRAS and tRC322Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte323Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte31.Number of SPD bytes written will typically be programmed as 128 or 176 bytes.2.Size of SPD device will typically be programmed as 256 bytes.3.From DDR3 SDRAM datasheet.4.These are optional, in accordance with the JEDEC spec.Byte Number Function Described Notes 24Minimum Refresh Recovery Delay Time (tRFCmin), Least Significant Byte3 25Minimum Refresh Recovery Delay Time (tRFCmin), Most Significant Byte3 26Minimum Internal Write to Read Command Delay Time (tWTRmin)3 27Minimum Internal Read to Precharge Command Delay Time (tRTPmin)3 28Upper Nibble for tFAW3 29Minimum Four Activate Window Delay Time (tFAWmin)3 30SDRAM Optional Features3 31SDRAM Thermal and Refresh Options3 32Module Thermal Sensor33SDRAM Device Type34 ~ 59Reserved, General Section60 ~ 116Module Type Specific Section, Indexed by Key Byte 3117 ~ 118Module ID: Module Manufacturer’s JEDEC ID Code119Module ID: Module Manufacturing Location120 ~ 121Module ID: Module Manufacturing Date122 ~ 125Module ID: Module Serial Number126 ~ 127Cyclical Redundancy Code128 ~ 145Module Part Number4 146 ~ 147Module Revision Code4 148 ~ 149DRAM Manufacturer’s JEDEC ID Code4 150 ~ 175Manufacturer’s Specific Data4 176 ~ 255Open for customer use1.Number of SPD bytes written will typically be programmed as 128 or 176 bytes.2.Size of SPD device will typically be programmed as 256 bytes.3.From DDR3 SDRAM datasheet.4.These are optional, in accordance with the JEDEC spec.2.0 Details of each byte2.1 General Section: Bytes 0 to 59This section contains defines bytes that are common to all DDR3 module types.Byte 0: Number of Bytes Used / Number of Bytes in SPD Device / CRC CoverageThe least significant nibble of this byte describes the total number of bytes used by the module manufacturer for the SPD data and any (optional) specific supplier information. The byte count includes the fields for all required and optional data.Bits 6 ~ 4 describe the total size of the serial memory used to hold the Serial Presence Detect data. Bit 7 indicates whether the unique module identifier (found in bytes 117 ~ 125) is covered by the CRC encoded on bytes 126 and 127.Byte 1: SPD RevisionThis byte describes the compatibility level of the encoding of the bytes contained in the SPD EEPROM, and the current collection of valid defined bytes. This byte must be coded as 0x10 for SPDs with revision level 1.0. Software shouldexamine the upper nibble (Encoding Level) to determine if it can correctly interpret the contents of the module SPD. The lower nibble (Additions Level) can optionally be used to determine which additional bytes or attribute bits have been defined; however, since any undefined additional byte must be encoded as 0x00 or undefined attribute bit must bedefined as 0, software can safely detect additional bytes and use safe defaults if a zero encoding is read for these bytes.The Additions Level is never reduced even after an increment of the Encoding Level. For example, if the current SPD revision level were 1.2 and a change in Encoding Level were approved, the next revision level would be 2.2. If additions to revision 2.2 were approved, the next revision would be 2.3. Changes in the Encoding Level are extremely rare, how-ever, since they can create incompatibilities with older systems.The exceptions to the above rule are the SPD revision levels used during development prior to the Revision 1.0 release. Revisions 0.0 through 0.9 are used to indicate sequential pre-production SPD revision levels, however the first production release will be Revision 1.0.Bit 7Bits 6 ~ 4Bits 3 ~ 0CRC CoverageSPD Bytes TotalSPD Bytes Used0 = CRC covers bytes 0 ~ 125 1 = CRC covers bytes 0 ~ 116 Bit [6, 5, 4] :000 = Undefined001 = 256All others reservedBit [3, 2, 1, 0] :0000 = Undefined 0001 = 128 0010 = 176 0011 = 256All others reservedProduction Status SPD Revision Encoding Level Additions LevelHex Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Pre-productionRevision0.00000000000Revision 0.10000000101............Revision0.90000100109Production Revision1.00001000010Revision 1.10001000111..............UndefinedUndefined11111111FFByte 2: Key Byte / DRAM Device TypeThis byte is the key byte used by the system BIOS to determine how to interpret all other bytes in the SPD EEPROM. The BIOS must check this byte first to ensure that the EEPROM data is interpreted correctly. Any DRAM or Module type that requires significant changes to the SPD format (beyond defining previously undefined bytes or bits) also requires a new entry in the key byte table below.Line #SDRAM / Module TypeCorresponding to Key ByteBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Hex0Reserved0000000000 1Standard FPM DRAM0000000101 2EDO0000001002 3Pipelined Nibble0000001103 4SDRAM0000010004 5ROM0000010105 6DDR SGRAM0000011006 7DDR SDRAM0000011107 8DDR2SDRAM0000100008 9DDR2SDRAM FB-DIMM000010010910DDR2 SDRAM FB-DIMMPROBE000010100A11DDR3SDRAM000010110B -----------253Reserved11111101FD 254Reserved11111110FE 255Reserved11111111FFByte 3: Key Byte / Module TypeThis byte is a Key Byte used to index the module specific section of the SPD from bytes 60 ~ 116. Byte 3 identifies the SDRAM memory module type which implies the width (D dimension) of the module. Other module physical characteris-tics, such as height (A dimension) or thickness (E dimension) are documented in the module specific section of the SPD. Refer to the relevant JEDEC JC-11 module outline (MO) documents for dimension definitions.Byte 4: SDRAM Density and BanksThis byte defines the total density of the DDR3 SDRAM, in bits, and the number of internal banks into which the memory array is divided. These values come from the DDR3 SDRAM data sheet.Bits 7 ~ 4Bits 3 ~ 0ReservedModule TypeBit [3, 2, 1, 0] :0000 = Undefined0001 = RDIMM (width = 133.35 mm nom) 0010 = UDIMM (width = 133.35 mm nom) 0011 = SO-DIMM (width = 67.6 mm nom) 0100 = Micro-DIMM (width = TBD mm nom) 0101 = Mini-RDIMM (width = TBD mm nom) 0110 = Mini-UDIMM (width = TBD mm nom)All others reserved Definitions:RDIMM: Registered Dual In-Line Memory Module UDIMM: Unbuffered Dual In-Line Memory ModuleSO-DIMM: Small Outline Dual In-Line Memory Module Micro-DIMM: Micro Dual In-Line Memory ModuleMini-RDIMM: Mini Registered Dual In-Line Memory Module Mini-UDIMM: Mini Unbuffered Dual In-Line Memory ModuleBit 7Bits 6 ~ 4Bits 3 ~ 0ReservedBank Address BitsTotal SDRAM capacity, in megabitsBit [6, 5, 4] :000 = 3 (8 banks) 001 = 4 (16 banks) 010 = 5 (32 banks) 011 = 6 (64 banks) All others reservedBit [3, 2, 1, 0] : 0000 = 256 Mb 0001 = 512 Mb 0010 = 1 Gb 0011 = 2 Gb 0100 = 4 Gb 0101 = 8 Gb0110 = 16 GbAll others reservedByte 5: SDRAM AddressingThis byte describes the row addressing and the column addressing in the SDRAM device. Bits 2 ~ 0 encode the number of column address bits, and bits 5 ~ 3 encode the number of row address bits. These values come from the DDR3 SDRAM data sheet.Byte 6: Module Nominal Voltage, VDDThis byte describes the Voltage Level for DRAM and other components on the module such as the register if applicable. Note that SPDs or thermal sensor components are on the VDDSPD supply and are not affected by this byte.'Operable' is defined as the VDD voltage at which module operation is allowed using the performance values programmed in the SPD.'Endurant' is defined as the VDD voltage at which the module may be powered without adversely affecting the lifeexpectancy or reliability. Further specifications will exist to define the amount of time that the ‘Endurant’ voltage can be applied to the module. Operation is not supported at this voltage.Examples:A value on bits 2~0 of 000 implies that the device supports nominal operable voltage of 1.5 V only.A value on bits 2~0 of 010 implies that the device supports nominal operable voltages of 1.35 V and 1.5 V.A value on bits 2~0 of 110 implies that the device supports nominal operable voltages of 1.2X V, 1.35 V, or 1.5 V.A value on bits 2~0 of 111 implies that the device supports nominal operable voltages of 1.2X V or 1.35 V. The device is furthermore endurant to 1.5 V.Byte 7: Module OrganizationThis byte describes the organization of the SDRAM module. Bits 2 ~ 0 encode the device width of the SDRAM devices. Bits 5 ~ 3 encode the number of physical ranks on the module. For example, for a double-rank module with x8 DRAMs, this byte is encoded 00 001 001, or 0x09.Bits 7 ~ 6Bits 5 ~ 3Bits 2 ~ 0ReservedRow Address BitsColumn Address BitsBit [5, 4, 3] : 000 = 12 001 = 13 010 = 14 011 = 15 100 = 16All others reservedBit [2, 1, 0] : 000 = 9 001 = 10 010 = 11 011 = 12All others reservedByte 6: Module Nominal Voltage, VDDReserved Module Minimum Nominal Voltage, VDDBit 7~3Bit 2Bit 1Bit 0Reserved0 = NOT 1.2X V operable 1 = 1.2X V operable0 = NOT 1.35 V operable 1 = 1.35 V operable0 = 1.5 V operable1 = NOT 1.5 V operableNotes:1.35 V LV DDR3 devices are required to be 1.5 V operable.All DDR3 devices are required to be 1.5 V endurant.The value on Bit 0 uses a different polarity as compared to Bits 1 and 2 for backward compatibility with previous DDR3 SPD definitions.Byte 8: Module Memory Bus WidthThis byte describes the width of the SDRAM memory bus on the module. Bits 2 ~ 0 encode the primary bus width. Bits 4 ~ 3 encode the bus extensions such as parity or ECC.Examples:•64 bit primary bus, no parity or ECC (64 bits total width): xxx 000 011•64 bit primary bus, with 8 bit ECC (72 bits total width): xxx 001 011Calculating Module CapacityThe total memory capacity of the module may be calculated from SPD values. For example, to calculate the total capacity, in megabytes or gigabytes, of a typical module:•SDRAM CAPACITY ÷ 8 * PRIMARY BUS WIDTH ÷ SDRAM WIDTH * RANKSwhere:•SDRAM CAPACITY = SPD byte 4 bits 3~0•PRIMARY BUS WIDTH = SPD byte 8 bits 2~0•SDRAM WIDTH = SPD byte 7 bits 2~0•RANKS = SPD byte 7 bits 5~3Example: 2 ranks of 1 Gb SDRAMs with x4 organization on a module with a 64 bit primary bus:•1 Gb ÷ 8 * 64 ÷ 4 * 2 = 4 GBExample: 1 rank of 2 Gb SDRAMs with x8 organization on a module with a 64 bit primary bus:•2 Gb ÷ 8 * 64 ÷ 8 * 1 = 2 GBBits 7 ~ 6Bits 5 ~ 3Bits 2 ~ 0ReservedNumber of RanksSDRAM Device WidthBit [5, 4, 3] : 000 = 1 Rank 001 = 2 Ranks 010 = 3 Ranks 011 = 4 Ranks All others reservedBit [2, 1, 0] : 000 = 4 bits 001 = 8 bits 010 = 16 bits 011 = 32 bitsAll others reservedBits 7 ~ 5Bits 4 ~ 3Bits 2 ~ 0ReservedBus width extension, in bitsPrimary bus width, in bitsBit [4, 3] :000 = 0 bits (no extension) 001 = 8 bitsAll others reservedBit [2, 1, 0] : 000 = 8 bits 001 = 16 bits 010 = 32 bits 011 = 64 bitsAll others reservedCommonly, parity or ECC are not counted in total module capacity, though they can also be included by adding the bus width extension in SPD byte 8 bits 4 ~ 3 to the primary bus width in the previous examples.Byte 9: Fine Timebase (FTB) Dividend / DivisorThis byte defines a value in picoseconds that represents the fundamental timebase for fine grain timing calculations. This value is used as a multiplier for formulating subsequent timing parameters. The fine timebase (FTB) is defined as the fine timebase dividend, bits 7 ~ 4, divided by the fine timebase divisor, bits 3 ~ 0.Examples:Byte 10: Medium Timebase (MTB) Dividend Byte 11: Medium Timebase (MTB) DivisorThese bytes define a value in nanoseconds that represents the fundamental timebase for medium grain timing calcula-tions. This value is typically the greatest common divisor for the range of clock frequencies (clock periods) supported by a particular SDRAM. This value is used as a multiplier for formulating subsequent timing parameters. The medium time-base (MTB) is defined as the medium timebase dividend (byte 10) divided by the medium timebase divisor (byte 11).Examples:To simplify BIOS implementation, DIMMs associated with a given key byte value may differ in MTB value only by a factor of two. For DDR3 modules, the defined MTB values are:Bits 7 ~ 4Bits 3 ~ 0Fine Timebase (FTB) DividendFine Timebase (FTB) DivisorValues defined from 1 to 15 Values defined from 1 to 15DividendDivisor Timebase (ps)Use515When time granularity of 5 ps is required 522.5When time granularity of 2.5 ps is requiredByte 10 Bits 7 ~ 0Byte 11 Bits 7 ~ 0Medium Timebase (MTB) DividendMedium Timebase (MTB) DivisorValues defined from 1 to 255Values defined from 1 to 255DividendDivisor Timebase (ns)Use180.125For clock frequencies of 400, 533, 667, and 800 MHzDividendDivisor Timebase (ns)Use180.125MTB Value for DDR31160.0625Reserved for future useByte 12: SDRAM Minimum Cycle Time (t CK min)This byte defines the minimum cycle time for the SDRAM module, in medium timebase (MTB) units. This number applies to all applicable components on the module. This byte applies to SDRAM and support components as well as the overall capability of the DIMM. This value comes from the DDR3 SDRAM and support component data sheets.Examples:Byte 13: ReservedBits 7 ~ 0Minimum SDRAM Cycle Time (t CK min)MTB UnitsValues defined from 1 to 255tCKmin (MTB units)Timebase(ns)tCKmin Result(ns)Use200.125 2.5DDR3 with 400 MHz clock 150.125 1.875DDR3 with 533 MHz clock 120.125 1.5DDR3 with 667 MHz clock 100.125 1.25DDR3 with 800 MHz clockByte 14: CAS Latencies Supported, Least Significant Byte Byte 15: CAS Latencies Supported, Most Significant ByteThese bytes define which CAS Latency (CL) values are supported. The range is from CL = 4 through CL = 18 with one bit per possible CAS Latency. A 1 in a bit position means that CL is supported, a 0 in that bit position means it is not sup-ported. Since CL = 6 is required for all DDR3 speed bins, bit 2 of SPD byte 14 is always 1. These values come from the DDR3 SDRAM data sheet.Example: DDR3-1600KByte 14 = 0xD4 (= 1101 0100) -- low byte.Byte 15 = 0x00 (= 0000 0000) -- high byte .Results: Actual CAS Latencies supported = 6, 8, 10, and 11.Byte 16: Minimum CAS Latency Time (t AA min)This byte defines the minimum CAS Latency in medium timebase (MTB) units. Software can use this information, along with the CAS Latencies supported (found in bytes 14 and 15) to determine the optimal cycle time for a particular module. This value comes from the DDR3 SDRAM data sheet.Examples:Byte 14: CAS Latencies Supported, Low ByteBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0CL = 11CL = 10CL = 9CL = 8CL = 7CL = 6CL = 5CL = 40 or 10 or 10 or 10 or 10 or 110 or 10 or 1Byte 15: CAS Latencies Supported, High ByteBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Reserved CL = 18CL = 17CL = 16CL = 15CL = 14CL = 13CL = 120 or 10 or 10 or 10 or 10 or 10 or 10 or 1For each bit position, 0 means this CAS Latency is not supported, 1 means this CAS Latency is supported.CAS Latencies x 181716151413121110987654CL Mask1111Bits 7 ~ 0Minimum SDRAM CAS Latency Time (t AA min)MTB Units Values defined from 1 to 255tAAmin (MTB units)Timebase (ns)tAAmin Result(ns)Use1000.12512.5DDR3-800D 1200.12515DDR3-800E 900.12511.25DDR3-1066E 1050.12513.125DDR3-1066F 1200.12515DDR3-1066G 840.12510.5DDR3-1333F 960.12512DDR3-1333G 1080.12513.5DDR3-1333HCAS Latency Calculation and ExamplesCAS latency is not a purely analog value as DDR3 SDRAMs use the DLL to synchronize data and strobe outputs with the clock. All possible frequencies may not be tested, therefore an application should use the next smaller JEDEC standard tCKmin value (2.5, 1.875, 1.5, or 1.25 ns for DDR3 SDRAMs) when calculating CAS Latency. This section shows how the BIOS may calculate CAS latency based on Bytes 12 ~ 16.Step 1: Determine the common set of supported CAS Latency values for all modules on the memory channel using the CAS Latencies Supported in SPD bytes 14 and 15.Step 2: Determine tAAmin(all) which is the largest tAAmin value for all modules on the memory channel (SPD byte 16).Step 3: Determine tCKmin(all) which is the largest tCKmin value for all modules on the memory channel (SPD byte 12).Step 4: For a proposed tCK value (tCKproposed) between tCKmin(all) and tCKmax, determine the desired CAS Latency. If tCKproposed is not a standard JEDEC value (2.5, 1.875, 1.5, or 1.25 ns) then tCKproposed must be adjusted to the next lower standard tCK value for calculating CLdesired.CLdesired = ceiling ( tAAmin(all) / tCKproposed )where tAAmin is defined in Byte 16. The ceiling function requires that the quotient be rounded up always.Step 5: Chose an actual CAS Latency (CLactual) that is greater than or equal to CLdesired and is supported by all mod-ules on the memory channel as determined in step 1. If no such value exists, choose a higher tCKproposed value and repeat steps 4 and 5 until a solution is found.1200.12515DDR3-1333J 800.12510DDR3-1600G 900.12511.25DDR3-1600H 1000.12512.5DDR3-1600J 1100.12513.75DDR3-1600KtAAmin (MTB units)Timebase (ns)tAAmin Result(ns)UseStep 6: Once the calculation of CLactual is completed, the BIOS must also verify that this CAS Latency value does not exceed tAAmax, which is 20 ns for all DDR3 speed grades, by multiplying CLactual times tCKproposed. If not, choose a lower CL value and repeat steps 5 and 6 until a solution is found.Example 1: Slot 0 = DDR3-1066E 6-6-6, Slot 1 = DDR3-1333H 9-9-9Step 1: CL in slot 0 = 5, 6, 7, 8; CL in slot 1 = 6, 8, 9; Common CL = 6, 8Step 2: tAAmin in slot 0 = 11.25 ns; tAAmin in slot 1 = 13.5 ns; tAAmin(all) = 13.5 ns Step 3: tCKmin in slot 0 = 1.875 ns; tCKmin in slot 1 = 1.5 ns; tCKproposed = 1.875 ns Step 4: CLdesired = ceiling( 13.5 / 1.875 ) = 8Step 5: CLactual = CLdesiredStep 6: CLactual * tCKproposed = 8 * 1.875 = 15 < 20 ns ... value is okay Results: tCKactual = 1.875 ns, CLactual = 8Example 2: Slot 0 = DDR3-800D 5-5-5, Slot 1 = DDR3-1066G 8-8-8Step 1: CL in slot 0 = 5, 6; CL in slot 1 = 6, 8; Common CL = 6Step 2: tAAmin in slot 0 = 12.5 ns; tAAmin in slot 1 = 15 ns; tAAmin(all) = 15 nsStep 3: tCKmin in slot 0 = 2.5 ns; tAAmin in slot 1 = 1.875 ns; tCKproposed = 2.5 ns Step 4: CLdesired = ceiling( 15 / 2.5 ns) = 6Step 5: CLactual = CLdesiredStep 6: CLactual * tCKproposed = 6 * 2.5 = 15 < 20 ns ... value is okay Results: tCKactual = 2.5 ns, CLactual = 6Example 3: Slot 0 = DDR3-800D 5-5-5, Slot 1 = DDR3-1066G 8-8-8, System Bringup & Debug limits operating frequency to 333 MHz (tCK = 3.3 ns)Step 1: CL in slot 0 = 5, 6; CL in slot 1 = 6, 8; Common CL = 6Step 2: tAAmin in slot 0 = 12.5 ns; tAAmin in slot 1 = 15 ns; tAAmin(all) = 15 ns Step 3: tCKproposed = 3.3 nsStep 4: CLdesired = ceiling( 15 / 3.3 ns) = 5Step 5: CLactual = 6Step 6: CLactual * tCKproposed = 6 * 3.3 = 19.8 < 20 ns ... value is okay Results: tCKactual = 3.3 ns, CLactual = 6Byte 17: Minimum Write Recovery Time (t WR min)This byte defines the minimum SDRAM write recovery time in medium timebase (MTB) units. This value comes from the DDR3 SDRAM data sheet.Example:Step 1: The BIOS first determines the common operating frequency of all modules in the system, ensuring that the corresponding value of tCK (tCKactual) falls between tCKmin (Byte 12) and tCKmax. If tCKactual is not a JEDEC standard value, the next smaller standard tCKmin value is used for calculating Write Recovery.Step 2: The BIOS then calculates the “desired” Write Recovery (WRdesired):WRdesired = ceiling ( tWRmin / tCKactual )Bits 7 ~ 0Minimum Write Recovery Time (t WR )MTB Units Values defined from 1 to 255tWRmin (MTB units)Timebase (ns)tWR Result(ns)Use1200.12515All DDR3 speed gradeswhere tWRmin is defined in Byte 17. The ceiling function requires that the quotient be rounded up always.Step 3: The BIOS then determines the “actual” Write Recovery (WRactual):WRactual = max ( WRdesired, min WR supported)where min WR is the lowest Write Recovery supported by the DDR3 SDRAM. Note that not all WR values supported by DDR3 SDRAMs are sequential, so the next higher supported WR value must be used in some age example for DDR3-1333G operating at DDR3-1333:tCKactual = 1.5 nsWRdesired = 15 / 1.5 = 10WRactual = max(10, 10) = 10Byte 18: Minimum RAS# to CAS# Delay Time (t RCD min)This byte defines the minimum SDRAM RAS# to CAS# Delay in medium timebase (MTB) units. This value comes from the DDR3 SDRAM data sheet.Examples:Byte 19: Minimum Row Active to Row Active Delay Time (t RRD min)This byte defines the minimum SDRAM Row Active to Row Active Delay Time in medium timebase units. This value comes from the DDR3 SDRAM data sheet. The value of this number may be dependent on the SDRAM page size; please refer to the DDR3 SDRAM data sheet section on Addressing to determine the page size for these devices. Con-troller designers must also note that at some frequencies, a minimum number of clocks may be required resulting in a larger tRRDmin value than indicated in the SPD. For example, tRRDmin for DDR3-800 must be 4 clocks.Bits 7 ~ 0Minimum RAS# to CAS# Delay (t RCD )MTB Units Values defined from 1 to 255tRCD (MTB units)Timebase (ns)tRCD Result(ns)Use1000.12512.5DDR3-800D 1200.12515DDR3-800E 900.12511.25DDR3-1066E 1050.12513.125DDR3-1066F 1200.12515DDR3-1066G 840.12510.5DDR3-1333F 960.12512DDR3-1333G 1080.12513.5DDR3-1333H 1200.12515DDR3-1333J 800.12510DDR3-1600G 900.12511.25DDR3-1600H 1000.12512.5DDR3-1600J 1100.12513.75DDR3-1600KExamples:Byte 20: Minimum Row Precharge Delay Time (t RP min)This byte defines the minimum SDRAM Row Precharge Delay Time in medium timebase (MTB) units. This value comes from the DDR3 SDRAM data sheet.Examples:Byte 21: Upper Nibbles for t RAS and t RCThis byte defines the most significant nibbles for the values of tRAS (byte 22) and tRC (byte 23). These values come from the DDR3 SDRAM data sheet.Bits 7 ~ 0Minimum Row Active to Row Active Delay (t RRD )MTB Units Values defined from 1 to 255tRRD (MTB units)Timebase (ns)tRRD Result(ns)Use480.125 6.0Example: DDR3-1333, 1KB page size 600.1257.5Example: DDR3-1333, 2KB page size 800.12510Example: DDR3-800, 1KB page sizeNote: tRRD is at least 4nCK independent of operating frequency.Bits 7 ~ 0Minimum Row Precharge Time (t RP )MTB Units Values defined from 1 to 255tRP (MTB units)Timebase (ns)tRP Result(ns)Use1000.12512.5DDR3-800D 1200.12515DDR3-800E 900.12511.25DDR3-1066E 1050.12513.125DDR3-1066F 1200.12515DDR3-1066G 840.12510.5DDR3-1333F 960.12512DDR3-1333G 1080.12513.5DDR3-1333H 1200.12515DDR3-1333J 800.12510DDR3-1600G 900.12511.25DDR3-1600H 1000.12512.5DDR3-1600J 1100.12513.75DDR3-1600KBits 7 ~ 4Bits 3 ~ 0t RC Most Significant Nibblet RAS Most Significant NibbleSee Byte 23 descriptionSee Byte 22 descriptionByte 22: Minimum Active to Precharge Delay Time (t RAS min), Least Significant ByteThe lower nibble of Byte 21 and the contents of Byte 22 combined create a 12-bit value which defines the minimum SDRAM Active to Precharge Delay Time in medium timebase (MTB) units. The most significant bit is Bit 3 of Byte 21, and the least significant bit is Bit 0 of Byte 22. This value comes from the DDR3 SDRAM data sheet.Examples:Byte 23: Minimum Active to Active/Refresh Delay Time (t RC min), Least Significant ByteThe upper nibble of Byte 21 and the contents of Byte 23 combined create a 12-bit value which defines the minimum SDRAM Active to Active/Refresh Delay Time in medium timebase (MTB) units. The most significant bit is Bit 7 of Byte 21, and the least significant bit is Bit 0 of Byte 23. This value comes from the DDR3 SDRAM data sheet.Examples:Byte 21 Bits 3 ~ 0, Byte 22 Bits 7 ~ 0Minimum Active to Precharge Time (t RAS )MTB Units Values defined from 1 to 4095tRAS (MTB units)Timebase (ns)tRAS Result(ns)Use3000.12537.5DDR3-800D 3000.12537.5DDR3-800E 3000.12537.5DDR3-1066E 3000.12537.5DDR3-1066F 3000.12537.5DDR3-1066G 2880.12536DDR3-1333F 2880.12536DDR3-1333G 2880.12536DDR3-1333H 2880.12536DDR3-1333J 2800.12535DDR3-1600G 2800.12535DDR3-1600H 2800.12535DDR3-1600J 2800.12535DDR3-1600KByte 21 Bits 7 ~ 4, Byte 23 Bits 7 ~ 0Minimum Active to Active/Refresh Time (t RC )MTB Units Values defined from 1 to 4095tRC (MTB units)Timebase (ns)tRC Result(ns)Use4000.12550DDR3-800D 4200.12552.5DDR3-800E 3900.12548.75DDR3-1066E 4050.12550.625DDR3-1066F 4200.12552.5DDR3-1066G 3720.12546.5DDR3-1333F 3840.12548DDR3-1333G 3960.12549.5DDR3-1333H 4080.12551DDR3-1333J 3600.12545DDR3-1600GByte 24: Minimum Refresh Recovery Delay Time (t RFC min), Least Significant Byte Byte 25: Minimum Refresh Recovery Delay Time (t RFC min), Most Significant ByteThe contents of Byte 24 and the contents of Byte 25 combined create a 16-bit value which defines the minimum SDRAM Refresh Recovery Time Delay in medium timebase (MTB) units. The most significant bit is Bit 7 of Byte 25, and the least significant bit is Bit 0 of Byte 24. These values come from the DDR3 SDRAM data sheet.Examples:Byte 26: Minimum Internal Write to Read Command Delay Time (t WTR min)This byte defines the minimum SDRAM Internal Write to Read Delay Time in medium timebase (MTB) units. This value comes from the DDR3 SDRAM data sheet. The value of this number may be dependent on the SDRAM page size; please refer to the DDR3 SDRAM data sheet section on Addressing to determine the page size for these devices. Con-troller designers must also note that at some frequencies, a minimum number of clocks may be required resulting in a larger tWTRmin value than indicated in the SPD. For example, tWTRmin for DDR3-800 must be 4 clocks.Examples:Byte 27: Minimum Internal Read to Precharge Command Delay Time (t RTP min)This byte defines the minimum SDRAM Internal Read to Precharge Delay Time in medium timebase (MTB) units. This value comes from the DDR3 SDRAM data sheet. The value of this number may be dependent on the SDRAM page size; please refer to the DDR3 SDRAM data sheet section on Addressing to determine the page size for these devices. Con-troller designers must also note that at some frequencies, a minimum number of clocks may be required resulting in a3700.12546.25DDR3-1600H 3800.12547.5DDR3-1600J 3900.12548.75DDR3-1600KByte 25 Bits 7 ~ 0, Byte 24 Bits 7 ~ 0Minimum Refresh Recover Time Delay (t RFC )MTB Units Values defined from 1 to 65535tRFC (MTB units)Timebase (ns)tRFC Result(ns)Use7200.12590512 Mb 8800.125110 1 Gb 12800.1251602 GbBits 7 ~ 0Internal Write to Read Delay Time (t WTR )MTB UnitsValues defined from 1 to 255tWTR (MTB units)Timebase (ns)tWTR Result(ns)Use600.1257.5All DDR3 SDRAM speed binsNote: tWTR is at least 4nCK independent of operating frequency.tRC (MTB units)Timebase (ns)tRC Result(ns)Use。
ddr
MDDR
MDDR是Mobile DDR的缩写，在一些行动电子设备中使用，像是使用移动、手持设备、数字音频播放器等。通 过包括降低电源电压和先进的刷新选项（advanced refresh options）技术，MDDR可以实现更高的电源效 率。
公式
利用下列公式，就可以计算出DDR SDRAM时钟频率。
ddr
双倍数据速率
01 简介
目录
02 规格
03 高密度比低密度
04 替换
05 MDDR
06 公式
DDR=Double Data Rate双倍速率,DDR SDRAM=双倍速率同步动态随机存储器，人们习惯称为DDR，其中， SDRAM是Synchronous Dynamic Random Access Memory的缩写，即同步动态随机存取存储器。而DDR SDRAM是 Double Data Rate SDRAM的缩写，是双倍速率同步动态随机存储器的意思。DDR内存是在SDRAM内存基础上发展 而来的，仍然沿用SDRAM生产体系，因此对于内存厂商而言，只需对制造普通SDRAM的设备稍加改进，即可实现 DDR内存的生产，可有效的降低成本。
为了要增加内存的容量和带宽，芯片会利用模块结合。例如，有关 DIMMs的64位bus需要8个 8位的芯片并发 处理。与常见的线（address lines）的多个芯片被称为memory rank。这个术语被引入，是要避免与芯片内部 row和bank的混乱。
高密度比低密度
PC3200是使用带宽 3200 MB / s的DDR - 400芯片设计，在200 MHz的DDR SDRAM由于 PC3200内存的上升 和下降时钟边沿的数据传输，其有效的时钟速率为 400 MHz。
DDR SDRAM之间有很大的设计上的差异，设计不同的时钟频率，例如，PC-1600被设计运行在100 MHz，至于 PC-2100被设计运行在133 MHz。
GDDR6给FPGA带来的大带宽存储优势以及性能测试
GDDR6给FPGA带来的大带宽存储优势以及性能测试在这样的数据高速增长的状况下，用于传输数据的网络带宽和处理数据所需要的算力也必需急速增长。
传统的CPU已经越来越不堪重负，所以用硬件加速来减轻CPU的负担是满足将来性能需求的重要进展方向。
将来的硬件进展需求对于用于加速的硬件平台提出了越来越高的要求，可以概括为三个方面：算力、数据传输带宽和存储器带宽。
Achronix的新一代采纳台积电7nm工艺的Speedster 7t FPGA芯片按照将来硬件加速和网络加速的需求，在这三个方面都做了优化，消退了传统FPGA的瓶颈。
下面我们重点说一说为了提高存储器带宽，Achronix 通过采纳硬核GDDR6控制器所带来的优势。
2. GDDR6的进展在GDDR的设计之初，其定位是针对图形显示卡所特殊优化的一种DDR 内存。
由于2000年后电脑嬉戏特殊是3D嬉戏的进展和火爆，使运行电脑嬉戏的显卡需要有大量的高速图像数据交互需求，GDDR在这种状况下应运而生。
第一个GDDR标准是基于DDR的GDDR2，随后进展到了基于DDR3的GDDR5，在一段时光中十分流行。
2016年，GDDR5X正式发布，它引入了具有16n预取的四倍数据速率模式，但代价是拜访粒度从GDDR5的32Byte提高到了64Byte。
2018年，GDDR6发布，数据速率达到了16Gbps，带宽几乎是GDDR5X的两倍，同时采纳了双通道设计，拜访粒度和GDDR5一样是32Byte。
3. GDDR6 和 DDR4/5的比较GDDR向来以来是针对图形显示卡所优化的一种DDR内存。
由于显卡处理图像数据，特殊是3D图像数据对显存带宽的要求更高，GPU和GDDR 之间的数据交换十分频繁。
而DDR内存专注于与CPU举行数据交换的效率，因此对于整体存取性能、低延迟更为看重，所以在CPU和传统的FPGA中基本都是用DDR4。
随着硬件加速需求对于存储器的带宽提出了越来越高的要求，传统的第1页共2页。
JESD79-4第5章片上终结电阻ODT
JESD79-4第5章⽚上终结电阻ODTJESD79-4 第5章⽚上终结电阻ODT DDR4 SDRAM⽀持ODT功能，此功能可通过ODT引脚控制、写命令或模式寄存器设置默认阻值来调整x4与x8设备的DQ, DQS_t, DQS_c与DM_n信号的终结电阻，x8设备除了上述引脚还可通过MR1.A11=1调整TDQS_t, TDQS_c的终结电阻。
对于x16设备，ODT功能适⽤于DQU, DQL, DQSU_t, DQSU_c, DQSL_t, DQSL_c, DMU_n and DML_n信号。
ODT功能通过控制器独⽴的控制所有或任何⼀个DRAM的终结电阻来有效提⾼存储器接⼝上的信号完整性。
在下⾯的⽂档中可找到更加详细的ODT控制模式与ODT时序模式。
ODT控制模式在章节5.1中描述ODT同步模式在章节5.2中描述动态ODT特性在章节5.3中描述ODT异步模式在章节5.4中描述ODT缓冲禁⽤模式在章节5.5中的“PD模式中的ODT缓冲禁⽤模式”内进⾏描述ODT功能在⾃刷新模式中禁⽤，⼀个简单的ODT结构图在下图中进⾏描述。
图中的开关是受控于ODT控制逻辑的。
ODT控制逻辑包含外部ODT引脚输⼊、模式寄存器配置以及其他的控制信息如下⽂所⽰。
RTT的值是受控与模式寄存器内的配置信息，详细见章节3.5。
如果在⾃刷新模式或MR1{A10,A9,A8}={0,0,0}将RTT_Nom禁⽤之后，ODT引脚的控制就被忽略了。
5.1 ODT模式寄存器与ODT状态列表DDR4 SDRAM的ODT功能⼀共有四个状态为：终结电阻禁⽤、RTT_WR、RTT_Nom以及RTT_PARK。
当MR1{A10,A9,A8}或MR2 {A10:A9}或MR5 {A8:A6}这些配置域不为全零时，ODT的功能就是打开的。
在这种情况下，ODT的实际值则是由这些配置域来确定的。
在进⼊⾃刷新模式后，DRAM⾃动的将ODT禁⽤，并且将所有的终结电阻设置为⾼阻状态以抛弃所有的模式寄存器设置。
怎么看CPU与主板的兼容性
怎么看CPU与主板的兼容性CPU与主板的兼容性，不仅最大程度的影响计算机速度。
而且还是影响一台计算机的性价比，最主要组装电脑时CPU的主频和主板一定要搭配才能发挥CPU的最佳性能。
下面是小编为你整理的相关内容，希望对你有帮助。
CPU与主板兼容性怎么配1.适用类型台式机CPU系列酷睿i7 CPU频率主频3GHz 最大睿频3.5GHz 总线频率8GT/sCPU插槽插槽类型LGA 2011 针脚数目2011pinCPU内核核心代号Haswell-E CPU架构Haswell核心数量八核心线程数十六线程制作工艺22纳米热设计功耗TDP140 CPU缓存三级缓存20MB 内存控制器DDR4 2133超线程技术支持虚拟化技术Intel VT 64位处理器是Turbo Boost技术支持。
2. CPU频率主频3GHz指CPU工作频率为3GHZ,最大睿频3.5GHz指CPU超频后最大频率不可超过3.5GHZ以免损坏CPU。
CPU的主频，即CPU内核工作的时钟频率(CPU Clock Speed)。
通常所说的某某CPU是多少兆赫的，而这个多少兆赫就是“CPU的主频”。
很多人认为CPU的主频就是其运行速度，其实不然。
CPU的主频表示在CPU内数字脉冲信号震荡的速度，与CPU实际的运算能力并没有直接关系。
主频和实际的运算速度存在一定的关系，但目前还没有一个确定的公式能够定量两者的数值关系，因为CPU的运算速度还要看CPU的流水线的各方面的性能指标(缓存、指令集，CPU的位数等等)。
由于主频并不直接代表运算速度，所以在一定情况下，很可能会出现主频较高的CPU实际运算速度较低的现象。
比如AMD公司的AthlonXP系列CPU大多都能已较低的主频，达到英特尔公司的Pentium 4系列CPU较高主频的CPU性能，所以AthlonXP系列CPU才以PR值的方式来命名。
因此主频仅是CPU性能表现的一个方面，而不代表CPU的整体性能。
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the receiver • DQS is edge--aligned with data for READs; cen-
ter--aligned with data for WRITEs • Differential clock inputs (CK and CK) • DLL aligns DQ and DQS transitions with CK transi-
Arlington, Virginia 22201-3834 or call (703) 907-7559
JEDEC Standard No. 79E
DOUBLE DATA RATE (DDR) SDRAM SPECIFICATION
(From JEDEC Board Ballot JCB-99-70, and modified by numerous other Board Ballots, formulated under the cognizance of Committee JC-42.3 on DRAM Parametrics.) Standard No. 79 Revision Log. Release 1, June 2000 Release 2, May 2002 Release C, March 2003 Release D, January 2004 Release E, May 2004 Scope This comprehensive standard defines all required aspects of 64Mb through 1Gb DDR SDRAMs with X4/X8/X16 data interfaces, including features, functionality, ac and dc parametrics, packages and pin assignments. This scope will subsequently be expanded to formally apply to x32 devices, and higher density devices as well. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 64Mb through 1Gb, X4/X8/X16 DDR SDRAMs. System designs based on the required aspects of this specification will be supported by all DDR SDRAM vendors providing JEDEC compliant devices.
-i-
JEDEC Standard No. 79E
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JESD79E Page 1
DOUBLE DATA RATE (DDR) SDRAM SPECIFICATION
16 M X4 (4 M X4 X4 banks), 8 M X8 (2 M X8 X4 banks), 4 M X16 (1 M X16 X4 banks) 32 M X4 (8 M X4 X4 banks), 16 M X8 (4 M X8 X4 banks), 8 M X16 (2 M X16 X4 banks) 64 M X4 (16 M X4 X4 banks), 32 M X8 (8 M X8 X4 banks), 16 M X16 (4 M X16 X4 banks) 128 M X4 (32 M X4 X4 banks), 64 M X8 (16 M X8 X4 banks), 32 M X16 (8 M X16 X4 banks) 256 M X4 (64 M X4 X4 banks), 128 M X8 (32 M X8 X4 banks), 64 M X16 (16 M X16 X4 banks)
CL = 3 • AUTO PRECHARGE option for each burst access • Auto Refresh and Self Refresh Modes • 2.5 V (SSTL_2 compatible) I/O • VDDQ: +2.5 V ±0.2 V for DDR 200, 266, or 333
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FEATURES • Double--data--rate architecture; two data transfers
per clock cycle • Bidirectional, data strobe (DQS) is transmitted/re-
ceived with data, to be used in capturing data at
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JEDEC STANDARD
Double Data Rate (DDR) SDRAM Specification
JESD79E
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May 2005