rfc2734.IPv4 over IEEE 1394
BGP路由黑洞
案例精解:BGP路由黑洞2008-10-19 15:05:37标签:路由反射器路由黑洞同步BGP联邦什么是路由黑洞?简单的说,它会默默的将数据包丢弃,使所有数据包有去无回,下面来看一个案例:如图所示:R1和R2建立EBGP邻居关系R2和R5建立IBGP邻居关系R5和R7建立EBGP邻居关系R2、R3、R5之间运行RIPv2首先看配置:hostname r1interface Loopback0ip address 1.1.1.1 255.255.255.0interface Serial1/0ip address 192.168.12.1 255.255.255.0serial restart-delay 0router bgp 100no synchronizationbgp router-id 1.1.1.1bgp log-neighbor-changesnetwork 1.1.1.0 mask 255.255.255.0network 192.168.12.0neighbor 2.2.2.2 remote-as 200neighbor 2.2.2.2 ebgp-multihop 255neighbor 2.2.2.2 update-source Loopback0 no auto-summary!ip route 2.2.2.0 255.255.255.0 192.168.12.2hostname r2interface Loopback0ip address 2.2.2.2 255.255.255.0!interface Serial1/0ip address 192.168.23.2 255.255.255.0serial restart-delay 0!interface Serial1/1ip address 192.168.12.2 255.255.255.0serial restart-delay 0!interface Serial1/2ip address 192.168.24.2 255.255.255.0serial restart-delay 0!router ripversion 2network 2.0.0.0network 192.168.23.0no auto-summary!router bgp 200no synchronizationbgp log-neighbor-changesnetwork 192.168.12.0network 192.168.23.0neighbor 1.1.1.1 remote-as 100neighbor 1.1.1.1 ebgp-multihop 255neighbor 1.1.1.1 update-source Loopback0 neighbor 5.5.5.5 remote-as 200neighbor 5.5.5.5 update-source Loopback0 neighbor 5.5.5.5 next-hop-selfno auto-summary!ip route 1.1.1.0 255.255.255.0 192.168.12.1hostname r3interface Loopback0ip address 3.3.3.3 255.255.255.0!interface Serial1/0ip address 192.168.35.3 255.255.255.0serial restart-delay 0!interface Serial1/1ip address 192.168.23.3 255.255.255.0 serial restart-delay 0router ripversion 2network 3.0.0.0network 192.168.23.0network 192.168.35.0no auto-summaryhostname r5interface Loopback0ip address 5.5.5.5 255.255.255.0!interface FastEthernet0/0no ip addressshutdownduplex half!interface Serial1/0ip address 192.168.57.5 255.255.255.0 serial restart-delay 0!interface Serial1/1ip address 192.168.35.5 255.255.255.0 serial restart-delay 0!interface Serial1/2ip address 192.168.45.5 255.255.255.0 serial restart-delay 0!interface Serial1/3no ip addressshutdownserial restart-delay 0!router ripversion 2network 5.0.0.0network 192.168.35.0no auto-summary!router bgp 200no synchronizationbgp log-neighbor-changesbgp confederation identifier 200neighbor 3.3.3.3 remote-as 200neighbor 7.7.7.7 remote-as 300neighbor 7.7.7.7 ebgp-multihop 255neighbor 7.7.7.7 update-source Loopback0 no auto-summary!ip route 7.7.7.0 255.255.255.0 192.168.57.7interface Serial1/1ip address 192.168.57.7 255.255.255.0serial restart-delay 0!interface Serial1/2no ip addressshutdownserial restart-delay 0!interface Serial1/3no ip addressshutdownserial restart-delay 0!router bgp 300no synchronizationbgp log-neighbor-changesneighbor 5.5.5.5 remote-as 200neighbor 5.5.5.5 ebgp-multihop 255no auto-summary!ip route 5.5.5.0 255.255.255.0 192.168.57.5现在查看R1的路由表r7#sh ip routeB 1.1.1.0 [20/0] via 5.5.5.5, 00:02:54 //为节约篇幅未完整显示可见R7学到了R1的路由,从表面上看这个实验很完美,达了目的,然而这时问题出现了,作个测试,在R7上PING R1r7#ping 1.1.1.1Type escape sequence to abort.Sending 5, 0-byte ICMP Echos to 7.7.7.7, timeout:.....这究竟是怎么回事呢?原来,我们在R5上关闭了同步,这时它会将一条并没有优化的路由传送给R7,当R7要发向R1发包时,它看到R5是它的下一跳,于是将包发给R5,然后R5又查看它的路由表,发现到R1的下一跳是R2,并继续查找,发现在通过R3可以达到R2,于是它将数据送给R3,这时问题出现了,因为R3没有运行BGP,它不知道R1怎么走,于是它将数据包丢弃,从而造成路由黑洞。
MSI H410M PRO 主板用户手册说明书
1ContentsContentsSafety Information ...........................................................................................2Specifications ...................................................................................................3Rear I/O Panel .................................................................................................7LAN Port LED Status Table . (7)Overview of Components (8)CPU Socket .................................................................................................................9DIMM Slots................................................................................................................10M2_1~2: M.2 Slots ...................................................................................................10PCI_E1~2: PCIe Expansion Slots ..............................................................................11SATA1~4: SATA 6Gb/s Connectors ...........................................................................11JFP1, JFP2: Front Panel Connectors .......................................................................12JAUD1: Front Audio Connector ................................................................................12ATX_PWR1, CPU_PWR1: Power Connectors ...........................................................13JUSB1: USB 2.0 Connector ......................................................................................14JUSB2: USB 3.2 Gen 1 5Gbps Connector .................................................................14CPU_FAN1, SYS_FAN1: Fan Connectors .................................................................15JTPM1: TPM Module Connector ...............................................................................15JCI1: Chassis Intrusion Connector ...........................................................................16JCOM1: Serial Port Connector .................................................................................16JBAT1: Clear CMOS (Reset BIOS) Jumper ...............................................................17EZ Debug LED ...........................................................................................................17JRGB1: RGB LED connector (H410M PRO) ..............................................................18JRAINBOW1: Addressable RGB LED connector (H410M PRO) ...............................18UEFI BIOS . (19)BIOS Setup ................................................................................................................20Entering BIOS Setup .................................................................................................20Resetting BIOS ..........................................................................................................20Updating BIOS...........................................................................................................21Installing OS, Drivers & Utilities . (22)Installing Windows ® 10..............................................................................................22Installing Drivers ......................................................................................................22Installing Utilities .. (22)Thank you for purchasing the MSI ® H410M PRO/ H410M-A PRO/ H410M PRO-VH motherboard. This User Guide gives information about board layout, component overview, BIOS setup and software installation.Safety Information∙The components included in this package are prone to damage from electrostatic discharge (ESD). Please adhere to the following instructions to ensure successful computer assembly.∙Ensure that all components are securely connected. Loose connections may cause the computer to not recognize a component or fail to start.∙Hold the motherboard by the edges to avoid touching sensitive components. ∙It is recommended to wear an electrostatic discharge (ESD) wrist strap when handling the motherboard to prevent electrostatic damage. If an ESD wrist strap is not available, discharge yourself of static electricity by touching another metal object before handling the motherboard.∙Store the motherboard in an electrostatic shielding container or on an anti-static pad whenever the motherboard is not installed.∙Before turning on the computer, ensure that there are no loose screws or metal components on the motherboard or anywhere within the computer case.∙Do not boot the computer before installation is completed. This could cause permanent damage to the components as well as injury to the user.∙If you need help during any installation step, please consult a certified computer technician.∙Always turn off the power supply and unplug the power cord from the power outlet before installing or removing any computer component.∙Keep this user guide for future reference.∙Keep this motherboard away from humidity.∙Make sure that your electrical outlet provides the same voltage as is indicated on the PSU, before connecting the PSU to the electrical outlet.∙Place the power cord such a way that people can not step on it. Do not place anything over the power cord.∙All cautions and warnings on the motherboard should be noted.∙If any of the following situations arises, get the motherboard checked by service personnel:▪Liquid has penetrated into the computer.▪The motherboard has been exposed to moisture.▪The motherboard does not work well or you can not get it work according touser guide.▪The motherboard has been dropped and damaged.▪The motherboard has obvious sign of breakage.∙Do not leave this motherboard in an environment above 60°C (140°F), it may damage the motherboard.2Safety Information3Specifications4Specifications5SpecificationsPlease refer to http:///manual/mb/DRAGONCENTER2.pdf formore details.6SpecificationsH410M-A PRO)Audio 7.1-channel ConfigurationTo configure 7.1-channel audio, you have to connect front audio I/O module to JAUD1 connector and follow the below steps.1. Click on the Realtek HD Audio Manager > Advanced Settings to open the dialog below.2. Select Mute the rear output device, when a front headphone plugged in.3. Plug your speakers to audio jacks on rear and front I/O panel. When you plug intoa device at an audio jack, a dialogue window will pop up asking you which device is current connected.7Rear I/O PanelOverview of Components* Distance from the center of the CPU to the nearest DIMM slot. 8Overview of Components9Overview of ComponentsImportant∙Always unplug the power cord from the power outlet before installing or removing the CPU.∙Please retain the CPU protective cap after installing the processor. MSI will deal with Return Merchandise Authorization (RMA) requests if only the motherboard comes with the protective cap on the CPU socket.∙When installing a CPU, always remember to install a CPU heatsink. A CPU heatsink is necessary to prevent overheating and maintain system stability.∙Confirm that the CPU heatsink has formed a tight seal with the CPU before booting your system.∙Overheating can seriously damage the CPU and motherboard. Always make sure the cooling fans work properly to protect the CPU from overheating. Be sure to apply an even layer of thermal paste (or thermal tape) between the CPU and the heatsink to enhance heat dissipation.∙Whenever the CPU is not installed, always protect the CPU socket pins by covering the socket with the plastic cap.∙If you purchased a separate CPU and heatsink/ cooler, Please refer to the docu-mentation in the heatsink/ cooler package for more details about installation.10Overview of ComponentsImportant∙Always insert memory modules in the DIMMA1 slot first.∙To ensure system stability for Dual channel mode, memory modules must be of the same type, number and density.∙Some memory modules may operate at a lower frequency than the marked value when overclocking due to the memory frequency operates dependent on its Serial Presence Detect (SPD). Go to BIOS and find the DRAM Frequency to set the memory frequency if you want to operate the memory at the marked or at a higher frequency. ∙It is recommended to use a more efficient memory cooling system for full DIMMs installation or overclocking.∙The stability and compatibility of installed memory module depend on installed CPU and devices when overclocking.∙Please refer for more information on compatible memory.M2_1~2: M.2 SlotsPlease install the M.2 device into the M.2 slot as shown below.13StandoffSupplied11Overview of Componentsunplug the power supply power cable from the power outlet. Read the expansion card’s documentation to check for any necessary additional hardware or software changes.∙If you install a large and heavy graphics card, you need to use a tool such as MSI Gaming Series Graphics Card Bolster to support its weight to prevent deformationof the slot.SATA1~4: SATA 6Gb/s ConnectorsThese connectors are SATA 6Gb/s interface ports. Each connector can connect to one SATA device.⚠Important∙Please do not fold the SATA cable at a 90-degree angle. Data loss may result during transmission otherwise.∙SATA cables have identical plugs on either sides of the cable. However, it is recommended that the flat connector be connected to the motherboard for space saving purposes.∙SATA4 will be unavailable when installing M.2 SATA SSD in the M.2 slot.JFP1, JFP2: Front Panel ConnectorsJAUD1: Front Audio Connector12Overview of ComponentsATX_PWR1, CPU_PWR1: Power ConnectorsImportantMake sure that all the power cables are securely connected to a proper ATX power supply to ensure stable operation of the motherboard.13Overview of Components14Overview of ComponentsJUSB2: USB 3.2 Gen 1 5Gbps ConnectorImportantNote that the Power and Ground pins must be connected correctly to avoid possible damage.JUSB1: USB 2.0 ConnectorImportant∙Note that the VCC and Ground pins must be connected correctly to avoid possible damage.∙In order to recharge your iPad,iPhone and iPod through USB ports, please install MSI® DRAGON CENTER utility.15Overview of ComponentsImportantYou can adjust fan speed in BIOS > Hardware Monitor.CPU_FAN1, SYS_FAN1: Fan ConnectorsPWM Mode fan connectors provide constant 12V output and adjust fan speed with speed control signal. When you plug a 3-pin (Non-PWM) fan to a fan connector in PWM mode, the fan speed will always maintain at 100%, which might create a lot ofnoise.JTPM1: TPM Module ConnectorThis connector is for TPM (Trusted Platform Module). Please refer to the TPMJCI1: Chassis Intrusion Connector(default)intrusion event Using chassis intrusion detector1. Connect the JCI1 connector to the chassis intrusion switch/ sensor on thechassis.2. Close the chassis cover.3. Go to BIOS > SETTINGS > Security > Chassis Intrusion Configuration.4. Set Chassis Intrusion to Enabled.5. Press F10 to save and exit and then press the Enter key to select Yes.6. Once the chassis cover is opened again, a warning message will be displayed onscreen when the computer is turned on.Resetting the chassis intrusion warning1. Go to BIOS > SETTINGS > Security > Chassis Intrusion Configuration.2. Set Chassis Intrusion to Reset.3. Press F10 to save and exit and then press the Enter key to select Yes. JCOM1: Serial Port Connector16Overview of ComponentsJBAT1: Clear CMOS (Reset BIOS) JumperThere is CMOS memory onboard that is external powered from a battery located on the motherboard to save system configuration data. If you want to clear the system(default)BIOSResetting BIOS to default values1. Power off the computer and unplug the power cord.2. Use a jumper cap to short JBAT1 for about 5-10 seconds.3. Remove the jumper cap from JBAT1.4. Plug the power cord and power on the computer.EZ Debug LEDThese LEDs indicate the status of the motherboard.CPU - indicates CPU is not detected or fail.DRAM - indicates DRAM is not detected or fail.VGA - indicates GPU is not detected or fail.BOOT - indicates booting device is not detected or fail.17Overview of ComponentsJRGB1: RGB LED connector (H410M PRO)Important∙The JRGB connector supports up to 2 meters continuous 5050 RGB LED strips (12V/G/R/B) with the maximum power rating of 3A (12V).∙Always turn off the power supply and unplug the power cord from the power outlet before installing or removing the RGB LED strip.∙Please use MSI’s software to control the extended LED strip. JRAINBOW1: Addressable RGB LED connector (H410M PRO)The JRAINBOW connector allows you to connect the WS2812B Individually Addressable RGB LED strips 5V.CAUTIONDo not connect the wrong type of LED strips. The JRGB connector and the JRAINBOW connector provide different voltages, and connecting the 5V LED strip to the JRGB connector will result in damage to the LED strip.⚠Important∙The JRAINBOW connector supports up to 75 LEDs WS2812B Individually Address-able RGB LED strips (5V/Data/Ground) with the maximum power rating of 3A (5V). In the case of 20% brightness, the connector supports up to 200 LEDs.∙Always turn off the power supply and unplug the power cord from the power outlet before installing or removing the RGB LED strip.∙Please use MSI’s software to control the extended LED strip.18Overview of ComponentsUEFI BIOSMSI UEFI BIOS is compatible with UEFI (Unified Extensible Firmware Interface) architecture. UEFI has many new functions and advantages that traditional BIOS cannot achieve, and it will completely replace BIOS in the future. The MSI UEFI BIOS uses UEFI as the default boot mode to take full advantage of the new chipset’s capabilities. However, it still has a CSM (Compatibility Support Module) mode to be compatible with older devices. That allows you to replace legacy devices with UEFI compatible devices during the transition.⚠ImportantThe term BIOS in this user guide refers to UEFI BIOS unless otherwise noted. UEFI advantages∙Fast booting - UEFI can directly boot the operating system and save the BIOS self-test process. And also eliminates the time to switch to CSM mode during POST.∙Supports for hard drive partitions larger than 2 TB.∙Supports more than 4 primary partitions with a GUID Partition Table (GPT).∙Supports unlimited number of partitions.∙Supports full capabilities of new devices - new devices may not provide backward compatibility.∙Supports secure startup - UEFI can check the validity of the operating system to ensure that no malware tampers with the startup process.Incompatible UEFI cases∙32-bit Windows operating system - this motherboard supports only 64-bit Windows 10 operating system.∙Older graphics card - the system will detect your graphics card. When display a warning message There is no GOP (Graphics Output protocol) support detected in this graphics card.⚠ImportantWe recommend that you to use a GOP/ UEFI compatible graphics card.How to check the BIOS mode?19UEFI BIOSBIOS SetupThe default settings offer the optimal performance for system stability in normal conditions. You should always keep the default settings to avoid possible system damage or failure booting unless you are familiar with BIOS.⚠Important∙BIOS items are continuous update for better system performance. Therefore, the description may be slightly different from the latest BIOS and should be held for reference only. You could also refer to the HELP information panel for BIOS item description.∙The BIOS items will vary with the processor. Entering BIOS SetupPress Delete key, when the Press DEL key to enter Setup Menu, F11 to enter Boot Menu message appears on the screen during the boot process.Function keyF1: General HelpF2: Add/ Remove a favorite itemF3: Enter Favorites menuF4: Enter CPU Specifications menuF5: Enter Memory-Z menuF6: Load optimized defaultsF7: Switch between Advanced mode and EZ modeF8: Load Overclocking ProfileF9: Save Overclocking ProfileF10: Save Change and Reset*F12: Take a screenshot and save it to USB flash drive (FAT/ FAT32 format only). Ctrl+F: Enter Search page* When you press F10, a confirmation window appears and it provides the modification information. Select between Yes or No to confirm your choice. Resetting BIOSYou might need to restore the default BIOS setting to solve certain problems. There are several ways to reset BIOS:∙Go to BIOS and press F6 to load optimized defaults.∙Short the Clear CMOS jumper on the motherboard.⚠ImportantPlease refer to the Clear CMOS jumper section for resetting BIOS.20UEFI BIOSUpdating BIOSUpdating BIOS with M-FLASHBefore updating:Please download the latest BIOS file that matches your motherboard model from MSI website. And then save the BIOS file into the USB flash drive.Updating BIOS:1. Insert the USB flash drive that contains the update file into the USB port.2. Please refer the following methods to enter flash mode.▪Reboot and press Ctrl + F5 key during POST and click on Yes to reboot the system.▪Reboot and press Del key during POST to enter BIOS. Click the M-FLASH button and click on Yes to reboot the system.3. Select a BIOS file to perform the BIOS update process.4. When prompted click on Yes to start recovering BIOS.5. After the flashing process is 100% completed, the system will reboot automatically.Updating the BIOS with Dragon CenterBefore updating:Make sure the LAN driver is already installed and the internet connection is set properly.Updating BIOS:1. Install and launch MSI DRAGON CENTER and go to Support page.2. Select Live Update and click on Advance button.3. Click on Scan button to search the latest BIOS file.4. Select the BIOS file and click on Download icon to download and install the latest BIOS file.5. Click Next and choose In Windows mode. And then click Next and Start to start updating BIOS.6. After the flashing process is 100% completed, the system will restart automatically.21UEFI BIOSInstalling OS, Drivers & UtilitiesPlease download and update the latest utilities and drivers at Installing Windows® 101. Power on the computer.2. Insert the Windows® 10 installation disc/USB into your computer.3. Press the Restart button on the computer case.4. Press F11 key during the computer POST (Power-On Self Test) to get into BootMenu.5. Select the Windows® 10 installation disc/USB from the Boot Menu.6. Press any key when screen shows Press any key to boot from CD or DVD...message.7. Follow the instructions on the screen to install Windows® 10. Installing Drivers1. Start up your computer in Windows® 10.2. Insert MSI® Driver Disc into your optical drive.3. Click the Select to choose what happens with this disc pop-up notification,then select Run DVDSetup.exe to open the installer. If you turn off the AutoPlayfeature from the Windows Control Panel, you can still manually execute theDVDSetup.exe from the root path of the MSI Driver Disc.4. The installer will find and list all necessary drivers in the Drivers/Software tab.5. Click the Install button in the lower-right corner of the window.6. The drivers installation will then be in progress, after it has finished it will promptyou to restart.7. Click OK button to finish.8. Restart your computer.Installing UtilitiesBefore you install utilities, you must complete drivers installation.1. Open the installer as described above.2. Click the Utilities tab.3. Select the utilities you want to install.4. Click the Install button in the lower-right corner of the window.5. The utilities installation will then be in progress, after it has finished it willprompt you to restart.6. Click OK button to finish.7. Restart your computer.22Installing OS, Drivers & Utilities。
研控科技MS-Mini3E总线型混合伺服驱动器用户手册说明书
目录前言 (4)1概述 (5)1.1产品介绍 (5)1.2特性 (5)1.3应用领域 (5)1.4产品命名规则 (5)2性能指标 (6)2.1 EtherCAT特性 (6)2.2电气特性 (6)2.3使用环境 (6)3安装 (7)3.1安装尺寸 (7)3.2安装方法 (7)4 驱动器端口与接线 (8)4.1接线示意图 (8)4.2端口定义 (8)4.2.1状态指示界面 (8)4.2.2旋钮拨码 (9)4.2.3状态指示灯 (9)4.2.4 EtherCAT通讯端口 (9)4.2.5控制信号输入/输出端口 (10)4.2.6编码器输入端口 (10)4.2.7电机输出端口 (10)4.2.8电源输入端口 (10)4.3输入/输出端口操作 (11)5适配电机 (14)5.1电机尺寸 (14)5.2电机规格 (17)5.3技术参数 (17)5.4电机线规格(仅适用闭环电机) (18)5.5编码器线规格(仅适用闭环电机) (18)5.6电机接线图 (19)6 EtherCAT总线 (22)6.1 EtherCAT技术原理 (22)6.2 EtherCAT数据结构 (22)6.3 EtherCAT报文寻址 (23)6.3.1 设备寻址 (24)6.3.2 逻辑寻址 (25)6.4 EtherCAT分布时钟 (25)6.5 EtherCAT通信模式 (25)6.5.1 Free Run模式 (25)6.5.2 SM2/3模式 (26)6.5.3 DC模式 (26)6.6 EtherCAT状态机 (27)6.7 应用层协议COE (27)6.7.1 COE对象字典 (28)6.7.2 服务数据对象(SDO) (28)6.7.3 过程数据对象(PDO) (28)7驱动器控制协议CiA 402 (29)7.1 CIA402状态机 (29)7.2 工作模式 (30)7.3循环同步位置模式(CSP) (31)7.4 循环同步速度模式(CSV)........................................................ 错误!未定义书签。
海康雷达区间测速卡口方案
高清雷达测速卡口解决方案(IS-3013VR)目录第1 章概述 (1)1.1 应用背景 (1)1.2 设计原则 (1)1.3 设计依据 (4)第2 章系统总体设计 (7)2.1 设计思想 (7)2.1.1坚持两个原则 (7)2.1.2遵循三个模式 (7)2.1.3保持四个一致 (7)2.2 技术路线 (8)2.2.1卡口系统前端设备技术路线 (8)2.2.2卡口系统中心管理平台技术路线 (8)2.3 系统结构 (9)2.4 系统组成 (10)2.5 功能描述 (11)2.5.1车辆捕获功能 (11)2.5.2车辆速度检测功能 (11)2.5.3车辆图像记录功能 (11)2.5.4超速抓拍功能 (12)2.5.5智能补光功能 (12)2.5.6车辆牌照自动识别功能 (13)2.5.7车身颜色识别功能 (14)2.5.8车型判别功能 (15)2.5.9车标识别功能 (15)2.5.10车辆子品牌识别功能 (15)2.5.11未系安全带检测功能 (15)2.5.12接打电话检测功能 (15)2.5.13人脸特征抠图 (15)2.5.14打开遮阳板检测 (16)2.5.15前端备份存储功能 (16)2.5.16数据断点续传功能 (16)2.5.17图像防篡改功能 (16)2.5.18网络远程维护功能 (16)2.5.19全景高清录像功能(选配) (16)2.5.20平台功能 (17)2.6 系统性能指标 (17)第3 章前端子系统设计 (20)3.1 前端子系统组成 (20)3.1.1前端子系统组成 (20)3.1.2车辆测速单元 (21)3.1.3图像采集识别处理单元 (21)3.1.4前端数据处理及上传单元 (22)3.1.5网络传输单元 (22)3.1.6视频监控单元(选配) (22)3.2 系统现场布局 (22)3.2.1现场布局俯视图 (23)3.2.2现场布局侧视图 (23)3.3 硬件设备配置原则 (23)3.4 前端系统主要设备选型 (24)3.4.1 300万卡口抓拍单元 (24)3.4.2雷达 (26)3.4.3补光灯 (27)3.4.4终端服务器 (28)第4 章网络传输子系统设计 (30)第5 章中心存储子系统设计 (31)5.1 存储方案 (31)5.1.1存储需求 (31)5.1.2存储技术对比 (31)5.1.3存储方案选择 (33)5.2 数据存储设计 (33)5.3 图片存储设计 (34)5.4 视频存储设计(选配) (34)第6 章中心管理平台子系统设计 (36)6.1 平台概述 (36)6.1.1平台整体架构 (36)6.1.2平台功能模块 (38)6.1.3平台业务支撑 (39)6.2 运行环境要求 (40)6.2.1硬件环境 (40)6.2.2软件环境 (41)6.2.3网络环境 (42)6.3 配置推荐原则 (42)6.4 平台功能设计 (51)6.4.1平台基础应用 (51)6.4.2平台增值应用 (72)6.4.3平台新技术应用 (90)第7 章系统特点 (99)7.1 一套卡口抓拍单元覆盖2/3个车道 (99)7.2 摄像机高密度集成技术应用提升卡口前端系统稳定性 (99)7.3 车牌前端识别技术 (99)7.4 视频检测模式保障系统工作稳定性 (100)7.5 雷达测速模式保障速度的准确性 (100)7.6 系统运维成本低 (101)7.7 前端系统结构简单稳定 (101)第8 章系统拍摄效果 (102)8.1 300万雷达卡口抓拍效果 (102)8.1.1白天抓拍效果 (102)8.1.2夜间抓拍效果 (104)。
IEEE1394
IEEE1394接口技术及其应用作者:王小丽来源:《电子世界》2011年第23期【摘要】本文详细分析了IEEE1394接口技术,并结合实例对其在中小电视台全数字化制作网络中的应用情况进行了阐述。
【关键词】IEEE1394;串行接口;局域网;应用技术1.引言IEEE1394最早由苹果(APPLE)、索尼(SONY)、美国德州仪器(Texas Instr-uments)等公司于提出,并于1995年由IEEE协会认定为IEEE1394-1995技术规范,全称为IEEE1394高性能串行总线标准。
IEEE1394作为一个工业标准的高速串行总线,其开放性、兼容性、非专利性以及该接口独具的传输速率高、支持同步、异步两种数据传输、价格低廉、占用空间小、支持即插即拨等优点而得到索尼、松下等著名公司的支持,并被不断完善发展。
目前广泛应用于个人PC机及专业摄、录、非线性编辑领域,成为视音频数据传输、交换最经济、简便的手段而得到飞速发展,为广播电视领域开辟了全数字化的从拍摄到制作的新环境。
2.IEEE1394接口技术(1)接口信号线及电器特性IEEE1394标准的接口信号线采用6芯电缆,其中4条信号线分别做成两对双绞线,用以传输信号,另外两条线是电源线,可通过IEEE1394接口为连接到主机上、功率不大的外围设备提供4~10V电源,并支持节能的挂机和唤醒模式,而且当设备断电或出现故障时,也不影响整个系统的正常运行。
(2)传输速率IEEE1394接口支持多种数据传输速率,其中IEEE1394a铜线电缆的数据传输速率为100Mbps、200Mbps、400Mbps。
按照IEEE1394-1995标准,数据传输速率为100Mbps、200Mbps、400Mbps的设备可以在同一网络上共存。
IEEE1394b接口进一步将数据传输速率提升到800Mbps,甚至1.6Gbps、3.2Gbps。
(3)传输距离IEEE1394接口连接电缆的传输距离与电缆线材参数有关:0.35mm铜线的传输距离(即两个节点之间)约为4.5米,0.5mm的铜线约为14m,而采用光纤则可将传输距离延长至100米以上。
ieee 1394
IEEE 1394a-2000(FireWire 400)
和IEEE 1394-1995几乎相同,改良数个地方之后制定的新规格。为了和后述的IEEE 1394b分别,因此称为“FireWire 400”。在工业上使用的时候,有时就单纯称呼为“.a”。
IEEE 1394b-2002(FireWire 800)
S1600和S3200
IEEE 1394的推广团体1394 Trade Association,在2007年12月宣布,将可以在2008年底使用新的扩张规格S1600(理论值达到1.6 Gbit/s)和S3200模式(理论值达3.2 Gbit/s)。这个扩张规格使用FireWire800现在使用的9 Pin接头和缆线,而且将会完全兼容于FireWire 400和FireWire 800的设备。这是为了迎战USB 3.0规格所作的准备。
FireWire 800即是理论最高速为800Mbps的高速规格,兼容于IEEE 1394a,但是接头的形状从IEEE 1394a的6 Pin变成9 Pin,因此需要经由转接线连接。在工业上使用的时候,有时就单纯称呼为“.b”。
IEEE 1394c-2006(FireWire S800T)
FireWire S800T公布于2007年6月8日,提供了一个重大的技术改进,新的接头规格和RJ45相同,并使用CAT-5(5类双绞线)和相同的自动协议,可以使用相同的端口来连接任何IEEE 1394设备或IEEE 802.3(1000BASE-T以太网双绞线)的设备。 虽然听起来相当地有魅力,但是直到2008年10月为止,市面上尚无任何产品或是芯片,包含这种能力。
IEEE1394接口是苹果公司开发的串行பைடு நூலகம்准,中文译名为火线接口(firewire)。同USB一样,IEEE1394也支持外设热插拔,可为外设提供电源,省去了外设自带的电源,能连接多个不同设备,支持同步数据传输。
2020年最新5G高级考试题库及答案——丽水市某信集团有限公司分公司二面试题等两套
温馨提示:同学们,经过培训学习,你一定积累了很多知识,现在请认真、仔细地完成这张试题吧。
加油!一、单选题( )1.VEM1一共支持_________________路的输入干接点。
A. 4B. 8C. 12D. 14正确答案:C( )2.HARQ-ACK是下列哪个的缩写A.Hybrid automatic repeatrequest acknowledgement;B.Hybrid automatic requestacknowledgement正确答案:A( )3.5G中sub-6GHz频段能支持的最大带宽为_________________A. 200MHzB. 100MHzC. 80MHzD. 60MHz正确答案:B( )4.低频信道传播损耗组成不包括_________________A.自由空间传播损耗B.穿透损耗C.雨衰和大气影响D.衍射绕射损耗正确答案:C( )5.除了IDLE状态外,NB-IoT引入了新的PSM状态,也就是终端关闭射频接收,进入休眠的状态,这种状态最长可以持续多长时间?A. 2.56hB. 2.92hC. 310hD. 620h正确答案:C( )6.对于SCS30kHz,BS侧100MHz带宽可以使用的RB数最多有几个?A.50B.100C.272D.273正确答案:D( )7.sub6G频段能支持的最大带宽为A.200MHz;B.100MHz;C.80MHz;D.60MHz正确答案:B( )8.对于上行PUCCH,下列说法错误的是_________________A. PUCCH包含5种格式B. PUCCHformat0可以反馈CSIC. PUCCH可以反馈ACK/NACKD. PUCCH可以反馈SR正确答案:B( )9.Which board can support NR?A. UMPTeB. LMPTC. UMPTaD. UMPTb正确答案:A( )10.NR小区SA部署时,Initial DL BWP的BW、SCS和CP由下面哪个CORESET定义A.CORESET0;B.CORESET1;C.CORESET2;D.CORESET3正确答案:A( )11.5GNR帧结构的基本时间单位是_________________A. subframeB. slotC. symbolD. Tc正确答案:D( )12.ZXRAN V9200支持_________________64T64R*100MHZ CellsA.15B.6C.30D.20正确答案:A( )13.除了Initial BWP之外,通过RRC signalling最多可以配置几个UL BWP、DL BWP或SULBWP_________________。
h248传输层承载的协议
H248传输层承载的协议引言H248传输层承载的协议(H.248/M eg ac o)是一种用于控制媒体网关的通信协议。
它定义了在媒体网关和控制器之间进行通信所使用的消息格式和过程,为实现语音、视频和数据的传输提供了支持。
本文将介绍H248传输层承载的协议的定义、特点、工作原理以及应用场景。
定义H248传输层承载的协议(H.248/M eg ac o)是国际电信联盟(IT U)制定的一项标准,用于控制媒体网关中的I P电话和传统电话系统之间的转换。
它通过定义消息格式和过程,提供了控制信令和媒体交互的能力。
特点H.248具有以下特点:协议灵活性1.:H.248协议对网关和控制器之间的通信进行了灵活的定义,使得不同厂商的设备可以通过此协议进行交互。
它采用基于文本的消息格式,使得协议扩展更加容易。
分布式架构2.:H.248协议使用分布式架构,将媒体控制器与媒体网关分开,实现了对媒体资源的统一管理和控制。
这种架构使得系统更加可靠和可扩展。
支持多种媒体类型3.:H.248协议可以同时控制语音、视频和数据等多种媒体类型的传输。
它定义了各种媒体的编解码方式、传输格式和参数设置等。
提供丰富的功能4.:H.248协议支持通话的建立、修改和终止操作,可以实现呼叫转接、媒体增强功能、音频/视频编码选择等丰富的功能。
工作原理H.248协议的工作原理如下:媒体网关注册1.:媒体网关通过与控制器建立T CP/I P连接并发送注册请求,完成媒体网关的注册过程。
资源描述2.:媒体网关向控制器发送资源描述消息,描述其支持的媒体类型、编码方式和传输参数等。
会话建立3.:控制器向媒体网关发送会话建立请求,包括呼叫号码、媒体类型和媒体描述等信息。
媒体协商4.:控制器与媒体网关进行媒体协商,协商媒体的编解码方式、传输格式和网络参数等。
媒体传输5.:媒体网关通过将媒体数据转发到合适的传输链路上,完成媒体的传输。
会话终止6.:控制器向媒体网关发送会话终止消息,终止当前会话并释放相关资源。
EPON-ONU-OLT配置手册
H3C EPON OLT 操作手册
目录
目录
第 1 章 EPON系统配置 ...........................................................................................................1-1 1.1 EPON系统简介 .................................................................................................................. 1-1 1.2 EPON系统配置任务简介.................................................................................................... 1-2 1.3 配置统计采样周期 .............................................................................................................. 1-3 1.3.1 配置统计采样周期.................................................................................................... 1-3 1.3.2 统计采样周期配置举例 ............................................................................................ 1-3 1.4 显示EPON系统端口信息.................................................................................................... 1-4 1.4.1 显示EPON系统端口信息 ......................................................................................... 1-5 1.4.2 EPON系统端口信息显示举例 .................................................................................. 1-5 1.5 EPON系统配置显示和维护 ................................................................................................ 1-6
工程师测试三
HDICT工程师测试三您的姓名: [填空题] *_________________________________1. "霸王锁体"的尺寸为?() [单选题] *A. 240mm*30mmB. 388mm*30mm(正确答案)C. 240mm*24mmD. 240mm*12mm2. 160MHz频宽,支持的空口速率约为(),实际使用约为() [单选题] *2400Mbps,1500Mbps(正确答案)2400Mbps,750Mbps1200Mbps,750Mbps1200Mbps,1500Mbps3. ARP协议的作用是由IP地址求MAC地址,ARP请求是单播发送,ARP响应是()发送。
[单选题] *光波广播(正确答案)组播无线电波4. FTTR光网关HN8145XR下行光口支持的速率是 [单选题] *A.下行2.488Gbps/上行1.244Gbps(正确答案)B.下行1000Mbps/上行1000MbpsC.下行2.488Gbps/上行2.488Gbps5. FTTR光网关最大支持下挂多少个光路由 [单选题] *A.8B.17C.22D.16(正确答案)6. FTTR施工明线施工线槽安装优点不包括() [单选题] *A.线缆不可见想对美观B.无需穿管器C.后期维护方便D.可靠性高(正确答案)7. G.657A1/A2普通皮线光纤盘纤半径应大于()mm [单选题] *A. 50(正确答案)B. 30C. 20D. 108. G.657B3微隐光纤过弯的弯曲半径应大于()mm [单选题] * A1B2C5(正确答案)D39. G.657B3微隐光纤盘纤半径应大于()mm [单选题] *A.30(正确答案)B.20C.10D.5010. ONU认证方式包含物理标识认证和()认证。
[单选题] *端口逻辑(正确答案)IP型号11. ONU设备加电后所有指示灯均不亮,可能原因包含以下那一项()。
1394芯片
1394芯片1394芯片,也叫做FireWire,是一种高速传输接口技术,最初由苹果公司在1995年推出。
它是一种基于串行总线架构的外部设备连接标准,用于连接各种多媒体设备,如相机、摄像机、音频设备、硬盘驱动器等等。
以下是关于1394芯片的内容。
1. 原理和技术:1394芯片基于串行总线架构,通过传输数据作为字节流,使得数据传输更加快速和高效。
它使用了异步通信方式,每个设备都有一个唯一的ID,可以直接与其他设备通信,无需经过计算机主机。
此外,1394芯片还采用了插拔热插拔技术,用户可以在计算机运行时连接或断开设备,无需重启计算机。
2. 特点和优势:- 高速传输:1394芯片提供了高达800Mbps的传输速度,比传统的USB 2.0接口更快。
这使得它在传输大容量数据,如高清视频和音频文件时非常有优势。
- 高质量音频和视频传输:1394芯片支持实时传输音频和视频数据,使得它在专业音频和视频设备中得到广泛应用。
它可以提供高质量的音频和视频传输,同时保持较低的延迟。
- 可靠性:1394芯片采用了差分信号传输,可以有效减少干扰和电磁辐射,提高数据传输的可靠性和稳定性。
此外,1394芯片还支持多个设备之间的高效协作,可以同时传输数据给多个设备。
- 在daisy-chain拓扑结构下的灵活性:1394芯片支持daisy-chain拓扑结构,使得多个设备可以通过一个接口连接,大大简化了设备的布线和连接。
这种拓扑结构可以减少系统内连接器数量,减小设备的物理体积。
3. 应用领域:- 影音传输:1394芯片在相机、摄像机和音频设备中得到广泛应用。
它可以快速传输高清视频和高保真音频数据,满足专业用户对音视频质量和传输效率的要求。
- 存储设备:1394芯片可以连接到外部硬盘驱动器,实现高速数据传输和备份。
它广泛用于图形设计师、视频编辑师和音频工程师等专业用户的工作环境中。
- 电子设备:1394芯片还可以用于连接电子设备,如打印机、扫描仪和数字相机等。
中国电信IP城域网设备测试规范-汇聚交换机v2.0
附件4:企业秘密中国电信IP城域网设备测试规范(汇聚交换机)(V2.0)中国电信集团公司二零零六年一月目录1. 概述 (1)1.1范围 (1)1.2引用标准 (1)1.3缩略语 (2)2. 测试环境和仪表 (3)2.1测试环境 (3)2.2测试仪表 (3)3. 测试内容 (4)4. 二层交换功能测试 (4)4.1基本功能测试 (4)4.1.1 超长帧转发能力 (4)4.1.2 异常帧检测功能测试 (5)4.1.3 广播抑制功能测试 (6)4.2镜像功能 (6)4.2.1 端口镜像功能测试 (6)4.2.2 流镜像功能测试 (7)4.3生成树协议测试 (8)4.3.1 标准生成树测试 (8)4.3.2 快速生成树测试 (9)4.3.3 多生成树测试 (10)4.4VLAN堆叠功能测试 (11)4.4.1 基本功能 (11)4.4.2 扩展功能 (12)4.5端口聚合 (14)4.5.1 聚合链路数量测试 (14)4.5.2 聚合效率测试 (15)4.5.3 聚合链路收敛时间测试 (16)4.6二层组播功能测试 (17)4.6.1 UNTAGGED端口IGMP SNOOPING功能测试 (17)4.6.2 TAGGED端口IGMP SNOOPING功能测试 (18)4.6.3 组播组加入/离开时间测试 (19)4.7P RIV ATE V LAN功能测试 (20)4.8V LAN交换功能测试 (21)5. 访问控制和QOS功能 (22)5.1访问控制表方向性测试 (22)5.2二层访问控制表测试 (23)5.2.1 MAC地址访问控制表测试 (23)5.2.2 VLAN访问控制表测试 (23)5.2.4 SVLAN访问控制表测试 (25)5.3三层访问控制表功能测试 (26)5.3.1 IP地址访问控制表功能测试 (26)5.3.2 四层端口访问控制表功能测试 (26)5.4访问控制表数量及性能测试 (27)5.5业务分级 (28)5.5.1 基于VLAN ID的业务分级 (28)5.5.2 基于四层端口的业务分级 (29)5.5.3 SVLAN内外层标签802.1P优先级映射 (30)5.6优先级队列 (31)5.6.1 严格优先级队列 (31)5.6.2 轮询队列 (31)5.7速率限制 (32)5.7.1 入方向速率限制功能测试 (32)5.7.2 出方向速率限制功能测试 (33)5.7.3 速率限制颗粒度及精确性测试 (34)6. 转发性能测试 (35)6.1MAC地址学习速度 (35)6.2MAC地址表容量 (35)6.3最大VLAN数量测试 (36)6.4单端口吞吐量和时延测试 (37)6.5板内交换性能测试 (38)6.6板间交换性能测试 (39)6.7综合转发性能测试 (40)7. 可靠性和安全性 (41)7.1设备可靠性 (41)7.1.1 主控板和交换矩阵冗余 (41)7.1.2 电源冗余 (42)7.1.3 业务卡热插拔 (42)7.1.4 设备重启动时间 (43)7.2网络安全 (44)7.2.1 端口地址数量限制 (44)7.2.2 设备防ARP攻击测试 (45)7.2.3 设备防ICMP攻击测试 (45)7.2.4 设备防BPDU攻击测试 (46)8. 运行维护和网络管理 (47)8.1运行维护功能测试 (47)8.1.1 远程认证管理 (47)8.1.2 SSH登录测试 (48)8.1.3 日志记录 (48)8.1.4 DHCP Option82功能测试 (49)8.2.1 SNMPv1、SNMPv2支持测试 (50)8.2.2 SNMPv3支持测试 (50)8.2.3 SNMP访问地址限制 (51)8.2.4 MIB View安全访问控制功能测试 (52)8.2.5 SNMP Trap功能测试 (52)8.3管理信息库 (53)8.3.1 端口MIB的功能测试 (53)8.3.2 VLAN MIB的功能测试 (53)8.3.3 CPU利用率、内存占用率的功能测试 (54)8.3.4 资源管理信息功能测试 (54)8.3.5 ACL管理信息功能测试 (55)8.3.6 QOS的管理功能测试 (55)8.3.7 二层组播MIB (56)8.3.8 SVLAN MIB (56)中国电信IP城域网设备测试规范-汇聚交换机1. 概述1.1 范围本规范主要参考我国相关标准、RFC标准、国际电信联盟ITU-T相关建议以及《中国电信城域网优化改造指导意见》、《中国电信城域网设备技术规范》编制。
rfc9334远程证明标准
rfc9334远程证明标准
摘要:
1.远程证明标准的背景和重要性
2.rfc9334 远程证明标准的具体内容
3.rfc9334 标准在网络安全领域的应用
4.我国对rfc9334 远程证明标准的采纳和实施
5.总结与展望
正文:
远程证明标准是网络安全领域中一个至关重要的组成部分,它为远程身份验证提供了统一的规范和指导。
其中,rfc9334 远程证明标准是当前被广泛接受和应用的一种标准。
rfc9334 远程证明标准是由IETF(互联网工程任务组)制定的,于2016 年发布。
该标准定义了一种通用的、可扩展的远程证明协议,用于在网络设备之间进行身份验证和授权。
具体来说,rfc9334 标准定义了一种名为“TLS 远程证明”的协议,该协议基于传输层安全(TLS)协议,可以提供强加密、数据完整性和认证服务。
在网络安全领域,rfc9334 远程证明标准被广泛应用于各种场景,如服务器认证、客户端认证、网络设备认证等。
通过使用该标准,可以有效降低网络攻击的风险,提高网络安全性。
我国对rfc9334 远程证明标准的采纳和实施也在逐步推进。
我国相关政府部门和标准化组织已经积极参与到rfc9334 标准的制定和完善过程中,并在我
国网络安全法规和标准中提出明确要求,鼓励和指导国内企业采用rfc9334 标准。
总之,rfc9334 远程证明标准为网络安全领域提供了重要支持。
随着网络攻击手段的不断升级,远程证明标准将发挥越来越重要的作用。
IEEE 1394接口基础知识
IEEE1394接口基础知识IEEE1394 又名 Firewire 或 iLinkTM,它的设计初衷是成为电子设备(包括便携式摄像机、个人电脑、数字电视机、音/视频接收器、DVD播放机、打印机等)之间的一个通用连接接口。
1394电缆可以传输不同类型的数字信号,包括视频、音频、数码音响、设备控制命令和计算机数据。
虽然具有1394接口的音/视频设备刚刚开始在市面上出现,人们家中的绝大多数设备仍然依靠S/PDIF连接器来与数字音响相连。
而另一方面,个人电脑配备1394连接器的可能性要比配置S/PDIF连接器的可能性高得多,使得它难以将数字音频信号(比如取自个人电脑的DVD音源)传输至基本的家用音响设备。
Firewire/S-PDIF使用户能轻松地使用自己的个人电脑来欣赏动听的数字音响娱乐节目。
IEEE1394 接口最早在国内出现是在97、98年左右,那时它对于我们绝大多数人来说只是简单的停留在概念的层面上,很少能在PC及其相关配件市场上看到具有IEEE1394接口类型的硬件设备,偶尔出现也只是那些“富人”才能享受的起。
进入20世纪以后,市场上带有IEEE1394接口类型的设备不断涌现,已经有了应用此接口的扫描仪,数码相机,Webcam,硬盘等设备。
一、IEEE1394的定义和特点1394卡的全称是IEEE1394 Interface Card,它是IEEE标准化组织制定的一项具有视频数据传输速度的串行接口标准。
它支持外接设备热插拔、同时可为外设提供电源,省去了外设自带的电源、支持同步数据传输。
IEEE1394接口最初由苹果公司开发,早期是为了取代并不普及的SCSI接口而设计的,英文取名为FIREWIRE。
后来大家称其为火线,一方面是因为速度快(接口最快传输速率达到了400MBPS,而且即将推出的IEEE1394B 标准更是将速度提升到了800MBPS甚至1.6GBPS的标准上,无可争议的坐在了外设接口的速度第一的宝座上),另一方面也是由此英文名翻译而来。
i Link
评价
由于速度的限制,在传输视频信号时只能传输隔行并且经过MPEG压缩的信号。虽然大多数人无法觉察到MPEG 压缩带来的图像质量损失,但是当然没有压缩是最好的。IEEE1394也不适合传输高清晰度视频信号。
波特率
link的最大波特率根据设备而变化 有三种类型。 s100 (约100mbps) s200 (约200mbps) s400 (约400mbps) 在每个装置使用说明书的“规格”下 当本摄像机连接至具有不同最大波特率的设备时,波特率可能与所指示的数值不同。 mbps表示“每秒兆位”,或一秒钟内可以发送或接收的数据量。例如,波特率100mbps其含义是一秒钟内可 以发送100兆字节的数据。 什么是mbps 摄像机也可以连接至其他sony生产的i.link (dv接口)兼容设备(如vaio系列个人计算机)以及视频设备。
i Link
索尼SONY公司设计的接口技术标准
01 基本信息
03 评价
目录
02 功能 04 波特率
i.Link,也叫IEEE1394。由于在数码摄影机上广泛应用,因此也叫DV接口。传输的最高数据率是400MBPS。
基本信息
i.Link是索尼SONY公司专门为个人电脑连接外围设备而特别设计的一个高性能串行总线的接口技术标准。 IEEE 1394在产业界称为i.Link。i.Link提出的插头插座技术可以使得多达63种外围设备连接在一起,数据交换 速度高达400兆比特每秒。这个标准对于各种外围设备和计算机微处理器之间的串行总线和数据路径做了详细的 描述。现在许多的外围设备都设计符合IEEE 1394中i.Link接口标准、苹果公司的火线接口标准或者IEEE 1394 中其它的接口标准。
功能
i.link是将数字视频、数字音频和其他数据传送到其他i.link兼容设备的数字串行接口。您也可以使用 i.link控制其他设备。可以使用i.link电缆连接i.link兼容设备。其最多的应用是各种数字av设备的操作和数 据处理。以菊花链将两台或多台i.link兼容设备连接至本摄像机,则可以链条式操作任何设备。请注意,操作方 法或数据处理可能会根据所连接设备的规格和特性而变化。
一种IEEE1394物理层IP的FPGA原型验证方法
一种IEEE1394物理层IP的FPGA原型验证方法王治;田泽;黎小玉;徐文进【摘要】According to the protocol,IEEE1394 PHY IP mainly implements the function of bus interconnection,connection management, bus arbitration,data transmission and so on. It is a kind of digital and analog mixed SoC integrated a high-speed Serdes. As it is hard to fully verify 1394 PHY IP before the Serdes chip is designed,therefore based on introduction of the 1394 PHY IP function,put forward a kind of method to meet the need for PHY IP verification,including using GTP of Xilinx FPGA instead of Serdes,constructing FPGA pro-totype verification platform,adopting hardwire logic work along with software to make verification works. Applying the platform can veri-fy the digital logic before the Serdes is completed,greatly shortening the development time of physics layer IP. Through the test items generation,test processing monitor,test result judgment under software control,can remarkably improve the verification efficiency.%符合IEEE1394协议的物理层IP主要完成总线连接检测、连接管理、仲裁、数据收发等功能,是一款集成高速Ser-des的数模混合SoC。
273规约
273规约
273规约是指在计算机领域中的一项规范,用于确保软件开发中的代码质量和可维护性。
它是由软件工程师约瑟夫·约翰逊在1974年提出的,被广泛应用于各种编程语言和开发环境中。
273规约的核心思想是通过一系列的规则和标准,来约束和规范代码的编写和组织,以提高代码的可读性、可理解性和可维护性。
它要求开发人员在编写代码时遵循一定的格式和命名规范,使用合适的注释和文档,以及避免一些常见的编码错误和陷阱。
在实际应用中,273规约可以帮助开发人员编写出更加清晰、简洁和易于理解的代码。
它不仅提高了代码的可读性,也方便了其他开发人员的维护和修改工作。
同时,273规约也能够减少代码中的潜在错误和bug,提高软件的质量和稳定性。
在遵循273规约的过程中,开发人员需要注意一些重要的方面。
首先,要保持代码的一致性和统一性,遵循统一的代码风格和命名规范。
其次,要注意代码的可扩展性和可重用性,尽量避免写出冗长和复杂的代码。
此外,还要避免使用过多的全局变量和魔法数字,以及合理地使用异常处理和日志记录等机制。
273规约是一项非常重要和实用的软件开发规范,它能够帮助开发人员编写出更加优秀和可维护的代码。
遵循273规约不仅有助于提高个人的编码水平和工作效率,也有助于提升整个团队和项目的质
量和竞争力。
因此,我强烈建议大家在日常的软件开发工作中积极应用273规约,以提高代码的质量和可维护性。
摄像头的工作原理说明加电路图
摄像头的工作原理说明加电路图随着中国网络事业的发展(直接的说,电脑的外部环境的变化→宽带网络的普及),大家对电脑摄像头的需求也就慢慢的加强。
比如用他来处理一些网络可视电话、视频监控、数码摄影和影音处理等。
话说回来,由于其的相对价格比较低廉(数码摄象机、数码照相机),技术含量不是太高,所以生产的厂家也就多了起来,中国IT市场就是如此,产品的质量和指标也就有比较大的差距。
一、首先来看看感光材料一般市场上的感光材料可以分为:CCD(电荷耦合)和CMOS(金属氧化物)两种。
前一种的优点是成像像素高,清晰度高,色彩还原系数高,经常应用在高档次数码摄像机、数码照相机中,缺点是价格比较昂贵,耗功较大。
后者缺点正好和前者互普,价格相对低廉,耗功也较小,但是,在成像方面要差一些。
如果你是需要效果好点的话,那么你就选购CCD元件的,但是你需要的¥就多一点了!二、像素也是一个关键指标现在市面上主流产品像素一般在130万左右,早些时候也出了一些10-30万左右像素的产品,由于技术含量相对较低效果不是很好,不久就退出历史舞台了。
这个时候也许有人会问,那是不是像素越高越好呢?从一般角度说是的。
但是从另一个方面来看也就不是那么了,对于同一个画面来说,像素高的产品他的解析图象能力就更高,呵呵,那么你所需要的存储器的容量就要很大了。
不然……我还是建议如果你选购的时候还是选购市面上比较主流的产品。
毕竟将来如果出问题了保修也比较好。
三、分辨率是大家谈的比较多的问题我想我没有必要到这里说分辨率这个东东了,大家最熟悉的应该就是:A:你的显示器什么什么品牌的。
分辨率可以上到多高,刷新率呢?B:呵呵,还好了,我用在1024*768 ,设计的时候就用在1280*1024。
玩游戏一般就800*600了。
但是摄像头的分辨率可不完全等同于显示器,切切的说,摄像头分辨率就是摄像头解析图象的能力。
现在市面上较多的CMOS的一般在640*480,有是也会在8 00*600。
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Network Working Group P. Johansson Request for Comments: 2734 Congruent Software, Inc. Category: Standards Track December 1999 IPv4 over IEEE 1394Status of this MemoThis document specifies an Internet standards track protocol for the Internet community, and requests discussion and suggestions forimprovements. Please refer to the current edition of the "InternetOfficial Protocol Standards" (STD 1) for the standardization stateand status of this protocol. Distribution of this memo is unlimited. Copyright NoticeCopyright (C) The Internet Society (1999). All Rights Reserved. ABSTRACTThis document specifies how to use IEEE Std 1394-1995, Standard for a High Performance Serial Bus (and its supplements), for the transport of Internet Protocol Version 4 (IPv4) datagrams; it defines thenecessary methods, data structures and codes for that purpose. These include not only packet formats and encapsulation methods fordatagrams, but also an address resolution protocol (1394 ARP) and amulticast channel allocation protocol (MCAP). Both 1394 ARP and MCAP are specific to Serial Bus; the latter permits management of SerialBus resources when used by IP multicast groups.TABLE OF CONTENTS1. INTRODUCTION (2)2. DEFINITIONS AND NOTATION (4)2.1 Conformance (4)2.2 Glossary (4)2.3 Abbreviations (6)2.4 Numeric values (6)3. IP-CAPABLE NODES (6)4. LINK ENCAPSULATION AND FRAGMENTATION (7)4.1 Global asynchronous stream packet (GASP) format (8)4.2 Encapsulation header (9)4.3 Link fragment reassembly (11)5. SERIAL BUS ADDRESS RESOLUTION PROTOCOL (1394 ARP) (11)6. CONFIGURATION ROM (14)6.1 Unit_Spec_ID entry (14)6.2 Unit_SW_Version entry (14)Johansson Standards Track [Page 1]6.3 Textual descriptors (15)7. IP UNICAST (16)8. IP BROADCAST (17)9. IP MULTICAST (17)9.1 MCAP message format (18)9.2 MCAP message domain (21)9.3 Multicast receive (21)9.4 Multicast transmit (22)9.5 Advertisement of channel mappings (23)9.6 Overlapped channel mappings (23)9.7 Transfer of channel ownership (24)9.8 Redundant channel mappings (25)9.9 Expired channel mappings (25)9.10 Bus reset (26)10. IANA CONSIDERATIONS (26)11. SECURITY CONSIDERATIONS (27)12. ACKNOWLEDGEMENTS (27)13. REFERENCES (28)14. EDITOR’S ADDRESS (28)15. Full Copyright Statement (29)1. INTRODUCTIONThis document specifies how to use IEEE Std 1394-1995, Standard for a High Performance Serial Bus (and its supplements), for the transport of Internet Protocol Version 4 (IPv4) datagrams. It defines thenecessary methods, data structures and codes for that purpose andadditionally defines methods for an address resolution protocol (1394 ARP) and a multicast channel allocation protocol (MCAP)---both ofwhich are specific to Serial Bus.The group of IEEE standards and supplements, draft or approved,related to IEEE Std 1394-1995 is hereafter referred to either as 1394 or as Serial Bus.1394 is an interconnect (bus) that conforms to the CSR architecture, ISO/IEC 13213:1994. Serial Bus permits communications between nodesover shared physical media at speeds that range, at present, from 100 to 400 Mbps. Both consumer electronic applications (such as digitalVCRs, stereo systems, televisions and camcorders) and traditionaldesktop computer applications (e.g., mass storage, printers andtapes), have adopted 1394. Serial Bus is unique in its relevance toboth consumer electronic and computer domains and is EXPECTED to form the basis of a home or small office network that combines both types of devices.Johansson Standards Track [Page 2]The CSR architecture describes a memory-mapped address space thatSerial Bus implements as a 64-bit fixed addressing scheme. Within the address space, ten bits are allocated for bus ID (up to a maximum of 1,023 buses), six are allocated for node physical ID (up to 63 perbus) while the remaining 48 bits (offset) describe a per node address space of 256 terabytes. The CSR architecture, by convention, splits a node’s address space into two regions with different behavioralcharacteristics. The lower portion, up to but not including 0xFFFFF000 0000, is EXPECTED to behave as memory in response to read andwrite transactions. The upper portion is more like a traditional IOspace: read and write transactions in this area usually have sideeffects. Control and status registers (CSRs) that have FIFO behavior customarily are implemented in this region.Within the 64-bit address, the 16-bit node ID (bus ID and physicalID) is analogous to a network hardware address---but 1394 node IDsare variable and subject to reassignment each time one or more nodes are added to or removed from the bus.NOTE: Although the 16-bit node ID contains a bus ID, at present there is no standard method to connect separately enumerated Serial Buses. Active development of a standard for Serial Bus to Serial Bus bridges is underway in the IEEE P1394.1 working group. Unless extended bysome future standard, the IPv4 over 1394 protocols specified by this document may not operate correctly across bridges.The 1394 link layer provides a packet delivery service with bothconfirmed (acknowledged) and unconfirmed packets. Two levels ofservice are available: "asynchronous" packets are sent on a best-effort basis while "isochronous" packets are guaranteed to bedelivered with bounded latency. Confirmed packets are alwaysasynchronous but unconfirmed packets may be either asynchronous orisochronous. Data payloads vary with implementations and may rangefrom one octet up to a maximum determined by the transmission speed(at 100 Mbps, named S100, the maximum asynchronous data payload is512 octets while at S400 it is 2048 octets).NOTE: Extensions underway in IEEE P1394b contemplate additionalspeeds of 800, 1600 and 3200 Mbps.Johansson Standards Track [Page 3]2. DEFINITIONS AND NOTATION2.1 ConformanceWhen used in this document, the keywords "MAY", "OPTIONAL","RECOMMENDED", "REQUIRED", "SHALL", "SHALL NOT", "SHOULD" and "SHOULD NOT" differentiate levels of requirements and optionality and are to be interpreted as described in RFC 2119.Several additional keywords are employed, as follows:EXPECTED: A keyword used to describe the behavior of the hardware or software in the design models assumed by this standard. Otherhardware and software design models may also be implemented.IGNORED: A keyword that describes bits, octets, quadlets or fieldswhose values are not checked by the recipient.RESERVED: A keyword used to describe either objects---bits, octets,quadlets and fields---or the code values assigned to these objects;the object or the code value is set aside for future standardization.A RESERVED object has no defined meaning and SHALL be zeroed by itsoriginator or, upon development of a future standard, set to a value specified by such a standard. The recipient of a RESERVED objectSHALL NOT check its value. The recipient of an object whose codevalues are defined by this standard SHALL check its value and reject RESERVED code values.2.2 GlossaryThe following terms are used in this standard:address resolution protocol: A method for a requester to determinethe hardware (1394) address of an IP node from the IP address of the node.bus ID: A 10-bit number that uniquely identifies a particular buswithin a group of multiple interconnected buses. The bus ID is themost significant portion of a node’s 16-bit node ID. The value 0x3FF designates the local bus; a node SHALL respond to requests addressed to its 6-bit physical ID if the bus ID in the request is either 0x3FF or the bus ID explicitly assigned to the node.encapsulation header: A structure that precedes all IP datatransmitted over 1394. See also link fragment.IP datagram: An Internet message that conforms to the formatspecified by STD 5, RFC 791.Johansson Standards Track [Page 4]link fragment: A portion of an IP datagram transmitted within asingle 1394 packet. The data payload of the 1394 packet contains both an encapsulation header and its associated link fragment. It ispossible to transmit datagrams without link fragmentation.multicast channel allocation protocol: A method for multicast groups to coordinate their use of Serial Bus resources (channels) ifmulticast datagrams are transmitted on other than the defaultbroadcast channel.multicast channel owner: A multicast source that has allocated achannel for one or more multicast addresses and transmits MCAPadvertisements to communicate these channel mapping(s) to otherparticipants in the IP multicast group. When more than one sourcetransmits MCAP advertisements for the same channel number, the source with the largest physical ID is the owner.node ID: A 16-bit number that uniquely identifies a Serial Bus nodewithin a group of multiple interconnected buses. The most significant ten bits are the bus ID and the least significant six bits are thephysical ID.node unique ID: A 64-bit number that uniquely identifies a node among all the Serial Bus nodes manufactured worldwide; also known as theEUI-64 (Extended Unique Identifier, 64-bits).octet: Eight bits of data.packet: Any of the 1394 primary packets; these may be read, write or lock requests (and their responses) or stream data. The term "packet" is used consistently to differentiate Serial Bus primary packets from 1394 ARP requests/responses, IP datagrams or MCAPadvertisements/solicitations.physical ID: On a particular bus, this 6-bit number is dynamicallyassigned during the self-identification process and uniquelyidentifies a node on that bus.quadlet: Four octets, or 32 bits, of data.stream packet: A 1394 primary packet with a transaction code of 0x0A that contains a block data payload. Stream packets may be eitherasynchronous or isochronous according to the type of 1394 arbitration employed.Johansson Standards Track [Page 5]2.3 AbbreviationsThe following are abbreviations that are used in this standard:1394 ARP Address resolution protocol (specific to 1394)CSR Control and status registerCRC Cyclical redundancy checksumEUI-64 Extended Unique Identifier, 64-bitsGASP Global asynchronous stream packetIP Internet protocol (within this document, IPv4)MCAP Multicast channel allocation protocol2.4 Numeric valuesDecimal and hexadecimal numbers are used within this standard. Byeditorial convention, decimal numbers are most frequently used torepresent quantities or counts. Addresses are uniformly representedby hexadecimal numbers, which are also used when the valuerepresented has an underlying structure that is more apparent in ahexadecimal format than in a decimal format.Decimal numbers are represented by Arabic numerals or by theirEnglish names. Hexadecimal numbers are prefixed by 0x and represented by digits from the character set 0 - 9 and A - F. For the sake oflegibility, hexadecimal numbers are separated into groups of fourdigits separated by spaces.For example, both 42 and 0x2A represent the same numeric value.3. IP-CAPABLE NODESNot all Serial Bus devices are capable of the reception andtransmission of 1394 ARP requests/responses or IP datagrams. An IP-capable node SHALL fulfill the following minimum requirements:- it SHALL implement configuration ROM in the general formatspecified by ISO/IEC 13213:1994 and SHALL implement the businformation block specified by IEEE P1394a and a unit directoryspecified by this standard;- the max_rec field in its bus information block SHALL be at least 8; this indicates an ability to accept block write requests andasynchronous stream packets with data payload of 512 octets. Thesame ability SHALL also apply to read requests; that is, the nodeSHALL be able to transmit a block response packet with a datapayload of 512 octets;Johansson Standards Track [Page 6]- it SHALL be isochronous resource manager capable, as specified byIEEE P1394a;- it SHALL support both reception and transmission of asynchronousstreams as specified by IEEE P1394a; and4. LINK ENCAPSULATION AND FRAGMENTATIONAll IP datagrams (broadcast, unicast or multicast), 1394 ARPrequests/responses and MCAP advertisements/solicitations that aretransferred via 1394 block write requests or stream packets SHALL be encapsulated within the packet’s data payload. The maximum size ofdata payload, in octets, is constrained by the speed at which thepacket is transmitted.Table 1 - Maximum data payloads (octets)Speed Asynchronous Isochronous+------------------------------------+| S100 | 512 | 1024 || S200 | 1024 | 2048 || S400 | 2048 | 4096 || S800 | 4096 | 8192 || S1600 | 8192 | 16384 || S3200 | 16384 | 32768 |+------------------------------------+NOTE: The maximum data payloads at speeds of S800 and faster may bereduced (but will not be increased) as a result of standardization by IEEE P1394b.The maximum data payload for asynchronous requests and responses may also be restricted by the capabilities of the sending or receivingnode(s); this is specified by max_rec in either the bus informationblock or 1394 ARP response.For either of these reasons, the maximum data payload transmissiblebetween IP-capable nodes may be less than the default 1500 octetmaximum transmission unit (MTU) specified by this document. Thisrequires that the encapsulation format also permit 1394 link-levelfragmentation and reassembly of IP datagrams.NOTE: IP-capable nodes may operate with an MTU size larger than thedefault, but the means by which a larger MTU is configured are beyond the scope of this document.Johansson Standards Track [Page 7]4.1 Global asynchronous stream packet (GASP) formatSome IP datagrams, as well as 1394 ARP requests and responses, may be transported via asynchronous stream packets. When asynchronous stream packets are used, their format SHALL conform to the globalasynchronous stream packet (GASP) format specified by IEEE P1394a.The GASP format illustrated below is INFORMATIVE and reproduced forease of reference, only.1 2 30 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+| data_length |tag| channel | 0x0A | sy |+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+| header_CRC |+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+| source_ID | specifier_ID_hi |+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+|specifier_ID_lo| version |+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+| |+--- data ---+| |+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+| data_CRC |+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+Figure 1 - GASP formatThe source_ID field SHALL specify the node ID of the sending node and SHALL be equal to the most significant 16 bits of the sender’sNODE_IDS register.The specifier_ID_hi and specifier_ID_lo fields together SHALL contain the value 0x00 005E, the 24-bit organizationally unique identifier(OUI) assigned by the IEEE Registration Authority (RA) to IANA.The version field SHALL be one.NOTE: Because the GASP format utilizes the first two quadlets of data payload in an asynchronous stream packet format, the maximum payloads cited in Table 1 are effectively reduced by eight octets. In theclauses that follow, references to the first quadlet of data payload mean the first quadlet usable for an IP datagram or 1394 ARP request or response. When the GASP format is used, this is the third quadlet of the data payload for the packet.Johansson Standards Track [Page 8]4.2 Encapsulation headerAll IP datagrams transported over 1394 are prefixed by anencapsulation header with one of the formats illustrated below.If an entire IP datagram may be transmitted within a single 1394packet, it is unfragmented and the first quadlet of the data payload SHALL conform to the format illustrated below.1 2 30 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+| lf| reserved | ether_type |+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+Figure 2 - Unfragmented encapsulation header formatThe lf field SHALL be zero.The ether_type field SHALL indicate the nature of the datagram thatfollows, as specified by the following table.ether_type Datagram+-------------------------+| 0x0800 | IPv4 || 0x0806 | 1394 ARP || 0x8861 | MCAP |+-------------------------+NOTE: Other network protocols, identified by different values ofether_type, may use the encapsulation formats defined herein but such use is outside of the scope of this document.In cases where the length of the datagram exceeds the maximum datapayload supported by the sender and all recipients, the datagramSHALL be broken into link fragments; the first two quadlets of thedata payload for the first link fragment SHALL conform to the format shown below.1 2 30 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+| lf|rsv| datagram_size | ether_type |+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+| dgl | reserved |+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+Figure 3 - First fragment encapsulation header formatJohansson Standards Track [Page 9]The second and subsequent link fragments (up to and including thelast) SHALL conform to the format shown below.1 2 30 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+| lf|rsv| datagram_size | rsv | fragment_offset |+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+| dgl | reserved |+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+Figure 4 - Subsequent fragment(s) encapsulation header formatThe definition and usage of the fields is as follows:The lf field SHALL specify the relative position of the linkfragment within the IP datagram, as encoded by the followingtable.lf Position+------------------------+| 0 | Unfragmented || 1 | First || 2 | Last || 3 | Interior |+------------------------+datagram_size: The encoded size of the entire IP datagram. Thevalue of datagram_size SHALL be the same for all link fragments of an IP datagram and SHALL be one less than the value of TotalLength in the datagram’s IP header (see STD 5, RFC 791).ether_type: This field is present only in the first link fragment and SHALL have a value of 0x0800, which indicates an IPv4datagram.fragment_offset: This field is present only in the second andsubsequent link fragments and SHALL specify the offset, in octets, of the fragment from the beginning of the IP datagram. The firstoctet of the datagram (the start of the IP header) has an offsetof zero; the implicit value of fragment_offset in the first linkfragment is zero.Johansson Standards Track [Page 10]dgl: The value of dgl (datagram label) SHALL be the same for alllink fragments of an IP datagram. The sender SHALL increment dglfor successive, fragmented datagrams; the incremented value of dgl SHALL wrap from 65,535 back to zero.All IP datagrams, regardless of the mode of transmission (block write requests or stream packets) SHALL be preceded by one of the abovedescribed encapsulation headers. This permits uniform softwaretreatment of datagrams without regard to the mode of theirtransmission.4.3 Link fragment reassemblyThe recipient of an IP datagram transmitted via more than one 1394packet SHALL use both the sender’s source_ID (obtained from eitherthe asynchronous packet header or the GASP header) and dgl toidentify all the link fragments from a single datagram.Upon receipt of a link fragment, the recipient may place the datapayload (absent the encapsulation header) within an IP datagramreassembly buffer at the location specified by fragment_offset. Thesize of the reassembly buffer may be determined from datagram_size.If a link fragment is received that overlaps another fragmentidentified by the same source_ID and dgl, the fragment(s) alreadyaccumulated in the reassembly buffer SHALL be discarded. A freshreassembly may be commenced with the most recently received linkfragment. Fragment overlap is determined by the combination offragment_offset from the encapsulation header and data_length fromthe 1394 packet header.Upon detection of a Serial Bus reset, recipient(s) SHALL discard all link fragments of all partially reassembled IP datagrams andsender(s) SHALL discard all not yet transmitted link fragments of all partially transmitted IP datagrams.5. SERIAL BUS ADDRESS RESOLUTION PROTOCOL (1394 ARP)Methods to determine the hardware address of a device from itscorresponding IP address are inextricably tied to the transportmedium utilized by the device. In the description below andthroughout this document, the acronym 1394 ARP pertains solely to an address resolution protocol whose methods and data structures arespecific to 1394.1394 ARP requests SHALL be transmitted by the same means as broadcast IP datagrams; 1394 ARP responses MAY be transmitted in the same wayor they MAY be transmitted as block write requests addressed to the Johansson Standards Track [Page 11]sender_unicast_FIFO address identified by the 1394 ARP request. A1394 ARP request/response is 32 octets and SHALL conform to theformat illustrated by Figure 5.1 2 30 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+| hardware_type (0x0018) | protocol_type (0x0800) |+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+| hw_addr_len | IP_addr_len | opcode |+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+| |+--- sender_unique_ID ---+| |+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+| sender_max_rec| sspd | sender_unicast_FIFO_hi |+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+| sender_unicast_FIFO_lo |+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+| sender_IP_address |+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+| target_IP_address |+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+Figure 5 - 1394 ARP request/response format1394 ARP requests and responses transported by asynchronous streampackets SHALL be encapsulated within the GASP format specified byIEEE P1394a (see also 4.1). The recipient of a 1394 ARP request orresponse SHALL ignore it unless the most significant ten bits of the source_ID field (whether obtained from the GASP header of anasynchronous stream packet or the packet header of a block writerequest) are equal to either 0x3FF or the most significant ten bitsof the recipient’s NODE_IDS register.Field usage in a 1394 ARP request/response is as follows:hardware_type: This field indicates 1394 and SHALL have a value of 0x0018.protocol_type: This field SHALL have a value of 0x0800; thisindicates that the protocol addresses in the 1394 ARPrequest/response conform to the format for IP addresses.hw_addr_len: This field indicates the size, in octets, of the1394-dependent hardware address associated with an IP address and SHALL have a value of 16.Johansson Standards Track [Page 12]IP_addr_len: This field indicates the size, in octets, of an IPversion 4 (IPv4) address and SHALL have a value of 4.opcode: This field SHALL be one to indicate a 1394 ARP request and two to indicate a 1394 ARP response.sender_unique_ID: This field SHALL contain the node unique ID ofthe sender and SHALL be equal to that specified in the sender’sbus information block.sender_max_rec: This field SHALL be equal to the value of max_rec in the sender’s configuration ROM bus information block.sspd: This field SHALL be set to the lesser of the sender’s linkspeed and PHY speed. The link speed is the maximum speed at which the link may send or receive packets; the PHY speed is the maximum speed at which the PHY may send, receive or repeat packets. Thetable below specifies the encoding used for sspd; all values notspecified are RESERVED for future standardization.Table 2 - Speed codesValue Speed+---------------+| 0 | S100 || 1 | S200 || 2 | S400 || 3 | S800 || 4 | S1600 || 5 | S3200 |+---------------+sender_unicast_FIFO_hi and sender_unicast_FIFO_lo: These fieldstogether SHALL specify the 48-bit offset of the sender’s FIFOavailable for the receipt of IP datagrams in the format specified by section 6. The offset of a sender’s unicast FIFO SHALL NOTchange, except as the result of a power reset.sender_IP_address: This field SHALL specify the IP address of the sender.target_IP_address: In a 1394 ARP request, this field SHALL specify the IP address from which the sender desires a response. In a 1394 ARP response, it SHALL be IGNORED.Johansson Standards Track [Page 13]6. CONFIGURATION ROMConfiguration ROM for IP-capable nodes SHALL contain a unit directory in the format specified by this standard. The unit directory SHALLcontain Unit_Spec_ID and Unit_SW_Version entries, as specified byISO/IEC 13213:1994.The unit directory may also contain other entries permitted byISO/IEC 13213:1994 or IEEE P1212r.6.1 Unit_Spec_ID entryThe Unit_Spec_ID entry is an immediate entry in the unit directorythat specifies the organization responsible for the architecturaldefinition of the Internet Protocol capabilities of the device.1 2 30 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+| 0x12 | unit_spec_ID (0x00 005E) |+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+Figure 6 - Unit_Spec_ID entry formatThe value of unit_spec_ID SHALL be 0x00 005E, the registration ID(RID) obtained by IANA from the IEEE RA. The value indicates that the IETF and its technical committees are responsible for the maintenance of this standard.6.2 Unit_SW_Version entryThe Unit_SW_Version entry is an immediate entry in the unit directory that, in combination with the unit_spec_ID, specifies the documentthat defines the software interface of the unit.1 2 30 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+| 0x13 | unit_sw_version (0x00 0001) |+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+Figure 7 - Unit_SW_Version entry formatThe value of unit_sw_version SHALL be one, which indicates that thedevice complies with the normative requirements of this standard. Johansson Standards Track [Page 14]。