DS90CR286

DS90CR285/DS90CR286+3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-66MHzGeneral DescriptionThe DS90CR285transmitter converts 28bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling)data streams.A phase-locked transmit clock is transmitted in par-allel with the data streams over a fifth LVDS link.Every cycle of the transmit clock 28bits of input data are sampled and transmitted.The DS90CR286receiver converts the LVDS data streams back into 28bits of CMOS/TTL data.At a trans-mit clock frequency of 66MHz,28bits of TTL data are trans-mitted at a rate of 462Mbps per LVDS data ing a 66MHz clock,the data throughput is 1.848Gbit/s (231Mbytes/s).The multiplexing of the data lines provides a substantial cable reduction.Long distance parallel single-ended buses typically require a ground wire per active signal (and have very limited noise rejection capability).Thus,for a 28-bit wide data and one clock,up to 58conductors are required.With the Channel Link chipset as few as 11conductors (4data pairs,1clock pair and a minimum of one ground)are needed.This provides a 80%reduction in required cable width,which provides a system cost savings,reduces con-nector physical size and cost,and reduces shielding require-ments due to the cables’smaller form factor.The 28CMOS/TTL inputs can support a variety of signal combinations.For example,seven 4-bit nibbles or three 9-bit (byte +parity)and 1control.Featuresn Single +3.3V supplyn Chipset (Tx +Rx)power consumption <250mW (typ)n Power-down mode (<0.5mW total)n Up to 231Megabytes/sec bandwidth n Up to 1.848Gbps data throughput n Narrow bus reduces cable sizen 290mV swing LVDS devices for low EMI n +1V common mode range (around +1.2V)n PLL requires no external components n Low profile 56-lead TSSOP package n Rising edge data stroben Compatible with TIA/EIA-644LVDS standard n ESD Rating >7kVnOperating Temperature:−40˚C to +85˚CBlock DiagramsTRI-STATE ®is a registered trademark of National Semiconductor Corporation.DS90CR285DS012910-1Order Number DS90CR285MTD See NS Package Number MTD56DS90CR286DS012910-27Order Number DS90CR286MTD See NS Package Number MTD56March 1999DS90CR285/DS90CR286+3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-66MHz©1999National Semiconductor Corporation Pin DiagramsTypical ApplicationDS90CR285DS012910-21DS90CR286DS012910-22DS012910-23 2Absolute Maximum Ratings(Note1)If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.Supply Voltage(V CC)−0.3V to+4V CMOS/TTL Input Voltage−0.3V to(V CC+0.3V) CMOS/TTL Output Voltage−0.3V to(V CC+0.3V) LVDS Receiver InputVoltage−0.3V to(V CC+0.3V) LVDS Driver Output Voltage−0.3V to(V CC+0.3V) LVDS Output Short CircuitDuration Continuous Junction Temperature+150˚C Storage Temperature−65˚C to+150˚C Lead Temperature(Soldering,4sec.)+260˚C Maximum Package Power Dissipation@+25˚CMTD56(TSSOP)Package:DS90CR285 1.63W DS90CR286 1.61W Package Derating:DS90CR28512.5mW/˚C above+25˚C DS90CR28612.4mW/˚C above+25˚C ESD Rating(HBM,1.5kΩ,100pF)>7kV Recommended Operating ConditionsMin Nom Max Units Supply Voltage(V CC) 3.0 3.3 3.6V Operating Free AirTemperature(T A)−40+25+85˚C Receiver Input Range0 2.4V Supply Noise Voltage(V CC)100mV PPElectrical CharacteristicsOver recommended operating supply and temperature ranges unless otherwise specifiedSymbol Parameter Conditions Min Typ Max Units CMOS/TTL DC SPECIFICATIONSV IH High Level Input Voltage 2.0V CC VV IL Low Level Input Voltage GND0.8VV OH High Level Output Voltage I OH=−0.4mA 2.7 3.3VV OL Low Level Output Voltage I OL=2mA0.060.3VV CL Input Clamp Voltage I CL=−18mA−0.79−1.5VI IN Input Current V IN=V CC,GND,2.5V or0.4V±5.1±10µAI OS Output Short Circuit Current V OUT=0V−60−120mA LVDS DRIVER DC SPECIFICATIONSV OD Differential Output Voltage R L=100Ω250290450mV∆V OD Change in V OD betweenComplimentary Output States35mVV OS Offset Voltage(Note4) 1.125 1.25 1.375V∆V OS Change in V OS betweenComplimentary Output States35mVI OS Output Short Circuit Current V OUT=0V,R L=100Ω−3.5−5mAI OZ Output TRI-STATE®Current PWR DWN=0V,±1±10µAV OUT=0V or V CCLVDS RECEIVER DC SPECIFICATIONSV TH Differential Input High Threshold V CM=+1.2V+100mVV TL Differential Input Low Threshold−100mVI IN Input Current V IN=+2.4V,V CC=3.6V±10µAV IN=0V,V CC=3.6V±10µA3Electrical Characteristics(Continued)Over recommended operating supply and temperature ranges unless otherwise specifiedSymbol Parameter Conditions Min Typ Max Units TRANSMITTER SUPPLY CURRENTI CCTW Transmitter Supply CurrentWorst Case(with Loads)R L=100Ω,C L=5pF,Worst CasePattern(Figures1,2),T A=−10˚C to+70˚Cf=32.5MHz3145mAf=37.5MHz3250mAf=66MHz3755mAR L=100Ω,C L=5pF,Worst CasePattern(Figures1,2),T A=−40˚C to+85˚Cf=40MHz3851mAf=66MHz4255mAI CCTZ Transmitter Supply CurrentPower Down PWR DWN=LowDriver Outputs in TRI-STATEunder Powerdown Mode1055µARECEIVER SUPPLY CURRENTI CCRW Receiver Supply Current WorstCase C L=8pF,Worst CasePattern(Figures1,3),T A=−10˚C to+70˚Cf=32.5MHz4965mAf=37.5MHz5370mAf=66MHz78105mAC L=8pF,Worst CasePattern(Figures1,3),T A=−40˚C to+85˚Cf=40MHz5582mAf=66MHz78105mAI CCRZ Receiver Supply Current PowerDown PWR DWN=LowReceiver Outputs Stay Low duringPowerdown Mode1055µANote1:“Absolute Maximum Ratings”are those values beyond which the safety of the device cannot be guaranteed.They are not meant to imply that the device should be operated at these limits.The tables of“Electrical Characteristics”specify conditions for device operation.Note2:Typical values are given for V CC=3.3V and T A=+25˚C.Note3:Current into device pins is defined as positive.Current out of device pins is defined as negative.Voltages are referenced to ground unless otherwise speci-fied(except V OD and∆V OD).Note4:V OS previously referred as V CM.Transmitter Switching CharacteristicsOver recommended operating supply and−40˚C to+85˚C ranges unless otherwise specifiedSymbol Parameter Min Typ Max Units LLHT LVDS Low-to-High Transition Time(Figure2)0.5 1.5ns LHLT LVDS High-to-Low Transition Time(Figure2)0.5 1.5ns TCIT TxCLK IN Transition Time(Figure4)5ns TCCS TxOUT Channel-to-Channel Skew(Figure5)250ps TPPos0Transmitter Output Pulse Position forBit0(Note7)(Figure16)f=40MHz−0.400.4nsTPPos1Transmitter Output Pulse Position forBit13.1 3.34.0nsTPPos2Transmitter Output Pulse Position forBit26.5 6.87.6ns 4Transmitter Switching Characteristics(Continued)Over recommended operating supply and−40˚C to+85˚C ranges unless otherwise specifiedSymbol Parameter Min Typ Max Units10.210.411.0ns TPPos3Transmitter Output Pulse Position forBit313.713.914.6ns TPPos4Transmitter Output Pulse Position forBit4TPPos5Transmitter Output Pulse Position for17.317.618.2nsBit521.021.221.8ns TPPos6Transmitter Output Pulse Position forBit6f=66MHz−0.400.3ns TPPos0Transmitter Output Pulse Position forBit0(Note6)(Figure16)1.82.2 2.5ns TPPos1Transmitter Output Pulse Position forBit1TPPos2Transmitter Output Pulse Position for4.0 4.4 4.7nsBit2TPPos3Transmitter Output Pulse Position for6.2 6.6 6.9nsBit38.48.89.1ns TPPos4Transmitter Output Pulse Position forBit4TPPos5Transmitter Output Pulse Position for10.611.011.3nsBit512.813.213.5ns TPPos6Transmitter Output Pulse Position forBit6TCIP TxCLK IN Period(Figure6)15T50ns TCIH TxCLK IN High Time(Figure6)0.35T0.5T0.65T ns TCIL TxCLK IN Low Time(Figure6)0.35T0.5T0.65T ns TSTC TxIN Setup to TxCLK IN(Figure6) 2.5ns THTC TxIN Hold to TxCLK IN(Figure6)0ns3 3.7 5.5ns TCCD TxCLK IN to TxCLK OUT Delay@25˚C,V CC=3.3V(Figure8)TPLLS Transmitter Phase Lock Loop Set(Figure10)10ms TPDD Transmitter Powerdown Delay(Figure14)100nsReceiver Switching CharacteristicsOver recommended operating supply and−40˚C to+85˚C ranges unless otherwise specifiedSymbol Parameter Min Typ Max Units CLHT CMOS/TTL Low-to-High Transition Time(Figure3) 2.2 5.0ns CHLT CMOS/TTL High-to-Low Transition Time(Figure3) 2.2 5.0ns RSPos0Receiver Input Strobe Position for Bit0(Note7)(Figure17)f=40MHz 1.0 1.4 2.15ns RSPos1Receiver Input Strobe Position for Bit1 4.5 5.0 5.8ns RSPos2Receiver Input Strobe Position for Bit28.18.59.15ns RSPos3Receiver Input Strobe Position for Bit311.611.912.6ns RSPos4Receiver Input Strobe Position for Bit415.115.616.3ns RSPos5Receiver Input Strobe Position for Bit518.819.219.9ns RSPos6Receiver Input Strobe Position for Bit622.522.923.6ns5Receiver Switching Characteristics(Continued)Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specifiedSymbol ParameterMinTyp Max Units RSPos0Receiver Input Strobe Position for Bit 0(Note 6)(Figure 17)f =66MHz0.7 1.1 1.4ns RSPos1Receiver Input Strobe Position for Bit 1 2.9 3.3 3.6ns RSPos2Receiver Input Strobe Position for Bit 2 5.1 5.5 5.8ns RSPos3Receiver Input Strobe Position for Bit 37.37.78.0ns RSPos4Receiver Input Strobe Position for Bit 49.59.910.2ns RSPos5Receiver Input Strobe Position for Bit 511.712.112.4ns RSPos6Receiver Input Strobe Position for Bit 613.914.314.6ns RSKM RxIN Skew Margin (Note 5)(Figure 18)f =40MHz 490ps f =66MHz400ps RCOP RxCLK OUT Period (Figure 7)15T 50ns RCOH RxCLK OUT High Time (Figure 7)f =40MHz 6.010.0ns f =66MHz 4.0 6.1ns RCOL RxCLK OUT Low Time (Figure 7)f =40MHz 10.013.0ns f =66MHz 6.07.8ns RSRC RxOUT Setup to RxCLK OUT (Figure 7)f =40MHz 6.514.0ns f =66MHz 2.58.0ns RHRC RxOUT Hold to RxCLK OUT (Figure 7)f =40MHz 6.08.0ns f =66MHz 2.5 4.0ns RCCD RxCLK IN to RxCLK OUT Delay (Figure 9)f =40MHz 4.0 6.78.0ns f =66MHz5.06.69.0ns RPLLS Receiver Phase Lock Loop Set (Figure 11)10ms RPDDReceiver Powerdown Delay (Figure 15)1µsNote 5:Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs.This margin takes into account the transmitter pulse positions (min and max)and the receiver input setup and hold time (internal data sampling window).This margin allows LVDS interconnect skew,inter-symbol interference (both dependent on type/length of cable),and clock jitter less than 250ps).Note 6:The min.and max.limits are based on the worst bit by applying a −400ps/+300ps shift from ideal position.Note 7:The min.and max.are based on the actual bit position of each of the 7bits within the LVDS data stream across PVT.AC Timing DiagramsDS012910-2FIGURE 1.“Worst Case”Test PatternDS012910-3DS012910-4FIGURE 2.DS90CR285(Transmitter)LVDS Output Load and Transition Times 6AC Timing Diagrams(Continued)DS012910-5DS012910-6 FIGURE3.DS90CR286(Receiver)CMOS/TTL Output Load and Transition TimesDS012910-7FIGURE4.DS90CR285(Transmitter)Input Clock Transition TimeDS012910-8Note8:Measurements at V DIFF=0VNote9:TCCS measured between earliest and latest LVDS edges.Note10:TxCLK Differential Low→High EdgeFIGURE5.DS90CR285(Transmitter)Channel-to-Channel SkewDS012910-9FIGURE6.DS90CR285(Transmitter)Setup/Hold and High/Low Times7AC Timing Diagrams(Continued)DS012910-10FIGURE7.DS90CR286(Receiver)Setup/Hold and High/Low TimesDS012910-11FIGURE8.DS90CR285(Transmitter)Clock In to Clock Out DelayDS012910-12FIGURE9.DS90CR286(Receiver)Clock In to Clock Out DelayDS012910-13FIGURE10.DS90CR285(Transmitter)Phase Lock Loop Set Time8AC Timing Diagrams(Continued)DS012910-14FIGURE11.DS90CR286(Receiver)Phase Lock Loop Set TimeDS012910-15FIGURE12.Seven Bits of LVDS in Once Clock CycleDS012910-16FIGURE13.28ParalIeI TTL Data Inputs Mapped to LVDS Outputs9AC Timing Diagrams(Continued)DS012910-17FIGURE14.Transmitter Powerdown DeIayDS012910-18FIGURE15.Receiver Powerdown DelayDS012910-19FIGURE16.Transmitter LVDS Output Pulse Position Measurement10AC Timing Diagrams(Continued)DS012910-28FIGURE17.Receiver LVDS Input Strobe Position11AC Timing Diagrams(Continued)Applications InformationThe DS90CR285and DS90CR286are backward compatible with the existing 5V Channel Link transmitter/receiver pair (DS90CR283,DS90CR284).To upgrade from a 5V to a 3.3V system the following must be addressed:1.Change 5V power supply to 3.3V.Provide this supply to the V CC ,LVDS V CC and PLL V CC .2.Transmitter input and control inputs except3.3V TTL/CMOS levels.They are not 5V tolerant.3.The receiver powerdown feature when enabled will lock receiver output to a logic low.However,the 5V/66MHz receiver maintain the outputs in the previous state when powerdown occurred.DS90CR285Pin Description—Channel Link TransmitterPin Name I/O No.DescriptionTxIN I 28TTL level input.TxOUT+O 4Positive LVDS differential data output.TxOUT−O 4Negative LVDS differential data output.TxCLK IN I 1TTL IeveI clock input.The rising edge acts as data strobe.Pin name TxCLK IN.TxCLK OUT+O 1Positive LVDS differential clock output.TxCLK OUT−O 1Negative LVDS differential clock output.PWR DWN I 1TTL level input.Assertion (low input)TRI-STATES the outputs,ensuring low current at power down.V CC I 4Power supply pins for TTL inputs.GND I 5Ground pins for TTL inputs.PLL V CC I 1Power supply pin for PLL.PLL GND I 2Ground pins for PLL.LVDS V CC I 1Power supply pin for LVDS outputs.LVDS GNDI3Ground pins for LVDS outputs.DS90CR286Pin Description—Channel Link ReceiverPin Name I/O No.DescriptionRxIN+I 4Positive LVDS differential data inputs.RxIN−I 4Negative LVDS differential data inputs.RxOUT O 28TTL level data outputs.RxCLK IN+I 1Positive LVDS differential clock input.RxCLK IN−I 1Negative LVDS differential clock input.RxCLK OUTO1TTL level clock output.The rising edge acts as data strobe.Pin name RxCLK OUT.DS012910-20C —Setup and Hold Time (Internal data sampling window)defined by Rspos (receiver input strobe position)min and max Tppos —Transmitter output pulse position (min and max)RSKM ≥Cable Skew (type,length)+Source Clock Jitter (cycle to cycle)(Note 11)+ISI (Inter-symbol interference)(Note 12)Cable Skew —typically 10ps–40ps per foot,media dependent Note 11:Cycle-to-cycle jitter is less than 250psNote 12:ISI is dependent on interconnect length;may be zeroFIGURE 18.Receiver LVDS Input Skew Margin 12Applications Information(Continued)DS90CR286Pin Description—Channel Link Receiver(Continued) Pin Name I/O No.DescriptionPWR DWN I1TTL level input.When asserted(low input)the receiver outputs are low. V CC I4Power supply pins for TTL outputs.GND I5Ground pins for TTL outputs.PLL V CC I1Power supply for PLL.PLL GND I2Ground pin for PLL.LVDS V CC I1Power supply pin for LVDS inputs.LVDS GND I3Ground pins for LVDS inputs.The Channel Link devices are intended to be used in a widevariety of data transmission applications.Depending uponthe application the interconnecting media may vary.For ex-ample,for lower data rate(clock rate)and shorter cablelengths(<2m),the media electrical performance is less criti-cal.For higher speed/long distance applications the media’sperformance becomes more critical.Certain cable construc-tions provide tighter skew(matched electrical length be-tween the conductors and pairs).Twin-coax for example,hasbeen demonstrated at distances as great as5meters andwith the maximum data transfer of1.848Gbit/s.Additionalapplications information can be found in the following Na-tional Interface Application Notes:AN=####TopicAN-1041Introduction to Channel LinkAN-1035PCB Design Guidelines for LVDS andLink DevicesAN-806Transmission Line TheoryAN-905Transmission Line Calculations andDifferential ImpedanceAN-916Cable InformationCABLES:A cable interface between the transmitter and re-ceiver needs to support the differential LVDS pairs.The21-bit CHANNEL LINK chipset(DS90CR215/216)requires fourpairs of signal wires and the28-bit CHANNEL LINK chipset(DS90CR285/286)requires five pairs of signal wires.Theideal cable/connector interface would have a constant100Ωdifferential impedance throughout the path.It is also recom-mended that cable skew remain below150ps(66MHzclock rate)to maintain a sufficient data sampling window atthe receiver.In addition to the four or five cable pairs that carry data andclock,it is recommended to provide at least one additionalconductor(or pair)which connects ground between thetransmitter and receiver.This low impedance ground pro-vides a common mode return path for the two devices.Someof the more commonly used cable types for point-to-point ap-plications include flat ribbon,flex,twisted pair and Twin-Coax.All are available in a variety of configurations and op-tions.Flat ribbon cable,flex and twisted pair generallyperform well in short point-to-point applications while Twin-Coax is good for short and long applications.When using rib-bon cable,it is recommended to place a ground line betweeneach differential pair to act as a barrier to noise coupling be-tween adjacent pairs.For Twin-Coax cable applications,it isrecommended to utilize a shield on each cable pair.All ex-tended point-to-point applications should also employ anoverall shield surrounding all cable pairs regardless of thecable type.This overall shield results in improved transmis-sion parameters such as faster attainable speeds,longerdistances between transmitter and receiver and reducedproblems associated with EMS or EMI.The high-speed transport of LVDS signals has been demon-strated on several types of cables with excellent results.However,the best overall performance has been seen whenusing Twin-Coax cable.Twin-Coax has very low cable skewand EMI due to its construction and double shielding.All ofthe design considerations discussed here and listed in thesupplemental application notes provide the subsystem com-munications designer with many useful guidelines.It is rec-ommended that the designer assess the tradeoffs of eachapplication thoroughly to arrive at a reliable and economicalcable solution.BOARD LAYOUT:To obtain the maximum benefit from thenoise and EMI reductions of LVDS,attention should be paidto the layout of differential lines.Lines of a differential pairshould always be adjacent to eliminate noise interferencefrom other signals and take full advantage of the noise can-celing of the differential signals.The board designer shouldalso try to maintain equal length on signal traces for a givendifferential pair.As with any high speed design,the imped-ance discontinuities should be limited(reduce the numbersof vias and no90degree angles on traces).Any discontinui-ties which do occur on one signal line should be mirrored inthe other line of the differential pair.Care should be taken toensure that the differential trace impedance match the differ-ential impedance of the selected physical media(this imped-ance should also match the value of the termination resistorthat is connected across the differential pair at the receiver’sinput).Finally,the location of the CHANNEL LINK TxOUT/RxIN pins should be as close as possible to the board edgeso as to eliminate excessive pcb runs.All of these consider-ations will limit reflections and crosstalk which adversely ef-fect high frequency performance and EMI.UNUSED INPUTS:All unused inputs at the TxIN inputs ofthe transmitter must be tied to ground.All unused outputs atthe RxOUT outputs of the receiver must then be left floating.TERMINATION:Use of current mode drivers requires a ter-minating resistor across the receiver inputs.The CHANNELLINK chipset will normally require a single100Ωresistor be-tween the true and complement lines on each differentialpair of the receiver input.The actual value of the terminationresistor should be selected to match the differential modecharacteristic impedance(90Ωto120Ωtypical)of the cable.Figure19shows an example.No additional pull-up or pull-down resistors are necessary as with some other differentialtechnologies such as PECL.Surface mount resistors arerecommended to avoid the additional inductance that ac- 13Applications Information(Continued)companies leaded resistors.These resistors should be placed as close as possible to the receiver input pins to re-duce stubs and effectively terminate the differential lines.DECOUPLING CAPACITORS:Bypassing capacitors are needed to reduce the impact of switching noise which could limit performance.For a conservative approach three parallel-connected decoupling capacitors (Multi-Layered Ce-ramic type in surface mount form factor)between each V CC and the ground plane(s)are recommended.The three ca-pacitor values are 0.1µF,0.01µF and 0.001µF.An example is shown in Figure 20.The designer should employ wide traces for power and ground and ensure each capacitor has its own via to the ground plane.If board space is limiting the number of bypass capacitors,the PLL V CC should receive the most filtering/bypassing.Next would be the LVDS V CC pins and finally the logic V CC pins.CLOCK JITTER:The CHANNEL LINK devices employ a PLL to generate and recover the clock transmitted across the LVDS interface.The width of each bit in the serialized LVDS data stream is one-seventh the clock period.For example,a 66MHz clock has a period of 15ns which results in a data bit width of 2.16ns.Differential skew (∆t within one differential pair),interconnect skew (∆t of one differential pair to an-other)and clock jitter will all reduce the available window for sampling the LVDS serial data streams.Care must be taken to ensure that the clock input to the transmitter be a clean low noise signal.Individual bypassing of each V CC to ground will minimize the noise passed on to the PLL,thus creating alow jitter LVDS clock.These measures provide more margin for channel-to-channel skew and interconnect skew as a part of the overall jitter/skew budget.COMMON MODE vs.DIFFERENTIAL MODE NOISE MAR-GIN:The typical signal swing for LVDS is 300mV centered at +1.2V.The CHANNEL LINK receiver supports a 100mV threshold therefore providing approximately 200mV of differ-ential noise mon mode protection is of more im-portance to the system’s operation due to the differential data transmission.LVDS supports an input voltage range of Ground to +2.4V.This allows for a ±1.0V shifting of the cen-ter point due to ground potential differences and common mode noise.POWER SEQUENCING AND POWERDOWN MODE:Out-puts of the CNANNEL LINK transmitter remain in TRI-STATE ®until the power supply reaches 2V.Clock and data outputs will begin to toggle 10ms after V CC has reached 3V and the Powerdown pin is above 1.5V.Either device may be placed into a powerdown mode at any time by asserting the Powerdown pin (active low).Total power dissipation for each device will decrease to 5µW (typical).The CHANNEL LINK chipset is designed to protect itself from accidental loss of power to either the transmitter or re-ceiver.If power to the transmit board is lost,the receiver clocks (input and output)stop.The data outputs (RxOUT)re-tain the states they were in when the clocks stopped.When the receiver board loses power,the receiver inputs are shorted to V CC through an internal diode.Current is limited (5mA per input)by the fixed current mode drivers,thus avoiding the potential for latchup when powering the device.DS012910-24FIGURE 19.LVDS Serialized Link TerminationDS012910-25FIGURE 20.CHANNEL LINK Decoupling Configuration 14Applications Information(Continued)DS012910-26FIGURE21.Single-Ended and Differential Waveforms15Physical Dimensions inches(millimeters)unless otherwise notedLIFE SUPPORT POLICYNATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-CONDUCTOR CORPORATION.As used herein:1.Life support devices or systems are devices or sys-tems which,(a)are intended for surgical implant intothe body,or(b)support or sustain life,and whose fail-ure to perform when properly used in accordancewith instructions for use provided in the labeling,canbe reasonably expected to result in a significant injuryto the user.2.A critical component is any component of a life supportdevice or system whose failure to perform can be rea-sonably expected to cause the failure of the life supportdevice or system,or to affect its safety or effectiveness.National SemiconductorCorporationAmericasTel:1-800-272-9959Fax:1-800-737-7018Email:support@National SemiconductorEuropeFax:+49(0)180-5308586Email:europe.support@Deutsch Tel:+49(0)180-5308585English Tel:+49(0)180-5327832Français Tel:+49(0)180-5329358Italiano Tel:+49(0)180-5341680National SemiconductorAsia Pacific CustomerResponse GroupTel:65-2544466Fax:65-2504466Email:sea.support@National SemiconductorJapan Ltd.Tel:81-3-5639-7560Fax:81-3-5639-7507Order Number DS90CR285MTD or DS90CR286MTDNS Package Number MTD56DS9CR285/DS9CR286+3.3VRisingEdgeDataStrobeLVDS28-BitChannelLink-66MHzNational does not assume any responsibility for use of any circuitry described,no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.。