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实验室用水的种类和区别

水是实验室内一个常常被忽视但至关重要的试剂。

实验室用水有那些种类？能达到什么级别？不同实验对水的要求有那些？实验室常见的水的种类：1、蒸馏水（Distilled Water ）：实验室最常用的一种纯水，虽设备便宜，但极其耗能和费水且速度慢，应用会逐渐减少。

蒸馏水能去除自来水内大部分的污染物，但挥发性的杂质无法去除，如二氧化碳、氨、二氧化硅以及一些有机物。

新鲜的蒸馏水是无菌的，但储存后细菌易繁殖；此外，储存的容器也很讲究，若是非惰性的物质，离子和容器的塑形物质会析出造成二次污染。

2、去离子水（Deionized Water ）：应用离子交换树脂去除水中的阴离子和阳离子，但水中仍然存在可溶性的有机物，可以污染离子交换柱从而降低其功效，去离子水存放后也容易引起细菌的繁殖。

3、反渗水（Reverse osmosis Water）：其生成的原理是水分子在压力的作用下，通过反渗透膜成为纯水，水中的杂质被反渗透膜截留排出。

反渗水克服了蒸馏水和去离子水的许多缺点，利用反渗透技术可以有效的去除水中的溶解盐、胶体，细菌、病毒、细菌内毒素和大部分有机物等杂质，但不同厂家生产的反渗透膜对反渗水的质量影响很大。

4、超纯水（Ultra-pure grade water）：其标准是水电阻率为18.2MΩ-cm。

但超纯水在TOC、细菌、内毒素等指标方面并不相同，要根据实验的要求来确定，如细胞培养则对细菌和内毒素有要求，而HPLC则要求TOC低。

评价水质的常用指标：1、电阻率（electrical resistivity）：衡量实验室用水导电性能的指标，单位为MΩ-cm，随着水内无机离子的减少电阻加大则数值逐渐变大，实验室超纯水的标准:电阻率为18.2MΩ-cm。

2、总有机碳（Total Organic Carbon ，TOC）：水中碳的的浓度，反映水中氧化的有机化合物的含量，单位为ppm 或 ppb。

3、内毒素（Endotoxin）：革兰氏阴性细菌的脂多糖细胞壁碎片，又称之为“热原”，单位cuf/ml。

流体力学：第5章势流理论-上

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信号与系统》专业术语中英文对照表

《信号与系统》专业术语中英文对照表第 1 章绪论信号（signal）系统（system）电压（voltage）电流（current）信息（information）电路（circuit）网络（network）确定性信号（determinate signal）随机信号（random signal）一维信号（one –dimensional signal）多维信号（multi–dimensional signal）连续时间信号（continuous time signal）离散时间信号（discrete time signal）取样信号（sampling signal）数字信号（digital signal）周期信号（periodic signal）非周期信号（nonperiodic（aperiodic）signal）能量（energy）功率（power）能量信号（energy signal）功率信号（power signal）平均功率（average power）平均能量（average energy）指数信号（exponential signal）时间常数（time constant）正弦信号（sine signal）余弦信号（cosine signal）振幅（amplitude）角频率（angular frequency）初相位（initial phase）周期（period）频率（frequency）欧拉公式（Euler’s formula）复指数信号（complex exponential signal）复频率（complex frequency）实部（real part）虚部（imaginary part）抽样函数Sa(t)（sampling（Sa）function）偶函数（even function）奇异函数（singularity function）奇异信号（singularity signal）单位斜变信号（unit ramp signal）斜率（slope）单位阶跃信号（unit step signal）符号函数（signum function）单位冲激信号（unit impulse signal）广义函数（generalized function）取样特性（sampling property）冲激偶信号（impulse doublet signal）奇函数（odd function）偶分量（even component）奇分量（odd component）正交函数（orthogonal function）正交函数集（set of orthogonal function）数学模型（mathematics model）电压源（voltage source）基尔霍夫电压定律（Kirchhoff’s voltage law（KVL））电流源（current source）连续时间系统（continuous time system）离散时间系统（discrete time system）微分方程（differential function）差分方程（difference function）线性系统（linear system）非线性系统（nonlinear system）时变系统（time–varying system）时不变系统（time–invariant system）集总参数系统（lumped–parameter system）分布参数系统（distributed–parameter system）偏微分方程（partial differential function）因果系统（causal system）非因果系统（noncausal system）因果信号（causal signal）叠加性（superposition property）均匀性（homogeneity）积分（integral）输入–输出描述法（input–output analysis）状态变量描述法（state variable analysis）单输入单输出系统（single–input and single–output system）状态方程（state equation）输出方程（output equation）多输入多输出系统（multi–input and multi–output system）时域分析法（time domain method）变换域分析法（transform domain method）卷积（convolution）傅里叶变换（Fourier transform）拉普拉斯变换（Laplace transform）第 2 章连续时间系统的时域分析齐次解（homogeneous solution）特解（particular solution）特征方程（characteristic function）特征根（characteristic root）固有（自由）解（natural solution）强迫解（forced solution）起始条件（original condition）初始条件（initial condition）自由响应（natural response）强迫响应（forced response）零输入响应（zero-input response）零状态响应（zero-state response）冲激响应（impulse response）阶跃响应（step response）卷积积分（convolution integral）交换律（exchange law）分配律（distribute law）结合律（combine law）第3 章傅里叶变换频谱（frequency spectrum）频域（frequency domain）三角形式的傅里叶级数（trigonomitric Fourier series）指数形式的傅里叶级数（exponential Fourier series）傅里叶系数（Fourier coefficient）直流分量（direct composition）基波分量（fundamental composition）n 次谐波分量（nth harmonic component）复振幅（complex amplitude）频谱图（spectrum plot（diagram））幅度谱（amplitude spectrum）相位谱（phase spectrum）包络（envelop）离散性（discrete property）谐波性（harmonic property）收敛性（convergence property）奇谐函数（odd harmonic function）吉伯斯现象（Gibbs phenomenon）周期矩形脉冲信号（periodic rectangular pulse signal）周期锯齿脉冲信号（periodic sawtooth pulse signal）周期三角脉冲信号（periodic triangular pulse signal）周期半波余弦信号（periodic half–cosine signal）周期全波余弦信号（periodic full–cosine signal）傅里叶逆变换（inverse Fourier transform）频谱密度函数（spectrum density function）单边指数信号（single–sided exponential signal）双边指数信号（two–sided exponential signal）对称矩形脉冲信号（symmetry rectangular pulse signal）线性（linearity）对称性（symmetry）对偶性（duality）位移特性（shifting）时移特性（time–shifting）频移特性（frequency–shifting）调制定理（modulation theorem）调制（modulation）解调（demodulation）变频（frequency conversion）尺度变换特性（scaling）微分与积分特性（differentiation and integration）时域微分特性（differentiation in the time domain）时域积分特性（integration in the time domain）频域微分特性（differentiation in the frequency domain）频域积分特性（integration in the frequency domain）卷积定理（convolution theorem）时域卷积定理（convolution theorem in the time domain）频域卷积定理（convolution theorem in the frequency domain）取样信号（sampling signal）矩形脉冲取样（rectangular pulse sampling）自然取样（nature sampling）冲激取样（impulse sampling）理想取样（ideal sampling）取样定理（sampling theorem）调制信号（modulation signal）载波信号（carrier signal）已调制信号（modulated signal）模拟调制（analog modulation）数字调制（digital modulation）连续波调制（continuous wave modulation）脉冲调制（pulse modulation）幅度调制（amplitude modulation）频率调制（frequency modulation）相位调制（phase modulation）角度调制（angle modulation）频分多路复用（frequency–division multiplex（FDM））时分多路复用（time –division multiplex（TDM））相干（同步）解调（synchronous detection）本地载波（local carrier）系统函数（system function）网络函数（network function）频响特性（frequency response）幅频特性（amplitude frequency response）相频特性（phase frequency response）无失真传输（distortionless transmission）理想低通滤波器（ideal low–pass filter）截止频率（cutoff frequency）正弦积分（sine integral）上升时间（rise time）窗函数（window function）理想带通滤波器（ideal band–pass filter）第 4 章拉普拉斯变换代数方程（algebraic equation）双边拉普拉斯变换（two-sided Laplace transform）双边拉普拉斯逆变换（inverse two-sided Laplace transform）单边拉普拉斯变换（single-sided Laplace transform）拉普拉斯逆变换（inverse Laplace transform）收敛域（region of convergence（ROC））延时特性（time delay）s 域平移特性（shifting in the s-domain）s 域微分特性（differentiation in the s-domain）s 域积分特性（integration in the s-domain）初值定理（initial-value theorem）终值定理（expiration-value）复频域卷积定理（convolution theorem in the complex frequency domain）部分分式展开法（partial fraction expansion）留数法（residue method）第 5 章策动点函数（driving function）转移函数（transfer function）极点（pole）零点（zero）零极点图（zero-pole plot）暂态响应（transient response）稳态响应（stable response）稳定系统（stable system）一阶系统（first order system）高通滤波网络（high-low filter）低通滤波网络（low-pass filter）二阶系统（second system）最小相移系统（minimum-phase system）维纳滤波器（Winner filter）卡尔曼滤波器（Kalman filter）低通（low-pass）高通（high-pass）带通（band-pass）带阻（band-stop）有源（active）无源（passive）模拟（analog）数字（digital）通带（pass-band）阻带（stop-band）佩利－维纳准则（Paley-Winner criterion）最佳逼近（optimum approximation）过渡带（transition-band）通带公差带（tolerance band）巴特沃兹滤波器（Butterworth filter）切比雪夫滤波器（Chebyshew filter）方框图（block diagram）信号流图（signal flow graph）节点（node）支路（branch）输入节点（source node）输出节点（sink node）混合节点（mix node）通路（path）开通路（open path）闭通路（close path）环路（loop）自环路（self-loop）环路增益（loop gain）不接触环路（disconnect loop）前向通路（forward path）前向通路增益（forward path gain）梅森公式（Mason formula）劳斯准则（Routh criterion）第 6 章数字系统（digital system）数字信号处理（digital signal processing）差分方程（difference equation）单位样值响应（unit sample response）卷积和（convolution sum）Z 变换（Z transform）序列（sequence）样值（sample）单位样值信号（unit sample signal）单位阶跃序列（unit step sequence）矩形序列(rectangular sequence)单边实指数序列（single sided real exponential sequence）单边正弦序列（single sided exponential sequence）斜边序列（ramp sequence）复指数序列（complex exponential sequence）线性时不变离散系统（linear time-invariant discrete-time system）常系数线性差分方程（linear constant-coefficient difference equation）后向差分方程（backward difference equation）前向差分方程（forward difference equation）海诺塔（Tower of Hanoi）菲波纳西（Fibonacci）冲激函数串（impulse train）第7 章数字滤波器（digital filter）单边Z 变换（single-sided Z transform）双边Z 变换(two-sided (bilateral) Z transform) 幂级数（power series）收敛（convergence）有界序列（limitary-amplitude sequence）正项级数（positive series）有限长序列（limitary-duration sequence）右边序列（right-sided sequence）左边序列（left-sided sequence）双边序列（two-sided sequence）Z 逆变换（inverse Z transform）围线积分法（contour integral method）幂级数展开法（power series expansion）z 域微分（differentiation in the z-domain）序列指数加权（multiplication by an exponential sequence）z 域卷积定理（z-domain convolution theorem）帕斯瓦尔定理（Parseval theorem）传输函数（transfer function）序列的傅里叶变换（discrete-time Fourier transform：DTFT）序列的傅里叶逆变换（inverse discrete-time Fourier transform：IDTFT）幅度响应（magnitude response）相位响应（phase response）量化（quantization）编码（coding）模数变换（A/D 变换：analog-to-digital conversion）数模变换（D/A 变换：digital-to- analog conversion）第8 章端口分析法（port analysis）状态变量（state variable）无记忆系统（memoryless system）有记忆系统（memory system）矢量矩阵（vector-matrix ）常量矩阵（constant matrix ）输入矢量（input vector）输出矢量（output vector）直接法（direct method）间接法（indirect method）状态转移矩阵（state transition matrix）系统函数矩阵（system function matrix）冲激响应矩阵（impulse response matrix）朱里准则（July criterion）。

计算机IT 英语专业词汇

数据结构基本英语词汇Recursion 递归pivot ['pivət] 轴数据抽象data abstraction数据元素data element数据对象data object数据项data item数据类型data type抽象数据类型abstract data type逻辑结构logical structure物理结构phyical structure线性结构linear structure非线性结构nonlinear structure基本数据类型atomic data type固定聚合数据类型fixed-aggregate data type可变聚合数据类型variable-aggregate data type线性表linear list栈stack队列queue串string数组array树tree图gragh查找，线索searching更新updating排序（分类) sorting插入insertion删除deletion前趋predecessor后继successor直接前趋immediate predecessor直接后继immediate successor双端列表deque(double-ended queue) 循环队列cirular queue指针pointer先进先出表（队列）first-in first-out list 后进先出表（队列）last-in first-out list 栈底bottom栈定top压入push弹出pop队头front队尾rear上溢overflow下溢underflow数组array矩阵matrix多维数组multi-dimentional array以行为主的顺序分配row major order 以列为主的顺序分配column major order三角矩阵truangular matrix对称矩阵symmetric matrix稀疏矩阵sparse matrix转置矩阵transposed matrix链表linked list线性链表linear linked list单链表single linked list多重链表multilinked list循环链表circular linked list双向链表doubly linked list十字链表orthogonal list广义表generalized list链link指针域pointer field链域link field头结点head node头指针head pointer尾指针tail pointer串string空白（空格）串blank string空串（零串）null string子串substring树tree子树subtree森林forest根root叶子leaf结点node深度depth层次level双亲parents孩子children兄弟brother祖先ancestor子孙descentdant二叉树binary tree平衡二叉树banlanced binary tree 满二叉树full binary tree完全二叉树complete binary tree遍历二叉树traversing binary tree 二叉排序树binary sort tree二叉查找树binary search tree线索二叉树threaded binary tree哈夫曼树Huffman tree有序数ordered tree无序数unordered tree判定树decision tree双链树doubly linked tree数字查找树digital search tree树的遍历traversal of tree先序遍历preorder traversal中序遍历inorder traversal后序遍历postorder traversal图graph子图subgraph有向图digraph(directed graph)无向图undigraph(undirected graph) 完全图complete graph连通图connected graph非连通图unconnected graph强连通图strongly connected graph 弱连通图weakly connected graph 加权图weighted graph有向无环图directed acyclic graph 稀疏图spares graph 稠密图dense graph重连通图biconnected graph二部图bipartite graph边edge顶点vertex弧arc路径path回路（环）cycle弧头head弧尾tail源点source终点destination汇点sink权weight连接点articulation point初始结点initial node终端结点terminal node相邻边adjacent edge相邻顶点adjacent vertex关联边incident edge入度indegree出度outdegree最短路径shortest path有序对ordered pair无序对unordered pair简单路径simple path简单回路simple cycle连通分量connected component邻接矩阵adjacency matrix邻接表adjacency list邻接多重表adjacency multilist遍历图traversing graph生成树spanning tree最小（代价）生成树minimum(cost)spanning tree生成森林spanning forest拓扑排序topological sort偏序partical order拓扑有序topological orderAOV网activity on vertex network AOE网activity on edge network关键路径critical path匹配matching最大匹配maximum matching增广路径augmenting path增广路径图augmenting path graph查找searching线性查找（顺序查找）linear search (sequential search)二分查找binary search分块查找block search散列查找hash search平均查找长度average search length电脑专业术语散列表hash table散列函数hash funticion直接定址法immediately allocating method数字分析法digital analysis method平方取中法mid-square method折叠法folding method除法division method随机数法random number method排序sort内部排序internal sort外部排序external sort插入排序insertion sort随小增量排序diminishing increment sort选择排序selection sort堆排序heap sort快速排序quick sort归并排序merge sort基数排序radix sort外部排序external sort平衡归并排序balance merging sort二路平衡归并排序balance two-way merging sort多步归并排序ployphase merging sort 置换选择排序replacement selection sort 文件file主文件master file顺序文件sequential file索引文件indexed file索引顺序文件indexed sequential file 索引非顺序文件indexed non-sequential file直接存取文件direct access file多重链表文件multilist file倒排文件inverted file目录结构directory structure树型索引tree indexJava基础常见英语词汇(共70个)Compile:编绎Run:运行Class:类Object:对象System:系统out:输出print:打印line:行variable:变量type:类型operation:操作,运算array:数组parameter:参数method:方法function:函数member-variable:成员变量member-function:成员函数get:得到set:设置public:公有的private:私有的protected:受保护的default:默认access:访问package:包import:导入static:静态的void:无(返回类型) extends:继承parent class:父类base class:基类super class:超类child class:子类derived class:派生类override:重写,覆盖overload:重载final:最终的,不能改变的abstract:抽象interface:接口implements:实现exception:异常Runtime:运行时ArithmeticException:算术异常ArrayIndexOutOfBoundsException:数组下标越界异常NullPointerException:空引用异常ClassNotFoundException:类没有发现异常NumberFormatException:数字格式异常(字符串不能转化为数字)Try:尝试Catch:捕捉Finally:最后Throw:抛出Throws: (投掷)表示强制异常处理Throwable:(可抛出的)表示所有异常类的祖先类Lang:language,语言Util:工具Display:显示Random:随机Collection:集合ArrayList:(数组列表)表示动态数组HashMap: 散列表,哈希表Swing:轻巧的Awt:abstract window toolkit:抽象窗口工具包Vertical:垂直Horizonatal:水平Label:标签TextField:文本框TextArea:文本域Button:按钮Checkbox:复选框Radiobutton:单选按钮Combobox:复选框Event:事件Mouse:鼠标Key:键Focus:焦点Listener:监听Tree:树Node:节点Jdbc:java database connectivity,java数据库连接DriverManager:驱动管理器Connection:连接Statement:表示执行对象Preparedstatement:表示预执行对象Resultset:结果集Next:下一个Close:关闭executeQuery:执行查询JSP中常用英文URL: Universal Resource Location:统一资源定位符IE: Internet Explorer 因特网浏览器JSP:java server page.java服务器页面Model:模型View:视图C:controller:控制器Tomcat:一种jsp的web服务器WebModule:web模块Servlet:小服务程序Request:请求Response:响应Init: initialize,初始化Service:服务Destroy:销毁Startup:启动Mapping:映射pattern:模式Getparameter:获取参数Session:会话Application:应用程序Context:上下文redirect:重定向dispatch:分发forward:转交setattribute:设置属性getattribute:获取属性page:页面contentType:内容类型charset:字符集include:包含tag:标签taglib:标签库EL:expression language,表达式语言Scope:作用域Empty:空JSTL:java standard tag library,java标准标签库TLD:taglib description,标签库描述符Core:核心Test:测试Foreach:表示循环Var:variable,变量Status:状态Items:项目集合Fmt:format,格式化Filter:过滤器。

《信号与系统》专业术语中英文对照表(20200705175237)

《信号与系统》专业术语中英文对照表第 1 章绪论信号（signal）系统（system）电压（voltage）电流（current）信息（information）电路（circuit）网络（network）确定性信号（determinate signal）随机信号（random signal）一维信号（one–dimensional signal）多维信号（multi–dimensional signal）连续时间信号（continuous time signal）离散时间信号（discrete time signal）取样信号（sampling signal）数字信号（digital signal）周期信号（periodic signal）非周期信号（nonperiodic（aperiodic） signal）能量（energy）功率（power）能量信号（energy signal）功率信号（power signal）平均功率（average power）平均能量（average energy）指数信号（exponential signal）时间常数（time constant）正弦信号（sine signal）余弦信号（cosine signal）振幅（amplitude）角频率（angular frequency）初相位（initial phase）周期（period）频率（frequency）欧拉公式（Euler’s formula）复指数信号（complex exponential signal）复频率（complex frequency）实部（real part）虚部（imaginary part）抽样函数 Sa(t)（sampling（Sa） function）偶函数（even function）奇异函数（singularity function）奇异信号（singularity signal）单位斜变信号（unit ramp signal）斜率（slope）单位阶跃信号（unit step signal）符号函数（signum function）单位冲激信号（unit impulse signal）广义函数（generalized function）取样特性（sampling property）冲激偶信号（impulse doublet signal）奇函数（odd function）偶分量（even component）奇分量（odd component）正交函数（orthogonal function）正交函数集（set of orthogonal function）数学模型（mathematics model）电压源（voltage source）基尔霍夫电压定律（Kirchhoff’s voltage law（KVL））电流源（current source）连续时间系统（continuous time system）离散时间系统（discrete time system）微分方程（differential function）差分方程（difference function）线性系统（linear system）非线性系统（nonlinear system）时变系统（time–varying system）时不变系统（time–invariant system）集总参数系统（lumped–parameter system）分布参数系统（distributed–parameter system）偏微分方程（partial differential function）因果系统（causal system）非因果系统（noncausal system）因果信号（causal signal）叠加性（superposition property）均匀性（homogeneity）积分（integral）输入–输出描述法（input–output analysis）状态变量描述法（state variable analysis）单输入单输出系统（single–input and single–output system）状态方程（state equation）输出方程（output equation）多输入多输出系统（multi–input and multi–output system）时域分析法（time domain method）变换域分析法（transform domain method）卷积（convolution）傅里叶变换（Fourier transform）拉普拉斯变换（Laplace transform）第 2 章连续时间系统的时域分析齐次解（homogeneous solution）特解（particular solution）特征方程（characteristic function）特征根（characteristic root）固有（自由）解（natural solution）强迫解（forced solution）起始条件（original condition）初始条件（initial condition）自由响应（natural response）强迫响应（forced response）零输入响应（zero-input response）零状态响应（zero-state response）冲激响应（impulse response）阶跃响应（step response）卷积积分（convolution integral）交换律（exchange law）分配律（distribute law）结合律（combine law）第3 章傅里叶变换频谱（frequency spectrum）频域（frequency domain）三角形式的傅里叶级数（trigonomitric Fourier series）指数形式的傅里叶级数（exponential Fourier series）傅里叶系数（Fourier coefficient）直流分量（direct composition）基波分量（fundamental composition） n 次谐波分量（nth harmonic component）复振幅（complex amplitude）频谱图（spectrum plot（diagram））幅度谱（amplitude spectrum）相位谱（phase spectrum）包络（envelop）离散性（discrete property）谐波性（harmonic property）收敛性（convergence property）奇谐函数（odd harmonic function）吉伯斯现象（Gibbs phenomenon）周期矩形脉冲信号（periodic rectangular pulse signal）周期锯齿脉冲信号（periodic sawtooth pulse signal）周期三角脉冲信号（periodic triangular pulse signal）周期半波余弦信号（periodic half–cosine signal）周期全波余弦信号（periodic full–cosine signal）傅里叶逆变换（inverse Fourier transform）频谱密度函数（spectrum density function）单边指数信号（single–sided exponential signal）双边指数信号（two–sided exponential signal）对称矩形脉冲信号（symmetry rectangular pulse signal）线性（linearity）对称性（symmetry）对偶性（duality）位移特性（shifting）时移特性（time–shifting）频移特性（frequency–shifting）调制定理（modulation theorem）调制（modulation）解调（demodulation）变频（frequency conversion）尺度变换特性（scaling）微分与积分特性（differentiation and integration）时域微分特性（differentiation in the time domain）时域积分特性（integration in the time domain）频域微分特性（differentiation in the frequency domain）频域积分特性（integration in the frequency domain）卷积定理（convolution theorem）时域卷积定理（convolution theorem in the time domain）频域卷积定理（convolution theorem in the frequency domain）取样信号（sampling signal）矩形脉冲取样（rectangular pulse sampling）自然取样（nature sampling）冲激取样（impulse sampling）理想取样（ideal sampling）取样定理（sampling theorem）调制信号（modulation signal）载波信号（carrier signal）已调制信号（modulated signal）模拟调制（analog modulation）数字调制（digital modulation）连续波调制（continuous wave modulation）脉冲调制（pulse modulation）幅度调制（amplitude modulation）频率调制（frequency modulation）相位调制（phase modulation）角度调制（angle modulation）频分多路复用（frequency–division multiplex（FDM））时分多路复用（time–division multiplex （TDM））相干（同步）解调（synchronous detection）本地载波（local carrier）系统函数（system function）网络函数（network function）频响特性（frequency response）幅频特性（amplitude frequency response）相频特性（phase frequency response）无失真传输（distortionless transmission）理想低通滤波器（ideal low–pass filter）截止频率（cutoff frequency）正弦积分（sine integral）上升时间（rise time）窗函数（window function）理想带通滤波器（ideal band–pass filter）第 4 章拉普拉斯变换代数方程（algebraic equation）双边拉普拉斯变换（two-sided Laplace transform）双边拉普拉斯逆变换（inverse two-sided Laplace transform）单边拉普拉斯变换（single-sided Laplace transform）拉普拉斯逆变换（inverse Laplace transform）收敛域（region of convergence（ROC））延时特性（time delay）s 域平移特性（shifting in the s-domain）s 域微分特性（differentiation in the s-domain） s 域积分特性（integration in the s-domain）初值定理（initial-value theorem）终值定理（expiration-value）复频域卷积定理（convolution theorem in the complex frequency domain）部分分式展开法（partial fraction expansion）留数法（residue method）第 5 章策动点函数（driving function）转移函数（transfer function）极点（pole）零点（zero）零极点图（zero-pole plot）暂态响应（transient response）稳态响应（stable response）稳定系统（stable system）一阶系统（first order system）高通滤波网络（high-low filter）低通滤波网络（low-pass filter）二阶系统（second system）最小相移系统（minimum-phase system）维纳滤波器（Winner filter）卡尔曼滤波器（Kalman filter）低通（low-pass）高通（high-pass）带通（band-pass）带阻（band-stop）有源（active）无源（passive）模拟（analog）数字（digital）通带（pass-band）阻带（stop-band）佩利－维纳准则（Paley-Winner criterion）最佳逼近（optimum approximation）过渡带（transition-band）通带公差带（tolerance band）巴特沃兹滤波器（Butterworth filter）切比雪夫滤波器（Chebyshew filter）方框图（block diagram）信号流图（signal flow graph）节点（node）支路（branch）输入节点（source node）输出节点（sink node）混合节点（mix node）通路（path）开通路（open path）闭通路（close path）环路（loop）自环路（self-loop）环路增益（loop gain）不接触环路（disconnect loop）前向通路（forward path）前向通路增益（forward path gain）梅森公式（Mason formula）劳斯准则（Routh criterion）第 6 章数字系统（digital system）数字信号处理（digital signal processing）差分方程（difference equation）单位样值响应（unit sample response）卷积和（convolution sum）Z 变换（Z transform）序列（sequence）样值（sample）单位样值信号（unit sample signal）单位阶跃序列（unit step sequence）矩形序列 (rectangular sequence)单边实指数序列（single sided real exponential sequence）单边正弦序列（single sided exponential sequence）斜边序列（ramp sequence）复指数序列（complex exponential sequence）线性时不变离散系统（linear time-invariant discrete-time system）常系数线性差分方程（linear constant-coefficient difference equation）后向差分方程（backward difference equation）前向差分方程（forward difference equation）海诺塔（Tower of Hanoi）菲波纳西（Fibonacci）冲激函数串（impulse train）第 7 章数字滤波器（digital filter）单边 Z 变换（single-sided Z transform）双边 Z 变换(two-sided (bilateral) Z transform) 幂级数（power series）收敛（convergence）有界序列（limitary-amplitude sequence）正项级数（positive series）有限长序列（limitary-duration sequence）右边序列（right-sided sequence）左边序列（left-sided sequence）双边序列（two-sided sequence） Z 逆变换（inverse Z transform）围线积分法（contour integral method）幂级数展开法（power series expansion） z 域微分（differentiation in the z-domain）序列指数加权（multiplication by an exponential sequence） z 域卷积定理（z-domain convolution theorem）帕斯瓦尔定理（Parseval theorem）传输函数（transfer function）序列的傅里叶变换（discrete-time Fourier transform：DTFT）序列的傅里叶逆变换（inverse discrete-time Fourier transform：IDTFT）幅度响应（magnitude response）相位响应（phase response）量化（quantization）编码（coding）模数变换（A/D 变换：analog-to-digital conversion）数模变换（D/A 变换：digital-to- analog conversion）第 8 章端口分析法（port analysis）状态变量（state variable）无记忆系统（memoryless system）有记忆系统（memory system）矢量矩阵（vector-matrix ）常量矩阵（constant matrix ）输入矢量（input vector）输出矢量（output vector）直接法（direct method）间接法（indirect method）状态转移矩阵（state transition matrix）系统函数矩阵（system function matrix）冲激响应矩阵（impulse response matrix）朱里准则（July criterion）。

莫加ioLogik E1200系列以太网远程输入输出（I O）及两口以太网交换机特点和优势说明书

ioLogik E1200SeriesEthernet remote I/O with2-port Ethernet switchFeatures and Benefits•User-definable Modbus TCP Slave addressing•Supports EtherNet/IP Adapter mode1•Supports RESTful API for IIoT applications•2-port Ethernet switch for daisy-chain topologies•Saves time and wiring costs with peer-to-peer communications•Active communication with MX-AOPC UA Server•Supports SNMP v1/v2c•Easy mass deployment and configuration with ioSearch utility•Friendly configuration via web browser•Simplifies I/O management with MXIO library for Windows or Linux•Class I Division2,ATEX Zone2certification2•Wide operating temperature models available for-40to75°C(-40to167°F)environmentsCertificationsIntroductionThe ioLogik E1200Series supports the most often-used protocols for retrieving I/O data,making it capable of handling a wide variety of applications.Most IT engineers use SNMP or RESTful API protocols,but OT engineers are more familiar with OT-based protocols,such as Modbus and EtherNet/IP.Moxa's Smart I/O makes it possible for both IT and OT engineers to conveniently retrieve data from the same I/O device.The ioLogik E1200Series speaks six different protocols,including Modbus TCP,EtherNet/IP,and Moxa AOPC for OT engineers,as well as SNMP, RESTful API,and Moxa MXIO library for IT engineers.The ioLogik E1200retrieves I/O data and converts the data to any of these protocols at the same time,allowing you to get your applications connected easily and effortlessly.Daisy-Chained Ethernet I/O ConnectionThis industrial Ethernet remote I/O comes with two switched Ethernet ports to allow for the free flow of information downstream to another local Ethernet device,or upstream to a control server via expandable daisy-chained Ethernet I/O arrays.Applications such as factory automation, security and surveillance systems,and tunneled connections can make use of daisy-chained Ethernet for building multidrop I/O networks over standard Ethernet cables.Many industrial automation users are familiar with multidrop as the configuration most typically used in fieldbus solutions.The daisy-chain capabilities supported by ioLogik Ethernet remote I/O units not only increase the expandability and installation possibilities for your remote I/O applications,but also lower overall costs by reducing the need for separate Ethernet switches.Daisy-chaining devices in this way will also reduce overall labor and cabling expenses.1.Requires online registration(available free of charge)2.Class I Division2and ATEX currently do not apply to the E1213/E1213-T models.Save Time and Wiring Costs with Peer-to-Peer CommunicationsIn remote automation applications,the control room and sensors areoften far removed,making wiring over long distances a constantchallenge.With peer-to-peer networking,users may now map a pairof ioLogik Series modules so that input values will be directlytransferred to output channels,greatly simplifying the wiring processand reducing wiring costs.User-Definable Modbus TCP Addressing for Painless Upgrading of Existing SystemsFor Modbus devices that are controlled and detected by fixedaddresses,users need to spend a vast amount of time researchingand verifying initial ers need to locate each device’snetworking details,such as I/O channels or vendor-definedaddresses,to enable the initial or start address of a SCADA system orPLC.Devices that support user-definable Modbus TCP addressingoffer greater flexibility and easier setup.Instead of worrying aboutindividual devices,users simply configure the function and addressmap to fit their needs.Push Technology for EventsWhen used with MX-AOPC UA Server,devices can use active pushcommunications when communicating changes in state and/orevents to a SCADA system.Unlike a polling system,when using apush architecture for communications with a SCADA system,messages will only be delivered when changes in state or configuredevents occur,resulting in higher accuracy and lower amounts of datathat need to be transferred.SpecificationsInput/Output InterfaceAnalog Input Channels ioLogik E1240models:8ioLogik E1242models:4Analog Output Channels ioLogik E1241models:4Configurable DIO Channels(by jumper)ioLogik E1212models:8ioLogik E1213/E1242models:4Digital Input Channels ioLogik E1210models:16ioLogik E1212/E1213models:8ioLogik E1214models:6ioLogik E1242models:4Digital Output Channels ioLogik E1211models:16ioLogik E1213models:4Isolation3k VDC or2k VrmsRelay Channels ioLogik E1214models:6RTD Channels ioLogik E1260models:6Thermocouple Channels ioLogik E1262models:8Buttons Reset buttonDigital InputsConnector Screw-fastened Euroblock terminalCounter Frequency250HzDigital Filtering Time Interval Software configurableDry Contact On:short to GNDOff:openI/O Mode DI or event counterPoints per COM ioLogik E1210/E1212models:8channelsioLogik E1213models:12channelsioLogik E1214models:6channelsioLogik E1242models:4channelsSensor Type Dry contactWet Contact(NPN or PNP)Wet Contact(DI to COM)On:10to30VDCOff:0to3VDCDigital OutputsConnector Screw-fastened Euroblock terminalCurrent Rating ioLogik E1211/E1212/E1242models:200mA per channelioLogik E1213models:500mA per channelI/O Mode DO or pulse outputI/O Type ioLogik E1211/E1212/E1242models:SinkioLogik E1213models:SourceOver-Current Protection ioLogik E1211/E1212/E1242models:2.6A per channel@25°CioLogik E1213models:1.5A per channel@25°COver-Temperature Shutdown175°C(typical),150°C(min.)Over-Voltage Protection35VDCPulse Output Frequency500Hz(max.)RelaysBreakdown Voltage500VACConnector Screw-fastened Euroblock terminalContact Current Rating Resistive load:5A@30VDC,250VAC,110VACContact Resistance100milli-ohms(max.)Electrical Endurance100,000operations@5A resistive loadInitial Insulation Resistance1,000mega-ohms(min.)@500VDCMechanical Endurance5,000,000operationsPulse Output Frequency0.3Hz at rated load(max.)Type Form A(N.O.)power relayNote Ambient humidity must be non-condensing and remain between5and95%.The relaysmay malfunction when operating in high condensation environments below0°C. Analog InputsAccuracy ioLogik E1240/E1242:±0.1%FSR@25°C±0.3%FSR@-10to60°CioLogik E1240-T/E1242-T:±0.1%FSR@25°C±0.3%FSR@-10to60°C±0.5%FSR@-40to75°CBuilt-in Resistor for Current Input120ohmsConnector Screw-fastened Euroblock terminalI/O Mode Voltage/CurrentI/O Type DifferentialInput Impedance10mega-ohms(min.)Input Range0to10VDC0to20mA4to20mA4to20mA(with burn-out detection)Resolution16bitsSampling Rate All channels:12samples/secPer channel:1.5samples/secAnalog OutputsAccuracy ioLogik E1241:±0.1%FSR@25°C±0.3%FSR@-10to60°CioLogik E1241-T:±0.1%FSR@25°C±0.3%FSR@-40to75°CConnector Screw-fastened Euroblock terminalVoltage Output Short-Circuit Protection10mAInternal Resistor400ohmsNote:24V of external power required when loading exceeds1000ohmsOutput Range0to10VDC4to20mAResolution12-bitRTDsAccuracy ioLogik E1260:±0.1%FSR@25°C±0.3%FSR@-10to60°CioLogik E1260-T:±0.1%FSR@25°C±0.3%FSR@-40to75°CConnector Screw-fastened Euroblock terminalInput Connection2-or3-wireInput Impedance625kilo-ohms(min.)Sensor Type PT1000(-200to350°C)PT50,PT100,PT200,PT500(-200to850°C)Resistance Type310,620,1250,and2200ohmsResolution0.1°C or0.1ohmsSampling Rate All channels:12samples/secPer channel:2samples/secThermocouplesMillivolt Accuracy ioLogik E1262:±0.1%FSR@25°C±0.3%FSR@-10to60°CioLogik E1262-T:±0.1%FSR@25°C±0.3%FSR@-40to75°CConnector Screw-fastened Euroblock terminalTC Accuracy Types J,T,E,S,B:±5°CTypes K,R,N:±8°CCJC Accuracy±0.5°C@25°C±1.5°C@-40to75°CInput Impedance10mega-ohms(min.)Millivolt Type±19.532mV±39.062mV±78.126mVFault and over-voltage protection:-35to+35VDC(power off);-25to+30VDC(poweron)Resolution16bitsSampling Rate All channels:12samples/secPer channel:1.5samples/secSensor Type J,K,T,E,R,S,B,NEthernet Interface10/100BaseT(X)Ports(RJ45connector)2,1MAC address(Ethernet bypass)Magnetic Isolation Protection 1.5kV(built-in)Ethernet Software FeaturesConfiguration Options Web Console(HTTP),Windows Utility(ioSearch)Industrial Protocols EtherNet/IP Adapter(Slave),Modbus TCP Server(Slave),Moxa AOPC(Active Tag),MXIO LibraryManagement BOOTP,RESTful API,DHCP Client,HTTP,IPv4,TCP/IP,UDP,SNMPv1Trap,SNMPv1/v2cMIB Device Settings MIBSecurity Access control listLED InterfaceLED Indicators Power,Ready,Port1,Port2Modbus TCPFunctions Supported1,2,3,4,5,6,15,16,23Mode ServerMax.No.of Client Connections10EtherNet/IPMode AdapterMax.No.of Scanner Connections9(for read-only),1(for read/write)Power ParametersPower Connector Screw-fastened Euroblock terminalNo.of Power Inputs1Input Voltage12to36VDCPower Consumption ioLogik E1210Series:110mA@24VDCioLogik E1211Series:200mA@24VDCioLogik E1212Series:155mA@24VDCioLogik E1213Series:130mA@24VDCioLogik E1214Series:188mA@24VDCioLogik E1240Series:121mA@24VDCioLogik E1241Series:194mA@24VDCioLogik E1242Series:139mA@24VDCioLogik E1260Series:110mA@24VDCioLogik E1262Series:118mA@24VDCPhysical CharacteristicsHousing PlasticDimensions27.8x124x84mm(1.09x4.88x3.31in)Weight200g(0.44lb)Installation DIN-rail mounting,Wall mountingWiring I/O cable,16to26AWGPower cable,12to24AWGEnvironmental LimitsOperating Temperature Standard Models:-10to60°C(14to140°F)Wide Temp.Models:-40to75°C(-40to167°F)Storage Temperature(package included)-40to85°C(-40to185°F)Ambient Relative Humidity5to95%(non-condensing)Altitude2000m3Standards and CertificationsEMC EN55032/24,EN61000-6-2/-6-4EMI CISPR32,FCC Part15B Class AEMS IEC61000-4-2ESD:Contact:4kV;Air:8kVIEC61000-4-3RS:80MHz to1GHz:10V/mIEC61000-4-4EFT:Power:2kV;Signal:1kVIEC61000-4-5Surge:Power:2kV;Signal:1kVIEC61000-4-6CS:10VIEC61000-4-8PFMFHazardous Locations ATEX,Class I Division24Safety UL508Shock IEC60068-2-27Freefall IEC60068-2-32Vibration IEC60068-2-6DeclarationGreen Product RoHS,CRoHS,WEEEMTBFTime ioLogik E1210Series:671,345hrsioLogik E1211Series:923,027hrsioLogik E1212Series:561,930hrsioLogik E1213Series:715,256hrsioLogik E1214Series:808,744hrsioLogik E1240Series:474,053hrsioLogik E1241Series:888,656hrsioLogik E1242Series:502,210hrsioLogik E1260Series:660,260hrsioLogik E1262Series:631,418hrsStandards Telcordia SR332WarrantyWarranty Period ioLogik E1214:2years5ioLogik E1210/E1211/E1212/E1213/E1240/E1241/E1242/E1260/E1262:5years Details See /warrantyPackage ContentsDevice1x ioLogik E1200Series remote I/OInstallation Kit1x terminal block,8-pin,3.81mm1x terminal block,12-pin,3.81mm1x terminal block,3-pin,5.00mmDocumentation1x quick installation guide1x warranty card3.Please contact Moxa if you require products guaranteed to function properly at higher altitudes.4.ATEX and Class I Division2currently do not apply to the ioLogik E1213/E1213-T models.5.Because of the limited lifetime of power relays,products that use this component are covered by a2-year warranty.DimensionsOrdering InformationModel Name Input/Output Interface Digital Output Type Operating Temp. ioLogik E121016x DI–-10to60°C ioLogik E1210-T16x DI–-40to75°C ioLogik E121116x DO Sink-10to60°C ioLogik E1211-T16x DO Sink-40to75°C ioLogik E12128x DI,8x DIO Sink-10to60°C ioLogik E1212-T8x DI,8x DIO Sink-40to75°C ioLogik E12138x DI,4x DO,4x DIO Source-10to60°C ioLogik E1213-T8x DI,4x DO,4x DIO Source-40to75°C ioLogik E12146x DI,6x Relay–-10to60°C ioLogik E1214-T6x DI,6x Relay–-40to75°C ioLogik E12408x AI–-10to60°C ioLogik E1240-T8x AI–-40to75°C ioLogik E12414x AO–-10to60°C ioLogik E1241-T4x AO–-40to75°C ioLogik E12424DI,4x DIO,4x AI Sink-10to60°C ioLogik E1242-T4DI,4x DIO,4x AI Sink-40to75°C ioLogik E12606x RTD–-10to60°C ioLogik E1260-T6x RTD–-40to75°C ioLogik E12628x TC–-10to60°C ioLogik E1262-T8x TC–-40to75°CAccessories(sold separately)SoftwareMX-AOPC UA Server OPC UA Server software for converting fieldbus to the OPC UA standard©Moxa Inc.All rights reserved.Updated Aug01,2019.This document and any portion thereof may not be reproduced or used in any manner whatsoever without the express written permission of Moxa Inc.Product specifications subject to change without notice.Visit our website for the most up-to-date product information.。

Source_初始化代码流程图_ADK_2.5.1

注意：Source ：SINK ：备注：Source 整套代码的初始化流程大概可以归纳如下：先申请整个Source TASK 和PS_CONFIG 变量的内存分配并初始化，注册任务消息处理函数，初始化Sys_Vol,初始化USB ，进入Main 入口函数，设置进入初始化状态，POWER_ON Device,A2dpEncodeerInput 初始化，获取PS 配置信息，inquiry 初始化，按键初始化，电源初始化，注册Profile 应用，注册应用按照REGISTERED_PROFILE_NONE, REGISTERED_PROFILE_CL,REGISTERED_PROFILE_CODEC,REGISTERED_PROFILE_A2DP,REGISTERED_PROFILE_AVRCP,REGISTERED_PROFILE _AGHFP 顺序依次做相应模块的初始化，其中每一个Porfile 注册完成都会往对应的Msg_Handler 消息处理函数发送对应的INIT_CFM 的消息，根据对消息传递状态（message->status ）判断当前Profile 是否注册成功，如果成功会继续注册下一个应用协议，直到所有的成功应用协议注册完成，那么整个Source 应用的初始化流程就算完整的结束。

Source 代码的初始化代码流程图：。

地下水溶质运移软件介绍

8
2、MT3DMS
一、MT3DMS的开发历史
1990年代以前，虽然已经有很多有关地下水中污染物运移的研究，但是，还很少见到一个完全公开的用于地下水中污染物运移的模拟软件。而地下水中污染物的运移过程要比地下水流本身的运动要复杂得多，再加上数值模拟污染物运移过程中存在的数值弥散和人工振荡，因此，开发一套能够有效应用于实际区域地下水中污染物运移的模块化软件成为一种必需。正是为了适应这一要求，C. Zheng（郑春苗）在S. S. Papadopulos & Associates公司工作期间，由美国环境保护署（U.S. Environmental Protection Agency，USEPA）资助开发并于1990年发布了一个用于地下水中污染物运移的一个实际应用模拟软件——MT3D。MT3D软件一经发布，其源代码即由USEPA完全公开。
12
三、MT3DMS的特点
1、程序结构的模块化 2、程序代码的公开化 3、离散方法的简单化 4、求解方法的多样化
13
四、MT3DMS软件的应用现状
运用MT3DMS软件不但能模拟地下水中污染物的对流、弥散，而且能够同时模拟多种污染物组分在地下水中的运移过程以及它们各自的变化反应过程（不包括各种组分之间的化学反应），包括平衡控制的等温吸附过程、非平衡吸附过程、放射性衰变或简单生物降解过程。
解的精度。
在程序中包含了多种对流-弥散方程的求解方法使得MT3D程序能够使用于不同的地下水流场条件，这是MT3D的一个最主要的特色，同时也是它被广泛认可的一个很重要的原因。
6
图1中是对一个均匀流场中连续点源问题的模拟结果(Zheng，1990)，其中地下水渗透流速为0．33m/d，纵向弥散度为10m，横向弥散度为3m，孔隙度为0.3，连续点源的注人流量为 1m/d，注入浓度为1000×10-6。对流弥散方程的求解采用HMOC方法。图1 是模拟时间为365d时地下水中污染物浓度的等值线与解析解的对比。可以看出，MT3D的模拟结果与解析解十分吻合。

CS4353资料

Preliminary Product InformationThis document contains information for a new product.Cirrus Logic reserves the right to modify this product without notice.3.3V Stereo Audio DAC with 2V RMS Line OutputFeaturesMulti-bit Delta-Sigma Modulator 106dB A-wt Dynamic Range -93dB THD+NSingle-ended Ground Centered AnalogArchitecture–No DC-blocking Capacitors Required–Integrated Step-up/Inverting Charge Pump –Filtered Line-level Outputs–Selectable 1 or 2V RMS Full-scale OutputLow Clock-jitter Sensitivity Low-latency Digital FilteringSupports Sample Rates up to 192kHz 24-bit Resolution+3.3V Charge Pump and Core Logic, +3.3VAnalog, and +0.9 to 3.3V Interface Power SuppliesLow Power Consumption24-pin QFN, Lead-free AssemblyDescriptionThe CS4353 is a complete stereo digital-to-analog sys-tem including digital interpolation, fifth-order multi-bit delta-sigma digital-to-analog conversion, digital de-em-phasis, analog filtering, and on-chip 2V RMS line-level driver from a 3.3V supply.The advantages of this architecture include ideal differ-ential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and temper-ature, high tolerance to clock jitter, and a minimal set of external components.The CS4353 is available in a 24-pin QFN package in both Automotive (-40°C to +105°C) and Commercial (-40°C to +85°C) grades. The CDB4353 Customer Demonstration Board is also available for device evalu-ation and implementation suggestions. Please see “Ordering Information” on page 26 for complete details.These features are ideal for cost-sensitive, 2-channel audio systems including video game consoles, DVD players and recorders, A/V receivers, set-top boxes,digital TVs, mini-component systems, and mixing consoles.CS4353TABLE OF CONTENTS1. PIN DESCRIPTIONS (4)2. CHARACTERISTICS AND SPECIFICATIONS (6)RECOMMENDED OPERATING CONDITIONS (6)ABSOLUTE MAXIMUM RATINGS (6)DAC ANALOG CHARACTERISTICS (COMMERCIAL - CNZ) (7)DAC ANALOG CHARACTERISTICS (AUTOMOTIVE - DNZ) (8)COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (9)SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE (10)DIGITAL INTERFACE CHARACTERISTICS (11)INTERNAL POWER-ON RESET THRESHOLD VOLTAGES (11)DC ELECTRICAL CHARACTERISTICS (12)3. TYPICAL CONNECTION DIAGRAM (13)4. APPLICATIONS (14)4.1.1 Ground-Centered Outputs (14)4.1.2 Full-Scale Output Amplitude Control (14)4.1.3 Pseudo-Differential Outputs (14)4.8.1 Power-Up Sequences (20)4.8.1.1 External RESET Power-Up Sequence (20)4.8.1.2 Internal Power-On Reset Power-Up Sequence (20)4.8.2 Power-Down Sequences (20)4.8.2.1 External RESET Power-Down Sequence (20)4.8.2.2 Internal Power-On Reset Power-Down Sequence (20)4.9.1 Capacitor Placement (21)5. DIGITAL FILTER RESPONSE PLOTS (22)6. PARAMETER DEFINITIONS (24)7. PACKAGE DIMENSIONS (25)8. ORDERING INFORMATION (26)9. REVISION HISTORY (27)LIST OF FIGURESFigure 1.Serial Input Timing (10)Figure 2.Power-On Reset Threshold Sequence (11)Figure 3.Typical Connection Diagram (13)Figure 4.Stereo Pseudo-Differential Output (14)Figure 5.I²S, up to 24-Bit Data (16)Figure 6.Left-Justified up to 24-Bit Data (16)Figure 7.De-Emphasis Curve, Fs = 44.1 kHz (17)Figure 8.Internal Power-On Reset Circuit (17)Figure 9.Initialization and Power-Down Sequence Diagram (19)Figure 10.Single-Speed Stopband Rejection (22)Figure 11.Single-Speed Transition Band (22)Figure 12.Single-Speed Transition Band (detail) (22)Figure 13.Single-Speed Passband Ripple (22)Figure 14.Double-Speed Stopband Rejection (22)Figure 15.Double-Speed Transition Band (22)Figure 16.Double-Speed Transition Band (detail) (23)Figure 17.Double-Speed Passband Ripple (23)Figure 18.Quad-Speed Stopband Rejection (23)Figure 19.Quad-Speed Transition Band (23)Figure 20.Quad-Speed Transition Band (detail) (23)Figure 21.Quad-Speed Passband Ripple (23)LIST OF TABLESTable 1. Power-On Reset Threshold Voltages (11)Table 2. Digital I/O Pin Characteristics (12)Table 3. CS4353 Operational Mode Auto-Detect (15)Table 4. Single-Speed Mode Standard Frequencies (15)Table 5. Double-Speed Mode Standard Frequencies (15)Table 6. Quad-Speed Mode Standard Frequencies (15)Table 7. Digital Interface Format (16)1. PIN DESCRIPTIONSPin Name Pin #Pin DescriptionSCLK 1Serial Clock (Input ) - Serial clock for the serial audio interface.MCLK 2Master Clock (Input ) - Clock source for the delta-sigma modulator and digital filters. VL 3Serial Audio Interface Power (Input ) - Positive power for the serial audio interface DGND 4Digital Ground (Input ) - Ground reference for the digital section.FLYP+FLYP-75Step-Up Charge Pump Cap Positive/Negative Nodes (Output) - Positive and Negative nodes for the step-up charge pump’s flying capacitor.VCP 6Charge Pump and Digital Core Logic Power (Input ) - Positive power supply for the step-up and invert-ing charge pumps as well as the digital core logic sections.VFILT+8Step-Up Charge Pump Filter Connection (Output) - Power supply from the step-up charge pump that provides the positive rail for the output amplifiersFLYN+FLYN-911Inverting Charge Pump Cap Positive/Negative Nodes (Output) - Positive and Negative nodes for the inverting charge pump’s flying capacitor.CPGND 10Charge Pump Ground (Input ) - Ground reference for the Charge Pump section.VFILT-12Inverting Charge Pump Filter Connection (Output) - Power supply from the inverting charge pump that provides the negative rail for the output amplifiers.AOUTB AOUTA 1315Analog Outputs (Output ) - The full-scale analog line output level is specified in the Analog Characteris-tics table.AOUT_REF 14Pseudo Diff. Analog Output Reference (Input ) - Ground reference for the analog output amplifiers. This pin must be at the same nominal DC voltage as the AGND pin.AGND16Analog Ground (Input ) - Ground reference for the low voltage analog section.S D I NL R C KI ²S /L JD E M1_2V R M SR E S E TF L Y P +V F I L T +F L Y N +C P G N DF L Y N -SCLK MCLKVL DGND FLYP-VBIAS VA AGND AOUT_REF AOUTBVCPV F I L T -AOUTAVA17Low Voltage Analog Power (Input) - Positive power supply for the analog section. VBIAS18Positive Voltage Reference (Output) - Positive reference voltage for the internal DAC.RESET19Reset (Input) - Optional connection for an external reset control. The device enters a powered-down state when this pin is set low (GND) OR when the VCP supply falls below the V off threshold (see Table1). This pin should be set high (VL) during normal operation.1_2VRMS201 or 2V RMS Select (Input) - Selects the analog output full-scale voltage. Setting this pin low (GND) selects 1V RMS, while setting it high (VL) selects 2V RMS.DEM21De-emphasis (Input) - Selects the standard 50µs/15µs digital de-emphasis filter response for 44.1 kHz sample rates when enabled.I²S/LJ22Digital Interface Format (Input) - Selects the serial audio interface format. Setting this pin low (GND) selects I²S, while setting it high (VL) selects Left-Justified.LRCK23Left / Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line.SDIN24Serial Audio Data Input (Input) - Input for two’s complement serial audio data.Thermal Pad-Thermal Relief Pad - This pad may be soldered to the board, however it MUST be electrically isolated from all board connections.2.CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONSAGND = DNGD = CPGND = 0V; all voltages with respect to ground.Notes:1.VCP and VA must be supplied with the same nominal voltage. Additional current draw will occur if the sup-ply voltages applied to VCP and VA differ by more than 0.5V.ABSOLUTE MAXIMUM RATINGSAGND = DNGD = CPGND = 0V; all voltages with respect to ground.WARNING:Operation at or beyond these limits may result in permanent damage to the device. Normal operationis not guaranteed at these extremes.ParametersSymbol Min TypMaxUnitsDC Power SupplyCharge Pump and Digital Core power (Note 1)Low Voltage Analog power (Note 1)Interface powerVCP VA VL 3.133.130.85 3.33.30.9 to 3.33.473.473.47V V V Ambient Operating Temperature (Power Applied)-CNZ-DNZT A T A-40-40--+85+105°C °CParametersSymbolMinMaxUnitsDC Power SupplyCharge Pump and Digital Core Logic PowerLow Voltage Analog Power Supply Voltage DifferenceInterface PowerVCP VA |VCP - VA|VL -0.3-0.3--0.3 3.633.630.53.63V V V V Input Current, Any Pin Except Supplies I in -±10mA Digital Input Voltage Digital Interface V IN-L -0.3V L + 0.4V Analog Input Voltage AOUT_REF V IN-A -0.30.5V Ambient Operating Temperature (Power Applied)T A -55+125°C Storage Temperature T stg-65+150°CTest conditions (unless otherwise specified): T A = 25°C; VCP =VA =3.3V; AOUT_REF =AGND = DGND =CPGND = 0V; VBIAS, +/-VFILT, and FLYP/N+/- capacitors as shown in Figure 3 on page 13; input test signal is a 997Hz sine wave at 0dBFS; measurement bandwidth 10Hz to 20kHz.Notes:2.Measured between the AOUTx and AOUT_REF pins.3.One-half LSB of triangular PDF dither is added to data.4.Measured with the specified minimum AC-Load Resistance present on the AOUTx pins. Additional im-pedance between the AOUTx pin and the load will lower the voltage delivered to the load.5.V PP is the controlling specification. V RMS specification valid for sine wave signals only.Note that for sine wave signals:6.Measured with AOUT_REF connected directly to ground. Additional impedance between AOUT_REFand ground will lower the AOUT_REF rejection.7.SDIN =0. AOUT_REF input test signal is a 60Hz, 50mVpp sine wave. Measured by applying the testsignal into the AOUT_REF pin and measuring the resulting output amplitude on the AOUTx pin. Spec-ification calculated by: 1_2VRMS =01_2VRMS =1ParameterSymbol MinTypMaxMinTypMaxUnitDynamic Performance, Fs = 48, 96, and 192kHz (Notes 2, 3)Dynamic Range24-bit A-Weightedunweighted 16-bit A-Weightedunweighted9491--100979289----10097--1061039895----dB dB dB dB Total Harmonic Distortion + Noise24-bit 0dB-20dB-60dB 16-bit 0dB-20dB-60dB THD+N--------93-77-37-93-75-29-87-71-31-----------93-83-43-93-75-35-87-77-37---dB dB dB dB dB dB Idle Channel Noise / Signal-to-Noise Ratio (A-wt)-100--106-dB Interchannel Isolation(1kHz)-115--115-dB Analog Output (Note 2)Full Scale AOUTx Output Voltage (Notes 4, 5)0.98 1.05 1.12 1.96 2.10 2.25V RMS 2.772.973.17 5.54 5.94 6.36V pp Max Current Draw from an AOUTx Pin I OUTmax-575--575-µA Interchannel Gain Mismatch -0.1--0.1-dB Output Offset -±5±8-±5±8mV Gain Drift-100--100-ppm/°C Output Impedance Z OUT -100--100-ΩAC-Load Resistance R L 5--5--k ΩLoad Capacitance C L --1000--1000pF AOUT_REF Rejection (Notes 6, 7)AOR-40--40-dB Analog Reference Input AOUT_REF Input Voltage(Note 8)--0.2--0.2VppV RMS V pp22---------=AOR dB 20log 10AOUT _REFAOUT _REF AOUTx–---------------------------------------------------------⎝⎠⎛⎞⋅=Test conditions (unless otherwise specified): TA = -40 to +85°C; VCP =VA =3.13V to 3.47V; AOUT_REF = AGND = DGND =CPGND = 0V; VBIAS, +/-VFILT, and FLYP/N+/- capacitors as shown in Figure 3 on page 13; input test signal is a 997Hz sine wave at 0dBFS; measurement bandwidth 10Hz to 20kHz.8.Applying a DC voltage on the AOUT_REF pin will cause a DC offset on the DAC output. See Section4.1.3 for more information.1_2VRMS =01_2VRMS =1ParameterSymbol MinTypMaxMinTypMaxUnitDynamic Performance, Fs = 48, 96, and 192kHz (Notes 2, 3)Dynamic Range24-bit A-Weightedunweighted 16-bit A-Weightedunweighted9491--100979289----10097--1061039895----dB dB dB dB Total Harmonic Distortion + Noise24-bit 0dB-20dB-60dB 16-bit 0dB-20dB-60dB THD+N--------93-77-37-93-75-29-87-71-31-----------93-83-43-93-75-35-87-77-37---dB dB dB dB dB dB Idle Channel Noise / Signal-to-Noise Ratio (A-wt)-100--106-dB Interchannel Isolation(1kHz)-115--115-dB Analog Output (Note 2)Full Scale AOUTx Output Voltage (Notes 4, 5)0.98 1.05 1.12 1.96 2.10 2.25V RMS 2.772.973.17 5.54 5.94 6.36V pp Max Current Draw from an AOUTx Pin I OUTmax-575--575-µA Interchannel Gain Mismatch -0.1--0.1-dB Output Offset -±5±8-±5±8mV Gain Drift-100--100-ppm/°C Output Impedance Z OUT -100--100-ΩAC-Load Resistance R L 5--5--k ΩLoad Capacitance C L --1000--1000pF AOUT_REF Rejection (Notes 6, 7)AOR-40--40-dB Analog Reference Input AOUT_REF Input Voltage(Note 8)--0.2--0.2VppCOMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSEThe filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sam-ple rate by multiplying the given characteristic by Fs. Notes:9.Response is clock-dependent and will scale with Fs.10.For Single- and Double-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs.For Quad-Speed Mode, the Measurement Bandwidth is from stopband to 1.34 Fs.11.De-emphasis is available only in Single-Speed Mode.12.Amplitude vs. Frequency plots of this data are available in “Digital Filter Response Plots” on page 22.ParameterMin TypMaxUnitSingle-Speed Mode - 48kHzPassband (Note 9)to -0.01dB corner to -3dB corner00--.454.499Fs Fs Frequency Response 10Hz to 20kHz -0.01-+0.01dB StopBand0.547--Fs StopBand Attenuation(Note 10)102--dB Total Group Delay (Fs = Sample Rate)-9.4/Fs -s Intra-channel Phase Deviation --±0.56/Fss Inter-channel Phase Deviation--0s De-emphasis Error (Note 11)(Relative to 1kHz)Fs = 44.1 kHz --±0.14dB Double-Speed Mode - 96kHzPassband (Note 9)to -0.01dB corner to -3dB corner00--.430.499Fs Fs Frequency Response 10Hz to 20kHz -0.01-0.01dB StopBand.583--Fs StopBand Attenuation(Note 10)80--dB Total Group Delay (Fs = Sample Rate)- 4.6/Fs -s Intra-channel Phase Deviation --±0.03/Fss Inter-channel Phase Deviation--0s Quad-Speed Mode - 192kHzPassband (Note 9)to -0.01 dB cornerto -3dB corner00--.105.490Fs Fs Frequency Response 10Hz to 20kHz -0.01-0.01dB StopBand.635--Fs StopBand Attenuation(Note 10)90--dB Total Group Delay (Fs = Sample Rate)- 4.7/Fs-sSWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACEParametersSymbol MinMaxUnitsMCLK Frequency 2.04851.2MHz MCLK Duty Cycle4555%Input Sample Rate (Auto selection)Single-Speed Mode Double-Speed Mode Quad-Speed ModeFs Fs Fs 88417054108216kHz kHz kHz LRCK Duty Cycle 4060%SCLK Pulse Width Low t sclkl 20-ns SCLK Pulse Width High t sclkh20-ns SCLK PeriodSingle-Speed Mode -s Double-Speed Mode -s Quad-Speed Mode-s SCLK rising to LRCK edge delay t slrd 20-ns SCLK rising to LRCK edge setup time t slrs 20-ns SDIN valid to SCLK rising setup time tsdlrs 20-ns SCLK rising to SDIN hold timet sdh20-nsFigure 1. Serial Input Timing1128()Fs ---------------------164()Fs ------------------164()Fs ------------------DIGITAL INTERFACE CHARACTERISTICSTest conditions (unless otherwise specified): AGND = DGND = CPGND = 0V; all voltages with respect to ground.INTERNAL POWER-ON RESET THRESHOLD VOLTAGESTest conditions (unless otherwise specified): AGND = DGND = CPGND = 0V; all voltages with respect to ground.Table 1. Power-On Reset Threshold VoltagesFigure 2. Power-On Reset Threshold SequenceParametersSymbolMin TypMaxUnitsHigh-Level Input Voltage 1.2V < VL ≤ 3.3V 0.9V ≤ VL ≤ 1.2V V IH V IH 0.7xVL 0.9xVL ----V V Low-Level Input Voltage 1.2V < VL ≤ 3.3V 0.9V ≤ VL ≤ 1.2VV IL V IL ----0.3xVL 0.1xVL V V Input Leakage Current I in--±10µA Input Capacitance-8-pFParametersSymbolMin Typ Max Units Internal Reset Asserted at Power-On V on1- 1.00-V Internal Reset Released at Power-On V on2- 2.14-V Internal Reset Asserted at Power-OffV off-2.00-VDC ELECTRICAL CHARACTERISTICSTest conditions (unless otherwise specified): VCP =VA =VL =3.3V; AGND = DGND = CPGND = 0V; SDIN =0; all voltages with respect to ground.Notes:13.Current consumption increases with increasing sample rate and increasing MCLK frequency. Typicalvalues are based on Fs =48kHz and MCLK =12.288MHz. Maximum values are based on highest sample rate and highest MCLK frequency; see Switching Specifications - Serial Audio Interface . Vari-ance between speed modes is small.14.Power-down is defined as RESET pin = Low with all clock and data lines held static low. All digital inputshave a weak pull-down (approximately 50k Ω) which is only present during reset. Opposing this pull-down will slightly increase the power-down current.15.Valid with the recommended capacitor value on VBIAS as shown in the typical connection diagram inSection 3.16.Typical voltage shown for “Initialization State”, see Section 4.7. Typical voltage may be up to 1.5V lowerduring normal operation.2.1Digital I/O Pin CharacteristicsInput and output levels and associated power supply voltage are shown in Table 2. Logic levels should not exceed the corresponding power supply voltage.Table 2. Digital I/O Pin CharacteristicsParametersSymbol Min Typ Max UnitsPower SuppliesPower Supply Current (Note 13)Normal OperationPower-Down, All Supplies (Note 14)I VCPI VA I VL I PD----362.40.1654330.2-mA mA mA µA Power Dissipation (All Supplies)Normal Operation, 1_2VRMS =0(Note 13)Power-Down (Note 14)--1271152-mW mW Power Supply Rejection Ratio (Note 15) (1 kHz)(60 Hz)PSRR --6060--dB dB DC Output VoltagesPin VoltageFLYP+ to FLYP-VFILT+ to GND (Note 16)FLYN+ to FLYN-GND to VFILT- (Note 16)VA to VBIAS-----3.36.66.66.62.1-----V V V V VPin Name Power SupplyI/O Driver ReceiverRESET VLInput -0.9V - 3.3V, with HysteresisMCLK Input -0.9V - 3.3V LRCK Input -0.9V - 3.3V SCLK Input -0.9V - 3.3V SDIN Input -0.9V - 3.3V DEM Input -0.9V - 3.3V I²S/LJ Input -0.9V - 3.3V 1_2VRMSInput-0.9V - 3.3V3.TYPICAL CONNECTION DIAGRAMFigure 3. Typical Connection Diagram4.APPLICATIONS4.1Line Outputs4.1.1Ground-Centered OutputsAn on-chip charge pump creates both positive and negative high-voltage supplies, which allows the full-scale output swing to be centered around ground. This eliminates the need for large DC-blocking capac-itors which create audible pops at power-on, allows the CS4353 to deliver a larger full-scale output at low-er supply voltages, and provides improved bandwidth frequency response.4.1.2Full-Scale Output Amplitude ControlThe full-scale output voltage amplitude is selected via the 1_2VRMS pin. When the pin is connected to VL, the full-scale output voltage at the AOUTx pins is approximately 2V RMS. When the pin is connected to GND, the full-scale output voltage at the AOUTx pins is approximately 1V RMS. Additional impedance between the AOUTx pin and the load will lower the voltage delivered to the load. See the DAC Analog Characteristics (Commercial - CNZ) or DAC Analog Characteristics (Automotive - DNZ) table for the com-plete specifications of the full-scale output voltage.4.1.3Pseudo-Differential OutputsThe CS4353 implements a pseudo-differential output stage. The AOUT_REF input is intended to be used as a pseudo-differential reference signal. This feature provides common mode noise rejection with single-ended signals. Figure4 shows a basic diagram outlining the internal implementation of the pseudo-differ-ential output stage, including a recommended stereo pseudo-differential output topology. If pseudo-differ-ential output functionality is not required, simply connect the AOUT_REF pin to ground next to the CS4353. If a split-ground design is used, the AOUT_REF pin should be connected to AGND. See the Ab-solute Maximum Ratings table for the maximum allowable voltage on the AOUT_REF pin. Applying a DC voltage on the AOUT_REF pin will cause a DC offset on the DAC output.Figure 4. Stereo Pseudo-Differential Output4.2Sample Rate Range/Operational Mode DetectThe CS4353 operates in one of three operational modes. The device will auto-detect the correct mode when the input sample rate (Fs), defined by the LRCK frequency, falls within one of the ranges illustrated in Table 3. Sample rates outside the specified range for each mode are not supported. In addition to a valid LRCK frequency, a valid serial clock (SCLK) and master clock (MCLK) must also be applied to the device for speed mode auto-detection; see Figure 9.Table 3. CS4353 Operational Mode Auto-Detect4.3System ClockingThe device requires external generation of the master (MCLK), left/right (LRCK) and serial (SCLK) clocks.The left/right clock, defined also as the input sample rate (Fs), must be synchronously derived from the MCLK signal according to specified ratios. The specified ratios of MCLK to LRCK, along with several stan-dard audio sample rates and the required MCLK frequency, are illustrated in Tables 4-6.Refer to Section 4.4 for the required SCLK timing associated with the selected Digital Interface Format and to “Switching Specifications - Serial Audio Interface” on page 10 for the maximum allowed clock frequen-cies.Table 4. Single-Speed Mode Standard FrequenciesTable 5. Double-Speed Mode Standard FrequenciesTable 6. Quad-Speed Mode Standard FrequenciesInput Sample Rate (Fs)Mode8 kHz - 54 kHz Single-Speed Mode 84 kHz - 108 kHz Double-Speed Mode 170 kHz - 216 kHzQuad-Speed ModeSample Rate(kHz)MCLK (MHz)256x384x512x768x1024x328.192012.288016.384024.576032.768044.111.289616.934422.579233.868845.15844812.288018.432024.576036.864049.1520Sample Rate(kHz)MCLK (MHz)128x192x256x384x512x88.211.289616.934422.579233.868845.15849612.288018.432024.576036.864049.1520Sample Rate(kHz)MCLK (MHz)128x192x256x176.422.579233.868845.158419224.576036.864049.15204.4Digital Interface FormatThe device will accept audio samples in either I²S or Left-Justified digital interface formats, as illustrated in Table 7.The desired format is selected via the I²S/LJ pin. For an illustration of the required relationship between the LRCK, SCLK and SDIN, see Figures 5-6. For all formats, SDIN is valid on the rising edge of SCLK. Also,SCLK must have at least 32 cycles per LRCK period in the Left-Justified format.For more information about serial audio formats, refer to Cirrus Logic Application Note AN282: The 2-Chan-nel Serial Audio Interface: A Tutorial , available at .Table 7. Digital Interface FormatFigure 5. I²S, up to 24-Bit DataFigure 6. Left-Justified up to 24-Bit DataI²S/LJDescriptionFigure0I²S, up to 24-bit Data51Left-Justified, up to 24-bit Data64.5De-Emphasis ControlThe device includes on-chip digital de-emphasis. Figure 7 shows the de-emphasis curve for Fs equal to 44.1kHz. The frequency response of the de-emphasis curve scales with changes in the sample rate, Fs.The de-emphasis error will increase for sample rates other than 44.1kHz.When the DEM pin is connected to VL, the 44.1kHz de-emphasis filter is activated. When the DEM pin is connected to GND, the de-emphasis filter is turned off.Note: De-emphasis is only available in Single-Speed Mode.4.6Internal Power-On ResetThe CS4353 features an internal power-on reset (POR) circuit. The POR circuit allows the RESET pin to be connected to VL during power-up and power-down sequences if the external reset function is not needed.This circuit monitors the VCP supply and automatically asserts or releases an internal reset of the DAC’s digital circuitry when the supply reaches defined thresholds (see “Internal Power-On Reset Threshold Volt-ages” on page 11). No external clocks are required for the POR circuit to function.Figure 8. Internal Power-On Reset CircuitWhen power is first applied, the POR circuit monitors the VCP supply voltage to determine when it reaches a defined threshold, V on1. At this time, the POR circuit asserts the internal reset low, resetting all of the digital circuitry. Once the VCP supply reaches the secondary threshold, V on2, the POR circuit releases the internal reset.Figure 7. De-Emphasis Curve, Fs = 44.1 kHzNote:For correct operation of the internal POR circuit, the voltage on VL must rise before or simulta-neously with VCP.When power is removed and the VCP voltage reaches a defined threshold, V off, the POR circuit asserts the internal reset low, resetting all of the digital circuitry.4.7InitializationWhen power is first applied, the DAC enters a reset (low power) state at the beginning of the initialization sequence. In this state, the AOUTx pins are weakly pulled to ground and VBIAS is connected to VA.The device will remain in the reset state until the RESET pin is brought high. Once the RESET pin is high, the internal digital circuitry is reset and the DAC enters a power-down state until MCLK is applied. Alterna-tively, if no external reset control is required, the internal power-on reset can be used by tying the RESET pin to VL (see Section 4.6).Once MCLK is valid, the device enters an initialization state in which the charge pump powers up and charg-es the capacitors for both the positive and negative high-voltage supplies.Once LRCK and SCLK are valid, the number of MCLK cycles is counted relative to the LRCK period to de-termine the MCLK/LRCK frequency ratio. Next, the device enters the power-up state in which the interpo-lation and decimation filters and delta-sigma modulators are turned on, the internal voltage reference, VBIAS, powers up to normal operation, the analog output pull-down resistors are removed, and power is applied to the output amplifiers.After this power-up state sequence is complete, normal operation begins and analog output is generated.If valid MCLK, LRCK, and SCLK are applied to the DAC before RESET is set high, the total time from RE-SET being set high to the analog audio output from AOUTx is less than 50ms.See Figure9 for a diagram of the device’s states and transition conditions.Figure 9. Initialization and Power-Down Sequence Diagram4.8Recommended Power-Up and Power-Down Sequences4.8.1Power-Up Sequences4.8.1.1External RESET Power-Up SequenceFollow the power-up sequence below if the external RESET pin is used:1.Hold RESET low while the power supplies are turned on.2.Set the I²S/LJ, 1_2VRMS, and DEM configuration pins to the desired state.3.Provide the correct MCLK, LRCK, and SCLK signals locked to the appropriate frequencies asdiscussed in Section 4.3.4.After the power supplies, configuration pins, and clock signals are stable, bring RESET high. Thedevice will initiate the power-up sequence seen in Figure9. The sequence will complete and audiowill be output from AOUTx within 50ms after RESET is set high.4.8.1.2Internal Power-On Reset Power-Up SequenceFollow the power-up sequence below if the internal power-on reset is used:1.Hold RESET high (connected to VL) while the power supplies are turned on. The power-on resetcircuitry will function as described in Section 4.6.2.Set the I²S/LJ, 1_2VRMS, and DEM configuration pins to the desired state.3.After the power supplies and configuration pins are stable, provide the correct MCLK, LRCK, andSCLK signals to progress from the ‘Power-Down State’ in the power-up sequence seen in Figure9.The sequence will complete and audio will be output from the AOUTx pins within 50ms after validclocks are applied.4.8.2Power-Down Sequences4.8.2.1External RESET Power-Down SequenceFollow the power-down sequence below if the external RESET pin is used:1.For minimal pops, set the input digital data to zero for at least 8192 consecutive samples.2.Bring RESET low.3.Remove the power supply voltages.4.8.2.2Internal Power-On Reset Power-Down SequenceFollow the power-down sequence below if the internal power-on reset is used:1.For minimal pops, set the input digital data to zero for at least 8192 consecutive samples.2.Remove the MCLK signal without applying any glitched pulses to the MCLK pin.3.Remove the power supply voltages.Note: A glitched pulse is any pulse that is shorter than the period defined by the minimum/maximum MCLK signal duty cycle specification and the nominal frequency of the input MCLK signal. A transient may occur on the analog outputs if the MCLK signal duty cycle specification is violated when the MCLK signal is removed during normal operation; see “Switching Specifications - Serial Audio Interface” on page10.。

精密电流current-sink-source电路或放大器配置

精密电流current-sink/source电路或放大器配置摘要：精密电流显示让你变换一个4 - 20mA 的变送器类型到另一个，或者创造一个扩大了电流环的长度的目的，中继器。

该电路包括一个input-sink/output-sink，一input-source/output-source。

4 - 20mA 的工业电流控制回路使用发射机可以实现为供电电流源，远程无电源电流源或几个其他I / O 组合。

为这些应用程序的一些有用的构建块是一种精密电流，它允许你转换一个发射机的类型到另一个，或创建一个循环的延伸长度的目的，中继器。

电路的例子包括input-sink/output-sink(图1a)和一个input-source/output-source(图1b)。

这些电路有类似的配置，但在性能上略有不同。

您也可以透过一个电路链接到其他input-sink/output-source 型后视和input-source/output-sink。

图1。

一个单位增益，input-sink/output-sink 电流(一)，以及一个单位增益，input-source/output-source(b)项。

在图1a - 1B 的电路都在108 至109 欧姆的输出阻抗范围，以及电流镜的精度，是指由它的匹配电阻率精确度(为图1a)。

对0.1%的电阻匹配使用，例如，生产一镜像精度相当于10 位的分辨率。

值的范围之内，这些匹配的电流感应电阻的绝对值不会对镜像精度的影响。

显示的值(30.1Ω)是有点武断，你可以增加额外的投入成本下降，以及在最低工作输出电压增加。

随着检测电阻值如图所示，图1b 电路增加了一个全规模的一个10 位的LSB 失调的不确定性，由于对MAX4123(600μV)偏移较大的对比，该MAX4236(20μV)在图1a 中使用。

较高值检测电阻的使用减少这种不确定性。

sinksource

When choosing the type of input or output module for your system (or D L05/D L06/D L105 I/O type), it is very important to have a solid understanding of sinking and sourcing concepts. Use of these terms occurs frequently in discussion of input or output circuits. It is the goal of this section to make these concepts easy to understand, so you can make the right choice the first time when selecting the type of I/O points for your application. This section provides short definitions, followed by general example circuits.First you will notice that the diagrams on this page are associated with only D C circuits and not AC, because of the refer-ence to (+) and (-) polarities. Therefore,sinking and sourcing terminology applies only to DC input and output circuits.Input and output points that are sinking or sourcing can conduct current in one direc-tion only. This means it is possible to connect the external supply and field device to the I/O point, with current trying to flow in the wrong direction, and the circuit will not operate. However, the supply and field device can be connected every time based on an understanding of sourcing and sinking.The figure below depicts a sinking input.To properly connect the external supply, it must be connected so the input provides a path to supply common(-). So, start at the PLC input terminal, follow through the input sensing circuit, exit at the common terminal, and connect the supply (-) to the common terminal. By adding the switch between the supply (+) and the input, the circuit is completed. Current flows in the direction of the arrow when the switch is closed.By applying the circuit principles to the four possible combinations of input/output sinking/sourcing types, there are four circuits, as shown above. The common terminal is the terminal that serves as the common return path for all I/O points in the bank.Sink/source I/O circuits combine sinking and sourcing capabilities. This means that the I/O circuitry in the PLC will allow current to flow in either direction, as shown at the right. The common terminal connects to one polarity, and the I/O point connects to the other polarity (through the field device). This provides flexibility in making connections to your field power supply. Please note:•Wire all I/O points with a shared common as either sinking or sourcing.•Do not use an AC power supply on a DC sink/source I/O point.Input S ensingPLCS ink/S ource InputS ink/S ource Output(IE SSinking and Sourcing ConceptsSinking = provides a path to supply common (-)Sourcing = provides a path to supply source (+)。

设置首字下沉的操作方法

设置首字下沉的操作方法首字下沉（initial sink）是一种排版技巧，指的是在段落开头的第一个字母向下与其他字母对齐，使整段排版看起来更加工整和美观。

在中文排版中，使用首字下沉可以让段落的首行缩进，增加段落之间的区别，凸显出文章的逻辑结构。

下面是几种常见的设置首字下沉的操作方法。

方法一：使用段落格式设定在常见的文字编辑软件中（如Microsoft Word），可以通过设置段落格式来实现首字下沉的效果。

1. 打开Word或其他文字编辑软件，选择需要设置首字下沉的段落。

2. 确保段落处于编辑状态，然后右击打开格式菜单，选择“段落”选项。

3. 在“缩进和间距”选项卡中，找到“特殊缩进”一栏，选择“首行缩进”。

4. 在“缩进”栏中输入需要下沉的距离（一般为1-2个字符的宽度），可以通过调整数字来改变下沉的程度。

5. 点击“确定”应用设置，即可实现首字下沉效果。

方法二：使用样式设定在一些专业排版软件（如Adobe InDesign）中，也可以通过样式设定来实现首字下沉的效果。

下面以Adobe InDesign为例，介绍具体操作方法。

1. 打开Adobe InDesign等排版软件，创建一个新文档，在页面中插入一个文2. 输入段落内容后，选中第一个字或整个段落。

3. 在菜单栏中选择“字符”>“段落样式”（可能需要在窗口菜单中找到“样式”选项）。

4. 在样式面板中，点击新建样式（一个+号）。

5. 在弹出的“新建段落样式”对话框中，设置名称，然后点击“首字缩进”。

6. 在“首字缩进”选项中，可以自行设置下沉的距离。

7. 点击“确定”保存样式。

8. 将样式应用到想要设置首字下沉的段落上，即可实现首字下沉效果。

方法三：使用CSS样式设定在网页设计中，也可以使用CSS样式设定来实现首字下沉的效果。

下面以简单的HTML文件为例，介绍具体操作方法。

1. 创建一个新的HTML文件，使用`标签包裹要设置首字下沉的段落文本。

CFD流体动力分析_Flow-3D_chinese

存储量 AFR - right AFB - back AFT - top VF 热交换区
∂ C ∂ C ∂ C ∂ C 1 ∂ C ∂C ∂C ∂C +u +v +w → + uA x + vA y + wA z ∂ t ∂ x ∂ y ∂ z Vf ∂ t ∂x ∂y ∂z
VOF (流体体积 )
Thermal Energy Transport Equation (能量方程式)
I = ∫ C (T ) dT + (1 − fs ) L
T
fs L k C(T) h Twall RISOR RIDIF
-固化率(是温度和浓度的函数); -潜热; -导热系数; -比热; -液/壁热传热系数; -壁温 - energy source/sink; -湍流扩散
3.更正步骤不可压缩流更正步骤(不可压缩流更正步骤不可压缩流) 调整的压力和速度，以满足连续性方程. 分量U = 0離散化结果在压力的泊松方程. 相邻单元之间迭代计算. 收敛准则epsi将在每个周期自动计算.
P
P
∇ • u > 0 D e c re a s e P
P
∇ • u < 0 Increase P
0.29 0.284
VOF (流体体积 )
单相流使用 TruVOF 方法保持界面清晰. CPU 时间 - 2 分钟
双相流使用部分VOF 方法可相互混合以及空气的扩散. CPU 时间 - 8 分钟
VOF (流体体积 )
空腔区域压力统一
气体流动液体/气体混合物流动
双流体模型是应用于分散两相流的最好模型，但是不能很好区分各种流体.
Volume-of-Fluid Advection Equation (VOF處理流體流動的方程式)

软件仿真——精选推荐

软件仿真⾸先声明，TCAD对于本⼈来说是副业，前⼏天⼩伙伴找我帮忙玩⼀下ESD，由于之前有些TCAD的经验就试着玩了⼀下，本⼈对ESD⾥理解还是很肤浅的，望各路⼤神指教。

关于ESD仿真，见过有些⽂章⽤medici的，silvaco还有例⼦。

之前也⽤过medici做过SEL，但是⽤起来都不如sentaurus顺⼿。

sentaurus是个⼊门时间⽐较长的东西，但是掌握了那些软件的相互关系，再改⼏个例⼦玩玩就能上⼿了，swb神器不解释⾸先是器件建模，能拿到foundry⼚recipe然后做sprocess⼤神可以⾼冷的嘲笑⼀下我等摸⿊前进的苦逼了。

我也曾经试过⽤sprocess跑过，但是实在是搞不定，感觉hold不住最后的mesh。

根据我的实践，有两种⾃定义的⽅法：第⼀种是process emulator，不知道的去sde⼿册⾥搜，⼀个很实⽤的⼯具，可以读版图，根据各层做掺杂，但是没有物理过程，相当于⼀个“伪”⼯艺仿真。

好处就是根据版图做三维结构很⽅便。

还可以根据版图做refinement，不过这⼀块我还没有玩过第⼆个就是写sde的command file了。

很多同志喜欢⽤sde⼿动画结构，我之前也⼿动画过，但是⼿动画的话在之后校准或者调参数会带来⼀些⿇烦。

我⾃⼰喜欢写好command file之后直接在sde ⾥⾯mesh好，觉得做完结构再加⼀个snmesh来mesh 还是太啰嗦了。

关于mesh，根据我的仿真，加⼀个MaxTransDiff的refinement function，multibox⼀定要加⼀些。

我见过暴⼒的直接整个结构按0.001来mesh，简直就是找死。

之前我是⼩⽩的时候也试过把结深附近的全做成⼀个尺⼨的mesh，作死不解释。

还有就是定义结构的时候适当定义⼀些中间变量，会⽅便很多。

顺便吐槽⼀下sde ⾥⾯，做运算居然是(define A (+ B D) ) 这种丧⼼病狂的格式。

最后要注意heatsink要做，⽽且衬底不能太薄以⾄于和真实的热⾎条件相差太⼤，⼏um就⾏。

汽车行业英文缩写

汽车行业英文缩写同时OTS也能够叫模具样品，LH 要求汇总书(一个项目的所有资料)TPB 产品技术描述(图纸、技术供货条件等等)DKM 数据操纵模型(汽车形状1:1的基准样车)P P认可＝打算认可(决定投入批量生产)B B认可＝采购认可(对生产手段的投资认可)D D认可＝零件生产和供应认可(为零批量)BMG 产品工程性能认可EM 进行首批样件检验的首批样件，首批样件检验也称首批样件认可。

EMPB EMPB＝首批样件检验报告(供货商对其样件检验的文件)2TP 两日生产(供货厂的批量预生产，用来验证批量能力)PVS 生产试制批量0S 零批量(在批量生产条件下的总演习)SF 批量认可(对批量生产的产品认可)EPF (批量供货)打算认可KAF 集团路试验收(质量方面的批量认可)SOP 生产启动(批量生产启动)ME 市场导入(提供给销售商)CAD 运算机辅助设计COP 沿用件(与先前车型通用的零件)CKD 全部拆散SKD 部分拆散HT 自制件KT 外购件(外部供货厂生产的零件)KD 售后服务OTS 用批量生产的模具生产的零件TE 技术开发部PE (合资厂中的)产品工程部TL 技术供货条件TS 产品零件表ZP 检查点ZSB 总成AEKO (产品)改动的操纵组织常用英文缩写对比表汽车行业英文缩写(2020-05-06 14:34:33)OSM- Outside of MaterialOTC Over The Counter 非处方药，可在柜台上卖的药PA Program Approvalpallet n. 托盘Passenger Vehicle 乘用车PAT- Program Attributes Team 产品属性小组PDL Product Design LetterPH Proportions&HardpointsPIPC- Percentage of Indexes with Process Capability 能力指数百分比PIST- Percentage of Inspection points Satisfying Tolerance 检测点中意工差百分比PMT- Program Moudle Team 产品模块小组PO Purchase OrderPPAP- Production Part Approval Process 生产件批准程序PPSR Production Preparation Status ReportPQA Process Quality AssurancePR Program ReadinessPre-Launch 试生产price-driven costing 价格引导成本Production Preparation-Final Nissan - PT2/Renault - PPProduction Preparation-Initial Nissan - PT1/Renault - PPP3Production Trial Run 试生产Prototype 样件QFD Quality Funtion Deploy质量功能展开QFTT Quality Functional Task TeamQR- Quality Reject 质量拒收QS Quality StandardRAN Release Authorisation Numberreverse 倒车档RFQ Request For Quotation询价RKD Reverse Knock DownRLQ Receiving Lot QuantityROC Rate of ClimbROI return on investment 酬劳率ROP Re-Order PointRTO Required To OperateSAIS Supplier Assessment & Improvement SystemSC Strategic Confirmation/significant Charac’teristicsSDS- System/ Design Specifications 系统/设计说明second gear 二档SFMEA System FMEAShipping Date 出货日、Invoice Date 发票日或On Board Date 装船日Side Windshield 侧窗玻璃SJ Strategic IntentSNP Standard Number of Parts1PP- First Phase of Production Prove-Out 第一次试生产3C Customer(顾客导向)、Competition(竞争导向)、Competence〔专长导向〕4S Sale, Sparepart零配件, Service, Survey信息反馈5S 整理，整顿，清理，清洁，素养8D- 8 DisciplineABS Anti-lock Braking SystemAIAG 美国汽车联合会ANPQP Alliance New Product Quality ProcedureApportionment 分配APQP Advanced Product Quality PlanBacklite Windshield 后窗玻璃Benchmark Data 样件资料bloodshot adj.充血的, 有血丝的BMW Bavarian Motor WorksSOW- state of work 工作申明SPC Statistical Process ControlSQA Supplier Quality AssuranceSREA- Supplier Request for Engineering Approval 供应商工程设计更换申请ST Surface TranferSTRS Supplier Test Report SystemSubcontractor 分承包商Sunroof Windshield 天窗玻璃SUV Sports Utility VehicleTAG Test Aptitude GraphiqueTCO Total Cost of Ownership 总持有成本TCRA Total Cost Reduction ActivityTGR Things Gone RightTGW Things Gone WorstTM Techinical ManualTPM Total Preventive MaintenanceTTO-Tool Try Out 工装验证UOM Unit Of MeasureVES Vehicle uation SystemVO- Vehicle Operation 主机厂VPP- Vehicle Program Plan 整车项目打算VQA Vehicle Quality AssuranceVTTO- Vendor Tool Try-Out 供应商工装验证WERS- World Wide Engineering Release System WVTA Whole Vehicle Type Approval凹坑 concave车床 lathe抽查试验spot check test出厂试验delivery test次品defective product调幅amplitude modulation (AM)调频 Frequency Modulation断差 offset对讲机 interphone法平面normal plane翻车rollover返工 re-doing防滑地板 no-skid floor仿真emulation副作用side effect改装厂 refitting factory隔热板heat shield后围侧板 rear wall side cover划痕 scratchC.P.M Certified Purchasing manger 认证采购经理人制度CB- Confirmation Build 确认样车制造CC- Change CutOff 设计变更冻结CCSC- critical/significant characteristicCCR Concern & Countermeasure RequestCCT Cross Company TeamCharacteristics Matrix 特性矩阵图COD Cash on Delivery 货到付现预付货款(T/T in advance) CP1- Confirmation Prototype 1st 第一次确认样车CP2- Confirmation Prototype 2nd 第二次确认样车Cpk 过程能力指数Cpk=Zmin/3CPO Complementary Parts OrderCraftsmanship 精巧工艺Cross-functional teams 跨功能小组CUV Car-Based Ultility VehicleD1：信息收集；8DD2：建立8D小组；D3：制定临时的围堵行动措施，幸免不良品流出；D4：定义和证实全然缘故，幸免再发；D5：依照差不多缘故制定永久措施；D6：执行和确认永久措施；D7：预防再发，实施永久措施；D8：认可团队和个人的奉献。

USBPD——精选推荐

USBPD7、电源供应7.1电源需求USB PD的source对遗留的Vbus端⼝具有向后兼容性，USB设备插上接⼝还没接通时，按照规范向Vbus提供相应的电流和电压。

硬置位后，Source回到vSafeOV后⼀段时间内升回vSafe5V。

source 控制Vbus 的下降、上升和过渡都有时间要求。

在USB power delivery系统中，PDO表明了各种电源类型及其相应的输出电压范围。

电压正向跃迁是可控，由低电平上升到vSrcNew 是单调变化，转化时间从t0 开始到被source 接收的GOODCRC信息的EOP的最后⼀位终⽌。

负向跃迁转化后的电压在vSrcValid最⼤和最⼩值之间。

如果协商后的电压是vSafe5V, vSrcValid限制转换时间和转换电压。

PPS转化过程是步进和线性变化结合，其输出电压值的变化与ADC转换器的最低有效位值相关。

在PPS 中，当sink需要更多的电流时，PPS需要启动折返功能，起到折返式限流作⽤。

电流电压从折返状态跃迁到恒压恒流时，或者从恒定状态跃迁到折返状态需要设置电流电压阀值。

如果出现意外情况，会硬重置使得Vbus回到Vsafe5V。

Fixed supply PDO提供规定的电压值（⽐如5V，9V, 15V，20V）,其提供的新电压的转换曲线如下：Variable supply PDO （没电池）提供的输出电压在给定的数值范围内。

PPS的输出电压是步进变化且有范围控制，每⼀步的变化值与LSB对应的压差相关，并有vPpsValid的范围控制。

硬重置条件下，会把Rp从Vconn端移掉，然后把Vbus拉到0V。

⾃供电设备在硬重置后不断开USB连接但没法执⾏全部功能，总线供电设备在硬重置后会与USB断掉连接。

⼀旦连接建⽴起来，如果出现警告信息则source 会硬重置。

在source 检测到电流不存在问题后，会启动恢复操作。

如果恢复默认状态后过流保护措施仍热执⾏，那么关闭端⼝或系统是应对的⼀种恰当的响应。

水力学河流动力学英语专业词汇

水力学、河流动力学、流体力学专业词汇Fundamental Glossary in HydraulicsHydrostatics 水静力学Hydrodynamics 水动力学Physical properties of water 水的物理性质Density 密度 specific gravity 比重Kinematic viscosity 运动粘性 absolute viscosity 动力粘性Elastic modulus 弹性模量 surface tension 表面张力Temperature 温度 isotropic (y) 各向同性Anisotropic (y) 各向异性 uniform (ity) 均匀(性)Heterogeneous (ity) 不均匀(性)Main force 主要作用力Gravity 重力 inertia force 惯性力 pressure 压力(强) drag 阻力Mass force 质量力 surface force 表面力Constitutive relationship 本构关系Stress 应力strain 应变 deformation 变形 displacement 位移 normal 法向 tangent 切向shear 剪力acceleration 加速度Angular deformation 角变形Local acceleration 当地加速度 convective acceleration 迁移加速度 compressibility 压缩性continuity连续性Scalar 纯量 vector 矢量 tensor 张量magnitude 模(大小) direction 方向Divergence 散度 curl 旋度 gradient 梯度Source 源 sink 汇Frequency 频率 amplitude 振幅 phase 相位resonance共振Mass conservation 质量守恒 momentum conservation 动量守恒energy conservation 能量守恒Initial condition 初始条件boundary condition边界条件Ordinal differential equation 常微分方程partial differential equation 偏微分方程Convection, advection 对流diffusion 扩散dispersion 弥散decay 衰减 degradation降解Flow pattern流态 flow type 流型Laminar flow 层流turbulent flow 紊流Supercritical flow 急流 subcritical flow 缓流 critical flow临界流Rapidly varied flow急变流 gradually varied flow渐变流Uniform flow 均匀流 non-uniform flow 非均匀流Mainstream flow 主流 wake flow 尾流Steady flow 恒定流unsteady flow 非恒定流One-dimensional flow 一维流 two-dimensional flow二维流three-dimensional flow 三维流Single-phase flow 单相流 double-phase flow 两相流multi-phase flow 多相流Irrotational flow 无旋流potential flow 势流 rotational flow 有旋流Open channel flow 明渠流 free surface flow 自由表面流(明渠流) Pipe flow 管流 pressure flow 有压流Jet 射流 plume 卷流(羽流) cross flow 横流Stagnation point驻点 separation point分离点Coherent structure相干结构 bursting猝发 turbulent intensity紊动强度Boundary layer 边界层 viscous sub-layer粘性底层displacement thickness排挤厚度mixing length混掺长度Flow field, current field 流场 flow net 流网Submerged discharge 淹没出流 unsubmerged discharge非淹没出流Renolds number雷诺数 Froude number 佛汝德数 Prandtl number普朗特数Courant number柯朗数 Peclet 彼克雷特数 dimensionless number无量纲数Streamline 流线path line迹线Vortex line 涡线vortex ring 涡环 vortex street涡街Flux 通量 circulation 环量 vorticity 涡度Water level , water stage 水位discharge , flow-rate , flow 流量Water depth 水深velocity 流速Roughness 糙率water surface profile 水面线bed slope 底坡Velocity fluctuation 脉动流速 pressure fluctuation 脉动压强Instantaneous velocity 瞬时流速mean velocity 平均流速time-averaged velocity时均流速Depth-averaged velocity 水深平均流速velocity gradient 流速梯度 pressure gradient压强梯度Cross-section of flow , wet cross section 过水断面Wetted perimeter 湿周 hydraulic radius水力半径Hydraulic head 水头Elevation head 位置水头 piezometric head测压管水头velocity head 流速水头Head loss水头损失 frictional loss 沿程损失 local head loss局部损失Entrance head loss 进口水头损失 exit head loss 出口水头损失bend head loss弯头水头损失 Abrupt expansion head loss 突扩损失contraction head loss收缩损失Transition head loss渐变段损失Hydraulic jump 水跃 hydraulic drop跌水conjugate depth共轭水深Weir堰Sharp-crested weir 尖顶堰 broad-crested weir 宽顶堰 practical weir实用堰Orifice 孔口 nozzle管嘴Dam 坝 sluice 水闸 spillway溢洪道Tunnel 隧洞penstock 压力水管 culvert涵洞Aqueduct 渡槽 siphon pipe虹吸管Energy dissipation device 消能工Stilling basin 消力池 roller bucket 消力戽Baffle pier 消力墩 plunge pool 跌水池Energy dissipation by hydraulic jump底流消能Energy dissipation by surface regime面流消能Ski-jump energy dissipation 挑流消能Nappe 水舌 vena-contracta收缩断面Cavitation 空化 cavitation damage 空蚀Aeration 掺气Water wave 水波 water hammer水锤Hydraulic and river dynamics 水力学及河流动力学Sediment 泥沙 bed load 床沙 suspension load 悬沙 wash load 冲泻质Incipient velocity起动流速 settling velocity沉速Fluvial process河床演变 de">Grounder water 地下水 seepage渗透permeability 渗透性Similarity[simi’læriti] theory 相似理论Hydraulic modeling水力模拟Physical modeling 物理模拟Undistorted model正态模型distorted model变态模型Similitude 相似准则 similarity 相似性 full scale 足尺 reduced scale缩尺Fluid measurement 流动量测 flow visualization 流动可视化Transducer，sensor 传感器 probe探头 scale 比尺 flume 水槽Numerical modeling数值模拟Finite element 有限元 finite difference有限差finite volume 有限体积boundary element边界元Characteristics 特征线Scheme 方法(格式) algorithm 算法turbulence model 紊流模型Large-eddy simulation 大涡模拟Grid 网格node结点 time step时间步长nodal spacing 结点间距Coefficient系数 parameter参数Explicit 显式 implicit隐式stability 稳定性 convergence收敛性robustness（坚固性）健壮性sensitivity 敏感性 accuracy 精度Error误差 calibration 率定 verification 验证 application 应用 prediction 预测 reproduction复演Estuary hydraulics 河口动力学Coastal hydraulics 海岸动力学Open channel hydraulics明渠水力学Wave hydrodynamics 水波动力学Groundwater Hydraulics地下水水力学regular wave 规则波 irregular wave 不规则波Tide潮汐 spring tide大潮 neap tide小潮diurnal tide全日潮 semi-diurnal tide半日潮Computational Hydraulics计算水力学Environmental Hydraulics环境水力学Eco-hydraulics 生态水力学Hydro-informatics 水利信息学Dissolved oxygen (DO) 溶解氧 chemical oxygen demand(COD) 化学需氧量Biochemical oxygen demand(BOD) 生化需氧量 dilution 稀释度Pollutant 污染物 constituent 组分 eutrophication 富营养化Hydrology水文学Flood洪水 flood routing调洪演算 flood peak flow洪峰流量Runoff径流 precipitation降水 evaporation蒸发evapotranspiration 腾发, 蒸散发。

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VERIFICATION OF THE STENNING PROTOCOLBenedetto L. DiVitoTechnical Report 26 August 1982Institute for Computing ScienceThe University of Texas at AustinAustin, Texas 78712This report contains the transcript of a mechanical verification of the Stenning protocol [3]. A description of this protocol, as well as complete documentation on the methods used, can be found in a separate report [2]. Reference to this report is necessary, since the following material is not self-contained. The transcripts themselves were produced by the Boyer-Moore theorem prover [1].VC Proof Log 27-Jun-82 09:54:20 ++++++++++++++++++++++++++++++++++++++++Proof of VC ’TRANSPORT#1’(IMPLIES (AND (SENDER.EXT SOURCE ACK.IN PKT.OUT)(RECEIVER.EXT PKT.IN SINK ACK.OUT)(FOLLOWS PKT.IN PKT.OUT)(FOLLOWS ACK.IN ACK.OUT))(INITIAL SINK SOURCE))This formula can be simplified, using the abbreviations SENDER.EXT, AND, and IMPLIES, to:(IMPLIES(AND (CONSISTENT (QUOTE SEQNO)(QUOTE EQUAL)PKT.OUT)(EQUAL SOURCE(FAPPLY (QUOTE MSSG)(RANGE (LATEST (QUOTE SEQNO) PKT.OUT)))) (RECEIVER.EXT PKT.IN SINK ACK.OUT)(FOLLOWS PKT.IN PKT.OUT)(FOLLOWS ACK.IN ACK.OUT))(INITIAL SINK SOURCE)),which we simplify, applying CONSISTENT.FOLLOWS, INITIAL.FAPPLY, INITIAL.CONSEC.FOLLOWS, NUMBERP.SEQNO, TEST.CONSISTENT, TEST, INITIAL.RANGE, and INITIAL.TRANS, and opening up RECEIVER.EXT and INITIAL, to:T.Q.E.D.13069 conses9.963 seconds0.0 seconds, garbage collection time----------------------------------------VC Proof Log 27-Jun-82 09:55:11 ++++++++++++++++++++++++++++++++++++++++Proof of VC ’SENDER#1’(SENDER.INT (NULL)(NULL)(NULL)(QUOTE IDLE)0 0(NULL)0)This formula can be simplified, using the abbreviation SENDER.INT,to the following six new conjectures:Case 6. (PMAPP (QUOTE (1QUOTE NULL))),which simplifies, opening up PMAPP, to:T.Case 5. (NUMBERP 0).This simplifies, clearly, to:T.Case 4. (FOLLOWS (RANGE (QUOTE (1QUOTE NULL)))(QUOTE (1QUOTE NULL))),which simplifies, opening up the definitions of RANGE and FOLLOWS, to:T.Case 3. (CONSISTENT (QUOTE SEQNO)(QUOTE EQUAL)(QUOTE (1QUOTE NULL))),which we simplify, opening up SEQP and CONSISTENT, to:T.Case 2. (EQUAL (QUOTE (1QUOTE NULL))(FAPPLY (QUOTE MSSG)(RANGE (LATEST (QUOTE SEQNO)(QUOTE (1QUOTE NULL)))))).This simplifies, opening up the definitions of SEQP, LATEST,RANGE, FAPPLY, and EQUAL, to:T.Case 1. (IF(EQUAL 0 0)(IF (EQUAL (QUOTE (1QUOTE NULL))(QUOTE (1QUOTE NULL)))(EQUAL (QUOTE (1QUOTE NULL))(QUOTE (1QUOTE NULL)))F)(IF (SEQP (QUOTE (1QUOTE NULL)))(IF (EQUAL (DOM (LST (LATEST (QUOTE SEQNO)(QUOTE (1QUOTE NULL)))))(SUB1 0))(IF (EQUAL (HIGHEST (FAPPLY (QUOTE SEQNO)(QUOTE (1QUOTE NULL))))(SUB1 0))(IF (SEQP (QUOTE (1QUOTE NULL)))(EQUAL (DOM (LST (QUOTE (1QUOTE NULL))))(SUB1 0))T)F)F)F)).This simplifies, opening up the function EQUAL, to:T.Q.E.D.1052 conses2.57 seconds0.0 seconds, garbage collection time----------------------------------------++++++++++++++++++++++++++++++++++++++++Proof of VC ’SENDER#2’(IMPLIES (SENDER.INT SOURCE ACK.IN PKT.OUT STATE UNACK NEXTQUEUE TOT)(SENDER.EXT SOURCE ACK.IN PKT.OUT))This conjecture can be simplified, using the abbreviationsSENDER.INT and IMPLIES, to:$ (IMPLIES(AND(PMAPP QUEUE)(NUMBERP NEXT)(FOLLOWS (RANGE QUEUE) PKT.OUT)(CONSISTENT (QUOTE SEQNO)(QUOTE EQUAL)PKT.OUT)(EQUAL SOURCE(FAPPLY (QUOTE MSSG)(RANGE (LATEST (QUOTE SEQNO) PKT.OUT)))) (IF(EQUAL NEXT 0)(IF (EQUAL PKT.OUT (QUOTE (1QUOTE NULL)))(EQUAL QUEUE (QUOTE (1QUOTE NULL)))F)(IF (SEQP PKT.OUT)(IF (EQUAL (DOM (LST (LATEST (QUOTE SEQNO) PKT.OUT)))(SUB1 NEXT))(IF (EQUAL (HIGHEST (FAPPLY (QUOTE SEQNO) PKT.OUT))(SUB1 NEXT))(IF (SEQP QUEUE)(EQUAL (DOM (LST QUEUE)) (SUB1 NEXT))T)F)F)F)))(SENDER.EXT SOURCE ACK.IN PKT.OUT)),which simplifies, opening up SENDER.EXT, LATEST, RANGE, SEQP, FAPPLY, EQUAL, and CONSISTENT, to:T.Q.E.D.15990 conses13.576 seconds3.261 seconds, garbage collection time----------------------------------------++++++++++++++++++++++++++++++++++++++++Proof of VC ’SENDER#3’(IMPLIES (AND (SENDER.INT SOURCE ACK.IN PKT.OUT STATE UNACKNEXT QUEUE TOT)(NUMBERP ACK)(LESSP UNACK ACK))(SENDER.INT SOURCE(APR ACK.IN ACK)PKT.OUT STATE UNACK NEXT(UPPER QUEUE ACK)TOT))This conjecture can be simplified, using the abbreviationsSENDER.INT, AND, and IMPLIES, to:(IMPLIES(AND(PMAPP QUEUE)(NUMBERP NEXT)(FOLLOWS (RANGE QUEUE) PKT.OUT)(CONSISTENT (QUOTE SEQNO)(QUOTE EQUAL)PKT.OUT)(EQUAL SOURCE(FAPPLY (QUOTE MSSG)(RANGE (LATEST (QUOTE SEQNO) PKT.OUT)))) (IF(EQUAL NEXT 0)(IF (EQUAL PKT.OUT (QUOTE (1QUOTE NULL)))(EQUAL QUEUE (QUOTE (1QUOTE NULL)))F)(IF (SEQP PKT.OUT)(IF (EQUAL (DOM (LST (LATEST (QUOTE SEQNO) PKT.OUT)))(SUB1 NEXT))(IF (EQUAL (HIGHEST (FAPPLY (QUOTE SEQNO) PKT.OUT))(SUB1 NEXT))(IF (SEQP QUEUE)(EQUAL (DOM (LST QUEUE)) (SUB1 NEXT))T)F)F)F))(NUMBERP ACK)(LESSP UNACK ACK))(SENDER.INT SOURCE(APR ACK.IN ACK)PKT.OUT STATE UNACK NEXT(UPPER QUEUE ACK)TOT)),which simplifies, rewriting with the lemmas LST.UPPER,FOLLOWS.RANGE.UPPER, and PMAPP.UPPER, and expanding the functions UPPER, FOLLOWS, SEQP, RANGE, PMAPP, SENDER.INT, LATEST, FAPPLY, EQUAL, and CONSISTENT, to:T.Q.E.D.24249 conses20.704 seconds0.0 seconds, garbage collection time----------------------------------------++++++++++++++++++++++++++++++++++++++++Proof of VC ’SENDER#4’(IMPLIES (AND (SENDER.INT SOURCE ACK.IN PKT.OUT STATE UNACKNEXT QUEUE TOT)(NUMBERP ACK)(EQUAL ACK NEXT))(SENDER.INT SOURCE(APR ACK.IN ACK)PKT.OUT(QUOTE IDLE)ACK NEXT(NULL)TOT))This conjecture can be simplified, using the abbreviationsSENDER.INT, AND, and IMPLIES, to:$(IMPLIES(AND(PMAPP QUEUE)(NUMBERP NEXT)(FOLLOWS (RANGE QUEUE) PKT.OUT)(CONSISTENT (QUOTE SEQNO)(QUOTE EQUAL)PKT.OUT)(EQUAL SOURCE(FAPPLY (QUOTE MSSG)(RANGE (LATEST (QUOTE SEQNO) PKT.OUT)))) (IF(EQUAL NEXT 0)(IF (EQUAL PKT.OUT (QUOTE (1QUOTE NULL)))(EQUAL QUEUE (QUOTE (1QUOTE NULL)))F)(IF (SEQP PKT.OUT)(IF (EQUAL (DOM (LST (LATEST (QUOTE SEQNO) PKT.OUT)))(SUB1 NEXT))(IF (EQUAL (HIGHEST (FAPPLY (QUOTE SEQNO) PKT.OUT))(SUB1 NEXT))(IF (SEQP QUEUE)(EQUAL (DOM (LST QUEUE)) (SUB1 NEXT))T)F)F)F))(NUMBERP ACK)(EQUAL ACK NEXT))(SENDER.INT SOURCE(APR ACK.IN ACK)PKT.OUT(QUOTE IDLE)ACK NEXT(QUOTE (1QUOTE NULL))TOT)),which simplifies, opening up FOLLOWS, SEQP, RANGE, PMAPP,SENDER.INT, LATEST, FAPPLY, EQUAL, and CONSISTENT, to:T.Q.E.D.21684 conses18.532 seconds3.342 seconds, garbage collection time----------------------------------------++++++++++++++++++++++++++++++++++++++++Proof of VC ’SENDER#5’(IMPLIES (SENDER.INT SOURCE ACK.IN PKT.OUT STATE UNACK NEXTQUEUE TOT)(SENDER.INT SOURCE ACK.IN(JOIN PKT.OUT (RANGE QUEUE))STATE UNACK NEXT QUEUE TOT))This conjecture can be simplified, using the abbreviationsSENDER.INT and IMPLIES, to:$(IMPLIES(AND(PMAPP QUEUE)(NUMBERP NEXT)(FOLLOWS (RANGE QUEUE) PKT.OUT)(CONSISTENT (QUOTE SEQNO)(QUOTE EQUAL)PKT.OUT)(EQUAL SOURCE(FAPPLY (QUOTE MSSG)(RANGE (LATEST (QUOTE SEQNO) PKT.OUT)))) (IF(EQUAL NEXT 0)(IF (EQUAL PKT.OUT (QUOTE (1QUOTE NULL)))(EQUAL QUEUE (QUOTE (1QUOTE NULL)))F)(IF (SEQP PKT.OUT)(IF (EQUAL (DOM (LST (LATEST (QUOTE SEQNO) PKT.OUT)))(SUB1 NEXT))(IF (EQUAL (HIGHEST (FAPPLY (QUOTE SEQNO) PKT.OUT))(SUB1 NEXT))(IF (SEQP QUEUE)(EQUAL (DOM (LST QUEUE)) (SUB1 NEXT))T)F)F)F)))(SENDER.INT SOURCE ACK.IN(JOIN PKT.OUT (RANGE QUEUE))STATE UNACK NEXT QUEUE TOT)),which simplifies, rewriting with the lemmas HIGHEST.JOIN.FOLLOWS, PISEQP.FAPPLY, FOLLOWS.FAPPLY, FAPPLY.JOIN, LATEST.JOIN.FOLLOWS, NUMBERP.SEQNO, CONSISTENT.JOIN.FOLLOWS, FOLLOWS.JOIN.2, andPMAPP.NLST, and expanding the functions RANGE, SEQP, JOIN, FOLLOWS, PMAPP, SENDER.INT, LATEST, FAPPLY, EQUAL, and CONSISTENT, to sixnew conjectures:Case 6. (IMPLIES(AND (PMAPP QUEUE)(NUMBERP NEXT)(FOLLOWS (RANGE QUEUE) PKT.OUT)(CONSISTENT (QUOTE SEQNO)(QUOTE EQUAL)PKT.OUT)(NOT (EQUAL NEXT 0))(SEQP PKT.OUT)(EQUAL (DOM (LST (LATEST (QUOTE SEQNO) PKT.OUT)))(SUB1 NEXT))(EQUAL (HIGHEST (FAPPLY (QUOTE SEQNO) PKT.OUT))(SUB1 NEXT))(NOT (SEQP QUEUE)))(EQUAL QUEUE (QUOTE (1QUOTE NULL)))),which again simplifies, opening up the definition of PMAPP, to: T.Case 5. (IMPLIES(AND (PMAPP QUEUE)(NUMBERP NEXT)(FOLLOWS (RANGE QUEUE) PKT.OUT)(CONSISTENT (QUOTE SEQNO)(QUOTE EQUAL)PKT.OUT)(NOT (EQUAL NEXT 0))(SEQP PKT.OUT)(EQUAL (DOM (LST (LATEST (QUOTE SEQNO) PKT.OUT)))(SUB1 NEXT))(EQUAL (HIGHEST (FAPPLY (QUOTE SEQNO) PKT.OUT))(SUB1 NEXT))(EQUAL (DOM (LST QUEUE)) (SUB1 NEXT))(NOT (SEQP QUEUE)))(EQUAL QUEUE (QUOTE (1QUOTE NULL)))),which we again simplify, opening up PMAPP, to:T.Case 4. (IMPLIES(AND (PMAPP QUEUE)(NUMBERP NEXT)(FOLLOWS (RANGE QUEUE) PKT.OUT)(CONSISTENT (QUOTE SEQNO)(QUOTE EQUAL)PKT.OUT)(NOT (EQUAL NEXT 0))(SEQP PKT.OUT)(EQUAL (DOM (LST (LATEST (QUOTE SEQNO) PKT.OUT)))(SUB1 NEXT))(EQUAL (HIGHEST (FAPPLY (QUOTE SEQNO) PKT.OUT))(SUB1 NEXT))(EQUAL (DOM (LST QUEUE)) (SUB1 NEXT))(SEQP QUEUE)(SEQP (NLST QUEUE)))(MPAIRP (LST (NLST QUEUE)))).However this simplifies again, expanding PMAPP, to:T.Case 3. (IMPLIES(AND (PMAPP QUEUE)(NUMBERP NEXT)(FOLLOWS (RANGE QUEUE) PKT.OUT)(CONSISTENT (QUOTE SEQNO)(QUOTE EQUAL)PKT.OUT)(NOT (EQUAL NEXT 0))(SEQP PKT.OUT)(EQUAL (DOM (LST (LATEST (QUOTE SEQNO) PKT.OUT)))(SUB1 NEXT))(EQUAL (HIGHEST (FAPPLY (QUOTE SEQNO) PKT.OUT))(SUB1 NEXT))(EQUAL (DOM (LST QUEUE)) (SUB1 NEXT))(SEQP QUEUE)(SEQP (NLST QUEUE)))(LESSP (DOM (LST (NLST QUEUE)))(DOM (LST QUEUE)))).But this simplifies again, unfolding the definition of PMAPP, to: T.Case 2. (IMPLIES(AND (PMAPP QUEUE)(NUMBERP NEXT)(FOLLOWS (RANGE QUEUE) PKT.OUT)(CONSISTENT (QUOTE SEQNO)(QUOTE EQUAL)PKT.OUT)(NOT (EQUAL NEXT 0))(SEQP PKT.OUT)(EQUAL (DOM (LST (LATEST (QUOTE SEQNO) PKT.OUT)))(SUB1 NEXT))(EQUAL (HIGHEST (FAPPLY (QUOTE SEQNO) PKT.OUT))(SUB1 NEXT))(EQUAL (DOM (LST QUEUE)) (SUB1 NEXT))(SEQP QUEUE)(NOT (SEQP (NLST QUEUE))))(EQUAL (NLST QUEUE)(QUOTE (1QUOTE NULL)))).This simplifies again, unfolding the function PMAPP, to:T.Case 1. (IMPLIES(AND (PMAPP QUEUE)(NUMBERP NEXT)(FOLLOWS (RANGE QUEUE) PKT.OUT)(CONSISTENT (QUOTE SEQNO)(QUOTE EQUAL)PKT.OUT)(NOT (EQUAL NEXT 0))(SEQP PKT.OUT)(EQUAL (DOM (LST (LATEST (QUOTE SEQNO) PKT.OUT)))(SUB1 NEXT))(EQUAL (HIGHEST (FAPPLY (QUOTE SEQNO) PKT.OUT))(SUB1 NEXT))(EQUAL (DOM (LST QUEUE)) (SUB1 NEXT))(SEQP QUEUE))(MPAIRP (LST QUEUE))).However this simplifies again, unfolding the function PMAPP, to: T.Q.E.D.26435 conses24.43 seconds3.375 seconds, garbage collection time----------------------------------------++++++++++++++++++++++++++++++++++++++++Proof of VC ’SENDER#6’(IMPLIES (SENDER.INT SOURCE ACK.IN PKT.OUT STATE UNACK NEXTQUEUE TOT)(SENDER.INT (APR SOURCE MESS)ACK.IN(APR PKT.OUT (PACKET MESS NEXT))(QUOTE BUSY)UNACK(ADD1 NEXT)(WITHE QUEUE NEXT (PACKET MESS NEXT))(PLUS TOT DELTA)))This conjecture can be simplified, using the abbreviations SENDER.INT and IMPLIES, to:$(IMPLIES(AND(PMAPP QUEUE)(NUMBERP NEXT)(FOLLOWS (RANGE QUEUE) PKT.OUT)(CONSISTENT (QUOTE SEQNO)(QUOTE EQUAL)PKT.OUT)(EQUAL SOURCE(FAPPLY (QUOTE MSSG)(RANGE (LATEST (QUOTE SEQNO) PKT.OUT)))) (IF(EQUAL NEXT 0)(IF (EQUAL PKT.OUT (QUOTE (1QUOTE NULL)))(EQUAL QUEUE (QUOTE (1QUOTE NULL)))F)(IF (SEQP PKT.OUT)(IF (EQUAL (DOM (LST (LATEST (QUOTE SEQNO) PKT.OUT)))(SUB1 NEXT))(IF (EQUAL (HIGHEST (FAPPLY (QUOTE SEQNO) PKT.OUT))(SUB1 NEXT))(IF (SEQP QUEUE)(EQUAL (DOM (LST QUEUE)) (SUB1 NEXT))T)F)F)F)))(SENDER.INT (APR SOURCE MESS)ACK.IN(APR PKT.OUT (PACKET MESS NEXT))(QUOTE BUSY)UNACK(ADD1 NEXT)(WITHE QUEUE NEXT (PACKET MESS NEXT))(PLUS TOT DELTA))).This simplifies, applying the lemmas LST.NSEQP, WITHE.LESSP.DOM.LST, DOM.MPAIR, SUB1.ADD1, LST.WITHE, TEST, APPLY2.EQUAL, SEQNO.PACKET, APPLY1.SEQNO, FOLLOWS.APR.IN, FOLLOWS.APR,FOLLOWS.SAME, FOLLOWS.TRANS, RNG.MPAIR, LST.APR, NLST.APR,PMAPP.WITHE, WITHE.EQUAL.DOM.LST, NLST.NSEQP, andCONSISTENT.APR.NOT.IN, and opening up LESSP, EQUAL, DOM, HIGHEST, MAX, FAPPLY, LATEST, CONSISTENT, CONSISTENT2, IN, RANGE, PMAPP, SENDER.INT, SEQP, and FOLLOWS, to the following 23 new goals:Case 23.(IMPLIES(AND (PMAPP QUEUE)(NUMBERP NEXT)(FOLLOWS (RANGE QUEUE) PKT.OUT)(CONSISTENT (QUOTE SEQNO)(QUOTE EQUAL)PKT.OUT)(NOT (EQUAL NEXT 0))(SEQP PKT.OUT)(EQUAL (DOM (LST (LATEST (QUOTE SEQNO) PKT.OUT)))(SUB1 NEXT))(EQUAL (HIGHEST (FAPPLY (QUOTE SEQNO) PKT.OUT))(SUB1 NEXT))(NOT (SEQP QUEUE)))(EQUAL QUEUE (QUOTE (1QUOTE NULL)))),which we again simplify, expanding the definition of PMAPP, to: T.Case 22.(IMPLIES(AND (PMAPP QUEUE)(NUMBERP NEXT)(FOLLOWS (RANGE QUEUE) PKT.OUT)(CONSISTENT (QUOTE SEQNO)(QUOTE EQUAL)PKT.OUT)(NOT (EQUAL NEXT 0))(SEQP PKT.OUT)(EQUAL (DOM (LST (LATEST (QUOTE SEQNO) PKT.OUT)))(SUB1 NEXT))(EQUAL (HIGHEST (FAPPLY (QUOTE SEQNO) PKT.OUT))(SUB1 NEXT))(NOT (SEQP QUEUE)))(CONSISTENT2 (QUOTE SEQNO)(QUOTE EQUAL)PKT.OUT(PACKET MESS NEXT))),which again simplifies, using linear arithmetic, applyingSEQNO.PACKET, APPLY1.SEQNO, NUMBERP.SEQNO, andCONSISTENT2.LESSP.HIGHEST, and opening up the functions PMAPP, RANGE, SEQP, and FOLLOWS, to:T.$Case 21.(IMPLIES(AND (PMAPP QUEUE)(NUMBERP NEXT)(FOLLOWS (RANGE QUEUE) PKT.OUT)(CONSISTENT (QUOTE SEQNO)(QUOTE EQUAL)PKT.OUT)(NOT (EQUAL NEXT 0))(SEQP PKT.OUT)(EQUAL (DOM (LST (LATEST (QUOTE SEQNO) PKT.OUT)))(SUB1 NEXT))(EQUAL (HIGHEST (FAPPLY (QUOTE SEQNO) PKT.OUT))(SUB1 NEXT))(NOT (SEQP QUEUE)))(EQUAL (APR (FAPPLY (QUOTE MSSG)(RANGE (LATEST (QUOTE SEQNO) PKT.OUT)))MESS)(FAPPLY (QUOTE MSSG)(RANGE (WITHE (LATEST (QUOTE SEQNO) PKT.OUT)NEXT(PACKET MESS NEXT)))))).This again simplifies, using linear arithmetic, applying thelemmas TEST, WITHE.LESSP.DOM.LST, RNG.MPAIR, LST.APR,NLST.APR, MSSG.PACKET, and APPLY1.MSSG, and unfolding PMAPP,RANGE, SEQP, FOLLOWS, and FAPPLY, to:T.Case 20.(IMPLIES(AND(PMAPP QUEUE)(NUMBERP NEXT)(FOLLOWS (RANGE QUEUE) PKT.OUT)(CONSISTENT (QUOTE SEQNO)(QUOTE EQUAL)PKT.OUT)(NOT (EQUAL NEXT 0))(SEQP PKT.OUT)(EQUAL (DOM (LST (LATEST (QUOTE SEQNO) PKT.OUT)))(SUB1 NEXT))(EQUAL (HIGHEST (FAPPLY (QUOTE SEQNO) PKT.OUT))(SUB1 NEXT))(NOT (SEQP QUEUE))(NOT (LESSP NEXT(DOM (LST (LATEST (QUOTE SEQNO) PKT.OUT)))))) (EQUAL (DOM (MPAIR NEXT (PACKET MESS NEXT)))NEXT)),which we again simplify, rewriting with DOM.MPAIR, and expanding the definitions of PMAPP, RANGE, SEQP, and FOLLOWS, to:T.Case 19.(IMPLIES(AND (PMAPP QUEUE)(NUMBERP NEXT)(FOLLOWS (RANGE QUEUE) PKT.OUT)(CONSISTENT (QUOTE SEQNO)(QUOTE EQUAL)PKT.OUT)(NOT (EQUAL NEXT 0))(SEQP PKT.OUT)(EQUAL (DOM (LST (LATEST (QUOTE SEQNO) PKT.OUT)))(SUB1 NEXT))(EQUAL (HIGHEST (FAPPLY (QUOTE SEQNO) PKT.OUT))(SUB1 NEXT))(NOT (SEQP QUEUE))(LESSP NEXT(DOM (LST (LATEST (QUOTE SEQNO) PKT.OUT))))) (EQUAL (DOM (LST (LATEST (QUOTE SEQNO) PKT.OUT)))NEXT)).But this again simplifies, using linear arithmetic, to:T.Case 18.(IMPLIES(AND (PMAPP QUEUE)(NUMBERP NEXT)(FOLLOWS (RANGE QUEUE) PKT.OUT)(CONSISTENT (QUOTE SEQNO)(QUOTE EQUAL)PKT.OUT)(NOT (EQUAL NEXT 0))(SEQP PKT.OUT)(EQUAL (DOM (LST (LATEST (QUOTE SEQNO) PKT.OUT)))(SUB1 NEXT))(EQUAL (HIGHEST (FAPPLY (QUOTE SEQNO) PKT.OUT))(SUB1 NEXT))(NOT (SEQP QUEUE))(LESSP (HIGHEST (FAPPLY (QUOTE SEQNO) PKT.OUT))NEXT))(EQUAL NEXT NEXT)),which again simplifies, using linear arithmetic, to:T.Case 17.(IMPLIES(AND (PMAPP QUEUE)(NUMBERP NEXT)(FOLLOWS (RANGE QUEUE) PKT.OUT)(CONSISTENT (QUOTE SEQNO)(QUOTE EQUAL)PKT.OUT)(NOT (EQUAL NEXT 0))(SEQP PKT.OUT)(EQUAL (DOM (LST (LATEST (QUOTE SEQNO) PKT.OUT)))(SUB1 NEXT))(EQUAL (HIGHEST (FAPPLY (QUOTE SEQNO) PKT.OUT))(SUB1 NEXT))(NOT (SEQP QUEUE))(NOT (SEQP (FAPPLY (QUOTE SEQNO) PKT.OUT))))(EQUAL NEXT NEXT)).This again simplifies, using linear arithmetic, to:T.Case 16.(IMPLIES(AND (PMAPP QUEUE)(NUMBERP NEXT)(FOLLOWS (RANGE QUEUE) PKT.OUT)(CONSISTENT (QUOTE SEQNO)(QUOTE EQUAL)PKT.OUT)(NOT (EQUAL NEXT 0))(SEQP PKT.OUT)(EQUAL (DOM (LST (LATEST (QUOTE SEQNO) PKT.OUT)))(SUB1 NEXT))(EQUAL (HIGHEST (FAPPLY (QUOTE SEQNO) PKT.OUT))(SUB1 NEXT))(NOT (SEQP QUEUE))(SEQP (FAPPLY (QUOTE SEQNO) PKT.OUT))(NOT (LESSP (HIGHEST (FAPPLY (QUOTE SEQNO) PKT.OUT))NEXT)))(EQUAL (HIGHEST (FAPPLY (QUOTE SEQNO) PKT.OUT))NEXT)),which we again simplify, using linear arithmetic, to:T.Case 15.(IMPLIES(AND (PMAPP QUEUE)(NUMBERP NEXT)(FOLLOWS (RANGE QUEUE) PKT.OUT)(CONSISTENT (QUOTE SEQNO)(QUOTE EQUAL)PKT.OUT)(NOT (EQUAL NEXT 0))(SEQP PKT.OUT)(EQUAL (DOM (LST (LATEST (QUOTE SEQNO) PKT.OUT)))(SUB1 NEXT))(EQUAL (HIGHEST (FAPPLY (QUOTE SEQNO) PKT.OUT))(SUB1 NEXT))(EQUAL (DOM (LST QUEUE)) (SUB1 NEXT)))(FOLLOWS (RANGE (WITHE QUEUE NEXT (PACKET MESS NEXT)))(APR PKT.OUT (PACKET MESS NEXT)))), which again simplifies, using linear arithmetic, applyingWITHE.LESSP.DOM.LST, RNG.MPAIR, LST.APR, NLST.APR, FOLLOWS.TRANS, FOLLOWS.SAME, FOLLOWS.APR, and FOLLOWS.APR.IN, and expandingRANGE and IN, to:T.Case 14.(IMPLIES(AND (PMAPP QUEUE)(NUMBERP NEXT)(FOLLOWS (RANGE QUEUE) PKT.OUT)(CONSISTENT (QUOTE SEQNO)(QUOTE EQUAL)PKT.OUT)(NOT (EQUAL NEXT 0))(SEQP PKT.OUT)(EQUAL (DOM (LST (LATEST (QUOTE SEQNO) PKT.OUT)))(SUB1 NEXT))(EQUAL (HIGHEST (FAPPLY (QUOTE SEQNO) PKT.OUT))(SUB1 NEXT))(EQUAL (DOM (LST QUEUE)) (SUB1 NEXT)))(CONSISTENT2 (QUOTE SEQNO)(QUOTE EQUAL)PKT.OUT(PACKET MESS NEXT))).This again simplifies, using linear arithmetic and applyingSEQNO.PACKET, APPLY1.SEQNO, NUMBERP.SEQNO, andCONSISTENT2.LESSP.HIGHEST, to:T.$Case 13.(IMPLIES(AND (PMAPP QUEUE)(NUMBERP NEXT)(FOLLOWS (RANGE QUEUE) PKT.OUT)(CONSISTENT (QUOTE SEQNO)(QUOTE EQUAL)PKT.OUT)(NOT (EQUAL NEXT 0))(SEQP PKT.OUT)(EQUAL (DOM (LST (LATEST (QUOTE SEQNO) PKT.OUT)))(SUB1 NEXT))(EQUAL (HIGHEST (FAPPLY (QUOTE SEQNO) PKT.OUT))(SUB1 NEXT))(EQUAL (DOM (LST QUEUE)) (SUB1 NEXT)))(EQUAL (APR (FAPPLY (QUOTE MSSG)(RANGE (LATEST (QUOTE SEQNO) PKT.OUT)))MESS)(FAPPLY (QUOTE MSSG)(RANGE (WITHE (LATEST (QUOTE SEQNO) PKT.OUT)NEXT(PACKET MESS NEXT)))))).However this simplifies again, using linear arithmetic, applying TEST, WITHE.LESSP.DOM.LST, RNG.MPAIR, LST.APR, NLST.APR, MSSG.PACKET, and APPLY1.MSSG, and expanding the functions RANGE and FAPPLY, to:T.Case 12.(IMPLIES(AND(PMAPP QUEUE)(NUMBERP NEXT)(FOLLOWS (RANGE QUEUE) PKT.OUT)(CONSISTENT (QUOTE SEQNO)(QUOTE EQUAL)PKT.OUT)(NOT (EQUAL NEXT 0))(SEQP PKT.OUT)(EQUAL (DOM (LST (LATEST (QUOTE SEQNO) PKT.OUT)))(SUB1 NEXT))(EQUAL (HIGHEST (FAPPLY (QUOTE SEQNO) PKT.OUT))(SUB1 NEXT))(EQUAL (DOM (LST QUEUE)) (SUB1 NEXT))(NOT (LESSP NEXT(DOM (LST (LATEST (QUOTE SEQNO) PKT.OUT)))))) (EQUAL (DOM (MPAIR NEXT (PACKET MESS NEXT)))NEXT)).This simplifies again, rewriting with DOM.MPAIR, to:T.Case 11.(IMPLIES(AND (PMAPP QUEUE)(NUMBERP NEXT)(FOLLOWS (RANGE QUEUE) PKT.OUT)(CONSISTENT (QUOTE SEQNO)(QUOTE EQUAL)PKT.OUT)(NOT (EQUAL NEXT 0))(SEQP PKT.OUT)(EQUAL (DOM (LST (LATEST (QUOTE SEQNO) PKT.OUT)))(SUB1 NEXT))(EQUAL (HIGHEST (FAPPLY (QUOTE SEQNO) PKT.OUT))(SUB1 NEXT))(EQUAL (DOM (LST QUEUE)) (SUB1 NEXT))(NOT (LESSP NEXT (DOM (LST QUEUE)))))(EQUAL (DOM (MPAIR NEXT (PACKET MESS NEXT)))NEXT)).This simplifies again, applying DOM.MPAIR, to:T.Case 10.(IMPLIES(AND (PMAPP QUEUE)(NUMBERP NEXT)(FOLLOWS (RANGE QUEUE) PKT.OUT)(CONSISTENT (QUOTE SEQNO)(QUOTE EQUAL)PKT.OUT)(NOT (EQUAL NEXT 0))(SEQP PKT.OUT)(EQUAL (DOM (LST (LATEST (QUOTE SEQNO) PKT.OUT)))(SUB1 NEXT))(EQUAL (HIGHEST (FAPPLY (QUOTE SEQNO) PKT.OUT))(SUB1 NEXT))(EQUAL (DOM (LST QUEUE)) (SUB1 NEXT))(LESSP NEXT(DOM (LST (LATEST (QUOTE SEQNO) PKT.OUT))))) (EQUAL (DOM (LST (LATEST (QUOTE SEQNO) PKT.OUT)))NEXT)),which again simplifies, using linear arithmetic, to:T.Case 9. (IMPLIES(AND (PMAPP QUEUE)(NUMBERP NEXT)(FOLLOWS (RANGE QUEUE) PKT.OUT)(CONSISTENT (QUOTE SEQNO)(QUOTE EQUAL)PKT.OUT)(NOT (EQUAL NEXT 0))(SEQP PKT.OUT)(EQUAL (DOM (LST (LATEST (QUOTE SEQNO) PKT.OUT)))(SUB1 NEXT))(EQUAL (HIGHEST (FAPPLY (QUOTE SEQNO) PKT.OUT))(SUB1 NEXT))(EQUAL (DOM (LST QUEUE)) (SUB1 NEXT))(LESSP (HIGHEST (FAPPLY (QUOTE SEQNO) PKT.OUT))NEXT))(EQUAL NEXT NEXT)),which again simplifies, using linear arithmetic, to:T.Case 8. (IMPLIES(AND (PMAPP QUEUE)(NUMBERP NEXT)(FOLLOWS (RANGE QUEUE) PKT.OUT)(CONSISTENT (QUOTE SEQNO)(QUOTE EQUAL)PKT.OUT)(NOT (EQUAL NEXT 0))(SEQP PKT.OUT)(EQUAL (DOM (LST (LATEST (QUOTE SEQNO) PKT.OUT)))(SUB1 NEXT))(EQUAL (HIGHEST (FAPPLY (QUOTE SEQNO) PKT.OUT))(SUB1 NEXT))(EQUAL (DOM (LST QUEUE)) (SUB1 NEXT))(NOT (SEQP (FAPPLY (QUOTE SEQNO) PKT.OUT))))(EQUAL NEXT NEXT)).This again simplifies, using linear arithmetic, to:T.Case 7. (IMPLIES(AND (PMAPP QUEUE)(NUMBERP NEXT)(FOLLOWS (RANGE QUEUE) PKT.OUT)(CONSISTENT (QUOTE SEQNO)(QUOTE EQUAL)PKT.OUT)(NOT (EQUAL NEXT 0))(SEQP PKT.OUT)(EQUAL (DOM (LST (LATEST (QUOTE SEQNO) PKT.OUT)))(SUB1 NEXT))(EQUAL (HIGHEST (FAPPLY (QUOTE SEQNO) PKT.OUT))(SUB1 NEXT))(EQUAL (DOM (LST QUEUE)) (SUB1 NEXT))(SEQP (FAPPLY (QUOTE SEQNO) PKT.OUT))(NOT (LESSP (HIGHEST (FAPPLY (QUOTE SEQNO) PKT.OUT))NEXT)))(EQUAL (HIGHEST (FAPPLY (QUOTE SEQNO) PKT.OUT))NEXT)),which again simplifies, using linear arithmetic, to:T.Case 6. (IMPLIES(AND (PMAPP QUEUE)(NUMBERP NEXT)(FOLLOWS (RANGE QUEUE) PKT.OUT)(CONSISTENT (QUOTE SEQNO)(QUOTE EQUAL)PKT.OUT)(NOT (EQUAL NEXT 0))(SEQP PKT.OUT)(EQUAL (DOM (LST (LATEST (QUOTE SEQNO) PKT.OUT)))(SUB1 NEXT))(EQUAL (HIGHEST (FAPPLY (QUOTE SEQNO) PKT.OUT))(SUB1 NEXT))(EQUAL (DOM (LST QUEUE)) (SUB1 NEXT))(LESSP NEXT (DOM (LST QUEUE))))(EQUAL (DOM (LST QUEUE)) NEXT)),which again simplifies, using linear arithmetic, to:T.Case 5. (IMPLIES(AND (PMAPP QUEUE)(NUMBERP NEXT)(FOLLOWS (RANGE QUEUE) PKT.OUT)(CONSISTENT (QUOTE SEQNO)(QUOTE EQUAL)PKT.OUT)(EQUAL NEXT 0)(EQUAL PKT.OUT (QUOTE (1QUOTE NULL)))(EQUAL QUEUE (QUOTE (1QUOTE NULL))))(EQUAL (APR (QUOTE (1QUOTE NULL)) MESS)(FAPPLY (QUOTE MSSG)(RANGE (WITHE (LATEST (QUOTE SEQNO) PKT.OUT)NEXT(PACKET MESS NEXT)))))).But this again simplifies, rewriting with WITHE.ZERO.2, RNG.MPAIR, LST.APR, NLST.APR, MSSG.PACKET, APPLY1.MSSG, and APR.EQUAL, and opening up the definitions of PMAPP, NUMBERP, RANGE, FOLLOWS,SEQP, CONSISTENT, LATEST, DOMAIN, IN, JOIN, and FAPPLY, to: (EQUAL (QUOTE (1QUOTE NULL))(FAPPLY (QUOTE MSSG)(QUOTE (1QUOTE NULL)))).This again simplifies, opening up the definitions of SEQP, FAPPLY, and EQUAL, to:T.Case 4. (IMPLIES(AND (PMAPP QUEUE)(NUMBERP NEXT)(FOLLOWS (RANGE QUEUE) PKT.OUT)(CONSISTENT (QUOTE SEQNO)(QUOTE EQUAL)PKT.OUT)(EQUAL NEXT 0)(EQUAL PKT.OUT (QUOTE (1QUOTE NULL)))(EQUAL QUEUE (QUOTE (1QUOTE NULL)))(NOT (EQUAL (DOM (LST (LATEST (QUOTE SEQNO) PKT.OUT)))0)))(EQUAL (DOM (LST (LATEST (QUOTE SEQNO) PKT.OUT)))NEXT)).But this again simplifies, expanding the definitions of PMAPP, NUMBERP, RANGE, FOLLOWS, SEQP, CONSISTENT, LATEST, LST, DOM, and EQUAL, to:T.Case 3. (IMPLIES(AND (PMAPP QUEUE)(NUMBERP NEXT)(FOLLOWS (RANGE QUEUE) PKT.OUT)(CONSISTENT (QUOTE SEQNO)(QUOTE EQUAL)PKT.OUT)(EQUAL NEXT 0)(EQUAL PKT.OUT (QUOTE (1QUOTE NULL)))(EQUAL QUEUE (QUOTE (1QUOTE NULL)))(EQUAL (DOM (LST (LATEST (QUOTE SEQNO) PKT.OUT)))0))(EQUAL (DOM (MPAIR NEXT (PACKET MESS NEXT)))NEXT)).But this simplifies again, applying DOM.MPAIR, and expanding the functions PMAPP, NUMBERP, RANGE, FOLLOWS, SEQP, CONSISTENT,LATEST, LST, DOM, and EQUAL, to:T.Case 2. (IMPLIES (AND (PMAPP QUEUE)(NUMBERP NEXT)(FOLLOWS (RANGE QUEUE) PKT.OUT)(CONSISTENT (QUOTE SEQNO)(QUOTE EQUAL)PKT.OUT)(EQUAL NEXT 0)(EQUAL PKT.OUT (QUOTE (1QUOTE NULL)))(EQUAL QUEUE (QUOTE (1QUOTE NULL)))(NOT (SEQP (FAPPLY (QUOTE SEQNO) PKT.OUT))))(EQUAL NEXT NEXT)),which again simplifies, using linear arithmetic, to:T.Case 1. (IMPLIES (AND (PMAPP QUEUE)(NUMBERP NEXT)(FOLLOWS (RANGE QUEUE) PKT.OUT)(CONSISTENT (QUOTE SEQNO)(QUOTE EQUAL)PKT.OUT)(EQUAL NEXT 0)(EQUAL PKT.OUT (QUOTE (1QUOTE NULL)))(EQUAL QUEUE (QUOTE (1QUOTE NULL)))(SEQP (FAPPLY (QUOTE SEQNO) PKT.OUT)))(EQUAL (HIGHEST (FAPPLY (QUOTE SEQNO) PKT.OUT))NEXT)),which again simplifies, expanding PMAPP, NUMBERP, RANGE, FOLLOWS, SEQP, CONSISTENT, and FAPPLY, to:T.Q.E.D.101452 conses94.17 seconds10.246 seconds, garbage collection time----------------------------------------VC Proof Log 27-Jun-82 10:06:29 ++++++++++++++++++++++++++++++++++++++++Proof of VC ’RECEIVER#1’(RECEIVER.INT (NULL)(NULL)(NULL)(NULL))This conjecture can be simplified, using the abbreviation RECEIVER.INT, to three new conjectures:Case 3. (PMAPP (QUOTE (1QUOTE NULL))),which simplifies, expanding the definition of PMAPP, to:T.Case 2. (NUMBERP 0),which we simplify, clearly, to:T.Case 1. (IMPLIES(CONSISTENT (QUOTE SEQNO)(QUOTE EQUAL)(QUOTE (1QUOTE NULL)))(IF(FOLLOWS (QUOTE (1QUOTE NULL))(UPPER (LATEST (QUOTE SEQNO)(QUOTE (1QUOTE NULL)))1))(IF(LESSP (REACH (LATEST (QUOTE SEQNO)(QUOTE (1QUOTE NULL))))0)F(IF(IN 0(DOMAIN (LATEST (QUOTE SEQNO)(QUOTE (1QUOTE NULL)))))(IF(LESSP 0 0)(EQUAL(QUOTE (1QUOTE NULL))(FAPPLY (QUOTE MSSG)(RANGE (LOWER (LATEST (QUOTE SEQNO)(QUOTE (1QUOTE NULL)))(SUB1 0)))))F)(IF (EQUAL 0 0)(EQUAL (QUOTE (1QUOTE NULL))(QUOTE (1QUOTE NULL)))F)))F)),which simplifies, expanding the functions SEQP, CONSISTENT,LATEST, UPPER, FOLLOWS, REACH, LESSP, DOMAIN, IN, and EQUAL, to: T.。