S-24C16A中文资料 - 360文档中心

FM24C16A-AT24C16中文资料

第 1页
Figure 1. Block Diagram
引脚定义
名称Ｉ／Ｏ
SDA Ｉ／Ｏ
ＳＣＬ输入
WP 输入
VDD VSS NC
电源电源空脚
描述
串行地址\数据管脚：这个双向引脚用来传送地址和输入输出数据。这是一个开漏输出，以便与其它器件通过”线或”并接在双线总线上。输入缓冲区集成施密特触发器用以提高抗干扰性能，输出驱动器具有下降沿斜率控制。此端口必须外加上拉电阻。串行时钟：两线制总线的串行时钟输入。数据在时钟的下降沿移出器件，在时钟的上升沿移入器件，时钟端口同样具有施密特触发器用以提高抗干扰性能。
对器件进行轮循以等待一个就绪状态，因为器
件是以总线速度进行写操作，一个新的总线
转输将数据移入器件的同时，一个写操作已经
完成，更为详尽的描述将在下面的接口界面章
ห้องสมุดไป่ตู้
节进行描述。
Figure 2. Typical System Configuration
需要指出的是，ＦＭ２４Ｃ１６Ａ没有类似内部电源管
图５描述的是单字节和多字节的操作。
第 5页
Figure 5. Single Byte Write
Figure 6. Multiple Byte Write
读操作
四种正确操作方法如下：
有两种基本类型的读操作：当前地址读操作 1、主机在第9个时钟不发应答信号，在第十个时
和随机地址读操作。对当前地址进行读操作
开始
当主机把SDA从高电平拉为低电平，同时SCL 信号为高电平时被认为是开始信号，所有的读写操作均由开始信号开始。任何时候发布一个开始信号，一个进行中的操作都会被中止。使用开始信号中止一个操作的同时，FM24C04A 也会处于开始一个新操作的就绪状态。在操作过程中，如果电压降低到规定电压的最低值以下时，ＦＭ２４Ｃ１６Ａ执行另外一个的操作之前，会认为出现了一个开始信号。

FT24C16`FT24C08 资料完整版

F MDCo nf i de n t i al© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page1Two-Wire Serial EEPROM4K, 8K and 16K (8-bit wide)FEATURES❑Low voltage and low power operations:FT24C04A/08A/16A: V CC = 1.8V to 5.5V❑ Maximum Standby current < 1µA (typically 0.02µA and 0.06µA @ 1.8V and 5.5V respectively). ❑ 16 bytes page write mode.❑ Partial page write operation allowed.❑ Internally organized: 512 x 8 (4K), 1024 x 8 (8K), 2048 x 8 (16K). ❑ Standard 2-wire bi-directional serial interface. ❑ Schmitt trigger, filtered inputs for noise protection. ❑ Self-timed Write Cycle (5ms maximum).❑ 1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) Compatibility. ❑ Automatic erase before write operation.❑ Write protect pin for hardware data protection.❑ High reliability: typically 1, 000,000 cycles endurance. ❑ 100 years data retention.❑ Industrial temperature range (-40o C to 85o C).❑Standard 8-lead DIP/SOP/MSOP/TSSOP/DFN and 5-lead SOT-23/TSOT-23 Pb-free packages.DESCRIPTIONThe FT24C04A/08A/16A series are 4,096/8,192/16,384 bits of serial Electrical Erasable andProgrammable Read Only Memory, commonly known as EEPROM. They are organized as 512/1,024/2,048 words of 8 bits (1 byte) each. The devices are fabricated with proprietary advanced CMOS process for low power and low voltage applications. These devices are available in standard 8-lead DIP, 8-lead SOP, 8-lead TSSOP, 8-lead DFN, 8-lead MSOP, and 5-lead SOT-23/TSOT-23 packages. A standard 2-wire serial interface is used to address all read and write functions. Our extended V CC range (1.8V to 5.5V) devices enables wide spectrum of applications.PIN CONFIGURATIONPin Name Pin FunctionA2, A1, A0 Device Address Inputs SDA Serial Data Input / Open Drain Output SCL Serial Clock Input WP Write Protect NC No-ConnectF MDCo nf i de nt i a l© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page2All these packaging types come in conventional or Pb-free certified.VCC W P SCL SDAA2A1A0G 8L DIP 8L SOP8L TSSOP W P VCCG ND FT24C04A/08A/16A 5L SOT-23SCL 8L DFN8L M SOP 5L TSO T-23ABSOLUTE MAXIMUM RATINGSIndustrial operating temperature: -40℃ to 85℃ Storage temperature:-50℃ to 125℃Input voltage on any pin relative to ground: -0.3V to V CC + 0.3V Maximum voltage: 8VESD protection on all pins: >2000V* Stresses exceed those listed under “Absolute Maximum Rating” may cause permanent damage to thedevice. Functional operation of the device at conditions beyond those listed in the specification is not guaranteed. Prolonged exposure to extreme conditions may affect device reliability or functionality .F MDCo nf i de nt i a l© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page3PIN DESCRIPTIONS(A) SERIAL CLOCK (SCL)The rising edge of this SCL input is to latch data into the EEPROM device while the falling edge of this clock is to clock data out of the EEPROM device.(B) DEVICE / CHIP SELECT ADDRESSES (A2, A1, A0)These are the chip select input signals for the serial EEPROM devices. Typically, these signals are hardwired to either V IH or V IL . If left unconnected, they are internally recognized as V IL . FT24C04A has A0 pin as no-connect. FT24C08A has both A0 and A1 pins as no-connect. For FT24C16A, all device address pins (A0-A2) are no-connect.(C) SERIAL DATA LINE (SDA)SDA data line is a bi-directional signal for the serial devices. It is an open drain output signal and can bewired-OR with other open-drain output devices.(D) WRITE PROTECT (WP)The FT24C04A/08A/16A devices have a WP pin to protect the whole EEPROM array from programming. Programming operations are allowed if WP pin is left un-connected or input to V IL . Conversely all programming functions are disabled if WP pin is connected to V IH or V CC . Read operations is not affected by the WP pin’s input level.Table AF MDCo nf i de nt i al© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page4Device Chip Select/DeviceAddress Pins UsedNo-Connect Pins Max number of similardevices on the samebusFT24C04A A2, A1 A0 4FT24C08A A2, A1, A0 2 FT24C16A(None)A2, A1, A01MEMORY ORGANIZATIONThe FT24C04A/08A/16A devices have 32/64/128 pages respectively. Since each page has 16 bytes, random word addressing to FT24C04A/08A/16A will require 9/10/11 bits data word addresses respectively.DEVICE OPERATION(A) SERIAL CLOCK AND DATA TRANSITIONSThe SDA pin is typically pulled to high by an external resistor. Data is allowed to change only whenSerial clock SCL is at V IL . Any SDA signal transition may interpret as either a START or STOP condition as described below. (B) START CONDITIONWith SCL V IH , a SDA transition from high to low is interpreted as a START condition. All valid commands must begin with a START condition.F MDCo nf i de nt i al© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page5(C) STOP CONDITIONWith SCL V IH , a SDA transition from low to high is interpreted as a STOP condition. All valid read or write commands end with a STOP condition. The device goes into the STANDBY mode if it is after a read command. A STOP condition after page or byte write command will trigger the chip into the STANDBY mode after the self-timed internal programming finish. (D) ACKNOWLEDGEThe 2-wire protocol transmits address and data to and from the EEPROM in 8 bit words. The EEPROM acknowledges the data or address by outputting a "0" after receiving each word. The ACKNOWLEDGE signal occurs on the 9th serial clock after each word. (E) STANDBY MODEThe EEPROM goes into low power STANDBY mode after a fresh power up, after receiving a STOP bit in read mode, or after completing a self-time internal programming operation.Figure 1: Timing diagram for START and STOP conditionsFigure 2: Timing diagram for output ACKNOWLEDGESCLSDASTART ConditionSTOP ConditionData Data Valid TransitionSCLData inData out START ConditionACKF MDCo nf i de nt i a l© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page6DEVICE ADDRESSINGThe 2-wire serial bus protocol mandates an 8 bits device address word after a START bit condition to invoke valid read or write command. The first four most significant bits of the device address must be 1010, which is common to all serial EEPROM devices. The next three bits are device address bits. These three device address bits (5th , 6th and 7th ) are to match with the external chip select/address pin states. If a match is made, the EEPROM device outputs an ACKNOWLEDGE signal after the 8th read/write bit, otherwise the chip will go into STANDBY mode. However, matching may not be needed for some or all device address bits (5th , 6th and 7th ) as noted below. The last or 8th bit is a read/write command bit. If the 8th bit is at V IH then the chip goes into read mode. If a “0” is detected, the device enters programming mode.FT24C04A uses A2 (5th ) and A1 (6th ) device address bits. Only four FT24C04A devices can be wired-OR on the same 2-wire bus. Their corresponding chip select address pins A2 and A1 must be hard wired and coded from 00 (b) to 11 (b). Chip select address pin A0 is not used.FT24C08A uses only A2 (5th ) device address bit. Only two FT24C08A devices can be wired-OR on the same 2-wire bus. Their corresponding chip select address pin A2 must be hard-wired and coded from 0 (b) to 1 (b). Chip select address pins A1 and A0 are not used.FT24C16A does not use any device address bit. Only one FT24C16A device can be used on the on 2-wire bus. Chip Select address pins A2, A1, and A0 are not used.WRITE OPERATIONS(A) BYTE WRITEA byte write operation starts when a micro-controller sends a START bit condition, follows by a proper EEPROM device address and then a write command. If the device address bits match the chip select address, the EEPROM device will acknowledge at the 9th clock cycle. The micro-controller will then send the rest of the lower 8 bits word address. At the 18th cycle, the EEPROM will acknowledge the 8-bit address word. The micro-controller will then transmit the 8 bit data. Following an ACKNOWLDEGE signal from the EEPROM at the 27th clock cycle, the micro-controller will issue a STOP bit. After receiving the STOP bit, the EEPROM will go into a self-timed programming mode during which all external inputs will be disabled. After a programming time of T WC , the byte programming will finish and the EEPROM device will return to the STANDBY mode.(B) PAGE WRITEA page write is similar to a byte write with the exception that one to sixteen bytes can be programmed along the same page or memory row. All FT24C04A/08A/16A are organized to have 16 bytes per memory row or page.With the same write command as the byte write, the micro-controller does not issue a STOP bit aftersending the 1st byte data and receiving the ACKNOWLEDGE signal from the EEPROM on the 27th clock cycle. Instead it sends out a second 8-bit data word, with the EEPROM acknowledging at the 36th cycle. This data sending and EEPROM acknowledging cycle repeats until the micro-controller sends a STOP bit after the n 9th clock cycle. After which the EEPROM device will go into a self-timed partial or full page programming mode. After the page programming completes after a time of T WC , the devices will return to the STANDBY mode.F MDCo nf i de nt i a l© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page7The least significant 4 bits of the word address (column address) increments internally by one after receiving each data word. The rest of the word address bits (row address) do not change internally, but pointing to a specific memory row or page to be programmed. The first page write data word can be of any column address. Up to 16 data words can be loaded into a page. If more then 16 data words are loaded, the 17th data word will be loaded to the 1st data word column address. The 18th data word will be loaded to the 2nd data word column address and so on. In other word, data word address (column address) will “roll” over the previously loaded data. (C) ACKNOWLEDGE POLLINGACKNOWLEDGE polling may be used to poll the programming status during a self-timed internal programming. By issuing a valid read or write address command, the EEPROM will not acknowledge at the 9th clock cycle if the device is still in the self-timed programming mode. However, if the programming completes and the chip has returned to the STANDBY mode, the device will return a valid ACKNOWLEDGE signal at the 9th clock cycle.READ OPERATIONSThe read command is similar to the write command except the 8th read/write bit in address word is set to “1”. The three read operation modes are described as follows:(A) CURRENT ADDRESS READThe EEPROM internal address word counter maintains the last read or write address plus one if the power supply to the device has not been cut off. To initiate a current address read operation, the micro-controller issues a START bit and a valid device address word with the read/write bit (8th ) set to “1”. The EEPROM will response with an ACKNOWLEDGE signal on the 9th serial clock cycle. An 8-bit data word will then be serially clocked out. The internal address word counter will then automatically increase by one. For current address read the micro-controller will not issue an ACKNOWLEDGE signal on the 18th clock cycle. The micro-controller issues a valid STOP bit after the 18th clock cycle to terminate the read operation. The device then returns to STANDBY mode.(B) SEQUENTIAL READThe sequential read is very similar to current address read. The micro-controller issues a START bitand a valid device address word with read/write bit (8th ) set to “1”. The EEPROM will response with an ACKNOWLEDGE signal on the 9th serial clock cycle. An 8-bit data word will then be serially clocked out. Meanwhile the internally address word counter will then automatically increase by one. Unlike current address read, the micro-controller sends an ACKNOWLEDGE signal on the 18th clock cycle signaling the EEPROM device that it wants another byte of data. Upon receiving the ACKNOWLEDGE signal, the EEPROM will serially clocked out an 8-bit data word based on the incremented internal address counter. If the micro-controller needs another data, it sends out an ACKNOWLEDGE signal on the 27th clock cycle. Another 8-bit data word will then be serially clocked out. This sequential read continues as long as the micro-controller sends an ACKNOWLEDGE signal after receiving a new data word. When the internal address counter reaches its maximum valid address, it rolls over to the beginning of the memory array address. Similar to current address read, the micro-controller can terminate the sequential read by not acknowledging the last data word received, but sending a STOP bit afterwards instead.(C) RANDOM READRandom read is a two-steps process. The first step is to initialize the internal address counter with a target read address using a “dummy write” instruction. The second step is a current address read.To initialize the internal address counter with a target read address, the micro-controller issues a START bit first, follows by a valid device address with the read/write bit (8th ) set to “0”. The EEPROM will then acknowledge. The micro-controller will then send the address word. Again the EEPROM willacknowledge. Instead of sending a valid written data to the EEPROM, the micro-controller performs a current address readinstruction to read the data. Note that once a START bit is issued, the EEPROM will reset the internal programming process and continue to execute the new instruction - which is to read the current address.laitnedifnoCDMF© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page8F MDCo nf i de nt i al© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page9Figure 8: SCL and SDA Bus TimingAC CHARACTERISTICS1.8 V2.5-5.0 V Symbol ParameterMin Max MinMax Unit f SCLClock frequency, SCL 400 1000 kHz t LOW Clock pulse width low1.20.7µst HIGH Clock pulse width high0.4 0.3 µst I Noise suppression time (1) 180 120 ns t AAClock low to data out valid 0.30.90.20.7µs t BUF Time the bus must be free before a new transmission can start (1)1.3 0.5µs t HD.STA START hold time0.6 0.25 µs t SU.STA START set-up time 0.6 0.25 µs t HD.DAT Data in hold time 0 0 µs t SU.DAT Data in set-up time100100nst R Input rise time (1)0.3 0.3 µst F Input fall time (1) 300 100 nst SU.STO STOP set-up time 0.6 0.25 µs t DH Date out hold time 50 50 ns WRWrite cycle time55msEndurance(1)25o C, Page Mode, 3.3V1,000,000Write CyclesNotes: 1. This Parameter is expected by characterization but are not fully screened by test.2. AC Measurement conditions: R L (Connects to Vcc): 1.3K ΩInput Pulse Voltages: 0.3Vcc to 0.7VccInput and output timing reference Voltages: 0.5VccF MDCo nf i de nt i al© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page10DC CHARACTERISTICSSymbol Parameter Test ConditionsMin Typical Max Units V CC1 24C A supply V CC1.8 5.5 V I CC Supply read currentV CC @ 5.0V SCL = 400 kHz0.5 1.0 mA I CCSupply write current V CC @ 5.0V SCL = 400 kHz2.03.0 mA I SB1 Supply current V CC @ 1.8V, V IN = V CC or V SS 1.0 µA I SB2 Supply current V CC @ 2.5V, V IN = V CC or V SS 1.0 µA I SB3 Supply currentV CC @ 5.0V, V IN = V CC or V SS 0.06 1.0 µA I ILInput leakagecurrentV IN = V CC or V SS 3.0 µA I LOOutput leakagecurrentV IN = V CC or V SS3.0µAV IL Input low level -0.6 V CC x 0.3 V V IHInput high levelV CC x 0.7V CC +0.5 VV OL1 Output low level V CC @ 1.8V, I OL = 0.15 mA0.2 V V OL2 Output low level V CC @ 3.0V, I OL = 2.1 mA0.4VF MDCo nf i de nt i a l© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page11ORDERING INFORMATION:Density PackageTemperatureRangeVcc HSF Packaging Ordering CodeRoHSTube FT24C04A-UDR-BDIP8 -40℃-85℃ 1.8V-5.5VGreen Tube FT24C04A-UDG-B Tube FT24C04A-USR-B RoHSTape and Reel FT24C04A-USR-TTube FT24C04A-USG-B SOP8 -40℃-85℃ 1.8V-5.5VGreen Tape and Reel FT24C04A-USG-TTube FT24C04A-UMR-B RoHS Tape and Reel FT24C04A-UMR-TTube FT24C04A-UMG-B MSOP8 -40℃-85℃ 1.8V-5.5VGreen Tape and Reel FT24C04A-UMG-TTube FT24C04A-UTR-B RoHSTape and Reel FT24C04A-UTR-TTube FT24C04A-UTG-B TSSOP8 -40℃-85℃ 1.8V-5.5VGreen Tape and Reel FT24C04A-UTG-T RoHS Tape and Reel FT24C04A-ULR-T SOT23-5 -40℃-85℃ 1.8V-5.5VGreen Tape and Reel FT24C04A-ULG-T RoHS Tape and Reel FT24C04A-UPR-T TSOT23-5 -40℃-85℃ 1.8V-5.5V Green Tape and Reel FT24C04A-UPG-T RoHS Tape and Reel FT24C04A-UNR-T 4kbitsDFN8 -40℃-85℃ 1.8V-5.5V Green Tape and Reel FT24C04A-UNG-TRoHS Tube FT24C08A-UDR-B DIP8 -40℃-85℃ 1.8V-5.5VGreen Tube FT24C08A-UDG-B Tube FT24C08A-USR-B RoHSTape and Reel FT24C08A-USR-TTube FT24C08A-USG-B 8kbitsSOP8 -40℃-85℃ 1.8V-5.5VGreenTape and Reel FT24C08A-USG-TD: DIP8 S: SOP8 M: MSOP8 T: TSSOP8 L: SOT23-5 P: TSOT23-5 N: DFN8Packaging B: TubeT: Tape and Reel HSF R: RoHS G: GreenU:-40F MDCo nf i de nt i a l© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page12Density Package TemperatureRangeVcc HSF Packaging Ordering CodeTube FT24C08A-UMR-BRoHSTape and Reel FT24C08A-UMR-TTube FT24C08A-UMG-B MSOP8 -40℃-85℃ 1.8V-5.5VGreen Tape and Reel FT24C08A-UMG-TTube FT24C08A-UTR-B RoHSTape and Reel FT24C08A-UTR-TTube FT24C08A-UTG-B TSSOP8 -40℃-85℃ 1.8V-5.5VGreen Tape and Reel FT24C08A-UTG-T RoHSTape and Reel FT24C08A-ULR-T SOT23-5 -40℃-85℃ 1.8V-5.5V Green Tape and Reel FT24C08A-ULG-T RoHS Tape and Reel FT24C08A-UPR-T TSOT23-5 -40℃-85℃ 1.8V-5.5V Green Tape and Reel FT24C08A-UPG-T RoHS Tape and Reel FT24C08A-UNR-T 8kbitsDFN8 -40℃-85℃ 1.8V-5.5V Green Tape and Reel FT24C08A-UNG-TRoHS Tube FT24C16A-UDR-B DIP8 -40℃-85℃ 1.8V-5.5VGreen Tube FT24C16A-UDG-B Tube FT24C16A-USR-B RoHSTape and Reel FT24C16A-USR-TTube FT24C16A-USG-B SOP8 -40℃-85℃ 1.8V-5.5VGreen Tape and Reel FT24C16A-USG-TTube FT24C16A-UMR-B RoHSTape and Reel FT24C16A-UMR-TTube FT24C16A-UMG-B MSOP8 -40℃-85℃ 1.8V-5.5VGreen Tape and Reel FT24C16A-UMG-TTube FT24C16A-UTR-B RoHS Tape and Reel FT24C16A-UTR-TTube FT24C16A-UTG-B TSSOP8 -40℃-85℃ 1.8V-5.5VGreen Tape and Reel FT24C16A-UTG-T RoHSTape and Reel FT24C16A-ULR-T SOT23-5 -40℃-85℃ 1.8V-5.5V Green Tape and Reel FT24C16A-ULG-T RoHS Tape and Reel FT24C16A-UPR-T TSOT23-5 -40℃-85℃ 1.8V-5.5VGreen Tape and Reel FT24C16A-UPG-T RoHS Tape and Reel FT24C16A-UNR-T 16kbitsDFN8 -40℃-85℃ 1.8V-5.5VGreenTape and Reel FT24C16A-UNG-TF MDCo nf i de nt i al© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page13DIP8 PACKAGE OUTLINEDIMENSIONSDimensions In MillimetersDimensions In InchesSymbolMin Max Min MaxA 3.710 4.310 0.146 0.170 A1 0.510 0.020 A2 3.200 3.600 0.126 0.142B 0.380 0.570 0.015 0.022B1 1.524（BSC ） 0.060（BSC ）C 0.204 0.360 0.008 0.014D 9.000 9.400 0.354 0.370E 6.200 6.600 0.244 0.260 E1 7.320 7.920 0.288 0.312 e 2.540 (BSC) 0.100（BSC ） L 3.000 3.600 0.118 0.142 E2 8.400 9.000 0.331 0.354F MDCo nf i de nt i al© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page14SOP8 PACKAGE OUTLINE DIMENSIONSDimensions In MillimetersDimensions In InchesSymbolMin Max Min MaxA 1.350 1.750 0.053 0.069A1 0.100 0.250 0.004 0.010A2 1.350 1.550 0.053 0.061 b 0.330 0.510 0.013 0.020 c 0.170 0.250 0.006 0.010D 4.700 5.100 0.185 0.200E 3.800 4.000 0.150 0.157 E1 5.800 6.200 0.228 0.244 e 1.270 (BSC)0.050 (BSC)L 0.400 1.270 0.016 0.050 θ 0° 8° 0° 8°F MDCo nf i de nt i al© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page15MSOP8 PACKAGE OUTLINE DIMENSIONSDimensions In MillimetersDimensions In InchesSymbolMin Max Min MaxA 0.820 1.100 0.320 0.043 A1 0.020 0.150 0.001 0.006 A2 0.750 0.950 0.030 0.037 b 0.250 0.380 0.010 0.015 c 0.090 0.230 0.004 0.009 D 2.900 3.100 0.114 0.122 e 0.65 (BSC) 0.026 (BSC) E 2.900 3.100 0.114 0.122 E1 4.750 5.050 0.187 0.199 L 0.400 0.800 0.016 0.031 θ 0° 6° 0° 6°F MDCo nf i de nt i al© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page16TSSOP8 PACKAGE OUTLINEDIMENSIONSDimensions In MillimetersDimensions In Inches SymbolMinMax Min Max D 2.900 3.100 0.114 0.122 E4.3004.5000.1690.177b 0.190 0.300 0.007 0.012c 0.090 0.200 0.004 0.008 E1 6.250 6.550 0.246 0.258 A 1.100 0.043 A2 0.800 1.000 0.031 0.039 A1 0.020 0.150 0.001 0.006e 0.65 (BSC) 0.026 (BSC) L 0.500 0.700 0.020 0.028H 0.25 (TYP) 0.01 (TYP)θ 1°7° 1° 7°F MDCo n f i de nt i a l© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page17SOT-23-5 PACKAGE OUTLINE DIMENSIONSDimensions In MillimetersDimensions In InchesSymbolMin Max Min MaxA 1.050 1.250 0.041 0.049A1 0.000 0.100 0.000 0.004 A2 1.050 1.150 0.041 0.045 b 0.300 0.500 0.012 0.020 c 0.100 0.200 0.004 0.008 D 2.820 3.020 0.111 0.119 E 1.500 1.700 0.059 0.067 E1 2.650 2.950 0.104 0.116 e 0.95 (BSC) 0.037 (BSC) e1 1.800 2.000 0.071 0.079 L 0.300 0.600 0.012 0.024 θ 0° 8° 0° 6°F MDCo nf i de nt i a l© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page18TSOT-23-5 PACKAGE OUTLINE DIMENSIONSDimensions In MillimetersDimensions In InchesSymbolMin Max Min MaxA 0.700 0.900 0.028 0.035A1 0.000 0.100 0.000 0.004 A2 0.700 0.800 0.028 0.031 b 0.350 0.500 0.014 0.020 c 0.080 0.200 0.003 0.008 D 2.820 3.020 0.111 0.119 E 1.600 1.700 0.063 0.067 E1 2.650 2.950 0.104 0.116 e 0.95 (BSC) 0.037 (BSC) e1 1.90 (BSC) 0.075 (BSC) L 0.300 0.600 0.012 0.024 θ 0° 8° 0° 8°F MDCo nf i de n t i al© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page19DFN8 PACKAGE OUTLINE DIMENSIONSDimensions In MillimetersSymbolMinNomMaxA 0.70 0.75 0.80A1 - 0.02 0.05 b 0.18 0.25 0.03 c 0.18 0.20 0.25 D 1.902.00 2.10D2 1.50REF e 0.50BSC Nd 1.50BSC E 2.90 3.00 3.10 E2 1.60REFL 0.30 0.40 0.50 h 0.20 0.25 0.30F MDCo nf i de n t i al© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page20Fremont Micro Devices (SZ) Limited* Information furnished is believed to be accurate and reliable. However, Fremont Micro Devices, Incorporated (BVI) assumes no responsibility for the consequences of use of such information or for any infringement of patents of other rights of third parties which may result from its use. No license is granted by implication orotherwise under any patent rights of Fremont Micro Devices, Incorporated (BVI). Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. Fremont Micro Devices, Incorporated (BVI) products are not authorized for use as critical components in life support devices or systems without express written approval of Fremont Micro Devices, Incorporated (BVI). The FMD logo is a registered trademark of Fremont Micro Devices, Incorporated (BVI). All other names are the property of their respective owners.。

S-24C16C

400 kHz（VCC = 1.6 V ~ 5.5 V）备有施密特触发器、噪声滤波器输入端子（SCL, SDA）
106次 / 字*1（＋25°C时） 100年（＋25°C时） 16 K位 100%
*1. 每个地址 (字：8 位) *2. 详情请参阅“ 产品型号的构成”。
■ 封装
• 8-Pin SOP（JEDEC） • 8-Pin TSSOP • SNT-8A • TMSOP-8 • WLP
■ 推荐工作条件
项目电源电压高电位输入电压低电位输入电压
符号
VCC VIH VIL
表7 条件读出写入
VCC = 1.6 V ~ 5.5 V VCC = 1.6 V ~ 5.5 V
最小值
1.6 1.7 0.7×VCC －0.3
最大值
5.5 5.5 5.5 0.3×VCC
单位
V V V V
■ 端子容量
4
GND
接地
5
SDA*3
串行数据输入输出
6
SCL*3
串行时钟输入
写入保护输入
7
WP
VCC连接：
保护有效
电气开路状态或与GND连接：保护无效
8
VCC
电源
*1. 请与 GND 或 VCC 相连接。 *2. 请与 GND 相连接。 *3. 请妥善处理，以防被输入高阻抗。
TMSOP-8 Top view
NC
－
1.0
－
1.0
－
1.0
ILO
SDA VOUT = GND ~ VCC
－
1.0
－
1.0
－
1.0
WP
IIL
VIN＜0.3×VCC

S-24C01A中文资料

元器件交易网
Rev. 2.2_30
CMOS 2-WIRE SERIAL EEPROM
S-24C01A/02A/04A
The S-24C0XA is a series of 2-wired, low power 1K/2K/4K-bit EEPROMs
with a wide operating range. They are organized as 128-word × 8-bit, 256-word × 8-bit, and 512-word × 8-bit, respectively. Each is capable of page write, and sequential read. The time for byte write and page write is the same, i. e., 1 msec. (max.)
during operation at 5 V ± 10%.
Features
• Low power consumption Standby: 1.0 µA Max. Operating: 0.4 mA Max. 0.3 mA Max.
(VCC=5.5 V) (VCC=5.5 V) (VCC=3.3 V)
TEST pin (S-24C01A): Connected to GND.
WP (Write Protection) pin (S-24C02A, S-24C04A):
* Connected to Vcc:
Protection valid
* Connected to GND: Protection invalid
Table 8 Measurement Conditions
Input pulse voltage Input pulse rising/falling time Output judgment voltage Output load

三星S3C2416开发板手册

简介 ..................................................................................................................................................1
第四章结构框图 ..........................................................................................................................26
第五章电源设计 ..........................................................................................................................27
第二章硬件特性 ............................................................................................................................4
2.1 参数特性 .......................................................................................................................................4 2.2 核心板外观 ...................................................................................................................................5 2.3 规格尺寸 .......................................................................................................................................5 2.4 底板正面图 ...................................................................................................................................6 2.5 底板结构布局 ...............................................................................................................................6 2.6 底板硬件接口 ...............................................................................................................................7 2.7 液晶屏模块（UT_LCD43C） .....................................................................................................8 2.8 核心板引脚定义 ...........................................................................................................................9

CAT24WC16GYETE13F资料

V A2A0A1CAT24WC01/02/04/08/16ABSOLUTE MAXIMUM RATINGS*Temperature Under Bias .................–55°C to +125°C Storage Temperature.......................–65°C to +150°C Voltage on Any Pin withRespect to Ground (1)...........–2.0V to +V CC + 2.0V V CC with Respect to Ground ...............–2.0V to +7.0V Package Power DissipationCapability (Ta = 25°C)...................................1.0W Lead Soldering Temperature (10 secs)............300°C Output Short Circuit Current (2)........................100mA *COMMENTStresses above those listed under “Absolute Maximum Ratings ” may cause permanent damage to the device.These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.RELIABILITY CHARACTERISTICS Symbol ParameterMin.Max.Units N END (3)Endurance 1,000,000Cycles/Byte T DR (3)Data Retention 100Years V ZAP (3)ESD Susceptibility 2000Volts I LTH (3)(4)Latch-up100mAD.C. OPERATING CHARACTERISTICSV CC = +1.8V to +5.5V, unless otherwise specified.Limits Symbol ParameterMin.Typ.Max.Units Test Conditions I CC Power Supply Current 3mA f SCL = 100 KHz I SB (5)Standby Current (V CC = 5.0V)1µA V IN = GND or V CC I LI Input Leakage Current 10µA V IN = GND to V CC I LO Output Leakage Current 10µA V OUT = GND to V CCV IL Input Low Voltage –1V CC x 0.3V V IH Input High VoltageV CC x 0.7V CC + 0.5V V OL1Output Low Voltage (V CC = 3.0V)0.4V I OL = 3 mA V OL2Output Low Voltage (V CC = 1.8V)0.5VI OL = 1.5 mA Note:(1)The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DCvoltage on output pins is V CC +0.5V, which may overshoot to V CC + 2.0V for periods of less than 20ns.(2)Output shorted for no more than one second. No more than one output shorted at a time.(3)These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100and JEDEC test methods.(4)Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V CC +1V.(5)Maximum standby current (I SB ) = 10µA for the Automotive and Extended Automotive temperature range.CAPACITANCE T A = 25°C, f = 1.0 MHz, V CC = 5V Symbol TestMax.Units Conditions C I/O (3)Input/Output Capacitance (SDA)8pF V I/O = 0V C IN (3)Input Capacitance (A0, A1, A2, SCL, WP)6pFV IN = 0VCAT24WC01/02/04/08/16Note:(1)This parameter is tested initially and after a design or process change that affects the parameter.(2)t PUR and t PUW are the delays required from the time V CC is stable until the specified operation can be initiated.The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.Write Cycle Limits Symbol Parameter Min.Typ.Max Units t WRWrite Cycle Time10msPower-Up Timing(1)(2)Symbol ParameterMax.Units t PUR Power-up to Read Operation 1ms t PUWPower-up to Write Operation1msA.C. CHARACTERISTICSV CC = +1.8V to +5.5V, unless otherwise specified.Read & Write Cycle Limitsl o b m y S r e t e m a r a P 8.1-X X C W 42T A C XX C W 42T A C s t i n U V5.5-V 8.1V 5.5-V 5.2V 5.5-V 5.4.n i M .x a M .n i M .x a M .n i M .x a M F L C S yc n e u q e r F k c o l C 001001004z H k T I)1(t a t n a t s n o C e m i T n o i s s e r p p u S e s i o N st u p n I A D S ,L C S 002002002s n t A A K C A d n a t u O a t a D A D S o t w o L L C S tu O 5.35.31µs t FU B )1(e r o f e B e e r F e b t s u M s u B e h t e m i T t r a t S n a C n o i s s i m s n a r T w e N a 7.47.42.1µs t A T S :D H e m i T d l o H n o i t i d n o C t r a t S 446.0µs t W O L d o i r e P w o L k c o l C 7.47.42.1µs t H G I H do i r e P h g i H k c o l C 446.0µs t A T S :U S em i T p u t e S n o i t i d n o C t r a t S )n o i t i d n o C t r a t S d e t a e p e R a r o f (7.47.46.0µs t T A D :D H e m i T d l o H n I a t a D 000s n t T A D :U S e m i T p u t e S n I a t a D 050505s n t R )1(e m i T e s i R L C S d n a A D S 113.0µs t F)1(e m i T l l a F L C S d n a A D S 003003003s n t O T S :U S e m i T p u t e S n o i t i d n o C p o t S 446.0µs t HD em i T d l o H t u O a t a D 001001001snCAT24WC01/02/04/08/16FUNCTIONAL DESCRIPTIONThe CAT24WC01/02/04/08/16 supports the I 2C Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. Data transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT24WC01/02/04/08/16 operates as a Slave device. Both the Mas-ter and Slave devices can operate as either transmitter or receiver, but the Master device controls which mode is activated. A maximum of 8 devices (CAT24WC01 and CAT24WC02), 4 devices (CAT24WC04), 2 devices (CAT24WC08) and 1 device (CAT24WC16) may be connected to the bus as determined by the device address inputs A0, A1, and A2.PIN DESCRIPTIONSSCL: Serial ClockThe CAT24WC01/02/04/08/16 serial clock input pin is used to clock all data transfers into or out of the device.This is an input pin.SDA: Serial Data/AddressThe CAT24WC01/02/04/08/16 bidirectional serial data/address pin is used to transfer data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs.A0, A1, A2: Device Address InputsThese inputs set device address when cascading mul-tiple devices. When these pins are left floating the default values are zeros.A maximum of eight devices can be cascaded whenFigure 3. Start/Stop Timing5020 FHD F055020 FHD F03SCLSDA INSDA OUTSTART BITSDASTOP BITSCLCAT24WC01/02/04/08/16using either CAT24WC01 or CAT24WC02 device. All three address pins are used for these densities. If only one CAT24WC01 or CAT24WC02 is addressed on the bus, all three address pins (A0, A1and A2) can be left floating or connected to V SS .A total of four devices can be addressed on a single bus when using CAT24WC04 device. Only A1 and A2address pins are used with this device. The A0 address pin is a no connect pin and can be tied to V SS or left floating. If only one CAT24WC04 is being addressed on the bus, the address pins (A1 and A2) can be left floating or connected to V SS .Only two devices can be cascaded when using CAT24WC08. The only address pin used with this device is A2. The A0 and A1 address pins are no connect pins and can be tied to V SS or left floating. If only one CAT24WC08 is being addressed on the bus, the address pin (A2) can be left floating or connected to V SS .The CAT24WC16 is a stand alone device. In this case,all address pins (A0, A1and A2) are no connect pins and can be tied to V SS or left floating.WP: Write ProtectIf the WP pin is tied to V CC the entire memory array becomes Write Protected (READ only). When the WP pin is tied to V SS or left floating normal read/write operations are allowed to the device.I 2C Bus ProtocolThe following defines the features of the I 2C bus protocol:(1)Data transfer may be initiated only when the bus isnot busy.(2)During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition.START ConditionThe START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIG H. The CAT24WC01/02/04/08/16monitor the SDA and SCL lines and will not respond until this condition is met.STOP ConditionA LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition.DEVICE ADDRESSINGThe bus Master begins a transmission by sending a START condition. The Master then sends the address of the particular slave device it is requesting. The four most significant bits of the 8-bit slave address are fixed as 1010 for the CAT24WC01/02/04/08/16 (see Fig. 5).The next three significant bits (A2, A1, A0) are the device address bits and define which device or which part of the device the Master is accessing. Up to eight CAT24WC01/02, four CAT24WC04, two CAT24WC08, and one CAT24WC16 may be individually addressed by the system. The last bit of the slave address specifies whether a Read or Write operation is to be performed.When this bit is set to 1, a Read operation is selected,and when set to 0, a Write operation is selected.After the Master sends a START condition and the slave address byte, the CAT24WC01/02/04/08/16 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slaveFigure 4. Acknowledge Timing5020 FHD F06ACKNOWLEDGESTARTSCL FROM MASTERDATA OUTPUTFROM TRANSMITTERDATA OUTPUT FROM RECEIVERCAT24WC01/02/04/08/16address. The CAT24WC01/02/04/08/16 then performs a Read or Write operation depending on the state of the R/W bit.AcknowledgeAfter a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledg-ing device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data.The CAT24WC01/02/04/08/16 responds with an ac-knowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8-bit byte.When the CAT24WC01/02/04/08/16 is in a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT24WC01/02/04/08/16 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition.WRITE OPERATIONSByte WriteIn the Byte Write mode, the Master device sends the START condition and the slave address information (with the R/W bit set to zero) to the Slave device. After the Slave generates an acknowledge, the Master sends the byte address that is to be written into the address pointer of the CAT24WC01/02/04/08/16. After receiving another acknowledge from the Slave, the Master device transmits the data byte to be written into the addressed memory location. The CAT24WC01/02/04/08/16 ac-knowledge once more and the Master generates the STOP condition, at which time the device begins its internal programming cycle to nonvolatile memory. While this internal cycle is in progress, the device will not respond to any request from the Master device.Page WriteThe CAT24WC01/02/04/08/16 writes up to 16 bytes of data in a single write cycle, using the Page Write operation. The Page Write operation is initiated in the same manner as the Byte Write operation, however instead of terminating after the initial word is transmitted,Figure 5. Slave Address Bits*A0, A1 and A2 correspond to pin 1, pin 2 and pin 3 of the device.**a8, a9 and a10 correspond to the address of the memory array address word.***A0, A1 and A2 must compare to its corresponding hard wired input pins (pins 1, 2 and 3).1010A2 A1 A0R/W1010A2A1a8R/W1010A2a9 a8R/W1010a10a9a8R/WCAT24WC01/02CAT24WC04CAT24WC08CAT24WC16CAT24WC01/02/04/08/1624WCXX F09Figure 7. Page Write Timing5020 FHD F08Figure 6. Byte Write Timing*P=7 for CAT24WC01 and P=15 for CAT24WC02/04/08/16* = Don't care for CAT24WC01BUS ACTIVITY:MASTERSDA LINEBYTE C KC KC KS T O C KC KS T A R SLAVE NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0WRITE PROTECTIONThe Write Protection feature allows the user to protect against inadvertent programming of the memory array.If the WP pin is tied to V CC , the entire memory array is protected and becomes read only. The CAT24WC01/02/04/08/16 will accept both slave and byte addresses,but the memory location accessed is protected from programming by the device ’s failure to send an acknowledge after the first byte of data is received.READ OPERATIONSThe READ operation for the CAT24WC01/02/04/08/16is initiated in the same manner as the write operation with the one exception that the R/W bit is set to a one.Three different READ operations are possible: Immediate Address READ, Selective READ and Sequential READ.Immediate Address ReadThe CAT24WC01/02/04/08/16’s address counter contains the address of the last byte accessed,incremented by one. In other words, if the last READ or WRITE access was to address N, the READ immediately following would access data from address N+1. If N=E (where E = 255 for 24WC02, 511 for 24WC04, 1023 for 24WC08, and 2047 for 24WC16), then the counter will 'wrap around' to address 0 and continue to clock out data. If N = E (where E = 127 for the CAT24WC01) the counter will not 'wrap around'.BYTE ADDRESSSLAVE ADDRESSSA C KA C KDATAA C K S T O P PBUS ACTIVITY:MASTERSDA LINES T A R T the Master is allowed to send up to fifteen additional bytes. After each byte has been transmitted the CAT24WC01/02/04/08/16 will respond with an acknowledge, and internally increment the low order address bits by one. The high order bits remain unchanged.If the Master transmits more than sixteen bytes prior to sending the STOP condition, the address counter ‘wraps around ’, and previously transmitted data will be overwritten.Once all sixteen bytes are received and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point all received data is written to the CAT24WC01/02/04/08/16 in a single write cycle.Acknowledge PollingThe disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host ’s write operation,the CAT24WC01/02/04/08/16 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the CAT24WC01/02/04/08/16 is still busy with the write operation, no ACK will be returned. If the CAT24WC01/02/04/08/16 has completed the write operation, an ACK will be returned and the host can then proceed with the next read or write operation.CAT24WC01/02/04/08/165020 FHD F10Figure 8. Immediate Address Read TimingSCL SDA 8TH BIT STOPNO ACKDATA OUT89SLAVE ADDRESSSA C KDATAN O A C KS T O P PBUS ACTIVITY:MASTERSDA LINES T A R T Selective ReadSelective READ operations allow the Master device to select at random any memory location for a READ operation. The Master device first performs a ‘dummy ’write operation by sending the START condition, slave address and byte address of the location it wishes to read. After the CAT24WC01/02/04/08/16 acknowledge the word address, the Master device resends the START condition and the slave address, this time with the R/W bit set to one. The CAT24WC01/02/04/08/16 then responds with its acknowledge and sends the 8-bit byte requested. The master device does not send an acknowledge but will generate a STOP condition.Sequential ReadThe Sequential READ operation can be initiated by either the immediate Address READ or Selective READoperations. After the 24WC01/02/04/08/16 sends initial 8-bit byte requested, the Master will respond with an acknowledge which tells the device it requires more data. The CAT24WC01/02/04/08/16 will continue to output an 8-bit byte for each acknowledge sent by the Master. The operation is terminated when the Master fails to respond with an acknowledge, thus sending the STOP condition.The data being transmitted from the CAT24WC01/02/04/08/16 is outputted sequentially with data from address N followed by data from address N+1. The READ operation address counter increments all of the CAT24WC01/02/04/08/16 address bits so that the entire memory array can be read during one operation. If more than the E (where E = 255 for 24WC02, 511 for 24WC04,1023 for 24WC08, and 2047 for 24WC16) bytes are read out, the counter will “wrap around ” and continue to clock out data bytes. If N = E (where E = 127 for the CAT24WC01) the counter will not 'wrap around'.CAT24WC01/02/04/08/165020 FHD F12Figure 10. Sequential Read Timing24WCXX F11Figure 9. Selective Read TimingSLAVE ADDRESSSA C KN O A C K S T O P PBUS ACTIVITY:MASTERSDA LINES T A R T BYTE ADDRESS (n)S A C KDATA nSLAVE ADDRESSA C KS T AR T *BUS ACTIVITY:MASTERSDA LINEDATA n+xDATA nC KC KDATA n+1C KS T O O A C KDATA n+2C KSLAVE ADDRESSCAT24WC01/02/04/08/16Notes:plies with JEDEC Publication 95 MS001 dimensions; however, some of the dimensions may be more stringent.2.All linear dimensions are in inches and parenthetically in millimeters.0.100 (2.54)BSC8-LEAD 300 MIL WIDE PLASTIC DIP (P, L, GL)8-LEAD 150 MIL WIDE SOIC (J, W, GW)Notes:plies with JEDEC publication 95 MS-012 dimensions; however, some dimensions may be more stringent.2.All linear dimensions are in inches and parenthetically in millimeters.CAT24WC01/02/04/08/1611Doc. No. 1022, Rev. N© 2005 by Catalyst Semiconductor, Inc.Characteristics subject to change without noticeSECTION A - ANotes:(1)All dimensions are in mm Angles in degrees.2Does not include Mold Flash, Protrusion or Gate Burrs. Mold Flash, Protrusions or Gate Burrs shall not exceed 0.15 mm. per side. 3Does not include Interlead Flash orProtrusion. Interlead Flash or Protrusion shall not exceed 0.25 mm per side. 4Does not include Dambar Protrusion, allowable Dambar Protrusion shall be 0.08 mm.(5)This part is compliant with JEDEC Specification MO-187 Variations AA.(6) Lead span/stand off height/coplanarity are considered as special characteristics. (S)(7) Controlling dimensions in inches. [mm]CAT24WC01/02/04/08/1612Doc. No. 1022, Rev. N© 2005 by Catalyst Semiconductor, Inc.Characteristics subject to change without notice8-LEAD TSSOP (U, Y, GY)CAT24WC01/02/04/08/1613Doc. No. 1022, Rev. N© 2005 by Catalyst Semiconductor, Inc.Characteristics subject to change without noticeORDERING INFORMATIONNotes:(1) The device used in the above example is a CAT24WC02JI-1.8TE13REV-E (SOIC, Industrial Temperature, 1.8 Volt to 5.5 VoltOperating Voltage, Tape & Reel, Die Revision E)** Available for CAT24WC01, CAT24WC02 and CAT24WC04Catalyst Semiconductor, Inc.Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089Phone: 408.542.1000Fax: 408.542.1200Publication #:1022Revison:NIssue date:08/12/05Copyrights, Trademarks and PatentsTrademarks and registered trademarks of Catalyst Semiconductor include each of the following:DPP ™AE 2 ™Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur.Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete.REVISION HISTORYDate Rev.Reason2/3/2004HAdded: CAT24WC01/02/16 not recommended for new designs. See CAT24FC01, CAT24FC02 and CAT24FC16 data sheets5/28/2004I Added Die Revision to ordering information 7/28/2004J Update DC operating characteristics and notes 1/27/2005K Added Die Revision E to ordering information 2/28/2005L Edit Ordering Information 3/18/2005M Edit Features08/12/05NEdit FeaturesEdit Pin FunctionsEdit Reliability CharacteristicsEdit D.C. Operating Characteristics Edit A.C. Characteristics Add Package Dimensions Edit Ordering Information。

AT24C02,AT24C04,AT24C16产品规格书

S P E C I F I C A T I O N24C02/24C04/24C08/24C16Version 1.0Two-wire Serial EEPROM2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8)▉FeaturesThe 24C02/24C04/24C08/24C16 provides 2048/4096/8192/16384 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 256/512/1024/2048 words of 8 bits each. The device is optimized for use in many industrial and commercial applications wherelow-power and low-voltage operation are essential. The 24C02/24C04/24C08/24C16 is available in space-saving 8-lead PDIP, 8-lead SOP, and 8-lead TSSOP packages and is accessed via a two-wire serial interface.▉Pin ConfigurationTwo-wire Serial EEPROM2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8)▉Pin DescriptionsTwo-wire Serial EEPROM2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8)▉Pin Descriptions24C02, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each, the 2K requires an 8-bit data word address for random word addressing.24C04, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each, the 4K requires a 9-bit data word address for random word addressing.24C08, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each, the 8K requires a 10-bit data word address for random word addressing.24C16, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes each, the 16K requires an 11-bit data word address for random word addressing.▉Device OperationTwo-wire Serial EEPROM 2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8)Two-wire Serial EEPROM2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8) The 2K, 4K, 8K and 16K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation (see to Figure 4 on page 7).The device address word consists of a mandatory "1", "0" sequence for the first four most significant bits as shown. This is common to all the Serial EEPROM devices.The next 3 bits are the A2, A1 and A0 device address bits for the 2K EEPROM. These 3 bits must compare to their corresponding hardwired input pins.The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a memory page address bit. The two device address bits must compare to their corresponding hardwired input pins. The A0 pin is no connect.The 8K EEPROM only uses the A2 device address bit with the next 2 bits being for memory page addressing. The A2 bit must compare to its corresponding hard-wired input pin. The A1 and A0 pins are no connect.The 16K does not use any device address bits but instead the 3 bits are used for memory page addressing. These page addressing bits on the 4K, 8K and 16K devices should be considered the most significant bits of the data word address which follows. The A0, A1 and A2 pins are no connect.The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low.Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the chip will return to a standby state.▉Write OperationsTwo-wire Serial EEPROM2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8) Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to "1". There are three read operations: current address read,random address read and sequential read.CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address "roll over" during read is from the last byte of the last memory page to the first byte of the first page. The address "roll over" during write is from the last byte of the current page to the first byte of the same page.Once the device address with the read/write select bit set to "1" is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input "0" but does generate a following stop condition (see Figure 7 on page 8).RANDOM READ: A random read requires a "dummy" byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a "0" but does generate a following stop condition (see Figure 8 on page 8). SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a randomTwo-wire Serial EEPROM 2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8)Two-wire Serial EEPROM2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8)l Absolute Maximum Stress RatingsDC Supply Voltage . . . . . . . . . . . . . . . . .-0.3V to +6.5V Input / Output Voltage . . . . . . . .GND-0.3V to V CC+0.3V Operating Ambient Temperature . . . . . -40℃to +85℃Storage Temperature . . . . . . . . . . . . -65℃to +150℃l CommentsStresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.Two-wire Serial EEPROM2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8)▉DC Electrical CharacteristicsApplicable over recommended operating range from TA = 25 ℃, f = 1.0 MHz, VCC = +1.8V Parameter Symbol Min. Typ. Max. Unit ConditionCI/O - - 8 pF VI/O = 0V Input/Output Capacitance(SDA)Input Capacitance (A0, A1,CIN - - 8 pF VIN = 0V A2, SCL)▉AC Electrical CharacteristicsTwo-wire Serial EEPROM2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8) Figure 10: SCL: Serial Clock, SDA: Serial Data I/OTwo-wire Serial EEPROM2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8)▉Write Cycle Timing。

FMD FT24C16A

Two-Wire Serial EEPROM4K, 8K and 16K (8-bit wide)FEATURES❑Low voltage and low power operations:FT24C04A/08A/16A: V CC = 1.8V to 5.5V❑Maximum Standby current < 1µA (typically 0.02µA and 0.06µA @ 1.8V and 5.5V respectively).❑16 bytes page write mode.❑Partial page write operation allowed.❑Internally organized: 512 x 8 (4K), 1024 x 8 (8K), 2048 x 8 (16K).❑Standard 2-wire bi-directional serial interface.❑Schmitt trigger, filtered inputs for noise protection.❑Self-timed Write Cycle (5ms maximum).❑ 1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) Compatibility.❑Automatic erase before write operation.❑Write protect pin for hardware data protection.❑High reliability: typically 1, 000,000 cycles endurance.❑100 years data retention.❑Industrial temperature range (-40o C to 85o C).❑Standard 8-lead DIP/SOP/MSOP/TSSOP/DFN and 5-lead SOT-23/TSOT-23 Pb-free packages. DESCRIPTIONThe FT24C04A/08A/16A series are 4,096/8,192/16,384 bits of serial Electrical Erasable and Programmable Read Only Memory, commonly known as EEPROM. They are organized as 512/1,024/2,048 words of 8 bits (1 byte) each. The devices are fabricated with proprietary advanced CMOS process for low power and low voltage applications. These devices are available in standard 8-lead DIP, 8-lead SOP, 8-lead TSSOP, 8-lead DFN, 8-lead MSOP, and 5-lead SOT-23/TSOT-23packages. A standard 2-wire serial interface is used to address all read and write functions. Our extended V CC range(1.8V to 5.5V)devices enables wide spectrum of applications.PIN CONFIGURATIONPin Name Pin FunctionA2, A1, A0 Device Address InputsSDA Serial Data Input / Open Drain OutputSCL Serial Clock InputWP Write ProtectNo-ConnectNC© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page1© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page2All these packaging types come in conventional or Pb-free certified.VCC W P SCL SDAA2A1A0G 8L DIP 8L SOP8L TSSOP W P VCCG ND FT24C04A/08A/16A 5L SOT-23SCL 8L DFN8L M SOP 5L TSO T-23ABSOLUTE MAXIMUM RATINGSIndustrial operating temperature: -40℃ to 85℃ Storage temperature:-50℃ to 125℃Input voltage on any pin relative to ground: -0.3V to V CC + 0.3V Maximum voltage: 8VESD protection on all pins: >2000V* Stresses exceed those listed under “Absolute Maximum Rating” may cause permanent damage to the device. Functional operation of the device at conditions beyond those listed in the specification is not guaranteed. Prolonged exposure to extreme conditions may affect device reliability or functionality .PIN DESCRIPTIONS(A) SERIAL CLOCK (SCL)The rising edge of this SCL input is to latch data into the EEPROM device while the falling edge of thisclock is to clock data out of the EEPROM device.(B) DEVICE / CHIP SELECT ADDRESSES (A2, A1, A0)These are the chip select input signals for the serial EEPROM devices. Typically, these signals are hardwired to either V IH or V IL. If left unconnected, they are internally recognized as V IL. FT24C04A has A0 pin as no-connect. FT24C08A has both A0 and A1 pins as no-connect. For FT24C16A, all device address pins (A0-A2) are no-connect.(C) SERIAL DATA LINE (SDA)SDA data line is a bi-directional signal for the serial devices. It is an open drain output signal and can be wired-OR with other open-drain output devices.(D) WRITE PROTECT (WP)The FT24C04A/08A/16A devices have a WP pin to protect the whole EEPROM array from programming.Programming operations are allowed if WP pin is left un-connected or input to V IL. Conversely all programming functions are disabled if WP pin is connected to V IH or V CC. Read operations is not affected by the WP pin’s input level.Table A© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page3Device Chip Select/DeviceAddress Pins UsedNo-Connect PinsMax number of similardevices on the samebusFT24C04A A2,A1 A0 4 FT24C08A A2, A1,A0 2 FT24C16A (None) A2, A1, A0 1MEMORY ORGANIZATIONThe FT24C04A/08A/16A devices have 32/64/128 pages respectively. Since each page has 16 bytes, random word addressing to FT24C04A/08A/16A will require 9/10/11 bits data word addresses respectively.DEVICE OPERATION(A) SERIAL CLOCK AND DATA TRANSITIONSThe SDA pin is typically pulled to high by an external resistor. Data is allowed to change only when Serial clock SCL is at V IL. Any SDA signal transition may interpret as either a START or STOP condition as described below.(B) START CONDITIONWith SCL V IH, a SDA transition from high to low is interpreted as a START condition. All valid commands must begin with a START condition.© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page4© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page5(C) STOP CONDITIONWith SCL V IH , a SDA transition from low to high is interpreted as a STOP condition. All valid read or write commands end with a STOP condition. The device goes into the STANDBY mode if it is after a read command. A STOP condition after page or byte write command will trigger the chip into the STANDBY mode after the self-timed internal programming finish. (D) ACKNOWLEDGEThe 2-wire protocol transmits address and data to and from the EEPROM in 8 bit words. The EEPROM acknowledges the data or address by outputting a "0" after receiving each word. The ACKNOWLEDGE signal occurs on the 9th serial clock after each word. (E) STANDBY MODEThe EEPROM goes into low power STANDBY mode after a fresh power up, after receiving a STOP bit in read mode, or after completing a self-time internal programming operation.Figure 1: Timing diagram for START and STOP conditionsFigure 2: Timing diagram for output ACKNOWLEDGESCLSDASTART ConditionSTOP ConditionData Data Valid TransitionSCLData inData out START ConditionACKDEVICE ADDRESSINGThe 2-wire serial bus protocol mandates an 8 bits device address word after a START bit condition to invoke valid read or write command. The first four most significant bits of the device address must be 1010, which is common to all serial EEPROM devices. The next three bits are device address bits. These three device address bits (5th, 6th and 7th) are to match with the external chip select/address pin states. If a match is made, the EEPROM device outputs an ACKNOWLEDGE signal after the 8th read/write bit, otherwise the chip will go into STANDBY mode. However, matching may not be needed for some or all device address bits (5th, 6th and 7th) as noted below. The last or 8th bit is a read/write command bit. If the 8th bit is at V IH then the chip goes into read mode. If a “0” is detected, the device enters programming mode.FT24C04A uses A2 (5th) and A1 (6th) device address bits. Only four FT24C04A devices can be wired-OR on the same 2-wire bus. Their corresponding chip select address pins A2 and A1 must be hard wired and coded from 00 (b) to 11 (b). Chip select address pin A0 is not used.FT24C08A uses only A2 (5th) device address bit. Only two FT24C08A devices can be wired-OR on the same 2-wire bus. Their corresponding chip select address pin A2 must be hard-wired and coded from 0 (b) to 1 (b). Chip select address pins A1 and A0 are not used.FT24C16A does not use any device address bit. Only one FT24C16A device can be used on the on 2-wire bus. Chip Select address pins A2, A1, and A0 are not used.WRITE OPERATIONS(A) BYTE WRITEA byte write operation starts when a micro-controller sends a START bit condition, follows by a properEEPROM device address and then a write command. If the device address bits match the chip select address, the EEPROM device will acknowledge at the 9th clock cycle. The micro-controller will then send the rest of the lower 8 bits word address. At the 18th cycle, the EEPROM will acknowledge the 8-bit address word. The micro-controller will then transmit the 8 bit data. Following an ACKNOWLDEGE signal from the EEPROM at the 27th clock cycle, the micro-controller will issue a STOP bit. After receiving the STOP bit, the EEPROM will go into a self-timed programming mode during which all external inputs will be disabled. After a programming time of T WC, the byte programming will finish and the EEPROM device will return to the STANDBY mode.(B) PAGE WRITEA page write is similar to a byte write with the exception that one to sixteen bytes can be programmedalong the same page or memory row. All FT24C04A/08A/16A are organized to have 16 bytes per memory row or page.With the same write command as the byte write, the micro-controller does not issue a STOP bit after sending the 1st byte data and receiving the ACKNOWLEDGE signal from the EEPROM on the 27th clock cycle. Instead it sends out a second 8-bit data word, with the EEPROM acknowledging at the 36th cycle.This data sending and EEPROM acknowledging cycle repeats until the micro-controller sends a STOP bit after the n 9th clock cycle. After which the EEPROM device will go into a self-timed partial or full page programming mode. After the page programming completes after a time of T WC, the devices will return to the STANDBY mode.© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page6The least significant 4 bits of the word address (column address) increments internally by one afterreceiving each data word. The rest of the word address bits (row address) do not change internally, butpointing to a specific memory row or page to be programmed. The first page write data word can be ofany column address. Up to 16 data words can be loaded into a page. If more then 16 data words areloaded, the 17th data word will be loaded to the 1st data word column address. The 18th data word willbe loaded to the 2nd data word column address and so on. In other word, data word address (columnaddress) will “roll” over the previously loaded data.(C) ACKNOWLEDGE POLLINGACKNOWLEDGE polling may be used to poll the programming status during a self-timed internalprogramming. By issuing a valid read or write address command, the EEPROM will not acknowledge atthe 9th clock cycle if the device is still in the self-timed programming mode. However, if the programmingcompletes and the chip has returned to the STANDBY mode, the device will return a validACKNOWLEDGE signal at the 9th clock cycle.READ OPERATIONSThe read command is similar to the write command except the 8th read/write bit in address word is set to “1”.The three read operation modes are described as follows:(A) CURRENT ADDRESS READThe EEPROM internal address word counter maintains the last read or write address plus one if thepower supply to the device has not been cut off. To initiate a current address read operation, the micro-controller issues a START bit and a valid device address word with the read/write bit (8th) set to “1”. TheEEPROM will response with an ACKNOWLEDGE signal on the 9th serial clock cycle. An 8-bit data wordwill then be serially clocked out. The internal address word counter will then automatically increase byone. For current address read the micro-controller will not issue an ACKNOWLEDGE signal on the 18thclock cycle. The micro-controller issues a valid STOP bit after the 18th clock cycle to terminate the readoperation. The device then returns to STANDBY mode.(B) SEQUENTIAL READThe sequential read is very similar to current address read. The micro-controller issues a START bitand a valid device address word with read/write bit (8th) set to “1”. The EEPROM will response with anACKNOWLEDGE signal on the 9th serial clock cycle. An 8-bit data word will then be serially clocked out.Meanwhile the internally address word counter will then automatically increase by one. Unlike currentaddress read, the micro-controller sends an ACKNOWLEDGE signal on the 18th clock cycle signalingthe EEPROM device that it wants another byte of data. Upon receiving the ACKNOWLEDGE signal, theEEPROM will serially clocked out an 8-bit data word based on the incremented internal address counter.If the micro-controller needs another data, it sends out an ACKNOWLEDGE signal on the 27th clockcycle. Another 8-bit data word will then be serially clocked out. This sequential read continues as longas the micro-controller sends an ACKNOWLEDGE signal after receiving a new data word. When theinternal address counter reaches its maximum valid address, it rolls over to the beginning of the memoryarray address. Similar to current address read, the micro-controller can terminate the sequential read bynot acknowledging the last data word received, but sending a STOP bit afterwards instead.(C) RANDOM READRandom read is a two-steps process. The first step is to initialize the internal address counter with atarget read address using a “dummy write” instruction. The second step is a current address read.To initialize the internal address counter with a target read address, the micro-controller issues a STARTbit first, follows by a valid device address with the read/write bit (8th) set to “0”. The EEPROM will thenacknowledge. The micro-controller will then send the address word. Again the EEPROM willacknowledge. Instead of sending a valid written data to the EEPROM, the micro-controller performs a current address read© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page7instruction to read the data. Note that once a START bit is issued, the EEPROM will reset the internal programming process and continue to execute the new instruction - which is to read the current address.© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page8© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page9Figure 8: SCL and SDA Bus TimingAC CHARACTERISTICS1.8 V2.5-5.0 V Symbol ParameterMin Max Min Max Unit f SCL Clock frequency, SCL 400 1000 kHz t LOW Clock pulse width low 1.20.7µst HIGH Clock pulse width high0.4 0.3 µst I Noise suppression time (1) 180 120 ns t AA Clock low to data out valid 0.3 0.9 0.2 0.7 µs t BUF Time the bus must be free before a new transmission can start (1)1.3 0.5 µs t HD.STA START hold time 0.6 0.25 µs t SU.STA START set-up time 0.6 0.25 µs t HD.DAT Data in hold time 0 0 µs t SU.DAT Data in set-up time 100100nst R Input rise time (1)0.3 0.3 µs t F Input fall time (1) 300 100 nst SU.STO STOP set-up time 0.6 0.25 µs t DH Date out hold time 50 50 ns WRWrite cycle time55msEndurance(1)25o C, Page Mode, 3.3V1,000,000Write CyclesNotes: 1. This Parameter is expected by characterization but are not fully screened by test.2. AC Measurement conditions: R L (Connects to Vcc): 1.3K ΩInput Pulse Voltages: 0.3Vcc to 0.7VccInput and output timing reference Voltages: 0.5VccDC CHARACTERISTICSSymbol Parameter TestConditions MinTypicalMaxUnitsV CC124C A supplyV CC1.8 5.5 VI CC Supply read current V CC@ 5.0V SCL = 400 kHz 0.5 1.0 mA I CC Supply write current V CC@ 5.0V SCL = 400 kHz 2.0 3.0 mA I SB1 Supplycurrent V CC@ 1.8V, V IN = V CC or V SS 1.0 µA I SB2 Supplycurrent V CC@ 2.5V, V IN = V CC or V SS 1.0 µA I SB3 Supplycurrent V CC@ 5.0V, V IN = V CC or V SS0.06 1.0 µAI IL Input leakagecurrentV IN = V CC or V SS 3.0 µAI LO Output leakagecurrentV IN = V CC or V SS 3.0 µAV IL Input low level -0.6 V CC x0.3 V V IH Input high level V CC x0.7V CC+0.5 V V OL1 Outputlowlevel V CC@ 1.8V, I OL = 0.15 mA 0.2 V V OL2 Outputlowlevel V CC@ 3.0V, I OL = 2.1 mA 0.4 V© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page10© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page11ORDERING INFORMATION:Density PackageTemperatureRangeVcc HSF Packaging Ordering CodeRoHSTube FT24C04A-UDR-B DIP8 -40℃-85℃ 1.8V-5.5VGreen Tube FT24C04A-UDG-B Tube FT24C04A-USR-B RoHSTape and Reel FT24C04A-USR-TTube FT24C04A-USG-B SOP8 -40℃-85℃ 1.8V-5.5VGreen Tape and Reel FT24C04A-USG-TTube FT24C04A-UMR-B RoHSTape and Reel FT24C04A-UMR-TTube FT24C04A-UMG-B MSOP8 -40℃-85℃ 1.8V-5.5VGreenTape and Reel FT24C04A-UMG-TTube FT24C04A-UTR-B RoHSTape and Reel FT24C04A-UTR-TTube FT24C04A-UTG-B TSSOP8 -40℃-85℃ 1.8V-5.5VGreenTape and Reel FT24C04A-UTG-T RoHS Tape and Reel FT24C04A-ULR-T SOT23-5 -40℃-85℃ 1.8V-5.5V Green Tape and Reel FT24C04A-ULG-T RoHS Tape and Reel FT24C04A-UPR-T TSOT23-5 -40℃-85℃ 1.8V-5.5V Green Tape and Reel FT24C04A-UPG-T RoHS Tape and Reel FT24C04A-UNR-T 4kbitsDFN8 -40℃-85℃ 1.8V-5.5V Green Tape and Reel FT24C04A-UNG-TRoHS Tube FT24C08A-UDR-B DIP8 -40℃-85℃ 1.8V-5.5VGreen Tube FT24C08A-UDG-B Tube FT24C08A-USR-B RoHSTape and Reel FT24C08A-USR-TTube FT24C08A-USG-B 8kbitsSOP8 -40℃-85℃ 1.8V-5.5VGreenTape and Reel FT24C08A-USG-TD: DIP8 S: SOP8 M: MSOP8 T: TSSOP8 L: SOT23-5 P: TSOT23-5 N: DFN8Packaging B: TubeT: Tape and Reel HSF R: RoHS G: GreenU:-40© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page12Density Package TemperatureRangeVcc HSF Packaging Ordering CodeTube FT24C08A-UMR-BRoHSTape and Reel FT24C08A-UMR-TTube FT24C08A-UMG-B MSOP8 -40℃-85℃ 1.8V-5.5VGreen Tape and Reel FT24C08A-UMG-TTube FT24C08A-UTR-B RoHSTape and Reel FT24C08A-UTR-TTube FT24C08A-UTG-B TSSOP8 -40℃-85℃ 1.8V-5.5VGreen Tape and Reel FT24C08A-UTG-T RoHSTape and Reel FT24C08A-ULR-T SOT23-5 -40℃-85℃ 1.8V-5.5V Green Tape and Reel FT24C08A-ULG-T RoHS Tape and Reel FT24C08A-UPR-T TSOT23-5 -40℃-85℃ 1.8V-5.5V Green Tape and Reel FT24C08A-UPG-T RoHS Tape and Reel FT24C08A-UNR-T 8kbitsDFN8 -40℃-85℃ 1.8V-5.5V Green Tape and Reel FT24C08A-UNG-TRoHS Tube FT24C16A-UDR-B DIP8 -40℃-85℃ 1.8V-5.5VGreen Tube FT24C16A-UDG-B Tube FT24C16A-USR-B RoHSTape and Reel FT24C16A-USR-TTube FT24C16A-USG-B SOP8 -40℃-85℃ 1.8V-5.5VGreen Tape and Reel FT24C16A-USG-TTube FT24C16A-UMR-B RoHSTape and Reel FT24C16A-UMR-TTube FT24C16A-UMG-B MSOP8 -40℃-85℃ 1.8V-5.5VGreenTape and Reel FT24C16A-UMG-TTube FT24C16A-UTR-B RoHSTape and Reel FT24C16A-UTR-TTube FT24C16A-UTG-B TSSOP8 -40℃-85℃ 1.8V-5.5VGreenTape and Reel FT24C16A-UTG-T RoHS Tape and Reel FT24C16A-ULR-T SOT23-5 -40℃-85℃ 1.8V-5.5V Green Tape and Reel FT24C16A-ULG-T RoHS Tape and Reel FT24C16A-UPR-T TSOT23-5 -40℃-85℃ 1.8V-5.5V Green Tape and Reel FT24C16A-UPG-T RoHS Tape and Reel FT24C16A-UNR-T 16kbitsDFN8 -40℃-85℃ 1.8V-5.5VGreenTape and Reel FT24C16A-UNG-TDIP8 PACKAGE OUTLINEDIMENSIONSDimensions In Millimeters Dimensions In InchesSymbolMin Max Min MaxA 3.710 4.310 0.146 0.170A1 0.510 0.020A2 3.200 3.600 0.126 0.142B 0.380 0.570 0.015 0.0221.524（BSC） 0.060（BSC）B1C 0.204 0.360 0.008 0.014D 9.000 9.400 0.354 0.370E 6.200 6.600 0.244 0.260E1 7.320 7.920 0.288 0.312(BSC) 0.100（BSC）e 2.540L 3.000 3.600 0.118 0.142E2 8.400 9.000 0.331 0.354© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page13SOP8 PACKAGE OUTLINE DIMENSIONSDimensions In Millimeters Dimensions In InchesSymbolMin Max Min MaxA 1.350 1.750 0.053 0.069A1 0.100 0.250 0.004 0.010A2 1.350 1.550 0.053 0.061b 0.330 0.510 0.013 0.020c 0.170 0.250 0.006 0.010D 4.700 5.100 0.185 0.200E 3.800 4.000 0.150 0.157E1 5.800 6.200 0.228 0.244(BSC)(BSC) 0.050e 1.270L 0.400 1.270 0.016 0.050θ0° 8° 0° 8°© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page14MSOP8 PACKAGE OUTLINE DIMENSIONSDimensions In Millimeters Dimensions In InchesSymbolMin Max Min MaxA 0.820 1.100 0.320 0.043A1 0.020 0.150 0.001 0.006A2 0.750 0.950 0.030 0.037b 0.250 0.380 0.010 0.015c 0.090 0.230 0.004 0.009D 2.900 3.100 0.114 0.122e 0.65 (BSC) 0.026 (BSC)E 2.900 3.100 0.114 0.122E1 4.750 5.050 0.187 0.199L 0.400 0.800 0.016 0.031θ0° 6° 0° 6°© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page15TSSOP8 PACKAGE OUTLINEDIMENSIONSDimensions In Millimeters Dimensions In InchesSymbolMin Max Min MaxD 2.900 3.100 0.114 0.122E 4.300 4.500 0.169 0.177b 0.190 0.300 0.007 0.012c 0.090 0.200 0.004 0.008E1 6.250 6.550 0.246 0.258A 1.100 0.043A2 0.800 1.000 0.031 0.039A1 0.020 0.150 0.001 0.006e 0.65 (BSC) 0.026 (BSC)L 0.500 0.700 0.020 0.028H 0.25 (TYP) 0.01 (TYP)θ 1° 7° 1° 7°© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page16SOT-23-5 PACKAGE OUTLINE DIMENSIONSDimensions In Millimeters Dimensions In InchesSymbolMin Max Min MaxA 1.050 1.250 0.041 0.049A1 0.000 0.100 0.000 0.004A2 1.050 1.150 0.041 0.045b 0.300 0.500 0.012 0.020c 0.100 0.200 0.004 0.008D 2.820 3.020 0.111 0.119E 1.500 1.700 0.059 0.067E1 2.650 2.950 0.104 0.116e 0.95 (BSC) 0.037 (BSC)e1 1.800 2.000 0.071 0.079L 0.300 0.600 0.012 0.024θ 0° 8° 0° 6°© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page17TSOT-23-5 PACKAGE OUTLINE DIMENSIONSDimensions In Millimeters Dimensions In InchesSymbolMin Max Min MaxA 0.700 0.900 0.028 0.035A1 0.000 0.100 0.000 0.004A2 0.700 0.800 0.028 0.031b 0.350 0.500 0.014 0.020c 0.080 0.200 0.003 0.008D 2.820 3.020 0.111 0.119E 1.600 1.700 0.063 0.067E1 2.650 2.950 0.104 0.116e 0.95 (BSC) 0.037 (BSC)e1 1.90 (BSC) 0.075 (BSC)L 0.300 0.600 0.012 0.024θ 0° 8° 0° 8°© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page18DFN8 PACKAGE OUTLINE DIMENSIONSDimensions In MillimetersSymbolMin Nom Max0.75 0.80A 0.700.02 0.05A1 -0.25 0.03b 0.180.20 0.25c 0.182.00 2.10D 1.90D2 1.50REFe 0.50BSCNd 1.50BSC3.10E 2.903.00E2 1.60REF0.40 0.50L 0.300.25 0.30h 0.20© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page19Fremont Micro Devices (SZ) Limited#5-8, 10/F, Changhong Building, Ke-Ji Nan 12 Road, Nanshan District, ShenzhenTel: (86 755) 86117811Fax: (86 755) 86117810Fremont Micro Devices (Hong Kong) Limited#16, 16/F, Blk B, Veristrong Industrial Centre, 34-36 Au Pui Wan Street, Fotan, Shatin, Hong KongTel: (852) 27811186Fax: (852) 27811144Fremont Micro Devices (USA), Inc.42982 Osgood Road Fremont, CA 94539Tel: (1-510) 668-1321Fax: (1-510) 226-9918Web Site: /* Information furnished is believed to be accurate and reliable. However, Fremont Micro Devices, Incorporated (BVI) assumes no responsibility for the consequences of use of such information or for any infringement of patents of other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent rights of Fremont Micro Devices, Incorporated (BVI). Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. Fremont Micro Devices, Incorporated (BVI) products are not authorized for use as critical components in life support devices or systems without express written approval of Fremont Micro Devices, Incorporated (BVI). The FMD logo is a registered trademark of Fremont Micro Devices, Incorporated (BVI). All other names are the property of their respective owners.© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page20。

FM24C16B-GTR;FM24C16B-G;中文规格书,Datasheet资料

Ordering Information
FM24C16B-G FM24C16B-GTR “Green”/RoHS 8-pin SOIC “Green”/RoHS 8-pin SOIC, Tape & Reel
This product conforms to specifications per the terms of the Ramtron standard warranty. The product has completed Ramtron’s internal qualification testing and has reached production status. Rev. 3.0 Jan. 2012
FM24C16B - 16Kb 5V I2C F-RAM
Counter
Address Latch
256 x 64 FRAM Array
8
SDA
`
Serial to Parallel Converter
Data Latch
SCL WP Control Logic
Figure 1. Block Diagram Pin Description Pin Name SDA Type I/O Pin Description Serial Data Address: This is a bi-directional data pin for the two-wire interface. It employs an open-drain output and is intended to be wire-OR’d with other devices on the two-wire bus. The input buffer incorporates a Schmitt trigger for noise immunity and the output driver includes slope control for falling edges. A pull-up resistor is required. Serial Clock: The serial clock input for the two-wire interface. Data is clocked-out on the falling edge and clocked-in on the rising edge. Write Protect: When WP is igh, the entire array is write-protected. When WP is low, all addresses may be written. This pin is internally pulled down. Supply Voltage (5V) Ground No connect

I2CFLASH--24C16芯片手册

1Features•Low-voltage and Standard-voltage Operation –2.7 (V CC = 2.7V to 5.5V)–1.8 (V CC = 1.8V to 5.5V)•Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K),1024 x 8 (8K) or 2048 x 8 (16K)•Two-wire Serial Interface•Schmitt Trigger, Filtered Inputs for Noise Suppression •Bidirectional Data Transfer Protocol•100 kHz (1.8V) and 400 kHz (2.7V , 5V) Compatibility •Write Protect Pin for Hardware Data Protection•8-byte Page (1K, 2K), 16-byte Page (4K, 8K, 16K) Write Modes •Partial Page Writes Allowed•Self-timed Write Cycle (5 ms max)•High-reliability–Endurance: 1 Million Write Cycles –Data Retention: 100 Years•Automotive Grade and Lead-free/Halogen-free Devices Available •8-lead PDIP , 8-lead JEDEC SOIC, 8-lead MAP , 5-lead SOT23,8-lead TSSOP and 8-ball dBGA2 Packages•Die Sales: Wafer Form, Waffle Pack and Bumped WafersDescriptionThe AT24C01A/02/04/08A/16A provides 1024/2048/4096/8192/16384 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The AT24C01A/02/04/08A/16A is available in space-saving 8-lead PDIP , 8-lead JEDEC SOIC, 8-lead MAP , 5-lead SOT23 (AT24C01A/AT24C02/AT24C04), 8-lead TSSOP , and 8-ball dBGA2 packages and is accessed via a Two-wire serial inter-face. In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V) versions.Table 1. Pin ConfigurationPin Name Function A0 - A2Address Inputs SDA Serial Data SCL Serial Clock Input WP Write Protect NC No Connect GND Ground VCCPower Supply8-lead SOIC8-lead PDIP8-lead MAPBottom View 5-lead SOT238-ball dBGA2Bottom View 8-lead TSSOP2AT24C01A/02/04/08A/16A0180V–SEEPR–8/05Figure 1. Block DiagramAbsolute Maximum RatingsOperating T emperature..................................–55°C to +125°C *NOTICE:Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Storage T emperature.....................................–65°C to +150°C Voltage on Any Pinwith Respect to Ground....................................–1.0V to +7.0V Maximum Operating Voltage ..........................................6.25V DC Output Current........................................................5.0 mA3AT24C01A/02/04/08A/16A0180V–SEEPR–8/05Pin DescriptionSERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open-collector devices.DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are hard wired for the AT24C01A and the AT24C02. As many as eight 1K/2K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section).The AT24C04 uses the A2 and A1 inputs for hard wire addressing and a total of four 4K devices may be addressed on a single bus system. The A0 pin is a no connect.The AT24C08A only uses the A2 input for hardwire addressing and a total of two 8K devices may be addressed on a single bus system. The A0 and A1 pins are no connects.The AT24C16A does not use the device address pins, which limits the number of devices on a single bus to one. The A0, A1 and A2 pins are no connects.WRITE PROTECT (WP): The AT24C01A/02/04/08A/16A has a Write Protect pin that provides hardware data protection. The Write Protect pin allows normal Read/Write operations when connected to ground (GND). When the Write Protect pin is connected to V CC , the write protection feature is enabled and operates as shown in Table 2.Table 2. Write ProtectMemory OrganizationAT24C01A, 1K SERIAL EEPROM: Internally organized with 16 pages of 8 bytes each,the 1K requires a 7-bit data word address for random word addressing.AT24C02, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each,the 2K requires an 8-bit data word address for random word addressing.AT24C04, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each,the 4K requires a 9-bit data word address for random word addressing.AT24C08A, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each,the 8K requires a 10-bit data word address for random word addressing.AT24C16A, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes each, the 16K requires an 11-bit data word address for random word addressing.WP Pin Status Part of the Array Protected24C01A 24C0224C0424C08A 24C16A At V CC Full (1K) ArrayFull (2K) ArrayFull (4K) ArrayFull (8K) ArrayFull (16K) ArrayAt GNDNormal Read/Write Operations4AT24C01A/02/04/08A/16A0180V–SEEPR–8/05Note:1.This parameter is characterized and is not 100% tested.Note:1.V IL min and V IH max are reference only and are not tested.Table 3. Pin Capacitance (1)Applicable over recommended operating range from T A = 25°C, f = 1.0 MHz, V CC = +1.8VSymbol Test ConditionMax Units Conditions C I/O Input/Output Capacitance (SDA)8pF V I/O = 0V C IN Input Capacitance (A 0, A 1, A 2, SCL)6pFV IN = 0VTable 4. DC CharacteristicsApplicable over recommended operating range from: T AI = –40°C to +85°C, V CC = +1.8V to +5.5V, V CC =+1.8V to +5.5V (unless otherwise noted)Symbol Parameter Test ConditionMin TypMax Units V CC1Supply Voltage 1.8 5.5V V CC2Supply Voltage 2.7 5.5V V CC3Supply Voltage4.55.5V I CC Supply Current V CC = 5.0V READ at 100 kHz 0.4 1.0mA I CC Supply Current V CC = 5.0V WRITE at 100 kHz 2.0 3.0mA I SB1Standby Current V CC = 1.8V V IN = V CC or V SS 0.6 3.0µA I SB2Standby Current V CC = 2.5V V IN = V CC or V SS 1.4 4.0µA I SB3Standby Current V CC = 2.7V V IN = V CC or V SS 1.6 4.0µA I SB4Standby Current V CC = 5.0V V IN = V CC or V SS 8.018.0µA I LI Input Leakage Current V IN = V CC or V SS 0.10 3.0µA I LO Output Leakage Current V OUT = V CC or V SS0.05 3.0µA V IL Input Low Level (1)–0.6V CC x 0.3V V IH Input High Level (1)V CC x 0.7V CC + 0.5V V OL2Output Low Level V CC = 3.0V I OL = 2.1 mA 0.4V V OL1Output Low Level V CC = 1.8VI OL = 0.15 mA 0.2V5AT24C01A/02/04/08A/16A0180V–SEEPR–8/05Note:1.This parameter is characterized.Table 5. AC CharacteristicsApplicable over recommended operating range from T AI = –40°C to +85°C, V CC = +1.8V to +5.5V, V CC = +2.7V to +5.5V,CL = 1 TTL Gate and 100pF (unless otherwise noted)Symbol Parameter1.8-volt2.7, 5.0-volt Units MinMax MinMax f SCL Clock Frequency, SCL 100400kHz t LOW Clock Pulse Width Low 4.7 1.2µs t HIGH Clock Pulse Width High 4.00.6µs t I Noise Suppression Time (1)10050ns t AA Clock Low to Data Out Valid 0.1 4.50.10.9µs t BUF Time the bus must be free before a new transmission can start (1) 4.7 1.2µs t HD.ST A Start Hold Time 4.00.6µs t SU.ST A Start Setup Time 4.70.6µs t HD.DA T Data In Hold Time 00µs t SU.DAT Data In Setup Time 200100ns t R Inputs Rise Time (1) 1.00.3µs t F Inputs Fall Time (1)300300ns t SU.STO Stop Setup Time 4.70.6µs t DH Data Out Hold Time 10050ns t WRWrite Cycle Time 55ms Endurance (1) 5.0V , 25°C, Byte Mode1M 1MWrite Cycles6AT24C01A/02/04/08A/16A0180V–SEEPR–8/05Device OperationCLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-nal device. Data on the SDA pin may change only during SCL low time periods (see Figure 4 on page 7). Data changes during SCL high periods will indicate a start or stop condition as defined below.START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 5 on page 8).STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 5 on page 8).ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle.STANDBY MODE: The AT24C01A/02/04/08A/16A features a low-power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations.MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by following these steps:1.Clock up to 9 cycles.2.Look for SDA high in each cycle while SCL is high.3.Create a start condition.7AT24C01A/02/04/08A/16A0180V–SEEPR–8/05Bus TimingFigure 2. SCL: Serial Clock, SDA: Serial Data I/OWrite Cycle TimingFigure 3. SCL: Serial Clock, SDA: Serial Data I/ONote:1.The write cycle time t WR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.Figure 4.Data Validity8AT24C01A/02/04/08A/16A0180V–SEEPR–8/05Figure 5. Start and Stop DefinitionFigure 6.Output Acknowledge9AT24C01A/02/04/08A/16A0180V–SEEPR–8/05Device AddressingThe 1K, 2K, 4K, 8K and 16K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation (refer to Figure 7).The device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. This is common to all the EEPROM devices.The next 3 bits are the A2, A1 and A0 device address bits for the 1K/2K EEPROM.These 3 bits must compare to their corresponding hard-wired input pins.The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a memory page address bit. The two device address bits must compare to their corre-sponding hard-wired input pins. The A0 pin is no connect.The 8K EEPROM only uses the A2 device address bit with the next 2 bits being for memory page addressing. The A2 bit must compare to its corresponding hard-wired input pin. The A1 and A0 pins are no connect.The 16K does not use any device address bits but instead the 3 bits are used for mem-ory page addressing. These page addressing bits on the 4K, 8K and 16K devices should be considered the most significant bits of the data word address which follows.The A0, A1 and A2 pins are no connect.The eighth bit of the device address is the read/write operation select bit. A read opera-tion is initiated if this bit is high and a write operation is initiated if this bit is low.Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the chip will return to a standby state.Write OperationsBYTE WRITE: A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condi-tion. At this time the EEPROM enters an internally timed write cycle, t WR , to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 8 on page 11).PAGE WRITE: The 1K/2K EEPROM is capable of an 8-byte page write, and the 4K, 8K and 16K devices are capable of 16-byte page writes.A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to seven (1K/2K) or fifteen (4K, 8K, 16K) more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 9 on page 11).The data word address lower three (1K/2K) or four (4K, 8K, 16K) bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address,internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than eight (1K/2K) or sixteen (4K, 8K, 16K) data words are transmitted to the EEPROM, the data word address will “roll over” and previ-ous data will be overwritten.10AT24C01A/02/04/08A/16A0180V–SEEPR–8/05ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero allowing the read or write sequence to continue.ReadOperationsRead operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read operations:current address read, random address read and sequential read.CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “roll over” during read is from the last byte of the last memory page to the first byte of the first page.The address “roll over” during write is from the last byte of the current page to the first byte of the same page.Once the device address with the read/write select bit set to one is clocked in and acknowl-edged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but does generate a following stop condi-tion (see Figure 10 on page 12).RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition.The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a fol-lowing stop condition (see Figure 11 on page 12).SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a ran-dom address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequential read will con-tinue. The sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition (see Figure 12 on page 12).11AT24C01A/02/04/08A/16A0180V–SEEPR–8/05Figure 7. Device AddressFigure 8. Byte WriteFigure 9. Page Write(* = DON’T CARE bit for 1K)12AT24C01A/02/04/08A/16A0180V–SEEPR–8/05Figure 10. Current Address ReadFigure 11. Random Read(* = DON’T CARE bit for 1K)Figure 12.Sequential Read13AT24C01A/02/04/08A/16A0180V–SEEPR–8/05Notes:1.For2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table.2.“U” designates Green Package + RoHS compliant.3.Available in waffle pack and wafer form; order as SL719 for wafer form. Bumped die available upon request. Please contactSerial EEPROM Marketing.AT24C01A Ordering Information (1)Ordering Code Package Operation Range A T24C01A-10PI-2.7A T24C01A-10SI-2.7A T24C01A-10TI-2.78P38S18A2Industrial T emperature (–40°C to 85°C)A T24C01A-10PI-1.8A T24C01A-10SI-1.8A T24C01A-10TI-1.88P38S18A2Industrial T emperature (–40°C to 85°C)A T24C01A-10PU-2.7(2)A T24C01A-10PU-1.8(2)A T24C01A-10SU-2.7(2)A T24C01A-10SU-1.8(2)A T24C01A-10TU-2.7(2)A T24C01A-10TU-1.8(2)A T24C01A-10TSU-1.8(2)A T24C01AU3-10UU-1.8(2)A T24C01AY1-10YU-1.8(2)8P38P38S18S18A28A25TS18U318Y1Lead-free/Halogen-free/Industrial T emperature (–40°C to 85°C)A T24C01A-W2.7-11(3)A T24C01A-W1.8-11(3)Die Sale Die SaleIndustrial T emperature (–40°C to 85°C)Package Type8P38-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)8S18-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)8A28-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)8Y18-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)5TS15-lead, 2.90 mm x 1.60 mm Body, Plastic Thin Shrink Small Outline Package (SOT23)8U3-18-ball, die Ball Grid Away Package (dBGA2)Options–2.7Low-voltage (2.7V to 5.5V)–1.8Low-voltage (1.8V to 5.5V)14AT24C01A/02/04/08A/16A0180V–SEEPR–8/05Notes:1.For2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table.2.“U” designates Green Package + RoHS compliant.3.Available in waffle pack and wafer form; order as SL719 for wafer form. Bumped die available upon request. Please contactSerial EEPROM Marketing.AT24C02 Ordering Information (1)Ordering Code Package Operation Range A T24C02-10PI-2.7A T24C02N-10SI-2.7A T24C02-10TI-2.78P38S18A2Industrial Temperature (–40°C to 85°C)A T24C02-10PI-1.8A T24C02N-10SI-1.8A T24C02-10TI-1.88P38S18A2Industrial Temperature (–40°C to 85°C)A T24C02-10PU-2.7(2)A T24C02-10PU-1.8(2)A T24C02N-10SU-2.7(2)A T24C02N-10SU-1.8(2)A T24C02-10TU-2.7(2)A T24C02-10TU-1.8(2)A T24C02Y1-10YU-1.8(2)A T24C02-10TSU-1.8(2)A T24C02U3-10UU-1.8(2)8P38P38S18S18A28A28Y15TS18U3-1Lead-free/Halogen-free/Industrial Temperature (–40°C to 85°C)A T24C02-W2.7-11(3)A T24C02-W1.8-11(3)Die Sale Die SaleIndustrial Temperature (–40°C to 85°C)Package Type8P38-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)8S18-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)8A28-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)8Y18-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)5TS15-lead, 2.90 mm x 1.60 mm Body, Plastic Thin Shrink Small Outline Package (SOT23)8U3-18-ball, die Ball Grid Away Package (dBGA2)Options–2.7Low-voltage (2.7V to 5.5V)–1.8Low-voltage (1.8V to 5.5V)15AT24C01A/02/04/08A/16A0180V–SEEPR–8/05Notes:1.For2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table.2.“U” designates Green Package + RoHS compliant.3.Available in waffle pack and wafer form; order as SL719 for wafer form. Bumped die available upon request. Please contactSerial EEPROM Marketing.AT24C04 Ordering Information (1)Ordering Code Package Operation Range A T24C04-10PI-2.7A T24C04N-10SI-2.7A T24C04-10TI-2.78P38S18A2Industrial T emperature (–40°C to 85°C)A T24C04-10PI-1.8A T24C04N-10SI-1.8A T24C04-10TI-1.88P38S18A2Industrial T emperature (–40°C to 85°C)A T24C04-10PU-2.7(2)A T24C04-10PU-1.8(2)A T24C04N-10SU-2.7(2)A T24C04N-10SU-1.8(2)A T24C04-10TU-2.7(2)A T24C04-10TU-1.8(2)A T24C04Y1-10YU-1.8(2)A T24C04-10TSU-1.8(2)A T24C04U3-10UU-1.8(2)8P38P38S18S18A28A28Y15TS18U3-1Lead-free/Halogen-free/Industrial T emperature (–40°C to 85°C)A T24C04-W2.7-11(3)A T24C04-W1.8-11(3)Die Sale Die SaleIndustrial T emperature (–40°C to 85°C)Package Type8P38-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)8S18-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)8A28-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)8Y18-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)5TS15-lead, 2.90 mm x 1.60 mm Body, Plastic Thin Shrink Small Outline Package (SOT23)8U3-18-ball, die Ball Grid Away Package (dBGA2)Options–2.7Low-voltage (2.7V to 5.5V)–1.8Low-voltage (1.8V to 5.5V)16AT24C01A/02/04/08A/16A0180V–SEEPR–8/05Notes:1.For2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table.2.“U” designates Green Package + RoHS compliant.3.Available in waffle pack and wafer form; order as SL719 for wafer form. Bumped die available upon request. Please contactSerial EEPROM Marketing.AT24C08A Ordering Information (1)Ordering Code PackageOperation Range A T24C08A-10PI-2.7A T24C08AN-10SI-2.7A T24C08A-10TI-2.78P38S18A2Industrial T emperature (–40°C to 85°C)A T24C08A-10PI-1.8A T24C08AN-10SI-1.8A T24C08A-10TI-1.88P38S18A2Industrial T emperature (–40°C to 85°C)A T24C08A-10PU-2.7(2)A T24C08A-10PU-1.8(2)A T24C08AN-10SU-2.7(2)A T24C08AN-10SU-1.8(2)A T24C08A-10TU-2.7(2)A T24C08A-10TU-1.8(2)A T24C08AY1-10YU-1.8(2)A T24C08AY5-10YU-1.8(2)A T24C08AU2-10UU-1.8(28P38P38S18S18A28A28Y18Y58U2-1Lead-free/Halogen-free/Industrial T emperature (−40°C to 85°C)A T24C08A-W2.7-11(3)A T24C08A-W1.8-11(3)Die Sale Die SaleIndustrial T emperature (−40°C to 85°C)Package Type8P38-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP)8S18-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)8A28-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)8Y18-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)8Y58-lead, 2.00 mm x 3.00 mm Body, Dual Footprint, Non-Leaded, Miniature Array Package (MAP)8U2-18-ball, die Ball Grid Array Package (dBGA2)Options−2.7Low Voltage (2.7V to 5.5V)−1.8Low Voltage (1.8V to 5.5V)17AT24C01A/02/04/08A/16A0180V–SEEPR–8/05Notes:1.For2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table.2.“U” designates Green Package + RoHS compliant.3.Available in waffle pack and wafer form; order as SL719 for wafer form. Bumped die available upon request. Please contactSerial EEPROM Marketing.AT24C16A Ordering Information (1)Ordering Code PackageOperation Range A T24C16A-10PI-2.7A T24C16AN-10SI-2.7A T24C16A-10TI-2.78P38S18A2Industrial T emperature (–40°C to 85°C)A T24C16A-10PI-1.8A T24C16AN-10SI-1.8A T24C16A-10TI-1.88P38S18A2Industrial T emperature (–40°C to 85°C)A T24C16A-10PU-2.7(2)A T24C16A-10PU-1.8(2)A T24C16AN-10SU-2.7(2)A T24C16AN-10SU-1.8(2)A T24C16A-10TU-2.7(2)A T24C16A-10TU-1.8(2)A T24C16AY1-10YU-1.8(2)A T24C16AY5-10YU-1.8(2)A T24C16AU2-10UU-1.8(2)8P38P38S18S18A28A28Y18Y58U2-1Lead-free/Halogen-free/Industrial T emperature (−40°C to 85°C)A T24C16A-W2.7-11(3)A T24C16A-W1.8-11(3)Die Sale Die SaleIndustrial T emperature (−40°C to 85°C)Package Type8P38-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP)8S18-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)8A28-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)8Y18-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)8Y58-lead, 2.00 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)8U2-18-ball, die Ball Grid Array Package (dBGA2)Options−2.7Low Voltage (2.7V to 5.5V)−1.8Low Voltage (1.8V to 5.5V)18AT24C01A/02/04/08A/16A0180V–SEEPR–8/05Packaging Information8P3 – PDIP19AT24C01A/02/04/08A/16A0180V–SEEPR–8/058S1 – JEDEC SOIC20AT24C01A/02/04/08A/16A0180V–SEEPR–8/058A2 – TSSOP21AT24C01A/02/04/08A/16A0180V–SEEPR–8/058Y1 – MAP22AT24C01A/02/04/08A/16A0180V–SEEPR–8/055TS1 – SOT2323AT24C01A/02/04/08A/16A0180V–SEEPR–8/058U3-1 – dBGA20180V–SEEPR–8/05Disclaimer: The information in this document is provided in connection with Atmel products. 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IS24C16-2GI中文资料

IS24C01IS24C02IS24C04IS24C08IS24C16ISSI®Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.1K-bit/2K-bit/4K-bit/8K-bit/16K-bit 2-WIRE SERIAL CMOS EEPROMAPRIL 2002DESCRIPTIONThe IS24CXX (refers to IS24C01, IS24C02, IS24C04,IS24C08, IS24C16) family is a low-cost and low voltage 2-wire Serial EEPROM. It is fabricated using ISSI’s advanced CMOS EEPROM technology and provides a low power and low voltage operation. The IS24CXX family features a write protection feature, and is available in 8-pin DIP and 8-pin SOIC packages.The IS24C01 is a 1K-bit EEPROM; IS24C02 is a 2K-bit EEPROM; IS24C04 is a 4K-bit EEPROM; IS24C08 is a 8K-bit EEPROM; IS24C16 is a 16K-bit EEPROM.The IS24C01 and IS24C02 are available in 8-pin MSOP package. The IS24C01, IS24C02, IS24C04, and IS24C08are available in 8-Pin TSSOP package.Automotive data is preliminary.FEATURES•Low Power CMOS Technology–Standby Current less than 8 µA (5.5V)–Read Current (typical) less than 1 mA (5.5V)–Write Current (typical) less than 3 mA (5.5V)•Flexible Voltage Operation–Vcc = 1.8V to 5.5V for –2 version –Vcc = 2.5V to 5.5V for –3 version •400 KHz (I 2C Protocol) Compatibility •Hardware Data Protection–Write Protect Pin •Sequential Read Feature•Filtered Inputs for Noise Suppression •8-pin PDIP and 8-pin SOIC packages •8-pin TSSOP (1K,2K, 4K & 8K only)•8-pin MSOP (1K,2K only)•Self time write cycle with auto clear 5 ms @ 2.5V •Organization:–IS24C01128x8(one block of 128 bytes)–IS24C02256x8(one block of 256 bytes)–IS24C04512x8(two blocks of 256 bytes)–IS24C081024x8(four blocks of 256 bytes)–IS24C162048x8(eight blocks of 256 bytes)•Page Write Buffer•Two-Wire Serial Interface–Bi-directional data transfer protocol •High Reliability–Endurance: 1,000,000 Cycles –Data Retention: 100 Years•Commercial, Industrial and Automotive tempera-ture ranges元器件交易网元器件交易网IS24C01IS24C02IS24C04IS24C08 IS24C16ISSI®FUNCTIONAL BLOCK DIAGRAM2Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.DIS24C01IS24C02IS24C04IS24C08 IS24C16ISSI®PIN DESCRIPTIONSA0-A2Address InputsSDA Serial Address/Data I/O SCL Serial Clock Input WP Write Protect Input Vcc Power Supply GNDGroundSCLThis input clock pin is used to synchronize the data transfer to and from the device.SDAThe SDA is a Bi-directional pin used to transfer addresses and data into and out of the device. The SDA pin is an open drain output and can be wire-Ored with other open drain or open collector outputs.The SDA bus requires a pullup resistor to Vcc.A0, A1, A2The A0, A1 and A2 are the device address inputs. The IS24C01 and IS24C02 use the A0, A1, and A2 for hardware addressing and a total of 8 devices may be used on a single bus system.PIN CONFIGURATION8-Pin DIP and SOIC8 Pin TSSOP (1K, 2K, 4K and 8K)8-Pin MSOP (1K, 2K)12348765A0A1A2GNDVCC WP SCL SDAThe IS24C04 uses A1 and A2 pins for hardwire addressing and a total of four devices may be addressed on a single bus system.The A0 pin is not used by IS24C04. This pin can be left floating or tied to GND or Vcc.The IS24C08 only use A2 input for hardwire addressing and a total of two devices may be addressed on a single bus system.The A0 and A1 pins are not used by IS24C08. They may be left floating or tied to either GND or Vcc.These pins are not used by IS24C16. A0 and A1 may be left floating or tied to either GND or Vcc. A2 should be tied to either GND or Vcc.WPWP is the Write Protect pin. On the 24C01, 24C02, IS24C04and 24C08, if the WP pin is tied to V CC the entire array becomes Write Protected (Read only). On the 24C16, if the WP pin is tied to Vcc the upper half array becomes Write Protected (Read only). When WP is tied to GND or left floating normal read/write operations are allowed to the device.元器件交易网IS24C01IS24C02IS24C04IS24C08 IS24C16ISSI®DEVICE OPERATIONThe IS24CXX family features a serial communication and supports a bi-directional 2-wire bus transmission protocol. 2-WIRE BUSThe two-wire bus is defined as a Serial Data line(SDA), and a Serial Clock Line (SCL). The protocol defines any device that sends data onto the SDA bus as a transmitter, and the receiving devices as a receiver. The bus is controlled by MASTER device which generates the SCL, controls the bus access and generates the STOP and START conditions. The IS24CXX is the SLAVE device on the bus.THE BUS PROTOCOL:--Data transfer may be initiated only when the bus is not busy--During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition.The state of the data line represents valid data when after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition.START CONDITIONThe START condition precedes all commands to the devices and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The IS24CXX monitors the SDA and SCL lines and will not respond until the START condition is met.STOP CONDITIONThe STOP condition is defined as a LOW to HIGH transition of SDA when SCL is HIGH. All operations must end with a STOP condition.ACKNOWLEDGEAfter a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledging device pulls down the SDA line.DEVICE ADDRESSINGThe MASTER begins a transmission by sending a START condition. The MASTER then sends the address of the particular slave devices it is requesting. The SLAVE address is 8 bytes.The four most significant bytes of the address are fixed as 1010 for the IS24CXX.For the IS24C16, the bytes(B2, B1 and B0) are used for memory page addressing (the IS24C16 is organized as eight blocks of 256 bytes).For the IS24C04 out of the next three bytes, B0 is for Memory Page Addressing (the IS24C04 is organized as two blocks of 256 bytes) and A2 and A1 bytes are used as device address bytes and must compare to its hard-wire inputs pins (A2 and A1). Up to four IS24C04's may be individually addressed by the system. The page addressing bytes for IS24Cxx should be considered the most significant bytes of the data word address which follows.For the IS24C08 out of the next three bytes, B1 and B0 are for memory page addressing (the IS24C08 is organized as four blocks of 256 bytes) and the A2 bit is used as device address bit and must compare to its hard-wired input pin (A2). Up to two IS24C08 may be individually addressed by the system. The page addressing bytes for IS24CXX should be considered the most significant bytes of the data word address which follows.For the IS24C01 and IS24C02, the A0, A1, and A2 are used as device address bytes and must compare to its hard-wired input pins (A0, A1, and A2) Up to Eight IS24C01 and/ or IS24C02's may be individually addressed by the system. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected.After the MASTER sends a START condition and the SLAVE address byte, the IS24CXX monitors the bus and responds with an Acknowledge (on the SDA line) when its address matches the transmitted slave address. The IS24CXX pulls down the SDA line during the ninth clock cycle, signaling that it received the eight bytes of data. The IS24CXX then performs a Read or Write operation depending on the state of the R/W bit.WRITE OPERATIONBYTE WRITEIn the Byte Write mode, the Master device sends the START condition and the slave address information(with the R/W set to Zero) to the Slave device. After the Slave generates an acknowledge, the Master sends the byte address that is to be written into the address pointer of the IS24CXX. After receiving another acknowledge from the Slave, the Master device transmits the data byte to be written into the address memory location. The IS24CXX acknowledges once more and the Master generates the STOP condition, at which time the device begins its internal programming cycle. While this internal cycle is in progress, the device will not respond to any request from the Master device.元器件交易网4Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.DIS24C01IS24C02IS24C04IS24C08 IS24C16ISSI®condition and the IS24CXX discontinues transmission. If 'n' is the last byte of the memory, then the data from location '0' will be transmitted. (Refer to Current Address Read Diagram.)RANDOM ADDRESS READSelective READ operations allow the Master device to select at random any memory location for a READ operation.The Master device first performs a 'dummy' write operation by sending the START condition, slave address and word address of the location it wishes to read. After the IS24CXX acknowledge the word address, the Master device resends the START condition and the slave address, this time with the R/W bit set to one. The IS24CXX then responds with its acknowledge and sends the data requested. The master device does not send an acknowledge but will generate a STOP condition. (Refer to Random Address Read Diagram.)SEQUENTIAL READSequential Reads can be initiated as either a Current Address Read or Random Address Read. After the IS24CXX sends initial byte sequence, the master device now responds with an ACKnowledge indicating it requires additional data from the IS24CXX. The IS24CXX continues to output data for each ACKnowledge received. The master device terminates the sequential READ operation by pulling SDA HIGH (no ACKnowledge) indicating the last data word to be read, followed by a STOP condition.The data output is sequential, with the data from address n followed by the data from address n+1, ... etc.The address counter increments by one automatically,allowing the entire memory contents to be serially read during sequential read operation. When the memory address boundary (127 for IS24C01; 255 for IS24C02; 511 for IS24C04; 1023 for IS24C08; 2047 for IS24C16) is reached,the address counter “rolls over” to address 0, and the IS24CXX continues to output data for each ACKnowledge received. (Refer to Sequential Read Operation Starting with a Random Address READ Diagram.)PAGE WRITEThe IS24CXX is capable of page-WRITE (8-byte for 24C01/02 and 16-byte for 24C04/08/16) operation. A page-WRITE is initiated in the same manner as a byte write, but instead of terminating the internal write cycle after the first data word is transferred, the master device can transmit up to N more bytes (N=7 for 24C01/02 and N=15 for 24C04/08/16). After the receipt of each data word, the IS24CXX responds immediately with an ACKnowledge on SDA line, and the three lower (24C01/24C02) or four lower (24C04/24C08/24C16) order data word address bits are internally incremented by one, while the higher order bits of the data word address remain constant. If the master device should transmit more than N+1 (N=7 for 24C01/02 and N=15 for 24C04/08/16) words, prior to issuing the STOP condition,the address counter will “roll over,” and the previously written data will be overwritten. Once all N+1 (N=7 for 24C01/02 and N=15 for 24C04/08/16) bytes are received and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the IS24CXX in a single write cycle. All inputs are disabled until completion of the internal WRITE cycle.ACKNOWLEDGE POLLINGThe disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host's write operation, the IS24CXX initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation.If the IS24CXX is still busy with the write operation, no ACK will be returned. If the IS24CXX has completed the write operation, an ACK will be returned and the host can then proceed with the next read or write operation.READ OPERATIONREAD operations are initiated in the same manner as WRITE operations, except that the read/write bit of the slave address is set to “1”. There are three READ operation options: current address read, random address read and sequential read.CURRENT ADDRESS READThe IS24CXX contains an internal address counter which maintains the address of the last byte accessed, incremented by one. For example, if the previous operation is either a read or write operation addressed to the address location n,the internal address counter would increment to address location n+1. When the IS24CXX receives the Device Addressing Byte with a READ operation (read/write bit set to “1”), it will respond an ACKnowledge and transmit the 8-bit data word stored at address location n+1. The master will not acknowledge the transfer but does generate a STOP元器件交易网元器件交易网IS24C01IS24C02IS24C04IS24C08 IS24C16ISSI®TYPICAL SYSTEM BUS CONFIGURATIONSTART AND STOP CONDITIONS6Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.D元器件交易网IS24C01IS24C02IS24C04IS24C08 IS24C16ISSI®DATA VALIDITY PROTOCOL元器件交易网IS24C01IS24C02IS24C04IS24C08 IS24C16ISSI®PAGE WRITE8Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.D元器件交易网IS24C01IS24C02IS24C04IS24C08 IS24C16ISSI®SEQUENTIAL READ元器件交易网IS24C01IS24C02IS24C04IS24C08 IS24C16ISSI®ABSOLUTE MAXIMUM RATINGS(1)Symbol Parameter Value UnitV S Supply Voltage0.5 to +6.25VV P Voltage on Any Pin–0.5 to Vcc + 0.5VT BIAS Temperature Under Bias–40 to +85°CT STG Storage Temperature–65 to +150°CI OUT Output Current5mANotes:1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may causepermanent damage to the device. This is a stress rating only and functional operation of thedevice at these or any other conditions above those indicated in the operational sections ofthis specification is not implied. Exposure to absolute maximum rating conditions forextended periods may affect reliability.OPERATING RANGE(IS24C01-2, IS24C02-2, IS24C04-2 IS24C08-2, & IS24C16-2)Range Ambient Temperature V CCCommercial0°C to +70°C 1.8V to 5.5VIndustrial–40°C to +85°C 1.8V to 5.5VOPERATING RANGE(IS24C01-3, IS24C02-3, IS24C04-3, IS24C08-3, & IS24C16-3)Range Ambient Temperature V CCCommercial0°C to +70°C 2.5V to 5.5VIndustrial–40°C to +85°C 2.5V to 5.5VAutomotive–40°C to +125°C 2.7V to 5.5VNote: Automotive data is preliminary.OPERATING RANGE(IS24C01-5, IS24C02-5, IS24C04-5 IS24C08-5, & IS24C16-5)Range Ambient Temperature V CCAuromotive–40°C to +125°C 4.5V to 5.5VNote: Automotive data is preliminary.10Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.DDC ELECTRICAL CHARACTERISTICSSymbol Parameter Test Conditions Min.Max.Unit V OL1Output LOW Voltage V CC = 1.8V, I OL = 0.15 mA—0.2V V OL2Output LOW Voltage V CC = 2.5V, I OL = 1.0 mA—0.4V V IH Input HIGH Voltage V CC X 0.7V CC + 0.5V V IL Input LOW Voltage–1.0V CC X 0.3VI LI Input Leakage Current V IN = V CC max.—3µAI LO Output Leakage Current—3µA Notes: V IL min and V IH max are reference only and are not tested.POWER SUPPLY CHARACTERISTICSSymbol Parameter Test Conditions Min.Max.UnitI CC1Vcc Operating Current READ at 100 KHz (Vcc = 5V)— 1.0mAI CC2Vcc Operating Current WRITE at 100 KHz (Vcc = 5V)— 3.0mAI SB1Standby Current Vcc = 1.8V— 4.0µAI SB2Standby Current Vcc = 5.5V—8.0µACAPACITANCE(1,2)Symbol Parameter Conditions Max.UnitC IN Input Capacitance V IN = 0V6pFC OUT Output Capacitance V OUT = 0V8pFNotes:1.Tested initially and after any design or process changes that may affect these parameters.2.Test conditions: T A = 25°C, f = 1 MHz, Vcc = 5.0V.12Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.D AC ELECTRICAL CHARACTERISTICS (Over Operating Range)Automotive (T A = –40°C to +125°C) 2.7V-5.5V 4.5V-5.5V Symbol Parameter Test ConditionsMin.Max.Min.Max.Unit f SCL SCL Clock Frequency 01000400KHz T Noise Suppression Time (1)—100—50ns t LOW Clock LOW Period 4.7— 1.2—µs t HIGH Clock HIGH Period4—0.6—µs t BUF Bus Free Time Before New Transmission 4.7— 1.2—µs t SU:STA Start Condition Setup Time 4.7—0.6—µs t SU:STO Stop Condition Setup Time 4.7—0.6—µs t HD:STA Start Condition Hold Time 4—0.6—µs t HD:STO Stop Condition Hold Time 4—0.6—µs t SU:DAT Data In Setup Time 200—100—ns t HD:DAT Data In Hold Time 0—0—ns t DH Data Out Hold Time SCL LOW to SDA Data Out Change 100—50—ns t AA Clock to Output SCL LOW to SDA Data Out Valid0.1 4.50.10.9µs t R SCL and SDA Rise Time(1)—1000—300ns t F SCL and SDA Fall Time (1)—300—300ns t WRWrite Cycle Time—10—10msNote:1. This parameter is characterized but not 100% tested.2. Automotive data is preliminary.AC ELECTRICAL CHARACTERISTICS (Over Operating Rnage)Commercial (T A = 0°C to +70°C) Industrial (T A = –40°C to +85°C) 1.8V-5.5V 2.5V-5.5V Symbol Parameter Test ConditionsMin.Max.Min.Max.Unit f SCL SCL Clock Frequency 01000400KHz T Noise Suppression Time (1)—100—50ns t LOW Clock LOW Period 4.7— 1.2—µs t HIGH Clock HIGH Period4—0.6—µs t BUF Bus Free Time Before New Transmission (1) 4.7— 1.2—µs t SU:STA Start Condition Setup Time 4.7—0.6—µs t SU:STO Stop Condition Setup Time 4.7—0.6—µs t HD:STA Start Condition Hold Time 4—0.6—µs t HD:STO Stop Condition Hold Time 4—0.6—µs t SU:DAT Data In Setup Time 200—100—ns t HD:DAT Data In Hold Time 0—0—ns t DH Data Out Hold Time SCL LOW to SDA Data Out Change 100—50—ns t AA Clock to Output SCL LOW to SDA Data Out Valid 0.1 4.50.10.9µs t R SCL and SDA Rise Time (1)—1000—300ns t F SCL and SDA Fall Time (1)—300—300ns t WRWrite Cycle Time—10—5msNote:1. This parameter is characterized but not 100% tested.AC WAVEFORMS BUS TIMINGWRITE CYCLE TIMINGORDERING INFORMATIONCommercial Range: 0°C to +70°CVol tageFrequency Range Part Number Package100 KHz 1.8V IS24C01-2P300-mil Plastic DIPto 5.5V IS24C01-2G Small Outline (JEDEC STD)IS24C01-2S MSOPIS24C01-2Z TSSOP100 KHz 1.8V IS24C02-2P300-mil Plastic DIPto 5.5V IS24C02-2G Small Outline (JEDEC STD)IS24C02-2S MSOPIS24C02-2Z TSSOP100 KHz 1.8V IS24C04-2P300-mil Plastic DIPto 5.5V IS24C04-2G Small Outline (JEDEC STD)IS24C04-2Z TSSOP100 KHz 1.8V IS24C08-2P300-mil Plastic DIPto 5.5V IS24C08-2G Small Outline (JEDEC STD)IS24C08-2Z TSSOP100 KHz 1.8V IS24C16-2P300-mil Plastic DIPto 5.5V IS24C16-2G Small Outline (JEDEC STD)400 KHz 2.5V IS24C01-3P300-mil Plastic DIPto 5.5V IS24C01-3G Small Outline (JEDEC STD)IS24C01-3S MSOPIS24C01-3Z TSSOP400 KHz 2.5V IS24C02-3P300-mil Plastic DIPto 5.5V IS24C02-3G Small Outline (JEDEC STD)IS24C02-3S MSOPIS24C02-3Z TSSOP400 KHz 2.5V IS24C04-3P300-mil Plastic DIPto 5.5V IS24C04-3G Small Outline (JEDEC STD)IS24C04-3Z TSSOP400 KHz 2.5V IS24C08-3P300-mil Plastic DIPto 5.5V IS24C08-3G Small Outline (JEDEC STD)IS24C08-3Z TSSOP400 KHz 2.5V IS24C16-3P300-mil Plastic DIPto 5.5V IS24C16-3G Small Outline (JEDEC STD)14Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.DORDERING INFORMATIONIndustrial Range: –40°C to +85°CVoltageFrequency Range Part Number Package100 KHz 1.8V IS24C01-2PI300-mil Plastic DIPto 5.5V IS24C01-2GI Small Outline (JEDEC STD)IS24C01-2SI MSOPIS24C01-2ZI TSSOP100 KHz 1.8V IS24C02-2PI300-mil Plastic DIPto 5.5V IS24C02-2GI Small Outline (JEDEC STD)IS24C02-2SI MSOPIS24C02-2ZI TSSOP100 KHz 1.8V IS24C04-2PI300-mil Plastic DIPto 5.5V IS24C04-2GI Small Outline (JEDEC STD)IS24C04-2ZI TSSOP100 KHz 1.8V IS24C08-2PI300-mil Plastic DIPto 5.5V IS24C08-2GI Small Outline (JEDEC STD)IS24C08-2ZI TSSOP100 KHz 1.8V IS24C16-2PI300-mil Plastic DIPto 5.5V IS24C16-2GI Small Outline (JEDEC STD) 400 KHz 2.5V IS24C01-3PI300-mil Plastic DIPto 5.5V IS24C01-3GI Small Outline (JEDEC STD)IS24C01-3SI MSOPIS24C01-3ZI TSSOP400 KHz 2.5V IS24C02-3PI300-mil Plastic DIPto 5.5V IS24C02-3GI Small Outline (JEDEC STD)IS24C02-3SI MSOPIS24C02-3ZI TSSOP400 KHz 2.5V IS24C04-3PI300-mil Plastic DIPto 5.5V IS24C04-3GI Small Outline (JEDEC STD)IS24C04-3ZI TSSOP400 KHz 2.5V IS24C08-3PI300-mil Plastic DIPto 5.5V IS24C08-3GI Small Outline (JEDEC STD)IS24C08-3ZI TSSOP400 KHz 2.5V IS24C16-3PI300-mil Plastic DIPto 5.5V IS24C16-3GI Small Outline (JEDEC STD)ORDERING INFORMATIONAutomotive Range: –40°C to +125°CVoltageFrequency Range Part Number Package100 KHz 2.7V IS24C01-3PA300-mil Plastic DIPto 5.5V IS24C01-3GA Small Outline (JEDEC STD)IS24C01-3SA MSOPIS24C01-3ZA TSSOP100 KHz 2.7V IS24C02-3PA300-mil Plastic DIPto 5.5V IS24C02-3GA Small Outline (JEDEC STD)IS24C02-3SA MSOPIS24C02-3ZA TSSOP100 KHz 2.7V IS24C04-3PA300-mil Plastic DIPto 5.5V IS24C04-3GA Small Outline (JEDEC STD)IS24C04-3ZA TSSOP100 KHz 2.7V IS24C08-3PA300-mil Plastic DIPto 5.5V IS24C08-3GA Small Outline (JEDEC STD)IS24C08-3ZA TSSOP100 KHz 2.7V IS24C16-3PA300-mil Plastic DIPto 5.5V IS24C16-3GA Small Outline (JEDEC STD)400 KHz 4.5V IS24C01-5PA300-mil Plastic DIPto 5.5V IS24C01-5GA Small Outline (JEDEC STD)IS24C01-5SA MSOPIS24C01-5ZA TSSOP400 KHz 4.5V IS24C02-5PA300-mil Plastic DIPto 5.5V IS24C02-5GA Small Outline (JEDEC STD)IS24C02-5SA MSOPIS24C02-5ZA TSSOP400 KHz 4.5V IS24C04-5PA300-mil Plastic DIPto 5.5V IS24C04-5GA Small Outline (JEDEC STD)IS24C04-5ZA TSSOP400 KHz 4.5V IS24C08-5PA300-mil Plastic DIPto 5.5V IS24C08-5GA Small Outline (JEDEC STD)IS24C08-5ZA TSSOP400 KHz 4.5V IS24C16-5PA300-mil Plastic DIPto 5.5V IS24C16-5GA Small Outline (JEDEC STD)Note: Automotive data is preliminary.16Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.D。

FM24C16中文资料

Interface
24 FM
3
FM24C16U/17U Rev. A.3

元器件交易网
FM24C16U/17U – 16K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Product Specifications Absolute Maximum Ratings
Connection Diagrams
Dual-in-Line Package (N) and SO Package (M8)
NC NC NC VSS 1 2 8 7 VCC NC SCL SDA
TSSOP Package (MT8)
NC VCC NC NC 1 2 8 7 SCL SDA VSS NC
Temp. Range
Voltage Operating Range
Blank T SCL Clock Frequency Blank F U
Process
Density
16 17 C
16K 16K with Write Protect CMOS Technology IIC Fairchild Non-Volatile Memory
Dual-in-Line Package (N) and SO Package (M8)
NC NC NC VSS 1 2 8 7 VCC WP SCL SDA
TSSOP Package (MT8)
WP VCC NC NC 1 2 8 7 SCL SDA VSS NC
24C17
3 4 6 5 3 4
24C17
Block Diagram
VCC VSS WP H.V. GENERATION TIMING &CONTROL START STOP LOGIC CONTROL LOGIC SLAVE ADDRESS REGISTER E2PROM ARRAY

I2CFLASH--24C16芯片手册

1Features•Low-voltage and Standard-voltage Operation –2.7 (V CC = 2.7V to 5.5V)–1.8 (V CC = 1.8V to 5.5V)•Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K),1024 x 8 (8K) or 2048 x 8 (16K)•Two-wire Serial Interface•Schmitt Trigger, Filtered Inputs for Noise Suppression •Bidirectional Data Transfer Protocol•100 kHz (1.8V) and 400 kHz (2.7V , 5V) Compatibility •Write Protect Pin for Hardware Data Protection•8-byte Page (1K, 2K), 16-byte Page (4K, 8K, 16K) Write Modes •Partial Page Writes Allowed•Self-timed Write Cycle (5 ms max)•High-reliability–Endurance: 1 Million Write Cycles –Data Retention: 100 Years•Automotive Grade and Lead-free/Halogen-free Devices Available •8-lead PDIP , 8-lead JEDEC SOIC, 8-lead MAP , 5-lead SOT23,8-lead TSSOP and 8-ball dBGA2 Packages•Die Sales: Wafer Form, Waffle Pack and Bumped WafersDescriptionThe AT24C01A/02/04/08A/16A provides 1024/2048/4096/8192/16384 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The AT24C01A/02/04/08A/16A is available in space-saving 8-lead PDIP , 8-lead JEDEC SOIC, 8-lead MAP , 5-lead SOT23 (AT24C01A/AT24C02/AT24C04), 8-lead TSSOP , and 8-ball dBGA2 packages and is accessed via a Two-wire serial inter-face. In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V) versions.Table 1. Pin ConfigurationPin Name Function A0 - A2Address Inputs SDA Serial Data SCL Serial Clock Input WP Write Protect NC No Connect GND Ground VCCPower Supply8-lead SOIC8-lead PDIP8-lead MAPBottom View 5-lead SOT238-ball dBGA2Bottom View 8-lead TSSOP2AT24C01A/02/04/08A/16A0180V–SEEPR–8/05Figure 1. Block DiagramAbsolute Maximum RatingsOperating T emperature..................................–55°C to +125°C *NOTICE:Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Storage T emperature.....................................–65°C to +150°C Voltage on Any Pinwith Respect to Ground....................................–1.0V to +7.0V Maximum Operating Voltage ..........................................6.25V DC Output Current........................................................5.0 mA3AT24C01A/02/04/08A/16A0180V–SEEPR–8/05Pin DescriptionSERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open-collector devices.DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are hard wired for the AT24C01A and the AT24C02. As many as eight 1K/2K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section).The AT24C04 uses the A2 and A1 inputs for hard wire addressing and a total of four 4K devices may be addressed on a single bus system. The A0 pin is a no connect.The AT24C08A only uses the A2 input for hardwire addressing and a total of two 8K devices may be addressed on a single bus system. The A0 and A1 pins are no connects.The AT24C16A does not use the device address pins, which limits the number of devices on a single bus to one. The A0, A1 and A2 pins are no connects.WRITE PROTECT (WP): The AT24C01A/02/04/08A/16A has a Write Protect pin that provides hardware data protection. The Write Protect pin allows normal Read/Write operations when connected to ground (GND). When the Write Protect pin is connected to V CC , the write protection feature is enabled and operates as shown in Table 2.Table 2. Write ProtectMemory OrganizationAT24C01A, 1K SERIAL EEPROM: Internally organized with 16 pages of 8 bytes each,the 1K requires a 7-bit data word address for random word addressing.AT24C02, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each,the 2K requires an 8-bit data word address for random word addressing.AT24C04, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each,the 4K requires a 9-bit data word address for random word addressing.AT24C08A, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each,the 8K requires a 10-bit data word address for random word addressing.AT24C16A, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes each, the 16K requires an 11-bit data word address for random word addressing.WP Pin Status Part of the Array Protected24C01A 24C0224C0424C08A 24C16A At V CC Full (1K) ArrayFull (2K) ArrayFull (4K) ArrayFull (8K) ArrayFull (16K) ArrayAt GNDNormal Read/Write Operations4AT24C01A/02/04/08A/16A0180V–SEEPR–8/05Note:1.This parameter is characterized and is not 100% tested.Note:1.V IL min and V IH max are reference only and are not tested.Table 3. Pin Capacitance (1)Applicable over recommended operating range from T A = 25°C, f = 1.0 MHz, V CC = +1.8VSymbol Test ConditionMax Units Conditions C I/O Input/Output Capacitance (SDA)8pF V I/O = 0V C IN Input Capacitance (A 0, A 1, A 2, SCL)6pFV IN = 0VTable 4. DC CharacteristicsApplicable over recommended operating range from: T AI = –40°C to +85°C, V CC = +1.8V to +5.5V, V CC =+1.8V to +5.5V (unless otherwise noted)Symbol Parameter Test ConditionMin TypMax Units V CC1Supply Voltage 1.8 5.5V V CC2Supply Voltage 2.7 5.5V V CC3Supply Voltage4.55.5V I CC Supply Current V CC = 5.0V READ at 100 kHz 0.4 1.0mA I CC Supply Current V CC = 5.0V WRITE at 100 kHz 2.0 3.0mA I SB1Standby Current V CC = 1.8V V IN = V CC or V SS 0.6 3.0µA I SB2Standby Current V CC = 2.5V V IN = V CC or V SS 1.4 4.0µA I SB3Standby Current V CC = 2.7V V IN = V CC or V SS 1.6 4.0µA I SB4Standby Current V CC = 5.0V V IN = V CC or V SS 8.018.0µA I LI Input Leakage Current V IN = V CC or V SS 0.10 3.0µA I LO Output Leakage Current V OUT = V CC or V SS0.05 3.0µA V IL Input Low Level (1)–0.6V CC x 0.3V V IH Input High Level (1)V CC x 0.7V CC + 0.5V V OL2Output Low Level V CC = 3.0V I OL = 2.1 mA 0.4V V OL1Output Low Level V CC = 1.8VI OL = 0.15 mA 0.2V5AT24C01A/02/04/08A/16A0180V–SEEPR–8/05Note:1.This parameter is characterized.Table 5. AC CharacteristicsApplicable over recommended operating range from T AI = –40°C to +85°C, V CC = +1.8V to +5.5V, V CC = +2.7V to +5.5V,CL = 1 TTL Gate and 100pF (unless otherwise noted)Symbol Parameter1.8-volt2.7, 5.0-volt Units MinMax MinMax f SCL Clock Frequency, SCL 100400kHz t LOW Clock Pulse Width Low 4.7 1.2µs t HIGH Clock Pulse Width High 4.00.6µs t I Noise Suppression Time (1)10050ns t AA Clock Low to Data Out Valid 0.1 4.50.10.9µs t BUF Time the bus must be free before a new transmission can start (1) 4.7 1.2µs t HD.ST A Start Hold Time 4.00.6µs t SU.ST A Start Setup Time 4.70.6µs t HD.DA T Data In Hold Time 00µs t SU.DAT Data In Setup Time 200100ns t R Inputs Rise Time (1) 1.00.3µs t F Inputs Fall Time (1)300300ns t SU.STO Stop Setup Time 4.70.6µs t DH Data Out Hold Time 10050ns t WRWrite Cycle Time 55ms Endurance (1) 5.0V , 25°C, Byte Mode1M 1MWrite Cycles6AT24C01A/02/04/08A/16A0180V–SEEPR–8/05Device OperationCLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-nal device. Data on the SDA pin may change only during SCL low time periods (see Figure 4 on page 7). Data changes during SCL high periods will indicate a start or stop condition as defined below.START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 5 on page 8).STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 5 on page 8).ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle.STANDBY MODE: The AT24C01A/02/04/08A/16A features a low-power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations.MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by following these steps:1.Clock up to 9 cycles.2.Look for SDA high in each cycle while SCL is high.3.Create a start condition.7AT24C01A/02/04/08A/16A0180V–SEEPR–8/05Bus TimingFigure 2. SCL: Serial Clock, SDA: Serial Data I/OWrite Cycle TimingFigure 3. SCL: Serial Clock, SDA: Serial Data I/ONote:1.The write cycle time t WR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.Figure 4.Data Validity8AT24C01A/02/04/08A/16A0180V–SEEPR–8/05Figure 5. Start and Stop DefinitionFigure 6.Output Acknowledge9AT24C01A/02/04/08A/16A0180V–SEEPR–8/05Device AddressingThe 1K, 2K, 4K, 8K and 16K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation (refer to Figure 7).The device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. This is common to all the EEPROM devices.The next 3 bits are the A2, A1 and A0 device address bits for the 1K/2K EEPROM.These 3 bits must compare to their corresponding hard-wired input pins.The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a memory page address bit. The two device address bits must compare to their corre-sponding hard-wired input pins. The A0 pin is no connect.The 8K EEPROM only uses the A2 device address bit with the next 2 bits being for memory page addressing. The A2 bit must compare to its corresponding hard-wired input pin. The A1 and A0 pins are no connect.The 16K does not use any device address bits but instead the 3 bits are used for mem-ory page addressing. These page addressing bits on the 4K, 8K and 16K devices should be considered the most significant bits of the data word address which follows.The A0, A1 and A2 pins are no connect.The eighth bit of the device address is the read/write operation select bit. A read opera-tion is initiated if this bit is high and a write operation is initiated if this bit is low.Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the chip will return to a standby state.Write OperationsBYTE WRITE: A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condi-tion. At this time the EEPROM enters an internally timed write cycle, t WR , to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 8 on page 11).PAGE WRITE: The 1K/2K EEPROM is capable of an 8-byte page write, and the 4K, 8K and 16K devices are capable of 16-byte page writes.A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to seven (1K/2K) or fifteen (4K, 8K, 16K) more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 9 on page 11).The data word address lower three (1K/2K) or four (4K, 8K, 16K) bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address,internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than eight (1K/2K) or sixteen (4K, 8K, 16K) data words are transmitted to the EEPROM, the data word address will “roll over” and previ-ous data will be overwritten.10AT24C01A/02/04/08A/16A0180V–SEEPR–8/05ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero allowing the read or write sequence to continue.ReadOperationsRead operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read operations:current address read, random address read and sequential read.CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “roll over” during read is from the last byte of the last memory page to the first byte of the first page.The address “roll over” during write is from the last byte of the current page to the first byte of the same page.Once the device address with the read/write select bit set to one is clocked in and acknowl-edged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but does generate a following stop condi-tion (see Figure 10 on page 12).RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition.The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a fol-lowing stop condition (see Figure 11 on page 12).SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a ran-dom address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequential read will con-tinue. The sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition (see Figure 12 on page 12).11AT24C01A/02/04/08A/16A0180V–SEEPR–8/05Figure 7. Device AddressFigure 8. Byte WriteFigure 9. Page Write(* = DON’T CARE bit for 1K)12AT24C01A/02/04/08A/16A0180V–SEEPR–8/05Figure 10. Current Address ReadFigure 11. Random Read(* = DON’T CARE bit for 1K)Figure 12.Sequential Read13AT24C01A/02/04/08A/16A0180V–SEEPR–8/05Notes:1.For2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table.2.“U” designates Green Package + RoHS compliant.3.Available in waffle pack and wafer form; order as SL719 for wafer form. Bumped die available upon request. Please contactSerial EEPROM Marketing.AT24C01A Ordering Information (1)Ordering Code Package Operation Range A T24C01A-10PI-2.7A T24C01A-10SI-2.7A T24C01A-10TI-2.78P38S18A2Industrial T emperature (–40°C to 85°C)A T24C01A-10PI-1.8A T24C01A-10SI-1.8A T24C01A-10TI-1.88P38S18A2Industrial T emperature (–40°C to 85°C)A T24C01A-10PU-2.7(2)A T24C01A-10PU-1.8(2)A T24C01A-10SU-2.7(2)A T24C01A-10SU-1.8(2)A T24C01A-10TU-2.7(2)A T24C01A-10TU-1.8(2)A T24C01A-10TSU-1.8(2)A T24C01AU3-10UU-1.8(2)A T24C01AY1-10YU-1.8(2)8P38P38S18S18A28A25TS18U318Y1Lead-free/Halogen-free/Industrial T emperature (–40°C to 85°C)A T24C01A-W2.7-11(3)A T24C01A-W1.8-11(3)Die Sale Die SaleIndustrial T emperature (–40°C to 85°C)Package Type8P38-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)8S18-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)8A28-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)8Y18-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)5TS15-lead, 2.90 mm x 1.60 mm Body, Plastic Thin Shrink Small Outline Package (SOT23)8U3-18-ball, die Ball Grid Away Package (dBGA2)Options–2.7Low-voltage (2.7V to 5.5V)–1.8Low-voltage (1.8V to 5.5V)14AT24C01A/02/04/08A/16A0180V–SEEPR–8/05Notes:1.For2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table.2.“U” designates Green Package + RoHS compliant.3.Available in waffle pack and wafer form; order as SL719 for wafer form. Bumped die available upon request. Please contactSerial EEPROM Marketing.AT24C02 Ordering Information (1)Ordering Code Package Operation Range A T24C02-10PI-2.7A T24C02N-10SI-2.7A T24C02-10TI-2.78P38S18A2Industrial Temperature (–40°C to 85°C)A T24C02-10PI-1.8A T24C02N-10SI-1.8A T24C02-10TI-1.88P38S18A2Industrial Temperature (–40°C to 85°C)A T24C02-10PU-2.7(2)A T24C02-10PU-1.8(2)A T24C02N-10SU-2.7(2)A T24C02N-10SU-1.8(2)A T24C02-10TU-2.7(2)A T24C02-10TU-1.8(2)A T24C02Y1-10YU-1.8(2)A T24C02-10TSU-1.8(2)A T24C02U3-10UU-1.8(2)8P38P38S18S18A28A28Y15TS18U3-1Lead-free/Halogen-free/Industrial Temperature (–40°C to 85°C)A T24C02-W2.7-11(3)A T24C02-W1.8-11(3)Die Sale Die SaleIndustrial Temperature (–40°C to 85°C)Package Type8P38-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)8S18-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)8A28-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)8Y18-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)5TS15-lead, 2.90 mm x 1.60 mm Body, Plastic Thin Shrink Small Outline Package (SOT23)8U3-18-ball, die Ball Grid Away Package (dBGA2)Options–2.7Low-voltage (2.7V to 5.5V)–1.8Low-voltage (1.8V to 5.5V)15AT24C01A/02/04/08A/16A0180V–SEEPR–8/05Notes:1.For2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table.2.“U” designates Green Package + RoHS compliant.3.Available in waffle pack and wafer form; order as SL719 for wafer form. Bumped die available upon request. Please contactSerial EEPROM Marketing.AT24C04 Ordering Information (1)Ordering Code Package Operation Range A T24C04-10PI-2.7A T24C04N-10SI-2.7A T24C04-10TI-2.78P38S18A2Industrial T emperature (–40°C to 85°C)A T24C04-10PI-1.8A T24C04N-10SI-1.8A T24C04-10TI-1.88P38S18A2Industrial T emperature (–40°C to 85°C)A T24C04-10PU-2.7(2)A T24C04-10PU-1.8(2)A T24C04N-10SU-2.7(2)A T24C04N-10SU-1.8(2)A T24C04-10TU-2.7(2)A T24C04-10TU-1.8(2)A T24C04Y1-10YU-1.8(2)A T24C04-10TSU-1.8(2)A T24C04U3-10UU-1.8(2)8P38P38S18S18A28A28Y15TS18U3-1Lead-free/Halogen-free/Industrial T emperature (–40°C to 85°C)A T24C04-W2.7-11(3)A T24C04-W1.8-11(3)Die Sale Die SaleIndustrial T emperature (–40°C to 85°C)Package Type8P38-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)8S18-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)8A28-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)8Y18-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)5TS15-lead, 2.90 mm x 1.60 mm Body, Plastic Thin Shrink Small Outline Package (SOT23)8U3-18-ball, die Ball Grid Away Package (dBGA2)Options–2.7Low-voltage (2.7V to 5.5V)–1.8Low-voltage (1.8V to 5.5V)16AT24C01A/02/04/08A/16A0180V–SEEPR–8/05Notes:1.For2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table.2.“U” designates Green Package + RoHS compliant.3.Available in waffle pack and wafer form; order as SL719 for wafer form. Bumped die available upon request. Please contactSerial EEPROM Marketing.AT24C08A Ordering Information (1)Ordering Code PackageOperation Range A T24C08A-10PI-2.7A T24C08AN-10SI-2.7A T24C08A-10TI-2.78P38S18A2Industrial T emperature (–40°C to 85°C)A T24C08A-10PI-1.8A T24C08AN-10SI-1.8A T24C08A-10TI-1.88P38S18A2Industrial T emperature (–40°C to 85°C)A T24C08A-10PU-2.7(2)A T24C08A-10PU-1.8(2)A T24C08AN-10SU-2.7(2)A T24C08AN-10SU-1.8(2)A T24C08A-10TU-2.7(2)A T24C08A-10TU-1.8(2)A T24C08AY1-10YU-1.8(2)A T24C08AY5-10YU-1.8(2)A T24C08AU2-10UU-1.8(28P38P38S18S18A28A28Y18Y58U2-1Lead-free/Halogen-free/Industrial T emperature (−40°C to 85°C)A T24C08A-W2.7-11(3)A T24C08A-W1.8-11(3)Die Sale Die SaleIndustrial T emperature (−40°C to 85°C)Package Type8P38-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP)8S18-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)8A28-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)8Y18-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)8Y58-lead, 2.00 mm x 3.00 mm Body, Dual Footprint, Non-Leaded, Miniature Array Package (MAP)8U2-18-ball, die Ball Grid Array Package (dBGA2)Options−2.7Low Voltage (2.7V to 5.5V)−1.8Low Voltage (1.8V to 5.5V)17AT24C01A/02/04/08A/16A0180V–SEEPR–8/05Notes:1.For2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table.2.“U” designates Green Package + RoHS compliant.3.Available in waffle pack and wafer form; order as SL719 for wafer form. Bumped die available upon request. Please contactSerial EEPROM Marketing.AT24C16A Ordering Information (1)Ordering Code PackageOperation Range A T24C16A-10PI-2.7A T24C16AN-10SI-2.7A T24C16A-10TI-2.78P38S18A2Industrial T emperature (–40°C to 85°C)A T24C16A-10PI-1.8A T24C16AN-10SI-1.8A T24C16A-10TI-1.88P38S18A2Industrial T emperature (–40°C to 85°C)A T24C16A-10PU-2.7(2)A T24C16A-10PU-1.8(2)A T24C16AN-10SU-2.7(2)A T24C16AN-10SU-1.8(2)A T24C16A-10TU-2.7(2)A T24C16A-10TU-1.8(2)A T24C16AY1-10YU-1.8(2)A T24C16AY5-10YU-1.8(2)A T24C16AU2-10UU-1.8(2)8P38P38S18S18A28A28Y18Y58U2-1Lead-free/Halogen-free/Industrial T emperature (−40°C to 85°C)A T24C16A-W2.7-11(3)A T24C16A-W1.8-11(3)Die Sale Die SaleIndustrial T emperature (−40°C to 85°C)Package Type8P38-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP)8S18-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)8A28-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)8Y18-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)8Y58-lead, 2.00 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)8U2-18-ball, die Ball Grid Array Package (dBGA2)Options−2.7Low Voltage (2.7V to 5.5V)−1.8Low Voltage (1.8V to 5.5V)18AT24C01A/02/04/08A/16A0180V–SEEPR–8/05Packaging Information8P3 – PDIP19AT24C01A/02/04/08A/16A0180V–SEEPR–8/058S1 – JEDEC SOIC20AT24C01A/02/04/08A/16A0180V–SEEPR–8/058A2 – TSSOP21AT24C01A/02/04/08A/16A0180V–SEEPR–8/058Y1 – MAP22AT24C01A/02/04/08A/16A0180V–SEEPR–8/055TS1 – SOT2323AT24C01A/02/04/08A/16A0180V–SEEPR–8/058U3-1 – dBGA20180V–SEEPR–8/05Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise,to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL ’S TERMS AND CONDI-TIONS OF SALE LOCATED ON ATMEL ’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 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Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.Atmel CorporationAtmel Operations2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 487-2600Regional HeadquartersEuropeAtmel SarlRoute des Arsenaux 41Case Postale 80CH-1705 Fribourg SwitzerlandTel: (41) 26-426-5555Fax: (41) 26-426-5500AsiaRoom 1219Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong KongTel: (852) 2721-9778Fax: (852) 2722-1369Japan9F, Tonetsu Shinkawa Bldg.1-24-8 ShinkawaChuo-ku, Tokyo 104-0033JapanTel: (81) 3-3523-3551Fax: (81) 3-3523-7581Memory2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 436-4314Microcontrollers2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 436-4314La Chantrerie BP 7060244306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18Fax: (33) 2-40-18-19-60ASIC/ASSP/Smart CardsZone Industrielle13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00Fax: (33) 4-42-53-60-011150 East Cheyenne Mtn. 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24C16存储器的原理

4
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上电时序符号 tPUR tPUW
广州周立功单片机发展有限公司 Tel
020 38730976 38730977 Fax 38730925
目录
1 CSI24WC0 1/02/04/08/16 ……………………………….2-10 2 CSI24WC32/64…………………………………………...11-18 3 CSI24WC128. ……………………………..…………….19-26 4 CSI24WC256. ………………………….….…………….27-34
写操作
字节写在字节写模式下主器件发送起始命令和从器件地址信息 R/W 位置零给从器件在从器件产生应答信号后主器件发送 CAT24WC01/02/04/08/16 的字节地址主器件在收到从器件的另一个应答信号后再发送数据到被寻址的存储单元 CAT24WC01/02/04/08/16 再次应答并在主器件产生停止信号后开始内部数据的擦写在内部擦写过程中 CAT24WC01/02/04/08/16 不再应答主器件的任何请求图 6 字节写时序
020 38730976 38730977 Fax 38730925
直流操作特性
Vcc=+1.8V +6.0V 除非特别说明
符号
参数
最小
ICC ISB ILI ILO VIL VIH VOL1 VOL2
电源电流备用电流(Vcc=5.0V) 输入漏电流输出漏电流输入低电压输入高电压输出低电压输出低电压

S-24CS16A0I-T8T1资料

Rev.4.4_002-WIRE CMOS SERIAL E2PROM S-24CS16AThe S-24CS16A is a 2-wired, low power and wide rangeoperation 16 K-bit E2PROM organized as 2048 words × 8bits.Page write and sequential read are available.Features• Low power consumption Standby: 5.0 µA Max. (V CC = 5.5 V)Read: 0.8 mA Max. (V CC = 5.5 V)• Operating voltage range Read: 1.8 to 5.5 VWrite: 2.7 to 5.5 V• Page write: 16 bytes / page• Sequential read• Operating frequency: 400 kHz (V CC = 5 V ±10 %)• Write disable function when power supply voltage is low• Endurance: 106 cycles / word*1 (at +25 °C) write capable,105 cycles / word*1 (at +85 °C)*1. For each address (Word: 8 bits)• Data retention: 10 years (after rewriting 105 cycles / word at +85 °C)• Write protection: 100%• Lead-free productsPackagesDrawing codePackage namePackage Tape Reel Land 8-Pin DIP DP008-F − −−8-Pin SOP(JEDEC) FJ008-A FJ008-D FJ008-D −8-PinTSSOP FT008-A FT008-E FT008-E −WLP-6A HA006-A HA006-A HA006-A −WLP-6E HE006-B HE006-B HE006-B −SNT-8A PH008-A PH008-A PH008-A PH008-ACaution This product is intended to use in general electronic devices such as consumer electronics, office equipment, and communications devices. Before using the product in medical equipment orautomobile equipment including car audio, keyless entry and engine control unit, contact to SII isindispensable.2-WIRE CMOS SERIAL E 2PROM S-24CS16ARev.4.4_00Pin Configurations8-Pin DIP Top viewTable 1Pin No.Symbol Description1 NC *1 No connection2 NC *1No connection 3 A2*2 TEST pin4 GND Ground5 SDA Serial data input / output6 SCL Serial clock input7 WP Write protection inputConnected to V CC : Protection validConnected to GND: Protection invalid8 VCC Power supply *1. Connect to GND or V CC . *2. Connect to GND.VCC WP SCL SDAFigure 1S-24CS16A0I-D8S1GRemark See Dimensions for details of the package drawings.8-Pin SOP(JEDEC)Top viewTable 2 Pin No.Sumbol Description1 NC *1 No connection2 NC *1No connection 3 A2*2 TEST pin4 GND Ground5 SDA Serial data input / output6 SCL Serial clock input7 WP Write protection inputConnected to V CC : Protection validConnected to GND: Protection invalid8 VCC Power supply *1. Connect to GND or V CC . *2. Connect to GND.VCC WP SCL SDANC NC GNDA2Figure 2S-24CS16A0I-J8T1GRemark See Dimensions for details of the package drawings.2-WIRE CMOS SERIAL E 2PROMRev.4.4_00S-24CS16A8-Pin TSSOP Top viewTable 3Pin No.Symbol Description1 NC *1 No connection2 NC *1No connection 3 A2*2 TEST pin4 GND Ground5 SDA Serial data input / output6 SCL Serial clock input7 WP Write protection inputConnected to V CC : Protection validConnected to GND: Protection invalid8 VCC Power supply *1. Connect to GND or V CC . *2. Connect to GND.VCC WP SCL SDAFigure 3S-24CS16A0I-T8T1GRemark See Dimensions for details of the package drawings.WLP-6A Bottom viewTable 4Pin No.Symbol Description1A2*1 TEST pin 2 VCCPower supply3 WP Write protection inputConnected to V CC : Protection validConnected to GND: Protection invalid4 SCL Serial clock input5 SDA Serial data input / output6 GND Ground *1. Connect to GND.(1.66 × 1.15 × 0.6 max.)Figure 4S-24CS16A0I-H6T1 Remark See Dimensions for details of the package drawings.WLP-6E(Low profile 0.39 mm max.)Bottom viewTable 5Pin No.Symbol Description1A2*1 TEST pin 2 VCCPower supply3 WP Write protection inputConnected to V CC : Protection validConnected to GND: Protection invalid4 SCL Serial clock input5 SDA Serial data input / output6 GND Ground *1. Connect to GND.(1.66 × 1.15 × 0.39 max.)Figure 5S-24CS16A0I-H6T3Remark See Dimensions for details of the package drawings.2-WIRE CMOS SERIAL E 2PROM S-24CS16ARev.4.4_00SNT-8A Top viewTable 6Pin No.Symbol Description1A2*1 TEST pin2 GND Ground3 SDA Serial data input / output4 SCL Serial clock input5 WP Write protection inputConnected to V CC : Protection validConnected to GND: Protection invalid6 VCC Power supply7 NC *2 No connection 8 NC *2 No connection*1. Connect to GND.*2. Connect to GND or V CC .Figure 6S-24CS16A0I-I8T1GRemark See Dimensions for details of the package drawings.2-WIRE CMOS SERIAL E2PROM Rev.4.4_00S-24CS16A Block DiagramSCLSDAFigure 72-WIRE CMOS SERIAL E2PROMS-24CS16A Rev.4.4_00Absolute Maximum RatingsTable 7Maximum Rating UnitAbsoluteItem SymbolPower supply voltage V CC −0.3 to +7.0 V Input voltage V IN −0.3 to V CC+ 0.3 VOutput voltage V OUT −0.3 to V CC VOperating ambient temperature T opr−40 to +85 °C Storage temperature T stg −65 to +150 °C Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions.Recommended Operating ConditionsTable 8Max.UnitTyp.Item SymbolConditionMin.Read Operation 1.8 − 5.5 V Power supply voltage V CCWrite Operation 2.7 − 5.5VV CC = 2.7 to 5.5 V 0.7 × V CC −V CC V High level input voltage V IHV CC = 1.8 to 2.7 V 0.8 × V CC−V CC VV CC = 2.7 to 5.5 V 0.0 − 0.3× V CC V Low level input voltage V ILV CC = 1.8 to 2.7 V 0.0 − 0.2× V CC VPin CapacitanceTable 9(Ta = 25 °C, f = 1.0 MHz, V CC = 5 V)Max.UnitTyp.Item Symbol Condition Min.Input capacitance C IN V IN = 0 V (SCL, A2, WP) −− 10 pFInput / output capacitance C I / O V I / O = 0 V (SDA) −− 10 pFEnduranceTable 10Max.UnitTyp.OperationMin.Item SymboltemperatureEndurance N W−40 to +85 °C 105−−cycles / word*1*1. For each address (Word: 8 bits)2-WIRE CMOS SERIAL E2PROM Rev.4.4_00S-24CS16A DC Electrical CharacteristicsTable 11V CC = 4.5 to 5.5 Vf = 400 kHz V CC = 2.7 to 4.5 Vf = 100 kHzV CC = 1.8 to 2.7 Vf = 100 kHzItem SymbolConditionMin. Typ.Max.Min. Typ.Max.Min. Typ. Max.UnitCurrent consumption(READ)I CC1−−− 0.8 −− 0.5 −− 0.3 mACurrent consumption(WRITE)I CC2−−− 4.0 −− 3.0 −−− mATable 12V CC = 4.5 to 5.5 V V CC = 1.8 to 4.5 V Item SymbolConditionMin. Typ. Max.Min. Typ. Max.Unit Standby current consumption I SB V IN = V CC or GND−− 5.0 −− 3.0 µA Input leakage current I LI V IN = GND to V CC− 0.1 1.0 − 0.1 1.0 µA Output leakage current I LO V OUT = GND to V CC− 0.1 1.0 − 0.1 1.0 µAI OL = 3.2 mA −− 0.4 −−− V Low level output voltage V OLI OL = 1.5 mA −− 0.3 −−0.3 V Current address hold voltage V AH− 1.5− 5.5 1.5 − 4.5 V2-WIRE CMOS SERIAL E 2PROM S-24CS16ARev.4.4_00AC Electrical CharacteristicsTable 13 Measurement ConditionsInput pulse voltage0.1 × V CC to 0.9 × V CC Input pulse rising / falling time 20 ns Output judgement voltage 0.5 × V CCOutput load 100 pF + Pull-up resistor 1.0 k ΩΩFigure 8 Output Load CircuitTable 14V CC = 4.5 to 5.5 V V CC = 3.0 to 4.5 V V CC = 1.8 to 3.0 VItem Symbol Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.UnitSCL clock frequency f SCL 0 − 400 0 − 400 0 − 100 kHz SCL clock time “L” t LOW 1.0 − − 1.0 − −4.7 − − µs SCL clock time ”H” t HIGH 0.9 − − 0.9 − − 4.0 − − µs SDA output delay time t AA 0.1 − 0.9 0.1 − 0.9 0.1 − 3.5 µs SDA output hold time t DH 50 − − 50 − − 100 − − ns Start condition setup time t SU.STA 0.6 − − 0.6 − − 4.7 − − µs Start condition hold time t HD.STA 0.6 − − 0.6 − − 4.0 − − µs Data input setup time t SU.DAT 100 − − 100 − − 200 − − ns Data input hold time t HD.DAT 0 − − 0 − − 0 − − ns Stop condition setup time t SU.STO 0.6 − − 0.6 − − 4.0 − − µs SCL y SDA rising time t R − − 0.3 − − 0.3 − − 1.0 µs SCL y SDA falling time t F − − 0.3 − − 0.3 − − 0.3 µs Bus release time t BUF 1.3 − − 1.3 − − 4.7 − − µs Noise suppression time t I − − 50 − − 100 − − 100 nsSCLSDA INSDA OUTFigure 9 Bus Timing2-WIRE CMOS SERIAL E 2PROMRev.4.4_00S-24CS16ATable 15Item Symbol Operating temperatureMin. Typ. Max. Unit −40 to +85 °C− 4.0 8.0 msWrite time t WR−40 to +70 °C− 4.0 5.0 msSCL SDA AcknowledgeFigure 10 Write Cycle Timing2-WIRE CMOS SERIAL E2PROMS-24CS16A Rev.4.4_00 Pin Functions1. A2 PinThe slave address cannot be assigned in the S-24CS16A since the addressing function is removed.The A2 pin should be connected to the GND.2. SDA (Serial Data Input / Output) PinThe SDA pin is used for bi-directional transmission of serial data. It consists of a signal input pin and an Nch open-drain output pin.The SDA line is usually pulled up to the V CC, and OR-wired with other open-drain or open-collector output devices.3. SCL (Serial Clock Input) PinThe SCL pin is used for serial clock input. Since signals are processed at the rising or falling edge of the SCL clock input signal, attention should be paid to the rising time and falling time to conform to the specifications.4. WP PinThe write protection is enabled by connecting the WP pin to the V CC. When there is no need for write protection, connect the pin to the GND.Operation1. Start ConditionStart is identified by a high to low transition of the SDA line while the SCL line is stable at high. Every operation begins from a start condition.2. Stop ConditionStop is identified by a low to high transition of the SDA line while the SCL line is stable at high.When a device receives a stop condition during a read sequence, the read operation is interrupted, and the device enters standby mode.When a device receives a stop condition during a write sequence, the reception of the write data is halted, and the E 2PROM initiates a write cycle.tt Start Condition Stop ConditionSCLSDAFigure 11 Start / Stop Conditions3. Data TransmissionChanging the SDA line while the SCL line is low, data is transmitted.Changing the SDA line while the SCL line is high, a start or stop condition is recognized.t SU.DAT t HD.DATSDAFigure 12 Data Transmission Timing4. AcknowledgeThe unit of data transmission is 8 bits. During the 9th clock cycle period the receiver on the bus pulls down the SDA line to acknowledge the receipt of the 8-bit data.When an internal write cycle is in progress, the device does not generate an acknowledge.SCL(E2SDASDA(E2Figure 13 Acknowledge Output Timing5. Device AddressingTo start communication, the master device on the system generates a start condition to the bus line. Next, the master device sends 7-bit device address and a 1-bit read / write instruction code on to the SDA bus.The 4 most significant bits of the device address are called the “Device Code”, and are fixed to “1010”.The successive 3 bits (P2, P1 and P0) are used to define a page address and choose the eight 256-byte memory blocks.Device CodeFigure 14 Device Address6. Write6. 1 Byte WriteWhen the master sends a 7-bit device address and a 1-bit read / write instruction code set to “0”, following a start condition, the E 2PROM acknowledges it. The E 2PROM then receives an 8-bit word address and responds with an acknowledge. After the E 2PROM receives 8-bit write data and responds with an acknowledge, it receives a stop condition and that initiates the write cycle at the addressed memory.During the write cycle all operations are forbidden and no acknowledge is generated.M S BA C KA C KFigure 15 Byte Write6. 2 Page WriteThe page write mode allows up to 16 bytes to be written in a single write operation in the S-24CS16A.Basic data transmission procedure is the same as that in the “Byte Write”. But instead of generating a stop condition, the master transmitts 8-bit write data up to 8 bytes before the page write.When the E2PROM receives a 7-bit device address and a 1-bit read / write instruction code set to “0”, following a start condition, it generates an acknowledge. Then the E2PROM receives an 8-bit word address, and responds with an acknowledge. After the E2PROM receives 8-bit write data and responds with an acknowledge, it receives 8-bit write data corresponding to the next word address, and generates an acknowledge. The E2PROM repeats reception of 8-bit write data and generation of acknowledge in succession. The E2PROM can receive as many write data as the maximum page size.Receiving a stop condition initiates a write cycle of the area starting from the designated memory address and having the page size equal to the received write data.Figure 16 Page WriteIn S-24CS16A, the lower 4 bits of the word address are automatically incremented every time when the E2PROM receives 8-bit write data. If the size of the write data exceeds 16 bytes, the upper 4 bits of the word address and page address (P2, P1 and P0) remain unchanged, and the lower 4 bits are rolled over and previously received data will be overwritten.6. 3 Write ProtectionWrite protection is available in the S-24CS16A. When the WP pin is connected to the V CC , write operation to memory area is forbidden at all.When the WP pin is connected to the GND, the write protection is invalid, and write operation in all memory area is available.Fix the level of the WP pin from the rising edge of SCL for loading the last write data (D0) until the end of the write time (10 ms max.). If the WP pin changes during this time, the address data being written at this time is not guaranteed.There is no need for using write protection, the WP pin should be connected to the GND. The write protection is valid in the operating voltage range.SDAWPSCLFigure 17 WP Pin Fixed Period6. 4 Acknowledge PollingAcknowledge polling is used to know the completion of the write cycle in the E 2PROM.After the E 2PROM receives a stop condition and once starts the write cycle, all operations are forbidden and no response is made to the signal transmitted by the master device.Accordingly the master device can recognize the completion of the write cycle in the E 2PROM by detecting a response from the slave device after transmitting the start condition, the device address and the read / write instruction code to the E 2PROM, namely to the slave devices.That is, if the E 2PROM does not generate an acknowledge, the write cycle is in progress and if the E 2PROM generates an acknowledge, the write cycle has been completed. Keep the level of the WP pin fixed until acknowledge is confirmed.It is recommended to use the read instruction “1” as the read / write instruction code transmitted by the master device.7. Read7. 1 Current Address ReadEither in writing or in reading the E 2PROM holds the last accessed memory address, internally incremented by one. The memory address is maintained as long as the power voltage is higher than the current address hold voltage V AH .The master device can read the data at the memory address of the current address pointer without assigning the word address as a result, when it recognizes the position of the address pointer in the E 2PROM. This is called “Current Address Read”.In the following the address counter in the E 2PROM is assumed to be “n”.When the E 2PROM receives a 7-bit device address and a 1-bit read / write instruction code set to “1” following a start condition, it responds with an acknowledge. However, the page address (P2, P1 and P0) become invalid and the memory address of the current address pointer becomes valid.Next an 8-bit data at the address “n” is sent from the E 2PROM synchronous to the SCL clock. The address counter is incremented at the falling edge of the SCL clock for the 8th bit data, and the content of the address counter becomes n +1.The master device outputs stop condition not an acknowledge, the reading of E 2PROM is ended.M S BFigure 18 Current Address ReadAttention should be paid to the following point on the recognition of the address pointer in the E 2PROM.In the read operation the memory address counter in the E 2PROM is automatically incremented at every falling edge of the SCL clock for the 8th bit of the output data. In the write operation, on the other hand, the upper bits of the memory address (the upper bits of the word address and page address)*1 are left unchanged and are not incremented at the falling edge of the SCL clock for the 8th bit of the received data.*1. The upper 4 bits of the word address and the page address P2, P1 and P0.7. 2 Random ReadRandom read is used to read the data at an arbitrary memory address.A dummy write is performed to load the memory address into the address counter.When the E2PROM receives a 7-bit device address and a 1-bit read / write instruction code set to “0” following a start condition, it responds with an acknowledge. The E2PROM then receives an 8-bit word address and responds with an acknowledge. The memory address is loaded to the address counter in the E2PROM by these operations.Reception of write data does not follow in a dummy write whereas reception of write data follows in a byte write and in a page write.Since the memory address is loaded into the memory address counter by dummy write, the master device can read the data starting from the arbitrary memory address by transmitting a new start condition and performing the same operation in the current address read.That is, when the E2PROM receives a 7-bit device address and a 1-bit read / write instruction code set to “1”, following a start condition signal, it responds with an acknowledge. Next, 8-bit data is transmitted from the E2PROM in synchronous to the SCL clock. The master device outputs stop condition not an acknowledge, the reading of E2PROM is ended.Figure 19 Random Read7. 3 Sequential ReadWhen the E 2PROM receives a 7-bit device address and a 1-bit read / write instruction code set to “1” following a start condition both in current and random read operations, it responds with an acknowledge.An 8-bit data is then sent from the E 2PROM synchronous to the SCL clock and the address counter is automatically incremented at the falling edge of the SCL clock for the 8th bit data.When the master device responds with an acknowledge, the data at the next memory address is transmitted. Response with an acknowledge by the master device has the memory address counter in the E 2PROM incremented and makes it possible to read data in succession. This is called “Sequential Read”. The master device outputs stop condition not an acknowledge, the reading of E 2PROM is ended.Data can be read in succession in the sequential read mode. When the memory address counter reaches the last word address, it rolls over to the first memory address.ADR INC ADR INCADR INC LINE ADR INCFigure 20 Sequential Read8. Address Increment TimingThe timing for the automatic address increment is the falling edge of the SCL clock for the 8th bit of the read data in read operation and the falling edge of the SCL clock for the 8th bit of the received data in write operation.SCLSDAAddress IncrementFigure 21 Address Increment Timing in ReadingAddress IncrementSCLSDAFigure 22 Address Increment Timing in WritingWrite Inhibition Function at Low Power VoltageThe S-24CS16A has a detection circuit for low power voltage. The detection circuit cancels a write instruction when the power voltage is low or the power switch is on. The detection voltage is 1.85 V typically and the release voltage is 1.95 V typically, the hysteresis of approximate 0.1 V thus exists. (See Figure 23.)When a low power voltage is detected, a write instruction is canceled at the reception of a stop condition.When the power voltage lowers during a data transmission or a write operation, the data at the address of the operation is not assured.Figure 23 Operation at Low Power VoltageUsing S-24CS16A1. Adding a pull-up resistor to SDA I/O pin and SCL input pinAdd a 1 to 5 kΩ pull-up resistor to the SCL input pin*1 and the SDA I/O pin in order to enable the functions of the I2C -bus protocol. Normal communication cannot be provided without a pull-up resistor.*1. When the SCL input pin of the E2PROM is connected to a tri-state output pin of the microprocessor, connect the same pull-up resistor to prevent a high impedance status from being input to the SCL input pin.This protects the E2PROM from malfunction due to an undefined output (high impedance) from the tri-state pin when the microprocessor is reset when the voltage drops.2. I/O pin equivalent circuitThe I/O pins of this IC do not include pull-up and pull-down resistors. The SDA pin is an open-drain output. The following shows the equivalent circuits.Figure 24 SCL PinFigure 25 SDA PinFigure 26 WP Pin3. Matching phases while E2PROM is accessedThe S-24CS16A does not have a pin for resetting (the internal circuit), therefore, the E2PROM cannot be forcibly reset externally. If a communication interruption occurs in the E2PROM, it must be reset by software.For example, even if a reset signal is input to the microprocessor, the internal circuit of the E2PROM is not reset as long as the stop condition is not input to the E2PROM. In other words, the E2PROM retains the same status and cannot shift to the next operation. This symptom applies to the case when only the microprocessor is reset when the power supply voltage drops. With this status, if the power supply voltage is restored, reset the E2PROM (after matching the phase with the microprocessor) and input an instruction. The following shows this reset method.[How to reset E2PROM]The E2PROM can be reset by the start and stop instructions. When the E2PROM is reading data “0” or is outputting the acknowledge signal, 0 is output to the SDA line. In this status, the microprocessor cannot output an instruction to the SDA line. In this case, terminate the acknowledge output operation or read operation, and then input a start instruction. Figure 27 shows this procedure.First, input the start condition. Then transmit 9 clocks (dummy clocks) of SCL. During this time, the microprocessor sets the SDA line to high level. By this operation, the E2PROM interrupts the acknowledge output operation or data output, so input the start condition*1. When a start condition is input, the E2PROM is reset. To make doubly sure, input the stop condition to the E2PROM. Normal operation is then possible.Figure 27 Resetting E2PROM*1.After 9 clocks (dummy clocks), if the SCL clock continues to be output without a start condition being input, a write operation may be started upon receipt of a stop condition. To prevent this, input a start condition after 9 clocks (dummy clocks).Remark It is recommended to perform the above reset using dummy clocks when the system is initialized after the power supply voltage has been raised.4. Acknowledge checkThe I2C-bus protocol includes an acknowledge check function as a handshake function to prevent a communication error. This function allows detection of a communication failure during data communication between the microprocessor and E2PROM. This function is effective to prevent malfunction, so it is recommended to perform an acknowledge check on the microprocessor side.5. Built-in power-on-clear circuitE2PROMs have a built-in power-on-clear circuit that initializes the E2PROM. Unsuccessful initialization may cause a malfunction. For the power-on-clear circuit to operate normally, the following conditions must be satisfied for raising the power supply voltage.5. 1 Raising power supply voltageRaise the power supply voltage, starting at 0.2 V maximum, so that the voltage reaches the power supply voltage to be used within the time defined by t RISE as shown in Figure 28.For example, when the power supply voltage to be used is 5.0 V, t RISE is 200 ms as shown in Figure 29. The power supply voltage must be raised within 200 ms.V INIT (Max.) Power supply voltage (V CC) 0 V*1*1. 0 V means there is no difference in potential between the V CC pin and the GND pin of the E2PROM. *2. t INIT is the time required to initialize the E2PROM. No instructions are accepted during this time.Figure 28 Raising Power Supply VoltageRise time (t RISE ) Max.[ms]Power supply voltage (V CC )[V]50 5.04.03.02.0100150 200For example: If your E 2PROM supply voltage = 5.0 V, raise the power supply voltage to 5.0 V within 200 ms.Figure 29 Raising Time of Power Supply VoltageWhen initialization is successfully completed via the power-on-clear circuit, the E 2PROM enters the standby status.If the power-on-clear circuit does not operate, the following are the possible causes.(1) Because the E 2PROM has not been initialized, an instruction formerly input is valid or an instruction may beinappropriately recognized. In this case, writing may be performed.(2) The voltage may have dropped due to power off while the E 2PROM is being accessed. Even if the microprocessoris reset due to the low power voltage, the E 2PROM may malfunction unless the power-on-clear operation conditions of E 2PROM are satisfied. For the power-on-clear operation conditions of E 2PROM, refer to 5.1 Raising power supply voltage .If the power-on-clear circuit does not operate, match the phase (reset) so that the internal E 2PROM circuit is normally reset. The statuses of the E 2PROM immediately after the power-on-clear circuit operates and when phase is matched (reset) are the same.5. 2 Wait for the initialization sequence to endThe E 2PROM executes initialization during the time that the supply voltage is increasing to its normal value. All instructions must wait until after initialization. The relationship between the initialization time (t INIT ) and rise time (t RISE ) is shown in Figure 30.Rise time (t RISE )[s]E 2PROMinitialization time (t INIT ) Max.[s] 100 m 10 m1.0 m 100 µ10 µ 1.0 µ1.0µ 10 µ 100 µ 1.0 m 10 m 100 mFigure 30 Initialization Time of E 2PROM6. Data hold time (t HD.DAT = 0 ns)If SCL and SDA of the E 2PROM are changed at the same time, it is necessary to prevent the start / stop condition from being mistakenly recognized due to the effect of noise. If a start/stop condition is mistakenly recognized during communication, the E 2PROM enters the standby status.It is recommended that SDA is delayed from the falling edge of SCL by 0.3 µs minimum in the S-24CS16A. This is to prevent time lag caused by the load of the bus line from generating the stop (or start) condition.Figure 31 E 2PROM Data Hold Time7. SDA pin and SCL pin noise suppression timeThe S-24CS16A includes a built-in low-pass filter to suppress noise at the SDA and SCL pins. This means that if the power supply voltage is 5.0 V, noise with a pulse width of 160 ns or less can be suppressed. The guaranteed for details, refer to noise suppression time (t I ) in Table 14.2001003002 3 4 5 Noise suppression time (t I ) Max. [ns]Power supply voltage (V CC )[V]Figure 32 Noise Suppression Time for SDA and SCL Pins8. Trap: E2PROM operation in case that the stop condition is received during write operation beforereceiving the defined data value (less than 8-bit) to SCL pinWhen the E2PROM receives the stop condition signal compulsorily, during receiving 1 byte of write data, “write”operation is aborted.When the E2PROM receives the stop condition signal after receiving 1 byte or more of data for “page write”, 8-bit of data received normally before receiving the stop condition signal can be written.9. Trap: E2PROM operation and write data in case that write data is input more than defined page size at“page write”When write data is input more than defined page size at page write operation, for example, S-24CS16A (which can be executed 16-byte page write) is received data more than 17 byte, 8-bit data of the 17th byte is over written to the first byte in the same page. Data over the capacity of page address cannot be written.10. Trap: Severe environmentsAbsolute maximum ratings: Do not operate these ICs in excess of the absolute maximum ratings (as listed on the data sheet). Exceeding the supply voltage rating can cause latch-up.Operations with moisture on the E2PROM pins may occur malfunction by short-circuit between pins. Especially, in occasions like picking the E2PROM up from low temperature tank during the evaluation. Be sure that not remain frost on E2PROM pin to prevent malfunction by short-circuit.Also attention should be paid in using on environment, which is easy to dew for the same reason.。

S3C2416芯片手册-中文不完整版

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]目录1、产品概述 (3)1、引言 (3)2、特点 (3)3、框图 (3)4、引脚分配 (1)4.1信号说明 (13)2系统控制器 (35)1概述 (35)2、特点 (35)3、框图 (36)4、功能说明 (36)4.1复位管理及类型 (36)4.2硬件复位 (37)4.3看门狗复位 (38)4.4软件复位 (38)4.5唤醒复位 (38)5时钟管理 (39)5.1时钟发生器概述 (39)5.2时钟源选择 (39)5.3PLL（锁相回路） (40)5.4在正常操作下，改变PLL设置 (41)5.5系统时钟控制 (41)5.6ARM和总线时钟分频比 (42)5.7配置时钟寄存器以产生AMBA时钟特定的频率 (42)5.8ESYSCLK控制 (43)6、电源管理 (43)6.1功率模式状态图 (43)6.2节能模式 (44)6.3唤醒事件 (47)6.4输出端口状态，以及停止和睡眠模式 (47)6.5省电模式进入/退出条件 (48)7寄存器说明 (48)7.1地址映射 (48)8独立的寄存器说明 (49)8.1时钟源控制寄存器（LOCKCON0，LOCKCON1，OSCSET，MPLLCON，与EPLLCON） (49)8.2时钟控制寄存器（CLKSRC，CLKDIV，HCLKCON，PCLKCON，与SCLKCON） (51)8.3电源管理寄存器（PWRMODE与PWRCFG） (54)8.4复位控制寄存器（SWRST和RSTCON） (56)8.5在普通模式和从休眠模式唤醒下，（I/O）保持位控制。

(56)8.6系统控制器状态寄存器（WKUPSTAT与RSTSTAT） (57)8.7总线配置寄存器（BUSPRI0，BUSPRI1，与BUSMISC） (57)8.8信息寄存器0,1,2,3 (59)8.9USB PHY控制寄存器（PHYCTRL） (59)8.10USB PHY电源控制寄存器（PHYPWR） (60)8.11USB复位控制寄存器（URSTCON） (60)8.12USB时钟控制寄存器（UCLKCON） (60)3总线矩阵和EBI (61)1概述 (61)2特殊功能寄存器 (61)2.1矩阵芯0优先级寄存器（BPRIORITY0） (61)2.2矩阵芯1优先级寄存器（BPRIORITY1） (61)2.3EBI控制寄存器（EBICON） (62)4总线优先事项 (63)1概述 (63)1.1总线优先图 (63)5静态存储控制器（SMC） (64)1概述 (64)2特点 (64)3框图 (65)3.1异步读 (65)3.2同步读/同步突发阅读 (66)21LCD控制 (68)1概述 (68)1.1特性 (68)1.1.1LCD控制器特点是： (68)2功能描述 (69)2.1子块简述 (69)2.2数据流程 (69)2.3接口 (70)2.4颜色数据概述 (70)1、产品概述1、引言本用户手册描述了三星的S3C2416X16/32-位RISC微处理器。

SLA24C16-S-3资料

Standard EEPROM ICs SLx24C08/168/16Kbit(1024/2048×8bit) Serial CMOS-EEPROM withI2C Synchronous2-Wire BusData Sheet1998-07-27I 2C BusPurchase of Siemens I 2C components conveys the license under the Philips I 2C patent to use the components in the I 2C system provided the system conforms to the I 2C specifications defined by Philips.Edition 1998-07-27Published by Siemens AG,Bereich Halbleiter,Marketing-Kommunikation,Balanstraße 73,81541München ©Siemens AG 1998.All Rights Reserved.Attention please!As far as patents or other rights of third parties are concerned,liability is only assumed for components,not for applications,processes and circuits implemented within components or assemblies.The information describes the type of component and shall not be considered as assured characteristics.Terms of delivery and rights to change design reserved.For questions on technology,delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list).Due to technical requirements components may contain dangerous substances.For information on the types in question please contact your nearest Siemens Office,Semiconductor Group.Siemens AG is an approved CECC manufacturer.PackingPlease use the recycling operators known to you.We can also help you –get in touch with your nearest sales office.By agreement we will take packing material back,if it is sorted.You must bear the costs of transport.For packing material that is returned to us unsorted or which we are not obliged to accept,we shall have to invoice you for any costs in-curred.Components used in life-support devices or systems must be expressly authorized for such purpose!Critical components 1of the Semiconductor Group of Siemens AG,may only be used in life-support devices or systems 2with the express written approval of the Semiconductor Group of Siemens AG.1A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system,or to affect its safety or effectiveness of that device or system.2Life support devices or systems are intended (a)to be implanted in the human body,or (b)to support and/or maintain and sustain hu-man life.If they fail,it is reasonable to assume that the health of the user may be endangered.SLx 24C08/16Revision History:Current Version:1998-07-27Previous Version:06.97Page (in previous Version)Page(in current Version)Subjects (major changes since last revision)33Text was changed to “Typical programming time 5ms for up to16bytes”.55WP =V CC protects upper half entire memory.4,54,5CS0,CS1and CS2were replaced by n.c.5–The paragraph “Chip Select (CS0,CS1,CS2)”was removed completely.11,1211,12The erase/write cycle is finished latest after 108ms.1515Figure 11:second command byte is a CSR and not CSW.1919“Capacitive load …”were added.2020Some timings were changed.2020The line “erase/write cycle”was removed.2020Chapter 7.4“Erase and Write Characteristics”has been added.8/16Kbit (1024/2048×8bit)Serial CMOS EEPROMs,I 2C Synchronous 2-Wire BusSLx 24C08/16Features•Data EEPROM internally organized as1024/2048bytes and 64/128pages ×16bytes •Low power CMOS•V CC =2.7to 5.5V operation•Two wire serial interface bus,I 2C-Bus compatible•Filtered inputs for noise suppression with Schmitt trigger•Clock frequency up to 400kHz •High programming flexibility –Internal programming voltage–Self timed programming cycle including erase –Byte-write and page-write programming,between 1and 16bytes–Typical programming time 5ms for up to 16bytes •High reliability–Endurance 106cycles 1)–Data retention 40years 1)–ESD protection 4000V on all pins •8pin DIP/DSO packages•Available for extended temperature ranges –Industrial:−40°C to +85°C –Automotive:−40°C to +125°C1)Values are temperature dependent,for further information please refer to your Siemens Sales office.Ordering Information Other types are available on request–Temperature range (– 55°C … +150°C)–Package (die,wafer delivery)1Pin ConfigurationFigure 1Pin Configuration (top view)Type Ordering Code Package Temperature Voltage SLA 24C08-D Q67100-H3572P-DIP-8-4–40°C …+85°C 4.5V...5.5V SLA 24C08-S Q67100-H3518P-DSO-8-3–40°C …+85°C 4.5V...5.5V SLA 24C08-D-3Q67100-H3435P-DIP-8-4–40°C …+85°C2.7V...5.5V SLA 24C08-S-3Q67100-H3517P-DSO-8-3–40°C …+85°C2.7V...5.5VSLE 24C08-D Q67100-H3226P-DIP-8-4–40°C …+125°C 4.5V...5.5V SLE 24C08-S Q67100-H3227P-DSO-8-3–40°C …+125°C 4.5V...5.5V SLA 24C16-D Q67100-H3513P-DIP-8-4–40°C …+85°C 4.5V...5.5V SLA 24C16-S Q67100-H3508P-DSO-8-3–40°C …+85°C 4.5V...5.5V SLA 24C16-D-3Q67100-H3512P-DIP-8-4–40°C …+85°C2.7V...5.5V SLA 24C16-S-3Q67100-H3507P-DSO-8-3–40°C …+85°C2.7V...5.5VSLE 24C16-D Q67100-H3229P-DIP-8-4–40°C …+125°C 4.5V...5.5VSLE 24C16-SQ67100-H3230P-DSO-8-3–40°C …+125°C 4.5V...5.5VPin Definitions and Functions Pin Description Serial Clock (SCL)The SCL input is used to clock data into the device on the rising edge and to clock data out of the device on the falling edge.Serial Data (SDA)SDA is a bidirectional pin used to transfer addresses,data or control information into the device or to transfer data out of the device.The output is open drain,performing a wired AND function with any number of other open drain or open collector devices.The SDA bus requires a pull-up resistor to V CC .Write Protection (WP)WP switched to V SS allows normal read/write operations.WP switched to V CC protects the entire EEPROM against changes (hardware write protection).Table 1Pin No.Symbol Function 1,2,3N.C.Not connected 4V SSGround5SDA Serial bidirectional data bus 6SCL Serial clock input 7WPWrite protection input 8V CCSupply voltage2DescriptionThe SLx24C08/16device is a serial electrically erasable and programmable read only memory(EEPROM),organized as1024/2048×8bit.The data memory is divided into 64/128pages.The16bytes of a page can be programmed simultaneously.The device conforms to the specification of the2-wire serial I2C-Bus.Low voltage design permits operation down to2.7V with low active and standby currents.The device operates at5.0V±10%with a maximum clock frequency of400kHz and at 2.7...4.5V with a maximum clock frequency of100kHz.The device is available as5Vtype(VCC =4.5…5.5V)with two temperature ranges for industrial and automotiveapplications and as3V type(VCC =2.7…5.5V)for industrial applications.TheEEPROMs are mounted in eight-pin DIP and DSO packages or are also supplied as chips.Figure2Block Diagram3I2C-Bus CharacteristicsThe SLx24C08/16devices support a master/slave bidirectional bus oriented protocol in which the EEPROM always takes the role of a slave. Array Figure3Bus ConfigurationMaster Device that initiates the transfer of data and provides the clock for both transmit and receive operations.Slave Device addressed by the master,capable of receiving and transmitting data.Transmitter The device with the SDA as output is defined as the transmitter.Due to the open drain characteristic of the SDA output the device applying a lowlevel wins.Receiver The device with the SDA as input is defined as the receiver.The conventions for the serial clock line and the bidirectional data line are shown in figure4.I2C-Bus Timing Conventions for START Condition,STOP Condition,Data Valida-tion and Transfer of Acknowledge ACKStandby Mode in which the bus is not busy(no serial transmission,noprogramming):both clock(SCL)and data line(SDA)are in highstate.The device enters the standby mode after a STOP conditionor after a programming cycle.START Condition High to low transition of SDA when SCL is high,preceding allcommands.STOP Condition Low to high transition of SDA when SCL is high,terminating allcommunications.A STOP condition initiates an EEPROMprogramming cycle.A STOP condition after reading a data bytefrom the EEPROM initiates the Standby mode.Acknowledge A successful reception of eight data bits is indicated by thereceiver by pulling down the SDA line during the following clockcycle of SCL(ACK).The transmitter on the other hand has torelease the SDA line after the transmission of eight data bits.The EEPROM as the receiving device responds with anacknowledge,when addressed.The master,on the other side,acknowledges each data byte transmitted by the EEPROM andcan at any time end a read operation by releasing the SDA line(noACK)followed by a STOP condition.Data Transfer Data must change only during low SCL state,data remains validon the SDA bus during high SCL state.Nine clock pulses arerequired to transfer one data byte,the most significant bit(MSB)is transmitted first.4Device Addressing and EEPROM AddressingAfter a START condition,the master always transmits a Command Byte CSW or CSR.After the acknowledge of the EEPROM a Control Byte follows,its content and the transmitter depend on the previous Command Byte.The description of the Command and Control Bytes is shown in table 2.The device has an internal address counter which points to the current EEPROM address.The address counter is incremented–after a data byte to be written has been acknowledged,during entry of further data byte–during a byte read,thus the address counter points to the following address after reading a data byte.Command ByteSelects operation:the least significant bit b0is low for a write operation (Chip Select Write Command Byte CSW)or set high for a read operation (Chip Select Read Command Byte CSR).Contains address information:in the CSW Command Byte,the bit positions b2or b3to b1are decoded for the two or three uppermost EEPROM address bits A9or A10to A8(in the CSR Command Byte,the bit positions b3to b1are left undefined).Control ByteFollowing CSW (b0=0):contains the eight lower bits of the EEPROM address (EEA)bit A7to A0.Following CSR (b0=1):contains the data read out,transmitted by the EEPROM.The EEPROM data are read as long as the master pulls down SDA after each byte in order to acknowledge the transfer.The read operation is stopped by the master by releasing SDA (no acknowledge is applied)followed by a STOP condition.Table 2Command and Control Byte for I 2C-Bus Addressing of Chip and EEPROMDefinitionFunctionb7b6b5b4b3b2b1b0CSW 1010A10A9A80Chip Select for Write CSR 11xxx1Chip Select for ReadEEAA7A6A5A4A3A2A1A0EEPROM addressThe timing conventions for read and write operations are described in figures 5and 6.Figure 5Timing of the Command Byte CSWFigure 6Timing of the Command Byte CSR5Write OperationsChanging of the EEPROM data is initiated by the master with the command byte CSW.Depending on the state of the Write Protection pin WP either one byte (Byte Write)or up to 16bytes (Page Write)are modified in one programming procedure.5.1Byte WriteFigure 7Byte Write SequenceThe erase/write cycle is finished latest after 8ms.Acknowledge polling may be used for speed enhancement in order to indicate the end of the erase/write cycle (refer to chapter 5.3Acknowledge Polling).Address SettingAfter a START condition the master transmits the Chip Select Write byte CSW.The EEPROM acknowledges the CSW byte during the ninth clock cycle.The following byte with the EEPROM address (A0to A7)is loaded into the address counter of the EEPROM and acknowledged by the EEPROM.Transmission of Data Finally the master transmits the data byte which is also acknowledged by the EEPROM into the internal buffer.Programming CycleThen the master applies a STOP condition which starts the internal programming procedure.The data bytes are written in the memory location addressed in the EEA byte (A0to A7)and the CSW byte (A8to A9or A10).The programming procedure consists of an internally timed erase/write cycle.In the first step,the selected byte is erased to “1”.With the next internal step,the addressed byte is written according to the contents of the buffer.5.2Page WriteThose bytes of the page that have not been addressed are not included in the programming.Figure 8Page Write SequenceThe erase/write cycle is finished latest after 8ms.Acknowledge polling may be used for speed enhancement in order to indicate the end of the erase/write cycle (refer to chapter 5.3Acknowledge Polling).Address SettingThe page write procedure is the same as the byte write procedure up to the first data byte.In a page write instruction however,entry of the EEPROM address byte EEA is followed by a sequence of one to maximum sixteen data bytes with the new data to be programmed.These bytes are transferred to the internal page buffer of the EEPROM.Transmission of DataThe first entered data byte will be stored according to the EEPROM address n given by EEA (A0to A7)and CSW (A8to A9or A10).The internal address counter is incremented automatically after the entered data byte has been acknowledged.The next data byte is then stored at the next higher EEPROM address.EEPROM addresses within the same page have common page address bits A4through A10.Only the respective four least significant address bits A0through A3are incremented,as all data bytes to be programmed simultaneously have to be within the same page.Programming CycleThe master stops data entry by applying a STOP condition,which also starts the internally timed erase/write cycle.In the first step,all selected bytes are erased to “1”.With the next internal step,the addressed bytes are written according to the contents of the page buffer.5.3Acknowledge PollingDuring the erase/write cycle the EEPROM will not respond to a new command byte until the internal write procedure is completed.At the end of active programming the chip returns to the standby mode and the last entered EEPROM byte remains addressed by the address counter.To determine the end of the internal erase/write cycle acknowledge polling can be initiated by the master by sending a START condition followed by a command byte CSR or CSW(read with b0=1or write with b0=0).If the internal erase/ write cycle is not completed,the device will not acknowledge the transmission.If the internal erase/write cycle is completed,the device acknowledges the received command byte and the protocol activities can continue. Array Figure9Flow Chart“Acknowledge Polling”Principle of Acknowledge Polling6Read OperationsReading of the EEPROM data is initiated by the Master with the command byte CSR.6.1Random ReadRandom read operations allow the master to access any memory location.Figure 11Random ReadAddress SettingThe master generates a START condition followed by the command byte CSW.The receipt of the CSW-byte is acknowledged by the EEPROM with a low on the SDA line.Now the master transmits the EEPROM address (EEA)to the EEPROM and the internal address counter is loaded with the desired address.Transmission of CSRAfter the acknowledge for the EEPROM address is received,the master generates a START condition,which terminates the initiated write operation.Then the master transmits the command byte CSR for read,which is acknowledged by the EEPROM.Transmission of EEPROM Data During the next eight clock pulses the EEPROM transmits the data byte and increments the internal address counter.STOP Condition from MasterDuring the following clock cycle the masters releases the bus and then transmits the STOP condition.6.2Current Address ReadThe EEPROM content is read without setting an EEPROM address,in this case the current content of the address counter will be used (e.g.to continue a previous read operation after the Master has served an interrupt).Figure 12Current Address ReadTransmission of CSRFor a current address read the master generates a START condition,which is followed by the command byte CSR (chip select read).The receipt of the CSR-byte is acknowledged by the EEPROM with a low on the SDA line.Transmission of EEPROM Data During the next eight clock pulses the EEPROM transmits the data byte and increments the internal address counter.STOP Condition from MasterDuring the following clock cycle the masters releases the bus and then transmits the STOP condition.6.3Sequential ReadA sequential read is initiated in the same way as a current read or a random read except that the master acknowledges the data byte transmitted by the EEPROM.The EEPROM then continues the data transmission.The internal address counter is incremented by one during each data byte transmission.A sequential read allows the entire memory to be read during one read operation.After the highest addressable memory location is reached,the internal address pointer“rolls over”to the address0and the sequential read continues.The transmission is terminated by the master by releasing the SDA line(no acknowledge)and generating a STOP condition(see figure13). Array Figure13Sequential Read7Electrical CharacteristicsThe listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread.If nototherwise specified,typical characteristics apply at TA =25°C and the given supplyvoltage.7.1Absolute Maximum RatingsStresses above those listed here may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this data sheet is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. Parameter Limit Values UnitsOperating temperature range1(industrial)range2(automotive)–40to+85–40to+125°C°CStorage temperature–65to+150°C Supply voltage–0.3to+7.0V All inputs and outputs with respect to ground–0.3to VCC+0.5V ESD protection(human body model)4000V 7.2DC CharacteristicsParameter Symbol Limit Values Units Test Conditionmin.typ.max.Supply voltage VCC4.55.5V5V typeVCC2.7 5.5V3V typeSupply current1) (write)ICC13mA VCC=5V;fc=100kHzStandby current2)ISB50µA Inputs at VCCor VSSInput leakage current ILI0.110µA VIN=VCCor VSSOutput leakage current ILO0.110µA VOUT=VCCor VSSInput low voltage VIL–0.30.3×VCCV1)The values for I CC are maximum peak values 2)Valid over the whole temperature range 3)This parameter is characterized onlyInput high voltage V IH 0.7×V CCV CC +0.5VOutput low voltage V OL 0.4V I OL =3mA;V CC =5V I OL =2.1mA;V CC =3V Input/output capacitance (SDA)C I/O83)pFV IN =0V;V CC =5VInputcapacitance (other pins)C IN63)pFV IN =0V;V CC =5VCapacitive load for each bus lineC b 400pF7.2DC Characteristics (cont’d)Parameter SymbolLimit ValuesUnits Test Conditionmin.typ.max.1)The minimum rise and fall times can be calculated as follows:20+(0.1/pF)×Cb [ns]Example:Cb =100pF→tR=20+0.1×100[ns]=30ns7.3AC CharacteristicsParameter Symbol Limit ValuesVCC =2.7-5.5VLimit ValuesVCC=4.5-5.5VUnitsmin.max.min.max.SCL clock frequency fSCL100400kHzClock pulse width low tlow4.7 1.2µsClock pulse width high thigh4.00.6µsSDA and SCL rise time tR10001)300nsSDA and SCL fall time tF3001)300nsStart set-up time tSU.STA4.70.6µsStart hold time tHD.STA4.00.6µsData in set-up time tSU.DAT200100nsData in hold time tHD.DAT00µsSCL low to SDA data out valid tAA0.1 4.50.10.9µsData out hold time tDH10050nsStop set-up time tSU.STO4.00.6µsTime the bus must be free before a new transmission can start tBUF4.7 1.2µsSDA and SCL spike suppression time at constant inputs tl5010050100ns7.4Erase and Write CharacteristicsParameter Symbol Limit ValuesVCC =2.7-5.5VLimit ValuesVCC=4.5-5.5VUnitstyp.max.typ.max. Erase+write cycle(per page)tWR5858ms Erase page protection bit 2.54 2.54ms Write page protection bit 2.54 2.54msBus Timing Data8Package Outlines。