Reviewing Bounds on the Circuit Size of the Hardest Functions

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Ultracapacitor - Battery Energy Storage System for Hybrid Electric Vehicles

ii
ACKNOWLEDGEMENT
This research was supported by a research grant from DaimlerChrysler, AG and by NASA Grant NAG3-2790 under subcontract from Bowling Green State University.
APPENDIX II: SYSTEM SCHEMATICS...................................................................... 69
ivபைடு நூலகம்
List of Figures
Figure 1.1 Figure 1.2 Figure 4.1 Figure 4.2 Figure 5.1 Figure 5.2 Figure 6.1 Figure 6.2 Figure 7.1 Figure 7.2 Figure 7.3 Figure 7.4 Figure 7.5 Figure 7.6 Figure 7.7 Figure 7.8 Figure 7.9 Figure 7.10 Figure 8.1 Figure 8.2 Figure 8.3 Figure 8.4 Figure 8.5 Figure 8.6 Figure 8.7 Figure 8.8 Figure 8.9 Figure 8.10 Hybrid Fuel Cell – Ultracapacitor ESS Hybrid Battery-Ultracapacitor ESS Equivalent circuit of a parallel battery/UC Hybrid UC-Battery Simulated Discharge Current Waveforms Proposed Hybrid Battery-UC ESS Simulated Constant Power Pulse First Battery Charging Method Second Battery Charging Method The Proposed Performance Characterization Method ICE Efficiency Map and The Power Split Rule Battery Charging and Routine Message Transmission Algorithm Analog Interface and Vehicle Simulation Algorithm Secondary Microcontroller Algorithms PC Monitor Software screen shot ABC-150 ROS Algorithm Battery Voltage Sense signal conditioning IR2118 Based Relay Driver Circuit LEM Current Sensor signal manipulation circuit Results for 300A / 5 sec. test currents Results for 300A / 8 sec. test currents Results for the Idle-Stop Test StampPlot Pro screen capture Simulator results to demonstrate battery charging and 52 53 54 55 56 57 Simulator results to demonstrate Power Assist Mode Simulator results to demonstrate Motor Only Mode Simulator results to demonstrate regenerative braking Buck Regulator Parallel Battery Charging System Results of the Parallel Battery Charger 2 2 11 12 15 18 20 21 26 31 34 35 39 40 43 44 45 46 48 49 50 51

A High Performance AC Permanent Magnet Contactor_2005

Hale Waihona Puke ISSN: 1109-9445
313
Issue 7, Volume 5, July 2008
WSEAS TRANSACTIONS on ELECTRONICS
Chieh-Tsung Chi
magnet to attain a fast transition time and be suitable for the existing products [19]. To overcome the above-mentioned drawbacks of the conventional ac EM contactor and the existed ac PM contactor, this paper aims at designing a colenoid actuator and its electronic control unit (ECU) to control the ac PM contactor. Like the reference in [2], there is a permanent magnet is arranged on the central pillar of fixed E-type core of new ac PM contactor. Since the electromagnetic force produced by the ac voltage source is dependent upon the number of windings of coil and its applying voltage source value, a large applying voltage value is adopted here for reducing the volume of breaking voltage capacitor. In the colenoid actuator, there are two types of exciting coils; the closing coil is used in the closing process, while the opening coil is used in the opening process. A voltage detector is designed in the ECU is used to monitor the operation state of ac PM contactor by reading the instantaneous ac voltage source value. Based on measured the value of ac voltage source, the ECU is then to drive the ac PM contactor in the closing process, the holding process, or the opening process. The main structure of this paper underlying the proposed ECU and its detailed operation principle will clearly be introduced. Furthermore, the feasibilities and effectiveness of the ECU and colenoid actuator in each operating process will be identified through simulation and experimental tests. For the assessment of the energy-saving performance, the proposed ac PM contactor with ECU and colenoid actuator will be compared with that of a conventional ac EM contactor.

Verifying Circuits

Input pairs (a=1,b=0) (a=0,b=1) and (a=1,b=1) all generate a carry, so we can test the inputs (a,b,c) = (1,0,1) (0,1,1) (1,0,1) (3 out of 8 cases) for each FA in parallel with the patterns 1111…1111 and 0000…0000 0000…0000 and 1111…1111 1111…1111 and 1111…1111 and a carry in set to 1
all 8 possible patterns were tried for each FA in the full ircuit
Random Testing
With automated test generation For example, use an FPGA to generate test vectors! Testing can be very fast ~109 tests / second is possible Programmed generation of random numbers can apply large numbers of tests in reasonable times However
Case study – Ripple carry adder
Composed of full adder circuits and carry chains Test the full adders 3 inputs, each with 2 possible values 23 = 8 possible inputs Exhaustive testing … 3. Finally we have the cases where

电专业英语阅读教程03

大连理工大学出版社同名教材配套电子教案Specialty English《电专业英语阅读教程》（第二版）温丹丽高源制作大连理工大学出版社Unit Three Electronic Apparatus and Instrument▪Passage One Electronic Components▪Passage Two Analog Instruments and Uses▪Passage Three Introductions to Common Digital Instruments ▪Passage Four Measuring voltage with oscilloscopes▪Passage Five Computer-based Test instrumentsUnit Three Electronic Apparatus and InstrumentPassage One Electronic ComponentsTraining target: In this part, our target is to train your reading comprehension. We have made the flexible sentences strong black and marked the subject, predicate and object of them. Try to grasp the main idea of these sentences.Speciality VocabulariesCathode 阴极field effect transistor (FET) 场效应管reverse bias 反向偏置integrate circuits 集成电路chips 芯片anode 阳极forward bias 正向偏置magnetic field 磁场Notes:1 Diodes（Diodes二极管）connected in such a way that only the positive half-cycles of an alternating current (AC) are permitted or pass are called rectifier tubes（rectifier tubes整流管）.2 Small variations in voltage at the grid, such as can be produced by a ratio or audio signal, will cause large variations in the flow of electrons from the cathode to the anode and, hence, in the circuitry connected to the anode.Unit Three Electronic Apparatus and InstrumentPassage One Electronic ComponentsNotes:3 When this diode is connected to a battery so that the p-type material is positive and the n-type is negative, electronics are repelled from the negative battery terminal and pass unimpeded（unimpeded无阻碍地）to the p-region, which lack electrons.4 The principle can be used to construct amplifiers in which a small signal applied to the forward-biased junction causes a large change in current in the reverse-biased junction.5 Variable resistors, with an adjustable sliding contact arm, are often used to control volume on radios and television sets.6 Inductors consist of a conducting wire wound（wind缠绕）into the form of a coil. When a current passes through the coil, a magnetic field is set up around it that tends to oppose rapid changes in current intensity（intensity强度）.Unit Three Electronic Apparatus and InstrumentPassage Two Analog Instruments and Uses Training target:In this part,our target is to train your reading speed;you should pay more attention to“word group”.Treating a group of words as a whole unit is a short cut to save your time.We have underlined the word groups in some sentences,and the rest can be practiced by yourself.If there are some new words,you may cover the note area with a piece of paper and try to guess their meaning without using the dictionary.Speciality Vocabulariesindicator 指示器calibration 刻度milliampere 毫安培hairspring 细弹簧，游丝milliammeter 毫安表multiplier 增效器，乘法器rectifier 整流器，校正器diagonal 对角Notes:1. The basic principle is that of a moving coil with attached indicator(indicator 指示器)turning in the field of a permanent(permanent 永久的) magnet specially designed so that the angular response of the moving system is uniform and the calibration（calibration标度，刻度）of the instrument does not change in time due to changes in the value of the field.Unit Three Electronic Apparatus and InstrumentPassage Two Analog Instruments and Uses Notes:2 In these instruments the current or voltage to be measured is used to excite a stationary coil in whose fields placed a moving vane of high permeability （permeability渗透性）steel together with a spring and pointer.3 This repulsion acts on the moving vane（vane叶片）which rotates the spindle(spindle轴，心轴) against the action of two springs.4 If these instruments are suitable constructed they have a response which is equal for direct or alternating voltages and so they are employed to calibrate the A.C. response of other instruments in terms of D.C. values.Unit Three Electronic Apparatus and InstrumentPassage Three Introductions to Common Digital Instruments Training target: In this part, you should try your best to form good readinghabits .In order to avoid your ill habits such as regression, you should keepreading the paragraphs from the beginning to the end without stopping.Speciality Vocabulariesactivate 激发flip-flop 触发器oscillator 振荡器oscilloscope 示波器exploit 开发，开拓，利用sample 采样. Text .1.Electronic Digital CounterCommon to all digital instruments is the electronic digital counter. The electronic counter, most often thought of as a device that totalizes（totalize统计）input events, is the basic building block for all digital test and measurement applications.A simple frequency counter consist of seven major functions: input conditioning,timer base oscillator, timer base dividers, main-gate flip-flop, main gate, counting register, and read out display. Central to the operation of the digital counter is the main gate.Passage Three Introductions to Common Digital Instruments The main gate is nothing more than a logic AND circuit. When both the inputconditioning and main-gate flip-flop are logically true. The main gate opens for aperiod of time that is determined by the timer base divider. While the main gate is open, the conditioned input signal pulses are passed through to the counting register, where they are tallied（tally记录）and then scaled（scale测量）for output by the display circuitry. At the end of the counting period, the main gate is closed and counter reset for the next sampling（sampling采样）period.2.Digital Frequency CountersThe digital counter has come a long way since it first appeared on the commercial market.Even in its original form it was recognized as perhaps the most useful measuring instrument to emerge from the laboratory since the oscilloscope.The original application of the digital counter was that of a frequency counter.When the main gate is controlled by an accurate（accurate精密的）time interval,the counter is in the frequency mode.The frequency mode is similar to the totalize mode described above,with the difference being in the way the gate control is operated.Passage Three Introductions to Common Digital InstrumentsFor frequency measurements,the counting time interval is precisely（precisely精确地）controlled to be multiples（multiple倍数）of a second.If,for example,45,500 pulses pass through to the counting register while the main gate remains open for one second,then the input signal frequency is45.5kHz.Depending on the number of digits in the read out,this number could be directly or expressed as powers of ten（10的幂）.To measure frequencies that would otherwise exceed the maximum count of the counting register,the time interval of the main gate can be reduced,with an appreciated change made to the scale factor（scale factor比例因数）.A similar number of pulses (45,500)accumulating in the counting register within a0.1second period,for example, would represent a frequency of455kHz;25,000pulses counter within10μs is2.5MHz, and so forth.Scaling can be done automatically by the positioning of the decimal point on the digital read out,as the timer base period is switched from range to range.Instead of manually switching to the appropriate timer range,some instruments have an automatic range selection system called auto ranging.The ranger usually consists of a circuit that generates voltage level;one of several transistor switches is turned on to s e l e c t t h e c o r r e c t t i m e r b a s e a n d d e c i m a l p o i n t p o s i t i o n.Passage Three Introductions to Common Digital Instruments Using the frequency counter as a frequency meter,however,is exploiting but one of its several electronic counter functions,A counter can also indicate the period of an input signal, compare two signals in the ratio mode,indicate the time between two points on a waveform, or do reciprocal（reciprocal倒数的）counting.3.Digital V oltmetersThe digital voltmeters (DTV) are perhaps the most prolific of all digital test instruments. Basically, the DVM circuitry is similar to the analog voltmeters, with the expectation that the read out is displayed digitally rather than on mechanical meter movement.Although there are numerous techniques used to convert analog values to digital numbers, the basic principles of operation are the same: The voltage unknown of the pulses are counted using a digital counter circuit, as described above, and the counter is displayed on a 7segment read out. Five methods of analog-to-digital conversion as commonly used. They are:V oltage to frequency integratingSingle rampDual-slope integratingSuccessive approximation potentiometerContinuous balance potentiometerUnit Three Electronic Apparatus and InstrumentPassage Four Measuring voltage with oscilloscopes Training target:In this part,our target is to train your reading comprehension.When reading this passage,pay attention to the questions on the right..Text .The oscilloscope has both advantage and disadvantage when used to measure voltage(or current). The most obvious advantage is that the oscilloscope shows waveform,frequency and phase simultaneously with the amplitude of the voltage(or current)being measured.The VOM（volt-ohmmeter）or electronic voltmeter shows only amplitude.Likewise,most meters are calibrated in relation to sine waves.When the signals being measured contain significant harmonics the calibrations are inaccurate.Whit the oscilloscope,the voltage is measured from the displayed wave,which includes any harmonic content.In certain applications,the lack of inertia and the high-speed response of an oscilloscope make it the only instrument capable of transient-voltage measurement. (When we use oscilloscopes to measure voltage or current,what are the advantages and disadvantages?)The only major disadvantage using an oscilloscope for voltage(or current)measurement is the problem of resolution.The scales of simple inexpensive VOMs or electronic voltmeters are easier or read than an oscilloscope.In most cases,the oscilloscope’s vertical scales are used for voltage(or current)measurement,with each scale division representing a given value of voltage(or current). W h e r e v o l t a g e s a r e l a rg e,i t i s d i f f i c u l t t o i n t e r p o l a t e b e t w e e n d i v i s i o n s.Unit Three Electronic Apparatus and InstrumentPassage Four Measuring voltage with oscilloscopes Another problem,although not a disadvantage,is that voltages measured with an oscilloscope are peak-to-peak,whereas most voltages specified in electronic maintenance and troubleshooting manuals are RMS.This requires that the peak-to-peak value be converted to RMS.To sum up,if the only value of interest is voltage(or current)amplitude,use the meter because of its simplicity in e the oscilloscope when wave-shape characteristics are of equal importance to amplitude.It is noted that the vertical amplifier of a laboratory oscilloscope usually has a step attenuator in which each step is related to a specific deflection factor(such as volts per centimeter).Many such oscilloscopes have a vertical gain adjusting knob that when adjusted against an internal calibrated source,sets the accuracy of the attenuator.These oscilloscopes need not be calibrated for voltage(or current)measurements,since calibration is an internal adjustment performed as part of routine maintenance. (What circumstance should we use oscilloscopes to measure voltage or current?) The vertical amplifiers of shop oscilloscope usually have variable attenuators and possibly a step attenuator.The steps do not,however,have a specific volts-per-centimeter deflection factor.Such oscilloscopes must be calibrated before they can be used to measure voltage (or current).Passage Five Computer-based Test instruments Training target: Read the following reading materials, and use the reading skills mentioned in the passages above. You may also choose some parts of this passage to practice.Speciality Vocabulariesinternal 内置external 外置knob 旋钮adapter 适配器umbilical cord操纵缆，电缆expansion slot 扩展槽pretrigger 触发前hotkey 热键. Text .Personal-computer-based test instruments have fast become the quick and easy way for companies of all sizes to realize the advantages of computer-aided testing(CAT)without incurring the enormous expense of program development and mainframe time.Such instruments are able to meet the goals of reduced labor cost,increased productivity,and the elimination of human error in reading and processing measurements,by utilizingthe power of software to perform many of the functions traditionally done by workbenches loaded with hardware.The general design of these instruments is around a desktop personal computer, such as the IBM PC or the IBM PC AT. PC instruments, as they have come to be known, are categorized as being either internal or external.Passage Five Computer-based Test instruments PC instruments designed for internal use are fabricate d on one or more computer adapter boards.These adapter boards are physically identical to the video and I/O adapter cards required by the computer for normal operation.To install the instrument into the computer,the card is simply plugged into an available expansion slot on the motherboard,and the system is powered up as e of the test instrument is then controlled by software from the computer’s keyboard.There are no knobs,switches,or indicators available to the user.The entire operation of the instruments is through the computer and its interfaces.In an externally connected PC instrument,the test instrument is housed in a onventional cabinet external to the computer’s cabinet.Installed in the cabinet may be input-output connectors,selector switches,and maybe an IED or two.There is also a connector cable coming from the external instrument that plugs into the PC.Inside the computer is an interface card that translates the signals coning from the external measuring instrument into digital pulses with voltage levels and timing requirements compatible with those on the computer bus.The connection between the external PC test instrument and the computer is in the form of an umbilical cord that feeds voltage,data,and control signals between the two devices. Without this connection,the test instrument is little more than a stand-alone device with features less than comparable to the ecumenical instruments.When connected to the c o m p u t e r,h o w e v e r,i t b e c o m e s a v i r t u a l p o w e r h o u s e.Passage Five Computer-based Test instruments In operation,the IS-16offers a1-MHz aggregate sampling rate capability on16individual input channels with12-bit resolution at input voltages within the range of–10to+10volts.Fully automated keystroke commands(which programmers call hotkeys)provide the user with control over all features of the instrument,including channel selection,trigger control(internal to any channel,external,+/–level or slop),sampling rate,and memory buffer size from1KB to64KB.In effect,the hotkeys are designated keys on the co mputer keyboard that act like the knobs and levers found on an oscilloscope’s front panel.Beyond the simulated mechanical aspects of an oscilloscope,the IS-16employs a ring buffer that allows the capture of data in pretrigger intervals of virtually any length.Software commands permit timer base expansion and contraction,left and right scrolling,independent vertical gain adjustment,and w a v e f o r m s t o r a g e a n d r e t r i e v a l.It is last feature,waveform storage and retrieval that set the PC-based IS-16oscilloscope apart from its mechanical counterpart.Input measurements can be stored in computer files or temporary computer memory(RAM)for archival purposes or further processing.The fact that the dynamic input becomes static in nature provides the user with the ability to modify the contents of an existing file in many useful ways,so that subsequent analysis of signal may be effectively performed.The entire operation is done in software, following the acquisition of the input signal.Passage Five Computer-based Test instruments The program begins by creating a verbatim copy of the input signal in a computer data file,using strings of binary words to represent instantaneous events and values in real time.Once saved,the entire measurement procedure can be duplicated down to the last detail by simply playing back the file record into the computer,in much the same way music is forever captured on a record disk or magnetic tape and played back upon demand.Each channel of data may be saved and processed separately using this method.The saved data may now be processed by the computer’s software to derive measurements not initially performed by the PC instrument.When one realizes that all these measurements can be made after the fact,the implications are staggering.One-time events that are elusive to conventional measurement can be done routinely in the leisure of an office setting by simply running the recorded data through the computer one more time using the appropriate software selection.Furthermore,the results can build one on another.For example,in the first pass, noise and amplification factors may be adjusted,resulting in a data file that can now be average,integrated,or differentiated to see the effects of each,without ever having to change the physical setup of the test instrument or device under test.。

Incomplete melting of the Si(100) surface from molecular-dynamics simulations using the Eff

a r X i v :c o n d -m a t /9604012v 1 2 A p r 1996Incomplete melting of the Si(100)surface frommolecular-dynamics simulations using the Eﬀective-MediumTight-Binding model.K.Stokbro,1,2,3K.W.Jacobsen,3J.K.Nørskov,3D.M.Deaven,4C.Z.Wang,4and K.M.Ho 41Mikroelektronik Centret,Danmarks Tekniske Universitet,Bygning 345ø,DK-2800Lyngby,Denmark.2Scuola Internazionale Superiore di Studi Avanzati,via Beirut 4,I-34014Trieste,Italy.3Center for Atomic-scale Materials Physics and Physics Department,Danmarks Tekniske Universitet,DK 2800Lyngby,Denmark 4Ames Laboratory,Ames,Iowa 50011Abstract We present molecular-dynamics simulations of the Si(100)surface in the temperature range 1100-1750K.To describe the total energy and forces we use the Eﬀective-Medium Tight-Binding model.The defect-free surface is found to melt at the bulk melting point,which we determine to be 1650K,but fora surface with dimer vacancies we ﬁnd a pre-melting of the ﬁrst two layers100K below the melting point.We show that these ﬁndings can rationalizerecent experimental studies of the high temperature Si(100)surface.Typeset using REVT E XI.INTRODUCTIONMost work on the Si(100)surface has focussed on the behaviour at low and intermediate temperatures,while to our knowledge there have to date only been two experimental studies [1,2]of the atomic structure at temperatures near the bulk melting point.Both of these studies indicate that the surface undergoes a phase transition at a temperature below the bulk melting point,however,there is no consistent picture of the nature of the transition, the exact transition temperature,and the atomic structure beyond the phase transition.Metois and Wolf[1]studied the structure of the Si(100)surface with Reﬂection-Electron Microscopy(REM).In the temperature interval1400-1455K the experiment shows a sudden increase in the number of holes on the surface,and at1455K the surface structure cannot be resolved any longer and it is suggested that the surface at this temperature becomes rough at the atomic scale.In the experimental study by Fraxedas et.al[2]the surface order of Si(100)was studied as a function of the surface temperature by means of X-ray Photo-electron Diﬀraction(XPD).At1400K the order suddenly decreases,and this is attributed to a phase transition where the twoﬁrst surface layers melt and form a liquid layer.For the Si(100)surface molecular-dynamics simulations based on the Stillinger-Weber potential have been used to study the solid-liquid interface[4],but there are no studies of the surface melting.To our knowledge,the onlyﬁrst principles molecular-dynamics study of the melting of a semiconductor surface is by Takeuchi et.al.[3].They study a Ge(111) surface at a temperature close to the melting point andﬁnd evidence for the existence of an incomplete melted phase.The experiment by Metois and Wolf shows that the Si(100)surface has an increasing concentration of vacancies as a function of the temperature.Since the vacancy formation takes place on a time scale of seconds,it is not possible to study the vacancy formation in a molecular dynamics simulations,however,given a certain vacancy concentration we can study what is the surface structure attained within a time scale of≈10−100ps.In this report we present a molecular-dynamics study of the Si(100)surface with andwithout vacancies for a number of temperatures in the range1100-1750K.To describe the bonding of Si we have used the Eﬀective-Medium Tight-Binding(EMTB)model[5].We show that this approximate total energy method describes the melting point and the prop-erties of liquid Si very ing the computational eﬃciency of the method to simulate a slab with a unit cell containing188atoms for up to35ns at a number of diﬀer-ent temperatures and surfaces with and without defects,we show that while the defect-free surface shows no sign of premelting,a surface with25%of dimer vacancies shows melting of theﬁrst layer100K below the melting point.We show that the results of the simulation can be used to understand the experimental observations for this system.II.TECHNICAL DETAILSThe Eﬀective-Medium Tight-Binding(EMTB)model[5]is based on Eﬀective-Medium Theory[6,7]in which the total energy calculations are simpliﬁed by comparisons to a ref-erence system(the eﬀective medium).The so-called one-electron energy sum is calculated using an LMTO tight-binding model[8].The main approximations in the model is the use of aﬁrst-order LMTO tight-binding model and a non-self-consistent electron density [9]and potential[10].In previous studies we have demonstrated the ability of the model to describe the low temperature structure of the Si(100)surface,[5]and generally we have found the accuracy for the total energy and atomic structure of solid Si systems to be cor-rect within10-20percent,which is comparable to plane-wave calculations with a cutoﬀof 8Ry.However,the EMTB method is in computational eﬃciency comparable to empirical tight-binding methods and for the system sizes treated here something like three orders of magnitude faster than plane-wave calculations.It is therefore very well suited for large scale molecular-dynamics simulations.The super-cell for the calculation is a12layer thick slab with16atoms in each layer except for the upper layer in which we have introduced a vacancy concentration of25percent by removing four atoms;thus a total of188atoms.Since all atoms are free to move we obtaininformation of a clean surface and a surface with vacancies in the same simulation run.The classical equations of motion for the nuclei are integrated using the Verlet algorithm with a time step of1.08fs and we control the temperature by using Langevin dynamics[11]with a friction coeﬃcient of2ps−1.The lattice constant is determined by scaling the EMTB (T=0K)value(10.167a0)using the experimental thermal-expansion coeﬃcient.III.RESULTSInitially,the atomic structure of the bottom surface consists of two dimer rows with each4dimers,while the vacancies are introduced on the upper surface by removing a dimer from each row.Starting from the c(2x4)reconstruction weﬁrst increase the temperature of the thermostat to1100K.After thermalization this system is followed over3ps.Theﬁnal conﬁguration is used as input for four other simulation temperatures:1450K,1550K,1650K, and1750K,which are followed over29ps,35ps,33ps and18ps,respectively.Weﬁrst summarize the calculations by showing in Fig.1the average structure factor parallel to the dimer rows,|S−11|2,as a function of the simulation temperature.The structure factor is projected onto3intervals of the z axis corresponding to the position of layers1-2, 3-4,and5-6on both the vacancy covered and the clean surface.The structure factor is averaged over the atomic conﬁgurations of the last2ps,15ps,15ps,15ps and5ps for each of theﬁve simulations temperatures,respectively.The calculated variances in the structure factors show that except for the1650K calculation,the simulations seem to have obtained an equilibrium state.In Fig.2we show the corresponding average atomic density perpendicular to the surfaces,and for the1550K calculation a snapshot of the atomic-structure is shown in Fig.3.The observed atomic structures obtained in the simulations are the following:At1100K the two surfaces show no tendency to break up the dimer rows;each dimer stays in a buckling mode moving up and down with a frequency of≈3THz,and the buckling angle reverses independently of the conﬁgurations of the other dimers.For the clean surface weﬁnd this tobe the picture up to1750K where the entire slab melts,and Fig.1b shows that the structure factor for this surface is constant up to the melting transition.The vacancy surface shows a much more complex behaviour.At1450K we observe diﬀusion of one of the vacancies within the simulation time.After the diﬀusion the dimers remain intact and the structure factor shown in Fig.1a is only slightly aﬀected.At1550K the twoﬁrst layers of the vacancy surface lose all their order and form a disordered state, see Fig.3,and there is a strong interaction with the third layer which forms an interface between the bulk structure and the disordered surface.From Fig.1a we see that now the structure factor has vanished for the two outermost layers,while the structure factor of the third layer is slightly decreased due to the interaction with the disordered state.At1650K theﬁrst four layers disorders(cf.Fig.1a and Fig.2).At1750K all the layers melt after a short transient period,and Fig.2shows a constant atomic density n=2.54g/cm3in the range−10a0<z<10a0.This is an increase of6percent compared to the crystalline density,and in good agreement with the experimental atomic density n=2.51g/cm3for liquid silicon at1750K.Weﬁrst extract from the simulations the Si bulk melting point,T m,predicted by the EMTB model.At1750K the whole slab melts,without a partially-melted transient period, and we therefore have T m<1750K.At1550K there are two phases present in the calculation with a large interaction between the two.Since Fig.1a shows that there are only small ﬂuctuations in the structure factor of the layers,this strongly suggests that the simulation has obtained an equilibrium state.Furthermore,if the melting temperature was close to 1550K,the temperature in the1650K simulation would be well above the melting point and the slab should readily melt since a melted phase is already present in the calculation. From these considerations we estimate a melting temperature of T m≈1650±100K,in good agreement with the experimental melting point of1685K.The rather large error bar in the melting temperature comes fromﬁnite size eﬀects leading to largeﬂuctuations in the temperature.On top of this there may be a systematic overestimate of the melting temperature in the simulation because of theﬁxed super-cellsize parallel to the slab.However,the possibility of the system to respond with volume changes perpendicular to the slab reduces this problem considerably.The presence of the surface thus allows the liquid to acquire the correct density as noted above.In the simulation with the thermostat set at1650K the temperatureﬂuctuates around the melting point,and we may have a coexistence of solid and liquid phases at this temperature. This suggests that the melting of the two additional layers in the1650K simulation is rather due to largeﬂuctuations of the temperature around the melting point than the existence of a surface phase transition where four layers disorders.Note also the largeﬂuctuations observed in the structure factor of layer5-6at this temperature,shown in Fig.1a,which makes it questionable whether an equilibrium state has been obtained within the simulation time.The temperature in the1550K simulation,on the other hand,is well below the bulk melting point and the atomic structure in this case must be due to a surface phase transition taking place at a temperature T F<1550.From simulations of metal surfaces it is known[14] that just at the surface melting temperature the defects become mobile,and we therefore estimate T F=1450±100K.Since we have T F<1550<T M we can expect to have obtained equilibrium within our simulation time for this temperature.We now consider the1550K simulation in more detail.In Fig.4we show the radial distribution function averaged over the atoms in layer2and layer6-7.For comparison we also show similar averages obtained for the1750K simulation in which case the whole slab has become liquid.Theﬁgure clearly shows that the two outermost layers in the1550K simulation have formed a liquid state,with an average coordination very diﬀerent from the bulk state,but almost identical to that of liquid Si.It is worth noting that the radial distribution function obtained for the liquid Si is in good agreement with experiment[12]and that obtained by Stich et.al.[13]in a Car-Parrinello calculation(the position of theﬁrst maximum is4.67a0(4.65a0)and integration up to5.90a0gives an average coordination of6.55(6.5),where the values obtained in Ref.[13]are given in parenthesis). The formation of a liquid surface bilayer in the1550K simulation is further illustrated byFig.5,where we from the lateral mean-square displacement of the surface atoms deduce a two dimensional diﬀusion constant of D=2.1×10−5cm2/s.We also observe a jump in the average potential energy during melting at1550K from which we deduce a latent heat of melting the surface atoms of∆E≈3eV.This must be compensated by an increase in the entropy∆E=Nk B T∆S(where N is the number of atoms taking part in the phase transition),which when attributed to the atoms in the twoﬁrst layers(N=28),gives an increase in the entropy of∆S≈0.8.We now relate our simulations for the Si(100)to those of Ref.[3]for the Ge(111)surface. The outermost layer of the Ge(111)surface consists of fourth a monolayer Ge adatoms, which gives this surface a more open structure than the Si(100)surface.The Ge(111)surface has more resemblance with the vacancy covered Si(100)surface,and there are indications that the adatoms on the Ge(111)surface and the vacancies on the Si(100)surface play similar roles in the surface melting process.Similar to the vacancy diﬀusion we found in the1450K simulation,Takeuchi et.al.found a metastable state in theﬁrst part of their simulation where only the adatoms diﬀuse.Afterwards the Ge(111)surface undergoes a phase transition where the twoﬁrst layers become liquid,and the increase in entropy and the diﬀusion constant are very similar to the values we have found for the vacancy covered Si(100)surface.(For Ge(111)the values are D Ge=3.5×10−5cm2/s,∆S Ge≈1.0).For the Ge(111)surface it was also found that the electronic structure of the melted layers was metallic,and lately this has been supported by an electron energy loss spectroscopy (EELS)study of the surface conductivity of Ge(111)[15].However,we onlyﬁnd a weak metallic behaviour for the incomplete melted Si(100)surface.This is illustrated in Fig.6, which shows the Projected Density of States(PDOS)of the atoms in the twoﬁrst layers of the vacancy surface(solid line)and the clean surface(dotted line),and we see that the number of states in the gap is only slightly increased for the incomplete melted vacancy surface compared to the non-melted clean surface.We therefore expect that the surface melting of Si(100)will be diﬃcult to detect with EELS.PARISON WITH EXPERIMENTSWe now compare ourﬁndings to the experimental results of Ref.[1,2].One of our results is that the phase transition only takes place when a high concentration of vacancies is present on the surface,and the question arises what are the vacancy concentrations in the exper-iments.STM studies yield estimates that the surface at room temperature has a vacancy concentration of5-10percent.[16]When the surface is heated up one may observe atoms evaporating,and since they leave a vacancy behind this process may increase the vacancy concentration.Metois and Wolf found that at temperatures below1400K the sublimation process proceeds slowly enough,that the sublimation holes areﬁlled with atoms diﬀusing from step edges and the vacancy concentration is relatively stable up to this temperature. In the temperature interval1400-1455K the number of holes increases drastically and at 1455K the surface structure cannot be resolved any longer.The experiment by Metois and Wolf is in a non-equilibrium state and they relate the observed behaviour to kinetic surface roughening.The kinetic roughening is caused by the larger activation energy for sublimation compared to the activation energy for diﬀusion, which means that the sublimation rate will increase faster with temperature than the dif-fusion rate,and at some temperature the sublimation rate will become too fast for the vacancies to beﬁlled with atoms diﬀusing from step edges.However,we note that the ob-served behaviour is not necessarily due to kinetic roughening but can alternatively be due to the existence of a roughening phase transition.Both kinetic roughening and a roughening phase transition will give rise to an increased vacancy concentration as a function of the temperature,and the vacancy concentration in the experiments of Ref.[1,2]at1450K will therefore be well above the5-10percent concentration at room temperature.From the avail-able data we cannot determine the exact vacancy concentration in the two experiments,and probably they will not have the same concentrations,since it will depend on experimental details,such as base pressure and the crystal miscut angle.It is not possible to use molecular dynamics simulations to determine the(equilibrium ornon-equilibrium)concentrations of vacancies since the simulation time scales are too short. However,for a given vacancy concentration molecular dynamics can be used to study the attained surface structure within a time scale of≈10−100ps,which is long compared to fundamental surface vibration frequencies.In the simulation we have studied a vacancy concentration of25percent,where weﬁnd a phase transition at1550K to an incomplete melted state with two melted layers.We expect the same phenomena to take place for higher or slightly lower vacancy concentrations.However,the results cannot be generalized to low vacancy concentrations,since in this case the time scale of the formation of an incomplete melted phase may become comparable to the time scale of the processes that alter the vacancy concentration.For instance,on the time scale of desorption of Si dimers(seconds) the simulation for the clean surface will show incomplete melting,since the desorption of Si dimers will give rise to an increased vacancy concentration on the surface.In a real experiment there will also be adatoms diﬀusing of step edges and adsorption of atoms from the gas phase,and these processes will lower the vacancy concentration.We now make quantitative comparisons with the experimental study of Ref.[2],where the XPD anisotropy(A(hkl)(T))is measured along the(100)and(111)directions as a function of temperature.The anisotropy in a given direction is deﬁned as A(hkl)(T)= (I max(T)−I min(T))/(I max(300K)−I min(300K)),where I max(I min)stands for the maxi-mum(minimum)intensity for a given peak.We have simulated the XPD intensity peaks using Single-Scattering Cluster(SSC)calculations[17],with the same SSC parameters as quoted in Ref.[18].For the electron mean-free path the value is25˚A(corresponding to the energy of the2s photo electrons),in spite of the generally accepted rule of using half of its nominal value.[19]The anisotropy along the(111)direction is extremely sensitive to the actual choice of mean-free path,and we have therefore chosen only to make comparison with the anisotropy along the(100)direction,which we have found to be rather insensitive to the value of the mean-free path.For each simulation temperature we have calculated the anisotropy along the(100)di-rection for20diﬀerent conﬁgurations and Fig.7shows the corresponding averages.Wehave performed calculations using both a mean-free path of12.5˚A and25˚A.In each case the anisotropies have been scaled such that at1100K the anisotropy of the clean surfaceﬁts the experimental measurements,and Fig.7shows that the relative anisotropies are quite insensitive to the choice of mean-free path.We may therefore relate our calculations directly to the experimental measurements.First of all we see that vacancies lead to a drop in the anisotropy,and the observed increase in the vacancy concentration of Ref.[1]should there-fore be measurerable by XPD.Weﬁnd that an increase in the vacancy concentration by10 percent would be consistent with the small decrease in the experimental anisotropy observed in the temperature range≈1390−1425K.Since we must expect[16]that the surface al-ready has a vacancy concentration around10percent at1390K,the vacancy concentration will be20percent at1425K,very similar to the concentration in our simulation.An increase in the vacancy concentration,however,can hardly describe the overall drop in the anisotropy observed in the range1390-1500K.Fig.7indicates strongly that the decrease in the anisotropy after1425K is related to the defect-induced disordering we have described above.This picture is in accordance with Ref.[18],where they found that the experimentally observed drop in anisotropy could be explained by assuming a disordered bilayer at the surface.The experiment also shows that the thickness of the melted layer is constant upto the bulk melting point,again indicating that the melting of the two additional layers in the1650K simulation is related to bulk melting rather than surface melting.V.SUMMARYIn summary,we have performed molecular-dynamics simulations for the Si(100)surface using the EMTB model.Weﬁnd that in the presence of a vacancy concentration of25 percent the surface undergoes a phase transition at1550K,where the twoﬁrst layers melt and form a liquid state.The incompletely melted state shows several similarities to the incomplete melting of Ge(111)[3],except that the electronic surface structure shows a much weaker metallic behaviour.We have also shown that the simulation results are in bothquantitative and qualitative agreement with experimental studies of the surface structure.ACKNOWLEDGMENTSWe thank C.Fadley for providing us the program for the SSC calculations and J.Fraxedas for instructions on how to use the program.Many discussions with P.Stoltze and E.Tosatti are gratefully acknowledged.The Center for Atomic-scale Materials Physics is sponsored by the Danish National Research Foundation.Kurt Stokbro acknowledges eec contract ERBCHBGCT920180and contract ERBCHRXCT930342and CNR project Supaltemp.REFERENCES[1]J.Metois and D.Wolf,Surf.Sci.298,71(93).[2]J.Fraxedas,S.Ferrer,and in,Europhys.Lett.25,119(1994).[3]N.Takeuchi,A.Selloni,and E.Tosatti,Phys.Rev.Lett.72,2227(1994).[4]ndman,W.D.Luedtke,R.N.Barnett,C.L.Clevelannd,M.W.Ribarsky,E.Arnold,S.Ramesh,H.Baumgart,A.Martinez,and B.Kahn,Phys.Rev.Lett.56,155 (1986).[5]K.Stokbro,N.Chetty,K.Jacobsen,and J.Nørskov,Phys.Rev.B50,10727(1994).[6]J.Nørskov and ng,Phys.Rev.B21,2131(1980).[7]K.Jacobsen,J.Nørskov,and M.Puska,Phys.Rev.B35,7423(1987).[8]O.Andersen and O.Jepsen,Phys.Rev.Lett.53,2571(1984).[9]N.Chetty,K.Jacobsen,and J.Nørskov,Lett.J.Phys.Condens.Matter3,5437(1991).[10]K.Stokbro,N.Chetty,K.Jacobsen,and J.Nørskov,J.Phys.Condens.Matter6,5415(1994).[11]D.Heermann,Computer Simulation Methods in Theoretical Physics(Springer-Verlag,Berlin,Heidelberg,1986).[12]Y.Waseda and K.Suzuki,Z.Phys.B.20,339(1975);P.Gabathuler and S.Steeb,Z.Naturforsch.Teil A34,1314(1979).[13]I.Stich,R.Car,and M.Parrinello,Phys.Rev.Lett.60,204(1988).[14]P.Stoltze,J.K.Nørskov,and ndman,Phys.Rev.Lett.61,440(1988).[15]S.Modesti,et.al.,Phys.Rev.Lett.73,1951(1994).[16]R.Hamers,R.Tromp,and J.Demuth,Phys.Rev.B34,5343(1986).[17]C.Fadley,Prog.in Surf.Sci.16,275(1984).[18]J.Fraxedas,S.Ferrer,and in,Surf.Sci.307-309,775(1994).[19]D.Naumovic et al.,Phys.Rev.B47,7462(1993).FIGURESFIG.1.The equilibrium average structure factor parallel to the dimer rows,|S−11|2,as a function of the simulation temperature.The structure factor is projected onto3intervals of the z axis corresponding to the position of layer1-2,3-4,and5-6,for a)The vacancy covered surface, and b)the clean surface.FIG.2.The equilibrium average atomic density perpendicular to the surfaces for each simula-tion temperature.FIG.3.A snapshot of the atomic structure in the1550K simulation at t=30ps.The supercell is repeated twice in the horizontal direction.FIG.4.The radial distribution function projected onto layer2and layer6-7for the1550K simulation(solid line)and the1750K simulation(dashed line).FIG.5.The atomic displacement in the surface plane projected onto layer1-2,3-4,and5-6, as a function of time for the1550K simulation.The2-dimensional diﬀusion constant,D,for layer 1-2is deﬁned by<r2>=4Dt.FIG.6.The PDOS of layer1-2of the vacancy surface(solid line)and the clean surface(dotted line)in the1550K simulation.The average is taken over the last15ps of the simulation.FIG.7.The XPD anisotropy as obtained from SSC calculations with an electron mean-free path of12.5˚A(solid line)and25˚A(dashed line)as a function of the simulation temperature.The experimental measurements are from Ref.[2].-20-15-10-5051015201100K1450K 1550K 1650K1750Kρ(z ) [a r b i t r a r y u n i t s ]0246810r [a 0]01234g (r )05101520253035time [ps]050100(x −x 0)2+(y −y 0)2[a 02]。

DIN_VDE V 0126-1-1 Rev A_Ueberarbeitung_Viotto英文

Februar2006DIN V VDE V 0126-1-1(VDE V 0126-1-1)Dies ist zugleich eine VDE-Vornorm im Sinne von VDE 0022. Sie ist unter der obenangeführten Nummer in das VDE-Vorschriftenwerk aufgenommen und in der …etzElektrotechnik + Automation“ bekannt gegeben worden.Vervielfältigung – auch für innerbetriebliche Zwecke – nicht gestattet.PrestandardICSSelbsttätige Schaltstelle zwischen einer netzparallelen Eigenerzeugungsanlage und demöffentlichen NiederspannungsnetzAutomatic disconnection device between a generator and the public low-voltage gridDispositif de déconnexion automatique entre un générateur et le réseau public à bassetensionEnglischsprachige ÜbersetzungGesamtumfang 15 SeitenDKE Deutsche Kommission Elektrotechnik Elektronik Informationstechnik im DIN und VDE© DIN Deutsches Institut für Normung e.V. und VDE Verband der Elektrotechnik Elektronik Informationstechnik e.V.Jede Art der Vervielfältigung, auch auszugsweise, nur mit Genehmigung des DIN, Berlin, unddes VDE, Frankfurt am Main, gestattet.Preisgr. K VDE-Vertr.-Nr.Einzelverkauf und Abonnements durch VDE VERLAG GMBH, 10625 Berlin Einzelverkauf auch durch Beuth Verlag GmbH, 10772 Berlin– Vornorm –DIN V VDE V 0126-1-1 (VDE V 0126-1-1):2006-02Beginn der GültigkeitDiese Vornorm gilt ab 2006-02-01.VorwortVorausgegangener Norm-Entwurf: E DIN VDE 0126-1-1 (VDE 0126-1-1):2005-05.Eine Vornorm ist das Ergebnis einer Normungsarbeit, das wegen bestimmter Vorbehalte zum Inhalt oder wegen des gegenüber einer Norm abweichenden Aufstellungsverfahrens vom DIN noch nicht als Norm herausgegeben wird. Erfahrungen mit dieser Vornorm sind erbeten an die DKE Deutsche Kommission Elektrotechnik Elektronik Informationstechnik im DIN und VDE, Stresemannallee 15, 60596 Frankfurt am Main.Für die vorliegende Vornorm ist das nationale Arbeitsgremium K 373 …Photovoltaische Solarenergie-Systeme“ der DKE Deutsche Kommission Elektrotechnik Elektronik Informationstechnik im DIN und VDE zuständig.Für den Fall einer undatierten Verweisung im normativen Text (Verweisung auf eine Norm ohne Angabe des Ausgabedatums und ohne Hinweis auf eine Abschnittsnummer, eine Tabelle, ein Bild usw.) bezieht sich die Verweisung auf die jeweils neueste gültige Ausgabe der in Bezug genommenen Norm.Für den Fall einer datierten Verweisung im normativen Text bezieht sich die Verweisung immer auf die in Bezug genommene Ausgabe der Norm.Der Zusammenhang der zitierten Normen mit den entsprechenden Deutschen Normen ergibt sich, soweit ein Zusammenhang besteht, grundsätzlich über die Nummer der entsprechenden IEC-Publikation. Beispiel: IEC 60068 ist als EN 60068 als Europäische Norm durch CENELEC übernommen und als DIN EN 60068 ins Deutsche Normenwerk aufgenommen.ÄnderungenGegenüber E DIN VDE 0126-1-1 (VDE 0126-1-1):2005-05 wurden im Wesentlichen folgende Änderungen vorgenommen:a) Komplette Überarbeitung der Abschnitte 4, 4.2, 4.5 und 6.6.2.2.1,b) Aufnahme von zusätzlichen Erläuterungen A2, A3 und A4.Frühere AusgabenE DIN VDE 0126-1-1 (VDE 0126-1-1):2005-052— Vornorm —DIN V VDE V 0126-1-1 (VDE V 0126-1-1):2006-02InhaltSeite Vorwort (2)1Scope (4)2Normative references (4)3Definitions (4)4Requirements (5)4.1Functional safety (6)4.2Voltage monitoring (7)4.3Frequency monitoring (7)4.4Direct current monitoring (7)4.5Detection of island operation (7)4.6Labelling (7)4.7Special requirements (8)5General requirements (8)6Type test (8)6.1Functional safety (8)6.2Voltage monitoring (8)6.3Frequency monitoring (8)6.4Direct current monitoring (9)6.5Detection of island operation (9)6.6Residual current monitoring (11)7Product conformity test (13)8Installation specifications (13)Annex A ( Informative) Comments (14)A.1Further methods of detecting islanding (14)A.2Frequency limits (14)A.3Operation of standby generating sets (14)A.4Short-term disconnections (14)Bibliography (15)Figure 1 - Block circuit diagram of an automatic disconnection device (photovoltaic example) (7)Figure 2 - Test circuit as per 6.5.1 - Example showing disconnection device integrated in inverter (9)Figure 3 - Test circuit as per 6.5.2 - Example showing disconnection device integrated in inverter (10)Figure 4 - Test circuit as per 6.6.2.1 - Set-up for single-phase feeding inverter (12)Table 1 - Maximum break times (8)3– Vornorm –DIN V VDE V 0126-1-1 (VDE V 0126-1-1):2006-0241 ScopeThe automatic disconnection device is used as a safety interface between the generator and the public low-voltage distribution grid and serves as a substitute for a disconnecting switch accessible at all times by the distributing network operator. It prevents the unintentional supply of electrical energy from the generator into a subnetwork disconnected from the rest of the distribution grid (islanding), thereby offering additional protection (to the measures specified in DIN VDE 0105-100 (VDE 0105-100), 6.2) to–operating staff, against voltage in the disconnected subnetwork –equipment, against inadmissible voltages and frequencies –consumers, against inadmissible voltages and frequencies – equipment, against the feeding of faults by the generator.In the case of faults in the low voltage grid, the automatic disconnection device protects the generation plant from– inadmissible voltages and– inadmissible frequencies.The automatic disconnection device does not protect the generator from overload and short circuiting. Such protection should be provided separately in accordance with DIN VDE 0100-712 (VDE 0100-712), DIN VDE 0100-430 (VDE 0100-430) and DIN VDE 0100-530 (VDE 0100-530).2 Normative referencesThe following referenced documents are indispensable for the application of this document. For dated references, only the edition cited applies. For undated references, the latest edition of the referenced document (including any amendments) applies.DIN EN 50160:2000-03, Merkmale der Spannung in öffentlichen Elektrizitätsversorgungsnetzen.DIN EN 50178 (VDE 0160), Ausrüstung von Starkstromanlagen mit elektronischen Betriebsmitteln . DIN EN 60664-1 (VDE 0110-1), Isolationskoordination für elektrische Betriebsmittel in Nieder-spannungsanlagen – Teil 1: Grundsätze, Anforderungen und Prüfungen.E DIN VDE 0664-100 (VDE 0664-100):2002-05, Fehlerstrom-Schutzschalter Typ B zur Erfassung von Wechsel- und Gleichströmen – Teil 100: RCCBs Typ B.DIN EN 61000-6-2 (VDE 0839-6-2), Elektromagnetische Verträglichkeit (EMV) – Teil 6-2: Fachgrundnormen – Störfestigkeit für Industriebereich.DIN EN 61000-6-3 (VDE 0839-6-3), Elektromagnetische Verträglichkeit (EMV) – Teil 6-3: Fachgrundnormen – Fachgrundnorm Störaussendung für Wohnbereich, Geschäfts- und Gewerbebereiche sowie Kleinbetriebe.DIN EN 61008-1 (VDE 0664-10), Fehlerstrom-/Differenzstrom-Schutzschalter ohne eingebautenÜberstromschutz (RCCBs) für Hausinstallationen und für ähnliche Anwendungen.DIN VDE 0100-430 (VDE 0100-430), Errichten von Niederspannungsanlagen – Teil 4-43: Schutzmaßnahmen – Schutz bei Überstrom.DIN VDE 0100-530 (VDE 0100-530), Errichten von Niederspannungsanlagen – Teil 530: Auswahl und Errichtung elektrischer Betriebsmittel – Schalt- und Steuergeräte.DIN VDE 0100-712 (VDE 0100-712), Errichten von Niederspannungsanlagen – Teil 7-712: Anforderungen für Betriebsstätten, Räume und Anlagen besonderer Art – Solar-Photovoltaik (PV) Stromversorgungssysteme . DIN VDE 0105-100 (VDE 0105-100), Betrieb von elektrischen Anlagen.3 DefinitionsThe following definitions apply for the purposes of this document:— Vornorm —DIN V VDE V 0126-1-1 (VDE V 0126-1-1):2006-02 3.1Disconnection deviceDevice for stopping the generator from feeding of electrical power into the grid via by disconnecting it from the grid.Note: The automatic disconnection device, which may be integrated in the generator, can obtain its supply voltage from the grid. Connection to the grid is also necessary for voltage and frequency measurement. Passive elements (e.g. EMC filters) can also be incorporated unswitched on the grid side.3.1.1Separate disconnection deviceDisconnection device which works independently regarding its safety function,3.1.2Integrated disconnection deviceDisconnection device which forms a functional unit with the generator.3.2Unintended islandingIsland network operation ("islanding") is when a subnetwork in which decentralised generators cover the consumption of the connected loads is disconnected from the larger rest of the grid. Possible causes for the disconnection include switching actions of the network operator, the triggering of protection devices or failures of equipment. In the case of unintended islanding, this process is outside the network operator's control. The network has no influence over the voltage and frequency of the disconnected subnetwork.3.3Earth leakage currentCurrent which flows to earth from the live parts of the installation without there being an insulation fault?NB: This current may have a capacitive component, caused especially by the use of capacitors.3.4Earth fault currentCurrent which flows to earth as the result of an insulation fault3.5Fault (or residual) currentVector sum of instantaneous values of the currents flowing in the primary circuit of the residual (fault) current protection device (expressed as r.m.s.)3.6Rated residual current (I　n)The value of the residual operating current set for the RCMU by the manufacturer at which it should switch off under specified conditions.3.7Simple separationIsolation of circuits or between a circuit and earth through basic insulation.3.8Residual current monitoring unit (RCMU)A residual current monitoring unit (RCMU) is a device which detects and switches off direct, pulse and alternating residual currents arising in the event of a fault in inverters with no simple separation between the network and the photovoltaic generator.4 RequirementsThe following requirements apply for both integrated and separate safety disconnection devices, unless otherwise specified.The disconnection device must disconnect the generator unit from the grid on the AC side due to– voltage and/or frequency fluctuations in the low voltage grid– d.c. feed into the low voltage grid– unintended islanding and （被动孤岛）5– Vornorm –DIN V VDE V 0126-1-1 (VDE V 0126-1-1):2006-02– intended islanding with standby generating unitsby means of two switches arranged in series.Before feeding into the grid, it is measured for 30 s to check whether the voltage and frequency remain within the tolerance band as defined in 4.2.1, 4.2.2 and 4.3. If this is the case, the can be connected and start feeding into the grid. From this time on 4.2 to 4.5 and 4.7 must be fulfilled. Following a disconnection of the generator triggered by one of the safety functions of the disconnection device, the connection is carried out in the same manner. Following a disconnection because of a short grid failure, the generator may be connected again once the voltage and frequency of the grid are within the tolerance band specified in 4.2 and 4.3 for a period of 5 s. A short grid failure, is characterised by the upper and lower limits of the grid frequency and/or voltage being exceeded for a maximum period of 3 s. Unintended islanding must also be detected when generation and consumption match each other in the separate network subsection.4.1 Functional safetyThe safety of the functions defined in 4.2 to 4.5 and 4.7 of the automatic disconnection device (see Fig. 1) must be ensured in all operating conditions of the network. It may be a stand-alone unit or an integral part of the generator. It must switch off and show the fault status in the event of a failure.4.1.1 Safety against single faultsObserving basic safety principles the disconnection device must be designed, built, selected, assembled and combined so that it can withstand the expected operating loads (e.g. reliability in terms of switching performance and its switching frequency) and external influences (e.g. mechanical vibration, external fields, interruptions or failures in the energy supply).An individual fault in the disconnection device should not result in a loss of the safety functions. Faults triggered by the same cause must be considered if the probability of the occurrence of such a fault is significant. If possible, the individual fault must be displayed and it should trigger a disconnection of the generator.NOTE 1 This requirement for detection of individual faults does not mean that all faults have to be detected. A large number of undetected faults can therefore lead to an unintended output signal and to a dangerous state.NOTE 2 This system response means that– the safety function remains operational when an individual fault occurs– some, but not all, faults are detected– an accumulation of undetected faults can lead to loss of the safety function.4.1.2 Requirements on the switchesThe switches arranged in series must, independently of each other, have a breaking capacity which matches the rated current of the generator. At least one switch must be a relay or contactor and be suitable for overvoltage category 2. In the case of single phase feeding units the switch must have a contact of this overvoltage category both for the neutral line and for the phase line. In the case of multiphase feed units, one contact of this overvoltage category is required for all active lines. The second switch may consist of the electronic switching elements of the inverter bridge circuit or another circuit if the electronic breaking elements can be switched off by control signals and it is ensured that a failure is detected and will stop operation at the latest when the feeding in is startet the next time.6— Vornorm —DIN V VDE V 0126-1-1 (VDE V 0126-1-1):2006-02Figure 1 - Block circuit diagram of an automatic disconnection device (photovoltaic example)4.2Voltage monitoring4.2.1 Voltage reduction (protection function)Voltages of ≤ 80 % U N in the phase conductor which are being fed in must trigger a disconnection within 0.2 seconds. It shall not be possible to change this limit in the device.4.2.2 Voltage increase (protection function)Voltages of ≥ 115 % U N in the phase conductor which are being fed in must trigger a disconnection within 0.2 seconds. It shall not be possible to change this limit in the device.4.2.3 Voltage increase (monitoring of voltage quality)The aim is to stay within the voltage limits at the point of common coupling. A floating average should be measured over a 10 minute interval for each phase conductor being fed into. The trigger threshold can be set between 110 % U N and 115 % U N to take into account the drop in voltage between the installation location and the point of common coupling. The factory-setting is a threshold of 110 % U N. Exceeding this set value must trigger a break. The setting of this limit should only be made in consultation with the network operator. 4.3 Frequency monitoringNetwork frequencies below 47.5 Hz and above 50.2 Hz must lead to a disconnection within 0.2 seconds.4.4 Direct current monitoringA direct current feed to the low voltage grid due to a defective generator operation must lead ot a disconnection within 0.2 s. For this, either the malfunction itself or a measured d.c. component of the current of more than 1 A can serve as a criterion.4.5Detection of island operation4.5.1 Single unit operationIsland network operation must lead to a disconnection under the test conditions of the type test specified in 6.5.4.5.2 Multiple unit operationIsland operation can be detected independently for each individual unit meaning that the requirements set out in 4.5.1 are fulfilled for each individual unit. Alternatively, the automatic disconnection device can receive disconnection commands via an interface from another protection device with equivalent island network detection. A disconnection command must lead to a disconnection within 0.2 s. The protection device issuing the signal and the interface must also fulfil the functional safety requirements defined in 4.1.1.4.6 LabellingA generator with automatic disconnection device must feature "VDE 0126-1-1" on the type plate which must be externally visible. Further labels as defined in DIN EN 50178 (VDE 0160) should be attached or included in the accompanying documentation as required.7– Vornorm –DIN V VDE V 0126-1-1 (VDE V 0126-1-1):2006-0284.7 Special requirements4.7.1 PhotovoltaicsA residual current monitoring unit (RCMU) is required for inverters without simple separation between the grid and the photovoltaic generator. In the event of a failure, the d.c. and a.c. component of the residual current depend on the type of inverter and the d.c. voltage of the PV generator.An external residual current device is required in a disconnection device without an integrated RCMU. In this case, the tests defined in 6.6. do not apply. The residual current device required should be specified by the manufacturer in the operating instructions.The generator-side insulation resistance before the switch to the grid must be ≥ 1 k Ω/V relative to the maximum inverter input voltage, and at least 500 k Ω. Leakage currents greater than 300 mA must trigger a break within 0.3 s. Irrespective of the rated power of the inverter, any sudden residual currents should trigger a break as in Table 1.Table 1 - Maximum break times r.m.s. value of residualcurrent/(mA) Break time/(s)30 0.360 0.15150 0.04The break times apply for the entire temperature range stated by the manufacturer.In the case of inverters without simple separation between the grid and the PV generator, both switches mentioned in 4.1.2. must be a relay or contactor with the requirements stipulated there.NB: A design featuring an interrupting device between the inverter and PV generator and an interrupting device between the inverter and grid is possible.5 General requirementsThe limits set out in DIN EN 61000-6-3 (VDE 0839-6-3) concerning radio interference shall be observed. The test interference quantities stipulated in DIN EN 61000-6-2 (VDE 0839-6-2) should be used as the basis for interference immunity.6 Type testThe following tests apply for integrated and separate disconnection devices, unless otherwise specified. A separate disconnecting device should be tested together with a suitable generator. It should be ensured that the break signal is generated by the disconnection device and not by the generator.6.1 Functional safetyOne-fault safety and fault recognition with subsequent break as defined in 4.1 shall be tested by means of a fault simulation.6.2 Voltage monitoringIn order to test the voltage monitoring, the automatic disconnection device should be run via an a.c. voltage source with variable amplitude at nominal voltage and arbitrary power level. The trigger time specified in 4.2 must not be exceeded in the case of voltage jumps in which do not fall below the lower limit according to 4.2 by more than 3% of the nominal voltage and do not exceed the upper limit by more than 3% of the nominal voltage. The test shall be carried out for each phase conductor which is fed into.6.3 Frequency monitoringIn order to test the frequency monitoring, the automatic disconnection device shall be run through an a.c. voltage source with variable amplitudes and frequencies. The trigger time of the frequency monitoring specified in 4.3 should not be exceeded during a gradual change in frequency from the nominal value up to— Vornorm —DIN V VDE V 0126-1-1 (VDE V 0126-1-1):2006-029the relevant limit with a change rate of 1 Hz/s. Functioning of the frequency monitoring shall be checked within the voltage range specified in 4.2: at the lower limit for nominal voltage and at the upper limit.6.4 Direct current monitoringTesting of the break following direct current feed is conducted using optionally a) or b):a) A direct current of 1 A is applied to the current measurement of the disconnection device (e.g. currenttransformer, resistance). The break should happen within 0.2 s.b) By simulating a fault a measurement should be taken to determine whether defective operation with adirect component of the input current of over 1 A triggers a break within 0.2 s.6.5 Detection of island operationTesting the break following unintended island operation is carried out using one of the methods described in6.5.1 to 6.5.3. The method used must fulfil the functional safety requirements set out in 4.1.6.5.1 Impedance measurement6.5.1.1 Test circuitThe test circuit (see Figure 2) simulates a balanced parallel feed/load status and voltage and frequency stability conditions of a network zone which can form a network island through interruption. Even under these conditions the automatic disconnection device must reliably detect the interruption to the network and switch off the generator within 5 s.The test circuit has the following properties:The direct voltage side of the inverter is supplied by a variable energy source. In the case of generators with no inverter, the power supply is provided by a suitable drive. On the alternating voltage side of the feeder, the resistors (R 1), reactors (L 1) and capacitors (C 1) are arranged in parallel to the output so that the level of the apparent power (taken or given) across the enclosed break device (S) for increasing the impedance of the grid connection is less than 5% of the rated power of the unit on the grid side (test alignment).The break device is arranged in parallel to a testing resistor of 1 Ω (R 3). Based on an impedance of Z N ≤ 0.5 Ω in the network in which the tests are carried out, the impedance (R 2, L 2) is increased in selectable stages with permitted deviations (including the operation network impedance fluctuations) of ± 0.25 Ω to values of up to 1 Ω ohmic resistance and up to 0.8 Ω ohmic resistance combined with 0.5 Ω reactance, thereby testing whether a break occurs within 5 s following a jump in impedance of 1 Ω.Figure 2 - Test circuit as per 6.5.1 - Example showing disconnection device integrated in aninverter6.5.1.2 Test procedureUsing the variable power source, 100% of the inverter's rated power is fed into its input. The rated power should also be set for generators without inverter. Resistors, reactors and capacitors should be set to test alignment on the a.c. voltage side. Break device S is then opened in this state. A break should be triggered within 5 s of the break device opening.If the voltage and frequency are within the tolerance band, the disconnection device should not reconnect until at least 30 s after the break.Between 20 s and 60 s after the disconnection device has reconnected, break device S should close and not reopen until at least 30 s later. A break should be triggered within 5 s of the break device opening.– Vornorm –DIN V VDE V 0126-1-1 (VDE V 0126-1-1):2006-0210 This test should be repeated at the different network impedances.To test a 3-phase disconnection unit, a test circuit should be connected to one of the phases in each case, as shown in Figure 2. The other two phases are then connected directly to the grid. The breaks should each be triggered within 5 seconds of the break device S opening.6.5.2 Oscillating circuit test6.5.2.1 Test circuitThe d.c. voltage side of the inverter is supplied by a suitable direct voltage source. In the case of generators with no inverter the power supply is provided by a suitable drive. Resistors, reactors and capacitors are arranged in parallel to the output on the a.c. voltage side of the generator. These form an RLC oscillating circuit and can be finely adjusted to the active and reactive output generated (Figure 3). Both the RLC oscillating circuit and the generator should be connected via separate switches to the grid or a suitable grid simulator.This oscillating circuit should have a Q factor of at least 2. The reactive output taken by the oscillating circuit must match that emitted by the generator or the inverter to at least ± 3 %. At nominal voltage, the harmonic distortion of the reactor current should be below 3 %. The following relationships apply for the inductance and capacity settings: 22U L f P Q =π⋅⋅⋅ 22P Q C f U⋅=π⋅⋅ where U is the grid voltage, f the grid frequency and P the reactive power fed from the generator.Figure 3 - Test circuit as per 6.5.2 - Example showing disconnection device integrated ininverter6.5.2.2 Test procedureThe test should be conducted as follows:1. The output of the generators is determined using the direct voltage source or a suitable drive for systemswithout inverter.2. The system is connected to the grid or the grid simulator by closing S3 and S2. Without any oscillationcircuit connected (S1 opened), the active (P ) and reactive (P Q,WR ) output flowing into the grid is now measured.3. The generator is disconnected from the grid (S2 open).4. The oscillating circuit is balanced as follows:a) The inductance is set so that Q > 2.b) The capacity is set so that P QC + P QL = –P Q,WR .c) The resistance is set so that the active power taken from the entire oscillating circuit is equal to P WR . d) The oscillating circuit and generator are connected to the grid (S1, S2 and S3 closed) and thegenerator is put into operation.NB: The purpose of the comparison is to keep the fundamental components of the current as small as possible using S3. Fine tuning of the oscillating circuit (step 6) allows the worst possible conditions to be created in terms of possible islanding.5. To start the test, S3 is opened and the time until the device switches off is measured.6. After each successful test one parameter (L or C) is altered by approx. 1 % within the total range ofapprox. ± 5 % and the test repeated.The entire test procedure shall be carried out at P = 25 %, 50 % and 100 % of the rated output. The entire test is deemed successful if the break time for each individual test is less than 5 s.The test shall be carried out at nominal frequency ± 0.1 Hz and nominal voltage ±3 %.To test a 3-phase disconnection device, a test circuit should be connected consecutively to each of the phases, as shown in Figure 3. The other two phase lines are then connected directly to the grid. The breaks should each be triggered within 5 seconds of the break device S opening.6.5.3 Three phase voltage monitoringOnly with single-phase feeders is three-phase monitoring of the phase line voltages permissible as a criterion for island network detection. As soon as at least one phase conductor voltage exceeds the limits of 80 % U N or 115 % U N given in 4.2, a break should take place within 0.2 s. Here, the requirements regarding functional security given in 4.1 should be fulfilled, as well.NB: Three-phase voltage monitoring is also permissible where a number of single-phase feeders which feed into different phase conductors are integrated in a single unit if the currents of these feeders are controlled independently of each other so that different phase relations can be set.In order to test the voltage monitoring, the automatic disconnection device should be run via an alternating voltage source with variable amplitude at nominal alternating voltage and any output. The trigger time specified in 4.2 must not be exceeded in the case of voltage jumps which do not fall below the lower limit according to 4.2 by more than 3% of the nominal voltage and do not exceed the upper limit by more than 3% of the nominal voltage. The test should be repeated for all phase line combinations.6.6 Residual current monitoringAll tests shall be carried out at 0.85 U N , U N and 1.10 U N .NB: These voltage limits ensure that the voltage monitoring does not trigger during the test.6.6.1 Separate disconnection deviceThe residual current monitoring of a disconnection device which is not integrated in the inverter is tested in accordance with E DIN VDE 0664-100 (VDE 0664 - 100):2002-05.9.9.1 "Test circuit" to 9.9.3 "Testing of correct triggering under load at reference temperature" are applied here. In the test in 9.9.2.2 "Test for correct triggering when switching on to a residual current" it should be noted that the disconnection device can connect with a delay. In this test the break time is the time between automatic switching on and switching off due to the residual current.Functioning with pulsating direct residual currents is tested under 9.21.1. Functioning with smooth direct residual currents is tested according to 9.21.2.1 "Test of correct triggering with continuous rise of smooth direct residual current" to 9.21.2.7 "Test of correct triggering with pulsating direct residual current with superimposition of smooth direct residual current".6.6.2 Integrated disconnection deviceThe residual current monitoring of a disconnection device integrated in the inverter is tested at rated output and maximum d.c. supply voltage in accordance with the following sections.circuit6.6.2.1 TestA,variable resistor is connected between a d.c. voltage line and the neutral line (N) via a switch. In the case of an inverter with PV+ and PV- d.c. voltage connections, there are two configurations (see Figure 4): N with PV+ (R1 in Figure 4), and N with PV– (R2 in Figure 4). A variable capacitor is mounted in parallel to the resistor in the test as per 6.6.2.2.3 (C1, C2 in Figure 4).。

A general theory of phase noise in electrical oscillators

A General Theory of Phase Noisein Electrical OscillatorsAli Hajimiri,Student Member,IEEE,and Thomas H.Lee,Member,IEEE Abstract—A general model is introduced which is capableof making accurate,quantitative predictions about the phasenoise of different types of electrical oscillators by acknowledgingthe true periodically time-varying nature of all oscillators.Thisnew approach also elucidates several previously unknown designcriteria for reducing close-in phase noise by identifying the mech-anisms by which intrinsic device noise and external noise sourcescontribute to the total phase noise.In particular,it explains thedetails of how1=f noise in a device upconverts into close-inphase noise and identiﬁes methods to suppress this upconversion.The theory also naturally accommodates cyclostationary noisesources,leading to additional important design insights.Themodel reduces to previously available phase noise models asspecial cases.Excellent agreement among theory,simulations,andmeasurements is observed.Index Terms—Jitter,oscillator noise,oscillators,oscillator sta-bility,phase jitter,phase locked loops,phase noise,voltagecontrolled oscillators.I.I NTRODUCTIONT HE recent exponential growth in wireless communicationhas increased the demand for more available channels inmobile communication applications.In turn,this demand hasimposed more stringent requirements on the phase noise oflocal oscillators.Even in the digital world,phase noise in theguise of jitter is important.Clock jitter directly affects timingmargins and hence limits system performance.Phase and frequencyﬂuctuations have therefore been thesubject of numerous studies[1]–[9].Although many modelshave been developed for different types of oscillators,eachof these models makes restrictive assumptions applicable onlyto a limited class of oscillators.Most of these models arebased on a linear time invariant(LTI)system assumptionand suffer from not considering the complete mechanism bywhich electrical noise sources,such as device noise,becomephase noise.In particular,they take an empirical approach indescribing the upconversion of low frequency noise sources,suchascorner in the phase noise spectrum is smallerthanis the amplitude,0018–9200/98$10.00©1998IEEEFig.1.Typical plot of the phase noise of an oscillator versus offset fromcarrier.is an arbitrary,ﬁxed phase refer-ence.Therefore,the spectrum of an ideal oscillator with norandom ﬂuctuations is a pair of impulsesat.In a practical oscillator,however,the output is more generally givenbyandis aperiodic function with period2andrepresents the single side-band power at a frequency offsetofandis dominated by its phaseportion,,known as phase noise,which we will simplydenoteas.Fig.2.A typical RLC oscillator.The semi-empirical model proposed in [1]–[3],known also as the Leeson–Cutler phase noise model,is based on an LTI assumption for tuned tank oscillators.It predicts the followingbehaviorfor:is an empirical parameter (often called the “deviceexcess noisenumber”),is the absolutetemperature,),andregion can beobtained by applying a transfer function approach as follows.The impedance of a parallel RLC,for,is easily calculated tobeHAJIMIRI AND LEE:GENERAL THEORY OF PHASE NOISE IN ELECTRICAL OSCILLATORS181Fig.3.Phase and amplitude impulse response model.a multiplicativefactor,a priori.One importantreason is that much of the noise in a practical oscillatorarises from periodically varying processes and is thereforecyclostationary.Hence,as mentioned in[3],region of the spectrum can be calculatedasregion is thus easily obtained,the expressionforthecorner of thephase noise is the same asthe(7)whereis the effective series resistance,givenbyare shown in Fig.2.Note that itis still not clear how tocalculateinputs(each associated with one noise source)and two outputsthat are the instantaneous amplitude and excess phase of theoscillator,,as deﬁned by(1).Noise inputs to thissystem are in the form of current sources injecting into circuitnodes and voltage sources in series with circuit branches.Foreach input source,both systems can be viewed as single-input,single-output systems.The time and frequency-domainﬂuctuationsof can be studied by characterizingthe behavior of two equivalent systems shown in Fig.3.Note that both systems shown in Fig.3are time variant.Consider the speciﬁc example of an ideal parallel LC oscillatorshown in Fig.4.If we inject a current impulse as shown,the amplitude and phase of the oscillator will have responsessimilar to that shown in Fig.4(a)and(b).The instantaneousvoltagechange182IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL.33,NO.2,FEBRUARY1998(a)(b)Fig.5.(a)A typical Colpitts oscillator and (b)a ﬁve-stage minimum size ring oscillator.capacitor and will not affect the current through the inductor.It can be seen from Fig.4that the resultant changeinis time dependent.In particular,if the impulse is applied at the peak of the voltage across the capacitor,there will be no phase shift and only an amplitude change will result,as shown in Fig.4(a).On the other hand,if this impulse is applied at the zero crossing,it has the maximum effect on the excessphase,which results in no phase change and changes only the amplitude,while applying an impulse atpointm CMOS inverter chain ring oscillatorshown in Fig.5(b).The results are shown in Fig.6(a)and (b),respectively.The impulse is applied close to a zerocrossing,(a)(b)Fig.6.Phase shift versus injected charge for oscillators of Fig.5(a)and (b).where it has the maximum effect on phase.As can be seen,the current-phase relation is linear for values of charge up to 10%of the total charge on the effective capacitance of the node of interest.Also note that the effective injected charges due to actual noise and interference sources in practical circuits are several orders of magnitude smaller than the amounts of charge injected in Fig.6.Thus,the assumption of linearity is well satisﬁed in all practical oscillators.It is critical to note that the current-to-phase transfer func-tion is practically linear even though the active elements may have strongly nonlinear voltage-current behavior.However,the nonlinearity of the circuit elements deﬁnes the shape of the limit cycle and has an important inﬂuence on phase noise that will be accounted for shortly.We have thus far demonstrated linearity,with the amount of excess phase proportional to the ratio of the injected charge to the maximum charge swing across the capacitor on the node,i.e.,when the impulseis injected.Therefore,the unit impulse response for excess phase can be expressedas(10)whereis the unit step.Wecallwhich describes how much phase shift results fromapplying a unit impulse attimeis a function of the waveformor,equivalently,the shape of the limit cycle which,in turn,is governed by the nonlinearity and the topology of the oscillator.Given the ISF,the output excessphaseHAJIMIRI AND LEE:GENERAL THEORY OF PHASE NOISE IN ELECTRICAL OSCILLATORS183(a)(b)Fig.7.Waveforms and ISF’s for(a)a typical LC oscillator and(b)a typical ring oscillator.where represents the input noise current injected into the node of interest.Since the ISF is periodic,it can be expanded in a Fourierseriesth harmonic.As will be seenlater,for an arbitrary inputcurrent injected into any circuit node,once the variousFourier coefﬁcients of the ISF have been found.As an illustrative special case,suppose that we inject a lowfrequency sinusoidal perturbation current into the node ofinterest at a frequencyof(14)where.The argumentsof all the integrals in(13)are at frequencies higherthanand are signiﬁcantly attenuated by the averaging nature ofthe integration,except the term arising from theﬁrst integral,whichinvolves.Therefore,the only signiﬁcant termin,denotedas.As an important second special case,consider a current at afrequency close to the carrier injected into the node of interest,givenby.A process similar to thatof the previous case occurs except that the spectrumofFig.8.Conversion of the noise around integer multiples of the oscillationfrequency into phase noise.consists of two impulsesat as shown in Fig.8.This time the only integral in(13)which will have a lowfrequency argument isfor is givenby.More generally,(13)suggests that applying acurrentclose to any integer multiple of theoscillation frequency will result in two equal sidebandsat.Hence,in the generalcaseusing(13).Computing the power spectral density(PSD)of the oscillatoroutputvoltage requires knowledge of how the outputvoltage relates to the excess phase variations.As shown inFig.8,the conversion of device noise current to output voltagemay be treated as the result of a cascade of two processes.Theﬁrst corresponds to a linear time variant(LTV)current-to-phase converter discussed above,while the second is anonlinear system that represents a phase modulation(PM),which transforms phase to voltage.To obtain the sidebandpower around the fundamental frequency,the fundamentalharmonic of the oscillatoroutputas the input.Substitutinggiven by(17).Therefore,an injected currentat(18)184IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL.33,NO.2,FEBRUARY1998(a)(b)Fig.9.Simulated power spectrum of the output with current injection at(a) f m=50MHz and(b)f0+f m=1:06GHz.This process is shown in Fig.8.Appearance of the frequencydeviation.This type of nonlinearity does not directlyappear in the phase transfer characteristic and shows itself onlyindirectly in the ISF.It is instructive to compare the predictions of(18)withsimulation results.A sinusoidal current of10MHz.This power spectrum is obtained usingthe fast Fourier transform(FFT)analysis in HSPICE96.1.Itis noteworthy that in this version of HSPICE the simulationartifacts observed in[9]have been properly eliminated bycalculation of the values used in the analysis at the exactpoints of interest.Note that the injected noise is upconvertedinto two equal sidebandsat,where is the average capacitance on each node of thecircuitand is the maximum swing across it.For thisoscillator,–whose power spectral density has both aﬂat region anda,which in turn becomeclose-in phase noise in the spectrumof,as illustrated inFig.11.It can be seen that thetotal is given by the sumof phase noise contributions from device noise in the vicinityof the integer multiplesof,weighted by thecoefﬁcients.This is shown in Fig.12(a)(logarithmic frequency scale).The resulting single sideband spectral noisedensity isplotted on a logarithmic scale in Fig.12(b).The sidebands inthe spectrumof,in turn,result in phase noise sidebandsin the spectrumof through the PM mechanism discussin the previous subsection.This process is shown in Figs.11and12.The theory predicts the existenceof,andﬂatregions for the phase noise spectrum.The low-frequency noisesources,such asﬂicker noise,are weighted by thecoefﬁcientand showaHAJIMIRI AND LEE:GENERAL THEORY OF PHASE NOISE IN ELECTRICAL OSCILLATORS185Fig.11.Conversion of noise to phase ﬂuctuations and phase-noise side-bands.the white noise terms are weighted byother coefﬁcients and give rise tothecontainsregions.Finally,the ﬂat noise ﬂoor in Fig.12(b)arises from the white noise ﬂoor of the noise sources in the oscillator.The total sideband noise power is the sum of these two as shown by the bold line in the same ﬁgure.To carry out a quantitative analysis of the phase noise sideband power,now consider an input noise current with a white power spectraldensityHz.Based on the foregoing development and (18),the total single sideband phase noise spectral density in dB below the carrier per unit bandwidth due to the source on one node at an offset frequencyof(20)where.As aresultregion of the phase noise spectrum.For a voltage noise source in series with aninductor,,wherecorner of thephase noise.It is important to note that it is by nomeans(a)(b)Fig.12.(a)PSD of (t )and (b)single sideband phase noise power spectrum,L f 1!g .obvious from the foregoing development thatthecanbe describedby(22)whereportion of the phasenoisespectrum:corner,corner in the phase noisespectrum:phase noise corner due to internal noisesources is not equal tothe186IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL.33,NO.2,FEBRUARY1998Fig.13.Collector voltage and collector current of the Colpitts oscillator of Fig.5(a).D.Cyclostationary Noise SourcesIn addition to the periodically time-varying nature of the system itself,another complication is that the statistical prop-erties of some of the random noise sources in the oscillator may change with time in a periodic manner.These sources are referred to as cyclostationary.For instance,the channel noise of a MOS device in an oscillator is cyclostationary because the noise power is modulated by the gate source overdrive which varies with time periodically.There are other noise sources in the circuit whose statistical properties do not depend on time and the operation point of the circuit,and are therefore called stationary.Thermal noise of a resistor is an example of a stationary noise source.A white cyclostationary noise current can be decom-posed as[13]:is a white cyclostationaryprocess,is awhite stationary processandis a deterministic periodic function describing the noise amplitude modulation.Wedeﬁneto be a normalized function with a maximum value of1.Thisway,is equal to the maximum mean square noisepower,,which changes periodically with time.Applying the above expression forto(11),(27)wherecan be derived easily from device noise character-istics and operating point.Hence,this effective ISF shouldbeFig.14.0(x ),0e (x ),and (x )for the Colpitts oscillator of Fig.5(a).used in all subsequent calculations,in particular,calculation of thecoefﬁcients .Note that there is a strong correlation between the cyclosta-tionary noise source and the waveform of the oscillator.The maximum of the noise power always appears at a certain point of the oscillatory waveform,thus the average of the noise may not be a good representation of the noise power.Consider as one example the Colpitts oscillator of Fig.5(a).The collector voltage and the collector current of the transistor are shown in Fig.13.Note that the collector current consists of a short period of large current followed by a quiet interval.The surge of current occurs at the minimum of the voltageacross the tank where the ISF is small.Functions,andfor this oscillator are shown in Fig.14.Note that,in thiscase,is quite differentfrom is at a maximum,i.e.,thesensitivity is large)at the same time the noise power is large.Functions,and for the ring oscillator of Fig.5(b)are shown in Fig.15.Note that in the case of theringoscillatorare almost identical.This indicates that the cyclostationary properties of the noise are less important in the treatment of the phase noise of ring oscillators.This unfortunate coincidence is one of the reasons why ring oscillators in general have inferior phase noise performance compared to a Colpitts LC oscillator.The other important reason is that ring oscillators dissipate all the stored energy during one cycle.E.Predicting Output Phase Noise with Multiple Noise Sources The method of analysis outlined so far has been used to predict how much phase noise is contributed by a single noise source.However,this method may be extended to multiple noise sources and multiple nodes,as individual contributions by the various noise sources may be combined by exploiting superposition.Superposition holds because the ﬁrst system of Fig.8is linear.HAJIMIRI AND LEE:GENERAL THEORY OF PHASE NOISE IN ELECTRICAL OSCILLATORS187Fig.15.0(x ),0e (x ),and (x )for the ring oscillator of Fig.5(b).The actual method of combining the individual contributions requires attention to any possible correlations that may exist among the noise sources.The complete method for doing so may be appreciated by noting that an oscillator has a current noise source in parallel with each capacitor and a voltage noise source in series with each inductor.The phase noise in the output of such an oscillator is calculated using the following method.1)Find the equivalent current noise source in parallel with each capacitor and an equivalent voltage source in series with each inductor,keeping track of correlated and noncorrelated portions of the noise sources for use in later steps.2)Find the transfer characteristic from each source to the output excess phase.This can be done as follows.a)Find the ISF for each source,using any of the methods proposed in the Appendix,depending on the required accuracy and simplicity.b)Find,the amount of charge swing across the effec-tive capacitor it is injectingintois the tank capacitor,andis the maximum voltage swing across the tank.Equation (19)reducesto,the result obtained in [8]istwo times larger than the result of (29).Assuming that the total noise contribution in a parallel tank oscillator can be modeled using an excess noisefactorandfor valuesofregionare suggested by (24),which shows thatthe188IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL.33,NO.2,FEBRUARY1998(a)(b)(c)(d)Fig.16.(a)Waveform and (b)ISF for the asymmetrical node.(c)Waveform and (d)ISF for one of the symmetrical nodes.waveform.One such property concerns the rise and fall times;the ISF will have a large dc value if the rise and fall times of the waveform are signiﬁcantly different.A limited case of this for odd-symmetric waveforms has been observed [14].Although odd-symmetric waveforms havesmall coefﬁcients,the class of waveforms withsmall is not limited to odd-symmetric waveforms.To illustrate the effect of a rise and fall time asymmetry,consider a purposeful imbalance of pull-up and pull-down rates in one of the inverters in the ring oscillator of Fig.5(b).This is obtained by halving the channelwidthAatMHz is applied to one of the symmetric nodes ofthe(a)(b)Fig.17.Simulated power spectrum with current injection at f m =50MHz for (a)asymmetrical node and (b)symmetrical node.oscillator.In the second experiment,the same source is applied to the asymmetric node.As can be seen from the power spectra of the ﬁgure,noise injected into the asymmetric node results in sidebands that are 12dB larger than at the symmetric node.Note that (30)suggests that upconversion of low frequency noise can be signiﬁcantly reduced,perhaps even eliminated,byminimizing ,at least in principle.Sincedepends on the waveform,this observation implies that a proper choice of waveform may yield signiﬁcant improvements in close-in phase noise.The following experiment explores this concept by changing the ratioofA of sinusoidal current at 100MHz intoone node.The sideband power below carrier as a function oftheA at 50MHz injected at the drain node of one of the buffer stages results in two equal sidebands,Fig.18.Simulated and predicted sideband power for low frequency injection versus PMOS to NMOS W=Lratio.Fig.19.Four-stage differential ring oscillator.upconversion of noise to close-in phase noise,even though differential signaling is used.Since the asymmetry is due to the voltage dependent con-ductance of the load,reduction of the upconversion might be achieved through the use of a perfectly linear resistive load,because the rising and falling behavior is governed by an RC time constant and makes the individual waveforms more symmetrical.It was ﬁrst observed in the context of supply noise rejection [15],[16]that using more linear loads can reduce the effect of supply noise on timing jitter.Our treatment shows that it also improves low-frequency noise upconversion into phase noise.Another symmetry-related property is duty cycle.Since the ISF is waveform-dependent,the duty cycle of a waveform is linked to the duty cycle of the ISF.Non-50%duty cyclesgenerally result inlargerforeven tank of an LC oscillator is helpful in this context,since ahighMHz,MHz,and MHz,and the sideband powersatis proportionalto,and hence the sideband power is proportionaltoA (rms)at20dB/decade,again in complete accordance with (18).The third experiment aims at verifying the effect of thecoefﬁcientson the sideband power.One of the predictions of the theory isthatis responsible for the upconver-sion of low frequency noise.As mentionedbefore,is a strong function of waveform symmetry at the node into which the current is injected.Noise injected into a node with an asymmetric waveform (created by making one inverter asymmetric in a ring oscillator)would result in a greater increase in sideband power than injection into nodes with more symmetric waveforms.Fig.22shows the results of an experiment performed on a ﬁve-stage ring oscillator in which one of the stages is modiﬁed to have an extra pulldownFig.21.Measured sideband power versus f m ,for injections in vicinity of multiples of f 0.Fig.22.Power of the sidebands caused by low frequency injection into symmetric and asymmetric nodes of the ring oscillator.NMOS device.A current of20m,5-V CMOS process runningatandregion.For thisprocess we have a gate oxide thicknessofnm and threshold voltagesofVand mandm m,and a lateral diffusionof fF.Therefore,Fig.23.Phase noise measurements for a ﬁve-stage single-ended CMOS ring oscillator.f 0=232MHz,2- m processtechnology.identical noise sources thenpredictskHz,this equationpredictskHz dBc/Hz,in good agreement with a measurementofregion,it is enough to calculatetheratio iscalculated to be 0.3,which predictsamandmm,whichresults in a total capacitance of 43.5fFand,or122.5d B c /H z ,a g a i n i na g r e e m e n t w i t h p r e d i c t i o n s .T h e r a t i o i s c a l c u l a t e t ob e 0.17w h ic h p r ed i c t sar e g i o n b e h a v i o r .I t i n v o l v e s a s e v es t a r v e d ,s i n g l e -e n d e d r i n g o s c i l l a t o r i s t a g e c o n s i s t s o f a n a d d i t i o n a l N M O S a i n s e r i e s .T h e g a t e d r i v e s o f t h e a d d e d i n d e p e n d e n t c o n t r o l o f t h e r i s e a n d f a l l t h e p h a s e n o i s e w h e n t h e c o n t r o l v o l t a g a c h i e v e s y m m e t r y v e r s u s w h e n t h e y a r e n c o n t r o l v o l t a g e s a r e a d j u s t e d t o k e e p t h eFig.24.Phase noise measurements for an 11-stage single-ended CMOS ring oscillator.f 0=115MHz,2- m processtechnology.Fig.25.Effect of symmetry in a seven-stage current-starved single-ended CMOS VCO.f 0=60MHz,2- m process technology.constant at 60MHz.As can be seen,making the waveform more symmetric has a large effect on the phase noise intheregion.Another experiment on the same circuit is shown in Fig.26,which shows the phase noise power spectrum at a 10kHz offset versus the symmetry-controlling voltage.For all the data points,the control voltages are adjusted to keep the oscillation frequency at 50MHz.As can be seen,the phase noise reaches a minimum by adjusting the symmetry properties of the waveform.This reduction is limited by the phase noiseinm CMOS process.Each stage istapped with an equal-sized buffer.The tail current source has a quiescent current of108fFand the voltage swingisV,which resultsin fF.The total channel noise current on eachnodeFig.26.Sideband power versus the voltage controlling the symmetry of the waveform.Seven-stage current-starved single-ended CMOS VCO.f 0=50MHz,2- m processtechnology.Fig.27.Phase noise measurements for a four-stage differential CMOS ring oscillator.f 0=200MHz,0.5- m process technology.is,the phase noise inthe,or103.9d B c /H z ,a g a i n i n a g r e e m e n t w i tA l s o n o t e t h a t d e s p i t e d i f f e r e n t i a l s y m m e trw h i l e k e e p i n g t h e e f f e c t i v ec a p a c i t a n ce c o n s t a n t t o m a i n t a iand e c r e a s e s t h e c o n d u c t i o n a n g l e ,a n d t h e r e f f e c t i ve.T h e p h a s e n o i s e u l t i m a t e l y i n c r e a s e s(h e r e ,a b o u t0.2)t h a t m i n i m i z e s t h e p h a s e n o i s e .T h i s r t h e o r e t i c a l b a s i s f o r t h e c o m m o n r u l e -o f -t hFig.28.Sideband power versus capacitive division ratio.Bipolar LC Colpitts oscillator f 0=100MHz.use)inColpitts oscillators [17].VI.C ONCLUSIONThis paper has presented a model for phase noise which explains quantitatively the mechanism by which noise sources of all types convert to phase noise.The power of the model derives from its explicit recognition of practical oscillators as time-varying systems.Characterizing an oscillator with the ISF allows a complete description of the noise sensitivity of an oscillator and also allows a natural accommodation of cyclostationary noise sources.This approach shows that noise located near integer mul-tiples of the oscillation frequency contributes to the total phase noise.The model speciﬁes the contribution of those noise components in terms of waveform properties and circuit parameters,and therefore provides important design insight by identifying and quantifying the major sources of phase noise degradation.In particular,it shows that symmetry properties of the oscillator waveform have a signiﬁcant effect on the upconversion of low frequency noise and,hence,thefromit.The second method is based on an analytical state-space approach to ﬁnd the excess phase change caused by an impulse of current from the oscillation waveforms.The third method is an easy-to-use approximate method.A.Direct Measurement of Impulse ResponseIn this method,an impulse is injected at different relative phases of the oscillation waveform and the oscillatorsimulatedFig.29.State-space trajectory of an n th-order oscillator.for a few cycles afterwards.By sweeping the impulse injec-tion time across one cycle of the waveform and measuring the resulting timeshiftis the period of oscillation.Fortunately,many implementations of SPICE have an internal feature to perform the sweep automatically.Since for each impulse one needs to simulate the oscillator for only a few cycles,the simulation executes rapidly.Onceth-order system can be represented by its trajectory inanwhich suddenly changes the state of the systemto.As discussed earlier,amplitude variations eventually die away,but phase variations do not.Application of the perturbation impulse causes a certain change in phase in either a negative or positive direction,depending on the state-vector and the direction of the perturbation.To calculate the equivalent time shift,we ﬁrst ﬁnd the projection of the perturbation vector on a unity vector in the direction of motion,i.e.,the normalized velocityvectoris the equivalent displacement along the trajectory,and,which arises from the projection operation.Theequivalent time shift is given by the displacement divided by。

jstd035声学扫描

JOINT INDUSTRY STANDARDAcoustic Microscopy for Non-HermeticEncapsulatedElectronicComponents IPC/JEDEC J-STD-035APRIL1999Supersedes IPC-SM-786 Supersedes IPC-TM-650,2.6.22Notice EIA/JEDEC and IPC Standards and Publications are designed to serve thepublic interest through eliminating misunderstandings between manufacturersand purchasers,facilitating interchangeability and improvement of products,and assisting the purchaser in selecting and obtaining with minimum delaythe proper product for his particular need.Existence of such Standards andPublications shall not in any respect preclude any member or nonmember ofEIA/JEDEC or IPC from manufacturing or selling products not conformingto such Standards and Publications,nor shall the existence of such Standardsand Publications preclude their voluntary use by those other than EIA/JEDECand IPC members,whether the standard is to be used either domestically orinternationally.Recommended Standards and Publications are adopted by EIA/JEDEC andIPC without regard to whether their adoption may involve patents on articles,materials,or processes.By such action,EIA/JEDEC and IPC do not assumeany liability to any patent owner,nor do they assume any obligation whateverto parties adopting the Recommended Standard or ers are alsowholly responsible for protecting themselves against all claims of liabilities forpatent infringement.The material in this joint standard was developed by the EIA/JEDEC JC-14.1Committee on Reliability Test Methods for Packaged Devices and the IPCPlastic Chip Carrier Cracking Task Group(B-10a)The J-STD-035supersedes IPC-TM-650,Test Method2.6.22.For Technical Information Contact:Electronic Industries Alliance/ JEDEC(Joint Electron Device Engineering Council)2500Wilson Boulevard Arlington,V A22201Phone(703)907-7560Fax(703)907-7501IPC2215Sanders Road Northbrook,IL60062-6135 Phone(847)509-9700Fax(847)509-9798Please use the Standard Improvement Form shown at the end of thisdocument.©Copyright1999.The Electronic Industries Alliance,Arlington,Virginia,and IPC,Northbrook,Illinois.All rights reserved under both international and Pan-American copyright conventions.Any copying,scanning or other reproduction of these materials without the prior written consent of the copyright holder is strictly prohibited and constitutes infringement under the Copyright Law of the United States.IPC/JEDEC J-STD-035Acoustic Microscopyfor Non-Hermetic EncapsulatedElectronicComponentsA joint standard developed by the EIA/JEDEC JC-14.1Committee on Reliability Test Methods for Packaged Devices and the B-10a Plastic Chip Carrier Cracking Task Group of IPCUsers of this standard are encouraged to participate in the development of future revisions.Contact:EIA/JEDEC Engineering Department 2500Wilson Boulevard Arlington,V A22201 Phone(703)907-7500 Fax(703)907-7501IPC2215Sanders Road Northbrook,IL60062-6135 Phone(847)509-9700Fax(847)509-9798ASSOCIATION CONNECTINGELECTRONICS INDUSTRIESAcknowledgmentMembers of the Joint IPC-EIA/JEDEC Moisture Classiﬁcation Task Group have worked to develop this document.We would like to thank them for their dedication to this effort.Any Standard involving a complex technology draws material from a vast number of sources.While the principal members of the Joint Moisture Classiﬁcation Working Group are shown below,it is not possible to include all of those who assisted in the evolution of this Standard.To each of them,the mem-bers of the EIA/JEDEC and IPC extend their gratitude.IPC Packaged Electronic Components Committee ChairmanMartin FreedmanAMP,Inc.IPC Plastic Chip Carrier Cracking Task Group,B-10a ChairmanSteven MartellSonoscan,Inc.EIA/JEDEC JC14.1CommitteeChairmanJack McCullenIntel Corp.EIA/JEDEC JC14ChairmanNick LycoudesMotorolaJoint Working Group MembersCharlie Baker,TIChristopher Brigham,Hi/FnRalph Carbone,Hewlett Packard Co. Don Denton,TIMatt Dotty,AmkorMichele J.DiFranza,The Mitre Corp. Leo Feinstein,Allegro Microsystems Inc.Barry Fernelius,Hewlett Packard Co. Chris Fortunko,National Institute of StandardsRobert J.Gregory,CAE Electronics, Inc.Curtis Grosskopf,IBM Corp.Bill Guthrie,IBM Corp.Phil Johnson,Philips Semiconductors Nick Lycoudes,MotorolaSteven R.Martell,Sonoscan Inc. Jack McCullen,Intel Corp.Tom Moore,TIDavid Nicol,Lucent Technologies Inc.Pramod Patel,Advanced Micro Devices Inc.Ramon R.Reglos,XilinxCorazon Reglos,AdaptecGerald Servais,Delphi Delco Electronics SystemsRichard Shook,Lucent Technologies Inc.E.Lon Smith,Lucent Technologies Inc.Randy Walberg,NationalSemiconductor Corp.Charlie Wu,AdaptecEdward Masami Aoki,HewlettPackard LaboratoriesFonda B.Wu,Raytheon Systems Co.Richard W.Boerdner,EJE ResearchVictor J.Brzozowski,NorthropGrumman ES&SDMacushla Chen,Wus Printed CircuitCo.Ltd.Jeffrey C.Colish,Northrop GrummanCorp.Samuel J.Croce,Litton AeroProducts DivisionDerek D-Andrade,Surface MountTechnology CentreRao B.Dayaneni,Hewlett PackardLaboratoriesRodney Dehne,OEM WorldwideJames F.Maguire,Boeing Defense&Space GroupKim Finch,Boeing Defense&SpaceGroupAlelie Funcell,Xilinx Inc.Constantino J.Gonzalez,ACMEMunir Haq,Advanced Micro DevicesInc.Larry A.Hargreaves,DC.ScientiﬁcInc.John T.Hoback,Amoco ChemicalCo.Terence Kern,Axiom Electronics Inc.Connie M.Korth,K-Byte/HibbingManufacturingGabriele Marcantonio,NORTELCharles Martin,Hewlett PackardLaboratoriesRichard W.Max,Alcatel NetworkSystems Inc.Patrick McCluskey,University ofMarylandJames H.Moffitt,Moffitt ConsultingServicesRobert Mulligan,Motorola Inc.James E.Mumby,CibaJohn Northrup,Lockheed MartinCorp.Dominique K.Numakura,LitchﬁeldPrecision ComponentsNitin B.Parekh,Unisys Corp.Bella Poborets,Lucent TechnologiesInc.D.Elaine Pope,Intel Corp.Ray Prasad,Ray Prasad ConsultancyGroupAlbert Puah,Adaptec Inc.William Sepp,Technic Inc.Ralph W.Taylor,Lockheed MartinCorp.Ed R.Tidwell,DSC CommunicationsCorp.Nick Virmani,Naval Research LabKen Warren,Corlund ElectronicsCorp.Yulia B.Zaks,Lucent TechnologiesInc.IPC/JEDEC J-STD-035April1999 iiTable of Contents1SCOPE (1)2DEFINITIONS (1)2.1A-mode (1)2.2B-mode (1)2.3Back-Side Substrate View Area (1)2.4C-mode (1)2.5Through Transmission Mode (2)2.6Die Attach View Area (2)2.7Die Surface View Area (2)2.8Focal Length(FL) (2)2.9Focus Plane (2)2.10Leadframe(L/F)View Area (2)2.11Reﬂective Acoustic Microscope (2)2.12Through Transmission Acoustic Microscope (2)2.13Time-of-Flight(TOF) (3)2.14Top-Side Die Attach Substrate View Area (3)3APPARATUS (3)3.1Reﬂective Acoustic Microscope System (3)3.2Through Transmission AcousticMicroscope System (4)4PROCEDURE (4)4.1Equipment Setup (4)4.2Perform Acoustic Scans..........................................4Appendix A Acoustic Microscopy Defect CheckSheet (6)Appendix B Potential Image Pitfalls (9)Appendix C Some Limitations of AcousticMicroscopy (10)Appendix D Reference Procedure for PresentingApplicable Scanned Data (11)FiguresFigure1Example of A-mode Display (1)Figure2Example of B-mode Display (1)Figure3Example of C-mode Display (2)Figure4Example of Through Transmission Display (2)Figure5Diagram of a Reﬂective Acoustic MicroscopeSystem (3)Figure6Diagram of a Through Transmission AcousticMicroscope System (3)April1999IPC/JEDEC J-STD-035iiiIPC/JEDEC J-STD-035April1999This Page Intentionally Left BlankivApril1999IPC/JEDEC J-STD-035 Acoustic Microscopy for Non-Hermetic EncapsulatedElectronic Components1SCOPEThis test method deﬁnes the procedures for performing acoustic microscopy on non-hermetic encapsulated electronic com-ponents.This method provides users with an acoustic microscopy processﬂow for detecting defects non-destructively in plastic packages while achieving reproducibility.2DEFINITIONS2.1A-mode Acoustic data collected at the smallest X-Y-Z region deﬁned by the limitations of the given acoustic micro-scope.An A-mode display contains amplitude and phase/polarity information as a function of time ofﬂight at a single point in the X-Y plane.See Figure1-Example of A-mode Display.IPC-035-1 Figure1Example of A-mode Display2.2B-mode Acoustic data collected along an X-Z or Y-Z plane versus depth using a reﬂective acoustic microscope.A B-mode scan contains amplitude and phase/polarity information as a function of time ofﬂight at each point along the scan line.A B-mode scan furnishes a two-dimensional(cross-sectional)description along a scan line(X or Y).See Figure2-Example of B-mode Display.IPC-035-2 Figure2Example of B-mode Display(bottom half of picture on left)2.3Back-Side Substrate View Area(Refer to Appendix A,Type IV)The interface between the encapsulant and the back of the substrate within the outer edges of the substrate surface.2.4C-mode Acoustic data collected in an X-Y plane at depth(Z)using a reﬂective acoustic microscope.A C-mode scan contains amplitude and phase/polarity information at each point in the scan plane.A C-mode scan furnishes a two-dimensional(area)image of echoes arising from reﬂections at a particular depth(Z).See Figure3-Example of C-mode Display.1IPC/JEDEC J-STD-035April1999IPC-035-3 Figure3Example of C-mode Display2.5Through Transmission Mode Acoustic data collected in an X-Y plane throughout the depth(Z)using a through trans-mission acoustic microscope.A Through Transmission mode scan contains only amplitude information at each point in the scan plane.A Through Transmission scan furnishes a two-dimensional(area)image of transmitted ultrasound through the complete thickness/depth(Z)of the sample/component.See Figure4-Example of Through Transmission Display.IPC-035-4 Figure4Example of Through Transmission Display2.6Die Attach View Area(Refer to Appendix A,Type II)The interface between the die and the die attach adhesive and/or the die attach adhesive and the die attach substrate.2.7Die Surface View Area(Refer to Appendix A,Type I)The interface between the encapsulant and the active side of the die.2.8Focal Length(FL)The distance in water at which a transducer’s spot size is at a minimum.2.9Focus Plane The X-Y plane at a depth(Z),which the amplitude of the acoustic signal is maximized.2.10Leadframe(L/F)View Area(Refer to Appendix A,Type V)The imaged area which extends from the outer L/F edges of the package to the L/F‘‘tips’’(wedge bond/stitch bond region of the innermost portion of the L/F.)2.11Reflective Acoustic Microscope An acoustic microscope that uses one transducer as both the pulser and receiver. (This is also known as a pulse/echo system.)See Figure5-Diagram of a Reﬂective Acoustic Microscope System.2.12Through Transmission Acoustic Microscope An acoustic microscope that transmits ultrasound completely through the sample from a sending transducer to a receiver on the opposite side.See Figure6-Diagram of a Through Transmis-sion Acoustic Microscope System.2April1999IPC/JEDEC J-STD-0353IPC/JEDEC J-STD-035April1999 3.1.6A broad band acoustic transducer with a center frequency in the range of10to200MHz for subsurface imaging.3.2Through Transmission Acoustic Microscope System(see Figure6)comprised of:3.2.1Items3.1.1to3.1.6above3.2.2Ultrasonic pulser(can be a pulser/receiver as in3.1.1)3.2.3Separate receiving transducer or ultrasonic detection system3.3Reference packages or standards,including packages with delamination and packages without delamination,for use during equipment setup.3.4Sample holder for pre-positioning samples.The holder should keep the samples from moving during the scan and maintain planarity.4PROCEDUREThis procedure is generic to all acoustic microscopes.For operational details related to this procedure that apply to a spe-ciﬁc model of acoustic microscope,consult the manufacturer’s operational manual.4.1Equipment Setup4.1.1Select the transducer with the highest useable ultrasonic frequency,subject to the limitations imposed by the media thickness and acoustic characteristics,package conﬁguration,and transducer availability,to analyze the interfaces of inter-est.The transducer selected should have a low enough frequency to provide a clear signal from the interface of interest.The transducer should have a high enough frequency to delineate the interface of interest.Note:Through transmission mode may require a lower frequency and/or longer focal length than reﬂective mode.Through transmission is effective for the initial inspection of components to determine if defects are present.4.1.2Verify setup with the reference packages or standards(see3.3above)and settings that are appropriate for the trans-ducer chosen in4.1.1to ensure that the critical parameters at the interface of interest correlate to the reference standard uti-lized.4.1.3Place units in the sample holder in the coupling medium such that the upper surface of each unit is parallel with the scanning plane of the acoustic transducer.Sweep air bubbles away from the unit surface and from the bottom of the trans-ducer head.4.1.4At aﬁxed distance(Z),align the transducer and/or stage for the maximum reﬂected amplitude from the top surface of the sample.The transducer must be perpendicular to the sample surface.4.1.5Focus by maximizing the amplitude,in the A-mode display,of the reﬂection from the interface designated for imag-ing.This is done by adjusting the Z-axis distance between the transducer and the sample.4.2Perform Acoustic Scans4.2.1Inspect the acoustic image(s)for any anomalies,verify that the anomaly is a package defect or an artifact of the imaging process,and record the results.(See Appendix A for an example of a check sheet that may be used.)To determine if an anomaly is a package defect or an artifact of the imaging process it is recommended to analyze the A-mode display at the location of the anomaly.4.2.2Consider potential pitfalls in image interpretation listed in,but not limited to,Appendix B and some of the limita-tions of acoustic microscopy listed in,but not limited to,Appendix C.If necessary,make adjustments to the equipment setup to optimize the results and rescan.4April1999IPC/JEDEC J-STD-035 4.2.3Evaluate the acoustic images using the failure criteria speciﬁed in other appropriate documents,such as J-STD-020.4.2.4Record the images and theﬁnal instrument setup parameters for documentation purposes.An example checklist is shown in Appendix D.5IPC/JEDEC J-STD-035April19996April1999IPC/JEDEC J-STD-035Appendix AAcoustic Microscopy Defect Check Sheet(continued)CIRCUIT SIDE SCANImage File Name/PathDelamination(Type I)Die Circuit Surface/Encapsulant Number Affected:Average%Location:Corner Edge Center (Type II)Die/Die Attach Number Affected:Average%Location:Corner Edge Center (Type III)Encapsulant/Substrate Number Affected:Average%Location:Corner Edge Center (Type V)Interconnect tip Number Affected:Average%Interconnect Number Affected:Max.%Length(Type VI)Intra-Laminate Number Affected:Average%Location:Corner Edge Center Comments:CracksAre cracks present:Yes NoIf yes:Do any cracks intersect:bond wire ball bond wedge bond tab bump tab leadDoes crack extend from leadﬁnger to any other internal feature:Yes NoDoes crack extend more than two-thirds the distance from any internal feature to the external surfaceof the package:Yes NoAdditional veriﬁcation required:Yes NoComments:Mold Compound VoidsAre voids present:Yes NoIf yes:Approx.size Location(if multiple voids,use comment section)Do any voids intersect:bond wire ball bond wedge bond tab bump tab lead Additional veriﬁcation required:Yes NoComments:7IPC/JEDEC J-STD-035April1999Appendix AAcoustic Microscopy Defect Check Sheet(continued)NON-CIRCUIT SIDE SCANImage File Name/PathDelamination(Type IV)Encapsulant/Substrate Number Affected:Average%Location:Corner Edge Center (Type II)Substrate/Die Attach Number Affected:Average%Location:Corner Edge Center (Type V)Interconnect Number Affected:Max.%LengthLocation:Corner Edge Center (Type VI)Intra-Laminate Number Affected:Average%Location:Corner Edge Center (Type VII)Heat Spreader Number Affected:Average%Location:Corner Edge Center Additional veriﬁcation required:Yes NoComments:CracksAre cracks present:Yes NoIf yes:Does crack extend more than two-thirds the distance from any internal feature to the external surfaceof the package:Yes NoAdditional veriﬁcation required:Yes NoComments:Mold Compound VoidsAre voids present:Yes NoIf yes:Approx.size Location(if multiple voids,use comment section)Additional veriﬁcation required:Yes NoComments:8Appendix BPotential Image PitfallsOBSERV ATIONS CAUSES/COMMENTSUnexplained loss of front surface signal Gain setting too lowSymbolization on package surfaceEjector pin knockoutsPin1and other mold marksDust,air bubbles,ﬁngerprints,residueScratches,scribe marks,pencil marksCambered package edgeUnexplained loss of subsurface signal Gain setting too lowTransducer frequency too highAcoustically absorbent(rubbery)ﬁllerLarge mold compound voidsPorosity/high concentration of small voidsAngled cracks in package‘‘Dark line boundary’’(phase cancellation)Burned molding compound(ESD/EOS damage)False or spotty indication of delamination Low acoustic impedance coating(polyimide,gel)Focus errorIncorrect delamination gate setupMultilayer interference effectsFalse indication of adhesion Gain set too high(saturation)Incorrect delamination gate setupFocus errorOverlap of front surface and subsurface echoes(transducerfrequency too low)Fluidﬁlling delamination areasApparent voiding around die edge Reﬂection from wire loopsIncorrect setting of void gateGraded intensity Die tilt or lead frame deformation Sample tiltApril1999IPC/JEDEC J-STD-0359Appendix CSome Limitations of Acoustic MicroscopyAcoustic microscopy is an analytical technique that provides a non-destructive method for examining plastic encapsulated components for the existence of delaminations,cracks,and voids.This technique has limitations that include the following: LIMITATION REASONAcoustic microscopy has difficulty inﬁnding small defects if the package is too thick.The ultrasonic signal becomes more attenuated as a function of two factors:the depth into the package and the transducer fre-quency.The greater the depth,the greater the attenuation.Simi-larly,the higher the transducer frequency,the greater the attenu-ation as a function of depth.There are limitations on the Z-axis(axial)resolu-tion.This is a function of the transducer frequency.The higher the transducer frequency,the better the resolution.However,the higher frequency signal becomes attenuated more quickly as a function of depth.There are limitations on the X-Y(lateral)resolu-tion.The X-Y(lateral)resolution is a function of a number of differ-ent variables including:•Transducer characteristics,including frequency,element diam-eter,and focal length•Absorption and scattering of acoustic waves as a function of the sample material•Electromechanical properties of the X-Y stageIrregularly shaped packages are difficult to analyze.The technique requires some kind ofﬂat reference surface.Typically,the upper surface of the package or the die surfacecan be used as references.In some packages,cambered packageedges can cause difficulty in analyzing defects near the edgesand below their surfaces.Edge Effect The edges cause difficulty in analyzing defects near the edge ofany internal features.IPC/JEDEC J-STD-035April1999 10April1999IPC/JEDEC J-STD-035Appendix DReference Procedure for Presenting Applicable Scanned DataMost of the settings described may be captured as a default for the particular supplier/product with speciﬁc changes recorded on a sample or lot basis.Setup Conﬁguration(Digital Setup File Name and Contents)Calibration Procedure and Calibration/Reference Standards usedTransducerManufacturerModelCenter frequencySerial numberElement diameterFocal length in waterScan SetupScan area(X-Y dimensions)Scan step sizeHorizontalVerticalDisplayed resolutionHorizontalVerticalScan speedPulser/Receiver SettingsGainBandwidthPulseEnergyRepetition rateReceiver attenuationDampingFilterEcho amplitudePulse Analyzer SettingsFront surface gate delay relative to trigger pulseSubsurface gate(if used)High passﬁlterDetection threshold for positive oscillation,negative oscillationA/D settingsSampling rateOffset settingPer Sample SettingsSample orientation(top or bottom(ﬂipped)view and location of pin1or some other distinguishing characteristic) Focus(point,depth,interface)Reference planeNon-default parametersSample identiﬁcation information to uniquely distinguish it from others in the same group11IPC/JEDEC J-STD-035April1999Appendix DReference Procedure for Presenting Applicable Scanned Data(continued) Reference Procedure for Presenting Scanned DataImageﬁle types and namesGray scale and color image legend deﬁnitionsSigniﬁcance of colorsIndications or deﬁnition of delaminationImage dimensionsDepth scale of TOFDeviation from true aspect ratioImage type:A-mode,B-mode,C-mode,TOF,Through TransmissionA-mode waveforms should be provided for points of interest,such as delaminated areas.In addition,an A-mode image should be provided for a bonded area as a control.12Standard Improvement FormIPC/JEDEC J-STD-035The purpose of this form is to provide the Technical Committee of IPC with input from the industry regarding usage of the subject standard.Individuals or companies are invited to submit comments to IPC.All comments will be collected and dispersed to the appropriate committee(s).If you can provide input,please complete this form and return to:IPC2215Sanders RoadNorthbrook,IL 60062-6135Fax 847509.97981.I recommend changes to the following:Requirement,paragraph number Test Method number,paragraph numberThe referenced paragraph number has proven to be:Unclear Too RigidInErrorOther2.Recommendations forcorrection:3.Other suggestions for document improvement:Submitted by:Name Telephone Company E-mailAddress City/State/ZipDate ASSOCIATION CONNECTING ELECTRONICS INDUSTRIESASSOCIATION CONNECTINGELECTRONICS INDUSTRIESISBN#1-580982-28-X2215 Sanders Road, Northbrook, IL 60062-6135Tel. 847.509.9700 Fax 847.509.9798。

Monotone

Monotone circuits for the majority functionShlomo Hoory Avner Magen†Toniann Pitassi†AbstractWe present a simple randomized construction of size O n3and depth53log n O1monotone circuits for the majority function on n variables.This result can be viewed as a reduction in the size anda partial derandomization of Valiant’s construction of an O n53monotone formula,[15].On the otherhand,compared with the deterministic monotone circuit obtained from the sorting network of Ajtai, Koml´o s,and Szemer´e di[1],our circuit is much simpler and has depth O log n with a small constant.The techniques used in our construction incorporate fairly recent results showing that expansion yields performance guarantee for the belief propagation message passing algorithms for decoding low-density parity-check(LDPC)codes,[3].As part of the construction,we obtain optimal-depth linear-size mono-tone circuits for the promise version of the problem,where the number of1’s in the input is promised to be either less than one third,or greater than two thirds.We also extend these improvements to general threshold functions.At last,we show that the size can be further reduced at the expense of increased depth,and obtain a circuit for the majority of size and depth about n1Department of Computer Science,University of British Columbia,Vancouver,Canada.†Department of Computer Science,University of Toronto,Toronto,Canada.1IntroductionThe complexity of monotone formulas/circuits for the majority function is a fascinating,albeit perplexing,problem in theoretical computer science.Without the monotonicity restriction,majority can be solvedwith simple linear-size circuits of depth O log n,where the best known depth(over binary AND,OR,NOT gates)is495log n O1[12].There are two fundamental algorithms for the majority function thatachieve logarithmic depth.Theﬁrst is a beautiful construction obtained by Valiant in1984[15]that achievesmonotone formulas of depth53log n O1and size O n53.The second algorithm is obtained from the celebrated sorting network constructed in1983by Ajtai,Koml´o s,and Szemer´e di[1].Restricting to binaryinputs and taking the middle output bit(median),reduces this network to a monotone circuit for the majorityfunction of depth K log n and size O n log n.The advantage of the AKS sorting network for majority is thatit is a completely uniform construction of small size.On the negative side,its proof is quite complicated andmore importantly,the constant K is huge:the best known constant K is about5000[11],and as observed byPaterson,Pippenger,and Zwick[12],this constant is important.Further converting the circuit to a formulayields a monotone formula of size O n K,which is roughly n5000.In order to argue about a quality of a solution to the problem,one should be precise about the differentresources and the tradeoffs between them.We care about the depth,the size,the number of random bitsfor a randomized construction,and formula vs circuit question.Finally,the conceptual simplicity of boththe algorithm and the correctness proof is also an important goal.Getting the best depth-size tradeoffs isperhaps the most sought after goal around this classical question,while achieving uniformity comes next. An interesting aspect of the problem is the natural way it splits into two subproblems,the solution to which gives a solution to the original problem.Problem I takes as input an arbitrary n-bit binary vector,and outputs an m-bit vector.If the input vector has a majority of1’s,then the output vector has at least a2/3fraction of 1’s,and if the input vector does not have a majority of1’s,then the output vector has at most a1/3fraction of1’s.Problem II is a promise problem that takes the m-bit output of problem I as its input.The output of Problem II is a single bit that is1if the input has at least a2/3fraction of1’s,and is a0if the input has at most a1/3fraction of1’s.Obviously the composition of these two functions solves the original majority problem.There are several reasons to consider monotone circuits that are constructed via this two-phase approach.First,Valiant’s analysis uses this viewpoint.Boppana’s later work[2]actually lower bounds each of thesesubproblems separately(although failing to provide lower bound for the entire problem).Finally,the secondsubproblem is of interest in its own right.Problem II can be viewed as an approximate counting problem,and thus plays an important role in many areas of theoretical computer science.Non monotone circuits forthis promise problem have been widely studied.Results The contribution of the current work is primarily in obtaining a new and simple construction ofmonotone circuits for the majority function of depth53log n and size O n3,hence signiﬁcantly reducing the size of Valiant’s formula while not compromising at all the depth parameter.Further,for subproblem II as deﬁned above,we supply a construction of a circuit size that is of a linear size,and it too does not compromise the depth compared to Valiant’s solution.A very appealing feature of this construction is that it is uniform,conditioned on a reasonable assumption about the existence of good enough expander graphs. To this end we introduce a connection between this circuit complexity question and another domain,namely message passing algorithms.The depth we achieve for the promise problem nearly matches the1954lower bound of Moore and Shannon[10].We further show how to generalize our solution to a general threshold function,and explore another optionin the tradeoffs between the different resources we use;speciﬁcally,we show that by allowing for a depth of roughly twice that of Valiant’s construction,we may get a circuit of size O n12Deﬁnitions and ampliﬁcationFor a monotone boolean function H on k inputs,we deﬁne its ampliﬁcation function A H:0101 as A H p Pr H X1X k1,where X i are independent boolean random variables that are one with probability p.Valiant[15],considered the function H on four variables,which is the OR of two AND gates,H x1x2x3x4x1x2x3x4.The ampliﬁcation function of H,depicted in Figure1,is A H p11p22,and has a non-trivialﬁxed point atβ512152.Let H k be the depth2k binary tree with alternating layers of AND and OR gates,where the root is labeled OR.Valiant’s construction uses the fact that A Hk is the composition of A H with itself k times.Therefore,H k probabilistically ampliﬁesβ∆β∆to βγεk∆βγεk∆,as long asγεk∆∆0.This implies that for any constantε0we can take2k33log n O1to probabilistically amplifyβΩ1nβΩ1n toε1ε,where33is any constant bigger thanαlogDeﬁnition1.Let F be a boolean function F:01n01m,and let S01n be some subset of the inputs.We say that F deterministically ampliﬁes p l p h to q l q h with respect to S,if for all inputs x S, the following promise is satisﬁed(we denote by x the number of ones in the vector x):F x q l m if x p l nF x q h m if x p h nNote that unlike the probabilistic ampliﬁcation,deterministic ampliﬁcation has to work for all inputs or scenarios in the given set S.From here on,whenever we simply say“ampliﬁcation”we mean deterministic ampliﬁcation.For an arbitrary small constantε0,the construction we give is composed of two independent phases that may be of independent interest.A circuit C1:01n01m for m O n that deterministically ampliﬁesβΩ1nβΩ1n toδ1δfor an arbitrarily small constantδ0.This circuit has size O n3and depth αεlog n O1.A circuit C2:01m01,such that C2x0if xδm and C2x1if x1δm,whereδ0is a sufﬁciently small constant.This circuit has size O m and depth2εlog m O1.Theﬁrst circuit C1is achieved by a simple probabilistic construction that resembles Valiant’s construction. We present two constructions for the second circuit,C2.Theﬁrst construction is probabilistic;the second construction is a simulation of a logarithmic number of rounds of a certain message passing algorithm on a good bipartite expander graph.The correctness is based on the analysis of a similar algorithm used to decode a low density parity check code(LDPC)on the erasure channel[3].Combining the two circuits together yields a circuit C:01n01for theβn-th threshold function. The circuit is of size O n3and depthα22εlog n O1.3Monotone circuits for MajorityIn this section we give a randomized construction of the circuit C:01n01such that C x is one if the portion of ones in x is at leastβn and zero otherwise.The circuit C has size O n3and depth2αεlog n O1for an arbitrary small constantε0.As we described before,we will describe C as the compositions of the circuits C1and C2whose parameters are given by the following two theorems: Theorem2.For everyεεc0,there exists a circuit C1:01n01m for m O n,of size O n3and depthαεlog n O1that deterministically ampliﬁes all inputs fromβc nβc n toε1ε. Theorem3.For everyε0,there existsε0and a circuit C2:01n01,of size O n and depth 2εlog n O1that deterministically ampliﬁes all inputs fromε1εto01.The two circuits use a generalization of the four input function H used in Valiant’s construction.For any integer d2,we deﬁne the function H d on d2inputs as the d-ary OR of d d-ary AND gates,i.e d i1d j1 x i j.Note that Valiant’s function H is just H2.Each of the circuits C1and C2is a layered circuit,where layer zero is the input,and each value at the i-th layer is obtained by applying H d to d2independently chosen inputs from layer i 1.However,the valuesof d we choose for C1and C2are different.For C1we have d2,while for C2we choose sufﬁciently large d dεto meet the depth requirement of the circuit.We let F n m F denote a random circuit mapping n inputs to m outputs,where F is aﬁxed monotone boolean circuit with k inputs,and each of the m output bits is calculated by applying F to k independently chosen random inputs.We start with a simple lemma that relates the deterministic ampliﬁcation properties of F to the probabilistic ampliﬁcation function A F.1Lemma4.For anyεδ0,the random function F deterministically ampliﬁes p l p h to A F p l1δA F p h1δwith respect to S01n with probability at least1ε,if:log S log1εmΩΘγ2εi1c nβγεγ2εi1c nThat is,we can chooseδas an increasing geometric sequence,starting fromΘ1n for i1,up toΘ1 for i logγ2εn.The implied layer size for error probability2n(which is much better than we need),is Θnδ2.Therefore,it decreases geometrically fromΘn3down toΘn.It is not difﬁcult to see that after achieving the desired ampliﬁcation fromβc n toβ∆0,only a constant number of layers is needed to get down toε.The corresponding value ofδin these last steps is a constant (that depends onε),and therefore,the required layer sizes are allΘn.Proof of Theorem3.The circuit C2is a composition of F n m1H d F m1m2H dF mt1m t H d,where d andthe layer sizes n m0m1m t1are suitably chosen parameters depending onε.We prove that with high probability such a circuit deterministically ampliﬁes all inputs fromε1εto01.As before,we restrict our attention to the lower end of the promise problem and prove that C2outputs zero on all inputs with portion of ones smaller thanε.As in the circuit C1,the layer sizes must be sufﬁciently large to allow accurate computation.However, for the circuit C2,accurate computation does not mean that the portion of ones in each layer is close to its expected value.Rather,our aim is to keep the portion of ones bounded by aﬁxed constantε,while making each layer smaller than the preceding one by approximately a factor of d.We continue this process until the layer size is constant,and then use a constant size circuit toﬁnish the computation.Therefore,since the number of layers of such a circuit is about log n log d,and the depth of the circuit for H d is2log d,the total depth is about2log n for large d.By the above discussion,it sufﬁces to prove the following:For everyε0there exists a real number δ0and two integers d n0,such that for all n n0the random circuit F n m H d with m1εn d, deterministically ampliﬁesδtoδwith respect to all inputs,with failure probability at most1n.Since A Hδ11δd d dδd,the probability of failure for any speciﬁc input with portion of ones at most δ,is bounded by:mδmA Hδδm eampliﬁcation method to analyze the performance of a belief propagation message passing algorithm for decoding low density parity check(LDPC)codes.Today the use of belief propagation for decoding LDPC codes is one of the hottest topics in error correcting codes[9,14,13].Let G V L V R;E be a d regular bipartite graph with n vertices on each side,V L V R n.Consider the following message passing algorithm,where we think of the left and right as two players.The left player “plays AND”and the right player“plays OR”.At time zero the left player starts by sending one boolean message through each left to right edge,where the value of the message m uv from u V L to v V R is the input bit x u.Subsequently,the messages at time t0are calculated from the messages at time t 1.At odd times,given the left to right messages m uv,the right player calculates the right to left messages m vw, from v V R to w V L by the formula m vw u N v w m uv.That is,the right player sends a1along the edge from v V R to w V L if and only if at least one of the incoming messages/values(not including the incoming message from w)is1.Similarly,at even times the algorithm calculates the left to right messages m vw,v V L,w V R,from the right to left messages m uv,by the formula m vw u N v w m uv.That is,the left player sends a1along the edge from v V L to w V R if and only if all of the incoming messages/values (not including the incoming message from w)are1.We further need the following deﬁnitions.We call a left vertex bad at even time t if it transmits at least one message of value one at time t.Similarly,a right vertex is bad at odd time t if it is a right vertex that transmits at least one message of value zero at time t.We let b t be the number of bad vertices at time t.These deﬁnitions will be instrumental in providing a potential function measuring the progress of the message passing algorithm which is expressed in Lemma5.We say that a bipartite graph G V L V R;E isλe-expanding,if for any vertex set S V L(or S V R)of size at mostλn,N S e S.It will be convenient to denote the expansion of the set S by e S N S S. Lemma5.Consider the message passing algorithm using a d4regular expander graph with d1e d12.If b tλn d2then b t2b tη,whereηd1d1ηt and so b2t10for t log a d2d e gets,and the better the time guarantee above gets.How good are the expanders that we may use?One can show the existence of such expanders for sufﬁciently large d large,and e d c for an absolute constant c.The best known explicit construction that gets close to what we need,is the result of[4].However,that result does not sufﬁce here for two reasons.Theﬁrst is that it only achieves expansion1εd for anyε0 and sufﬁciently large d depending onε.The second is that it only guarantees left-to-right expansion,while our construction needs both left-to-right and right-to-left expansion.We refer the reader to the survey[6] for further reading and background.For such expanders,ηd1d1log d1log d1iterations,all mes-sages contain the right answer,whereεcan be made arbitrarily small by choosing sufﬁciently large d.It remains to convert the algorithm into a monotone circuit,which introduces a depth-blowup of log d1 owing to the depth of a binary tree simulating a d1-ary gate.Thus we get a2εlog n-depth circuit for arbitrarily smallε0.The size is obviously dn depth O n log n.To get a linear circuit,further work is needed,which we now describe.The idea is to use a sequence of graphs G 0G G 1,where each graph is half the size of its preceding graph,but has the same degree and expansion parameters.We start the message passing algorithm using the graph G G 0,and every t 0rounds (each round consists of OR and then AND),we switch to the next graph in the sequence.Without the switch,the portion of bad vertices should decrease by a factor of ηt 0,every t 0rounds.We argue that each switch can be performed,while losing at most a constant factor.To describe the switch from G i to G i 1,we identify V L G i 1with an arbitrary half of the vertices V L G i ,and start the message passing algorithm on G i 1with the left to right messages from each vertex in V L G i 1,being the same as at the last round of the algorithm on G i .As the number of bad left vertices cannot increase at a switch,their portion,at most doubles.For the right vertices,the exact argument is slightly more involved,but it is clear that the portion of bad right vertices in the ﬁrst round in G i 1,increases by at most a constant factor c ,compared with what it should have been,had there been no switch.(Precise calculation,yields c 2d η.)Therefore,to summarize,as the circuit consists of a geometrically decreasing sequence of blocks starting with a linear size block,the total size is linear as well.As for the depth,the amortized reduction in the portion of bad vertices per round,is by a factor of ηηc 1t 0.Therefore,the resulting circuit is only deeper than the one described in the previous paragraph,by a factor of log ηlog η.By choosing a sufﬁciently large value for t 0,we obtain:Theorem 6.For any ε0,there exists a 0such that for any n there exists a monotone circuit of depth 2εlog n O 1and size O n that solves a-promise problem.We note here that O log n depth monotone circuits for the a -promise problem can also be obtained from ε-halvers.These are building blocks used in the AKS network.However,our monotone circuits for the a -promise problem have two advantages.First,our algorithm relates this classical problem in circuit com-plexity to recent popular message passing algorithms.And second,the depth that we obtain is nearly ly,Moore and Shannon [10]prove that any monotone formula/circuit for majority requires depth 2log n O 1,and the lower bound holds for the a -promise problem as well.Proof of Lemma 5.(based on Burshtein and Miller [3])We consider only the case of bad left vertices.The proof for bad right vertices follows from the same proof,after exchanging ones with zeroes,ANDs with ORs,and lefts with rights.Let B V L be the set of bad leftvertices,and assume Bλd 2at some even time t and B the set of bad vertices at time t 2.We bound the size of B by considering separately B B and B B .Note that all sets considered in the proof have size at most λn ,and therefore expansion at least e.N(B’)To bound B B ,consider the set Q N B B N B N B B N B .Since vertices in Q are not adjacent to B ,then at time t 1they send right to left messages valued zero.On the other hand,any vertex in B B can receive at most one such zero message (otherwise all its messages at time t 2will be valuedzero and it cannot be in B).Therefore,since each vertex in Q must have at least one neighbour in B B,it follows that Q B B.Therefore,we have:N B B N B Q N B B B e B B B BOn the other hand,N B B e B B e B B B.Combining the above two inequalities,we obtain:B B e Be2B B1d12B(2) Combining inequalities(1)and(2)we get that:B B e B ed12Since e d12,and e B e,this yields the required bound:B B2d e d1As noted before in Section2,replacing the last2log n layers of Valiant’s tree with2log r n layers of r-ary AND/OR gates,results in an arbitrarily small increase in the depth of the corresponding formula for a large value of r.It is interesting to compare the expected behavior of the suggested belief-propagation algorithm to the behavior of the d1-ary tree.Assume that the graph G is chosen at random(in theconﬁguration model),and that the number of rounds k is sufﬁciently small,d12k n.Then,almost surely the computation of all but o1fraction of the k-th round messages is performed by evaluating a d1-ary depth k trees.Moreover,introducing an additional o1error,one may assume that the leaves are independently chosen boolean random variables that are one with probability p,where p is the portion of ones in the input.This observation sheds some light on the performance of the belief propagation algorithm. However,our analysis proceeds far beyond the number of rounds for which a cycle free analysis can be applied.4Monotone formulas for threshold-k functionsConsider the case of the k-th threshold function,T k n,i.e.a function that is one on x01n if xk1and zero otherwise.We show that,by essentially the same techniques of Section3,we can construct monotone circuits to this more general problem.We assume henceforth that k n2,since otherwise, we construct the circuit T n1k n and switch AND with OR gates.For k nΘ1,the construction yields circuits of depth53log n O1and size O n3.However,when k o n,circuits are shallower and smaller (this not surprising fact is also discussed in[2]in the context of formulas).The construction goes as follows:(i)Amplify k n k1n toβΩ1kβΩ1k by randomly applying to the input a sufﬁciently large number of OR gates with arityΘn k(ii)AmplifyβΩ1kβΩ1k to O11O1using a variation of phase I,and(iii)Amplify O11O1to01using phase II.We now give a detailed description.For the sake of the section to follow,we require the following lemma which is more general than is needed for the results of this section.Lemma7.Let S01n,andε0.Then,for any k,there is a randomized construction of a monotone circuit that evaluates T k n correctly on all inputs from S and hasdepth log n23log k2εloglog S O1size O log S k nHere k min k n1k,and the constants of the O depend only onε.Proof.Let s log S,and let i be the OR function with arity i.Then An kk n11k n n k,while An k k1n11k1n n k.Hence An kk n is a constant bounded from zero andone.We further notice thatAn k k1nΘ1kIt is not hard to see that we can pick a constantρso that Aρn k knβΩ1k.Therefore,ρn k probabilistically amplify k n k1n toβΩ1kβΩingLemma4withδΘ1k and m sk2we get that F n mρn k ampliﬁes k n k1n toβΩ1kβΩ1k with arbitrarily high probability.The depth required to implement the above circuit is log n k and the size is O skn.Next we apply a slight modiﬁcation of phase I.The analysis there remains the same except that the starting point is separation guarantee ofΩ1k instead ofΩ1n,and log S is s instead of n.This leads to a circuit of depthαεlog k O1and of size O sk2,for an arbitrarily small constantε0.Also,we note that the output of this phase is of sizeΘs.Finally,we apply phase II,where the number of inputs isΘs instead ofΘn,to obtain an ampliﬁcation from O11O1to01.This requires depth2εlog s O1and size O s,for an arbitrarily small constantε0.To guarantee the correctness of a monotone circuit for T n k,it sufﬁces to check its output on inputs of weight k k1(as the circuit is monotone).Therefore,S n k n k1,implying that log S O k log n k. Therefore,we have:Theorem8.There is a randomized construction of a monotone circuit for T k n with:depth log n43log k O loglog n ksize O k2n log n kwhere k min k n1k,and the constants of the O are absolute.5Reducing the circuit sizeThe result obtained so far for the majority,is a monotone circuit of depth53log n O1and size O n3.In this section,we would like to obtain smaller circuit size,at the expense of increasing the depth somewhat. The crucial observation is that the size of our circuit depends linearly on the logarithm of the number of scenarios it has to handle.Therefore,applying a preprocessing stage to reduce the wealth of scenarios may save up to a factor of n in the circuit size.We propose a recursive construction that reduces the circuit size to about n1We chooseαi2σi1to equate1αiσi with3αi.This implies thatσi132σi1,and δi153δi22σi1,resulting in the following sequence:iαiσiδi2,and the sequence of δi tends to129896.Therefore,we have:Theorem9.There is a randomized construction of a monotone circuit for the majority of size n1There are two central open problems related to this work.First,is the promise version really simpler than majority?A lower bound greater than2log n on the communication complexity of mMaj-search would settle this question.Boppana[2]and more recent work[5]show lower bounds on a particular method for obtaining monotone formulas for majority.However we are asking instead for lower bounds on the size/depth of unrestricted monotone formulas/circuits.Secondly,the original question remains unresolved. Namely,we would like to obtain explicit uniform formulas for majority of optimal or near optimal size.A related problem is to come up with a natural(top-down)communication complexity protocol for mMaj-Search that uses O log n many bits.References[1]M.Ajtai,J.Koml´o s,and E.Szemer´e di.Sorting in c log n parallel binatorica,3(1):1–19,1983.[2]R.B.Boppana.Ampliﬁcation of probabilistic boolean formulas.IEEE Symposium on Foundations ofComputer Science(FOCS),pages20–29,1985.[3]D.Burshtein and ler.Expander graph arguments for message-passing algorithms.IEEE Trans.Inform.Theory,47(2):782–790,2001.[4]M.Capalbo,O.Reingold,S.Vadhan,and A.Wigderson.Randomness conductors and constant-degreeexpansion beyond the degree2barrier.In Proceedings34th Symposium on Theory of Computing, pages659–668,2002.[5]M.Dubiner and U.Zwick.Ampliﬁcation by read-once formulas.SIAM put.,26(1):15–38,1997.[6]S.Hoory,N.Linial,and A.Wigderson.Expander graphs and their applications.survey article toappear in the Bulletin of the AMS.[7]Mauricio Karchmer and Avi Wigderson.Monotone circuits for connectivity require super-logarithmicdepth.In Proceedings of the Twentieth Annual ACM Symposium on Theory of Computing,pages539–550,Chicago,IL,May1988.[8]M.Luby,M.Mitzenmacher,and A.Shokrollahi.Analysis of random processes via and-or tree evalu-ation.In ACM-SIAM Symposium on Discrete Algorithms(SODA),1998.[9]M.Luby,M.Mitzenmacher,A.Shokrollahi,and D.A.Spielman.Analysis of low density codes andimproved designs using irregular graphs.ACM Symposium on Theory of Computing(STOC),1998.[10]E.F.Moore and C.E.Shannon.Reliable circuits using less reliable relays.I,II.J.Franklin Inst.,262:191–208,281–297,1956.[11]M.S.Paterson.Improved sorting networks with O log N depth.Algorithmica,5(1):75–92,1990.[12]M.S.Paterson,N.Pippenger,and U.Zwick.Optimal carry save networks.In Boolean functioncomplexity(Durham,1990),volume169of London Math.Soc.Lecture Note Ser.,pages174–201.Cambridge Univ.Press,Cambridge,1992.[13]T.Richardson and R.Urbanke.Modern coding theory.Draft of a book.[14]T.Richardson and R.Urbanke.The capacity of low-density parity-check codes under message-passingdecoding.IEEE rm.Theory,47(2):599–618,2001.[15]L.G.Valiant.Short monotone formulae for the majority function.J.Algorithms,5(3):363–366,1984.。

P电力电子领域出现的新问题及分析roblems Chptrs 19-30

Supplemental ProblemsPart II: Chapters 19 - 30to accompany the 3rd Edition ofPower Electronics: Converters, Applications and DesignbyNed Mohan, Tore Undeland, and William RobbinsCopyright 2002Chapter 19 - Semiconductor PhysicsS19.1An abrupt pn junction has 1014 cm -3 donors on the n-type side and 1014 cm -3 acceptorson the p-type side. At what temperature will the properties of junction disappear?S19.2.Consider the bar of n-type silicon shown below with a current of 10 ma flowing throughit.a.What is voltage drop, V bar , at room temperature?b.The voltage V bar changes with temperature as illustrated below. Explain qualitatively the observed behavior.c.Estimate the temperature T 0.5 where the voltage drop across the bar is 50% of the room temperature value. You may assume temperature independent mobilities.10 mAVbarN = 10 cm d 15-31 cmArea A =0.42 cm 2TemperatureT 0.525 °CV barVb0.5V bChapter 20 - Power DiodesS20.1Consider the circuit shown below. All components in the circuit are ideal except for thediode. The characteristics of the diode are listedbelow. For simplicity, assume that the reverse-recovery current waveform of the diode is triangular, i.e. that the current growstowards I rr at a constant rate given by di Rdt and then falls towards zero from I rr at a rate controlled by the snappiness factor S.dI = 100 A o L = 100 nHDiodeCharacteristics BV = 400 V Excess carrier Lifetime = 50 ns Snappiness S =1a.Estimate the reverse-recovery current I rr and reverse-recovery time t rr .b.Is a snubber circuit required to protect the diode? Justify your answer.S20.2.A signal level diode and a fast power rectifier are tested in the circuit shown below. Thevoltage and current responses of the two diodes are also shown below. Qualitatively, but briefly explain the causes or reasons for the differences in the behavior of the two types of diodes.v +-i tP +-N +N Signal level diode Power rectifier v(t)v(t)P +NS20.3.Consider the two diode structures shown below. The punch-thru structure has the samebreakdown voltage as the standard diode geometry. However the punch-thru diode is expected to have a significantly smaller reverse recovery time t rr compared to the standard diode geometry.N +P +N -10 cm12-3N +P +N -50 m m10 cm-314m mPunch-thru diode Standard diodea. Qualitatively explain why the punch thru diode geometry is expected to have a significantlyshorter reverse recovery time t rr .b. Will any aspects of the behavior of the punch-thru diode be inferior to the standard diode?Briefly and qualitatively explain.c.Approximately estimate how much shorter t rr in the punch-thru diode will be compared to the standard diode.S20.4.The diode rectifier circuit shown below must deliver 100 kW of power to the load R L . Thediodes are all identical. T j,max = 150 °C ; R q j-c = .1 °C/W250 v base-to-peak 1 kHz square waveRL1 V2 V 500 AV IAa. Specify what the blocking voltage rating and maximum average forward current rating of the diodes should be. Include a factor of safety of 25% in the ratings.b. Specify the required value of thermal resistance R q,c-a of a heat sink for the diodes.S20.5.A one-sided step junction with a p-side doping density N A much greater than the n-sidedoping density of N D conducts a current I when forward biased by a voltage V F . Thecurrent is to be increased by a factor of two (to 2I) by adjusting the carrier lifetime t . What adjustment is required in the carrier lifetime to realize this change in current?S20.6.Consider the diode shown below .N +P +N-2x10 cm-314100 m m10101919a. Estimate the breakdown voltage BV BD of the diode.b. Estimate the leakage current of the diode assuming that the area of the diode is 1 cm 2.c.Estimate the on-state voltage for a forward current of 500 amps.S20.7 Consider the silicon diode structure shown below. This diode is used as a free-wheelingdiode in the step-down converter shown below. Estimate the reverse-recovery current I rrand reverse recovery time t rr of the diode when it is used in the circuit. The switch S w is ideal. Assume that the snappiness factor S of the diode is equal to one.D f+-V d = 600 VSwL = 1 m HI =200 Ao N +P+N -10 cm14-350 microns m mS20.8 The silicon p-i-n diode shown below is to be designed to have a breakdown voltage of1500 V.a.What should be the length, L, of the drift region and what should be the doping density?b.The diode will be used as the free-wheeling diode D f in the step-down converter shown below. The switch S w has a current rise and fall time of 100 nsec.Approximately estimate the expected magnitudes of the reverse recovery current, I rr , and reverse-recovery time, t rr.LN -+NP +Chapter 21 - BJTsS21.1.Consider the one dimensional model of a BJT shown below. Assume that the transistor has a beta of 20.EBCN = 10cm d 19-3N = 10cmd 19-3W = ?dN = ?d N =10cm -317a 3 m ma. (Approximately estimate what the drift region doping level can be if BV CEO = 100V.b.Approximately estimate the required length W d of the drift region.c.What should be the excess carrier lifetime in the drift region?S21.2.Consider the transistor geometry shown below. The beta (b ) of the transistor is equal to10.BN +N -N +10 1910 19-3cm -3cm -3cm -3cm P 5x10152x1014W BEC100 micronsa.What is the breakdown voltage BV CEO of the transistor?b.How large must the base width W B in order to avoid reach-thru?S21.3.Why are NPN transistors used much more than PNP transistors as switches in power electronics applications?S21.4.An NPN transistor is used in the step-down converter circuit shown below. A simplediagram of the transistor's internal structure is also given below. Estimate the turn-on delay time of the transistor in this circuit. Use average values of space-charge capacitance. Clearly explain your averaging proceedure.QIo = 40 ARg = 4 W Vg(t)+- Vd = 100 V +-DfDf = ideal diodeVg(t)tArea = 2 cm2All pn junctions = step junctionsS21.5.In designing a transistor for a specific value of BV CEO , the base width must belarge enough to avoid reach-through. This requires that the base width W B >x pC (BV CBO ) + x pE (BV EBO ). x pC (BV CBO ) is theprotusion of the CBdepletion layer on to the base side of the CB junction at V CB = BV CBO and x pE (BV EBO ) is the protusion of the BE depletion layer on to the base side of the BE junction at V BE = - BV EBO . However device manufacturers make W B several times larger than this minimum value.a.Explain why they do this. (The answer is not to provide a margin of safety against reach-through.)b.For the BJT shown below, find the required value of W B assuming that the manufacturer uses the design criteria of W B = 5 [x pC (BV CBO ) + x pE (BV EBO )].BN +N -N +10 1910 19-3cm -3cm-3cm -3cm P 10165x1014W B EC100 micronsS21.6Consider the transistor geometry shown below. The beta (b) of the transistor is equal to10. Specify a blocking voltage rating for this transistor. Include a 50% factor of safety.BN +N -N +10191019-3cm -3cm -3cm -3cm P 101610138 micronsEC40 micronsChapter 22 - MOSFETsS22.1Consider the MOSFET step-down converter circuit shown below. The voltage rise and fall times, t rv and t fv, are much larger than current rise and fall times, t ri and t fi. Briefly explain why this is so. You may assume that the value of C gd is a constant independent of V DS and the free wheeling diode D f is ideal.v (t)iI oS22.2.In the step-down converter circuit of Problem #1, V d = 250 V and I o = 50 A.The MOSFET parameters are listed below:BV DSS = 400 V , I D,max = 80 A, V GS,th = 5 V, r DS(on) = .05 W,T j,max = 175 °C, R q j-a = .5 °C/W, t d(on) = t d(on) = 10 ns, t ri = t fi = 25 ns,t rv = t fv = 175 nsa. What is the power dissipation in the MOSFET assuming a switching frequencyf s = 10 kHz and a duty cycle D = 50%?b. What is the maximum average power that can be dissipated in the MOSFET? Assume anambient temperature of 25 °C.c. The duty cycle D will vary from 20% to 90%. What is the maximum permissibleswitching frequency f s? Assume that the period 1/f s is large compared to the switching times of the MOSFET.S22.3. In the step-down converter circuit shown below, V d = 300 V and I o= 30 A.v (t)iI oThe MOSFET parameters are listed below:BV DSS = 400 V , I D,max = 80 A, V GS,th = 5 V, r DS(on) = .1 W,T j,max = 175 °C, R q j-c = .25 °C/W = junction-to-case thermal resistance,The switching times are adjustable over a wide range by the magnitude of thegate-source voltage provided by the drive circuit.a. The power dissipation in the MOSFET at a switching frequency f s = 10 kHz and a dutycycle D = 50% is to be limited to 100 W. What should be the the switching times t ri, t fv.t fi, and t rv. Assume that t rv = t fv = 6t ri = 6t fi and further assume that t d(off) = t d(on) = 0.b. The maximum average power dissipated in the MOSFET will be limited to 200 W.Assuming an ambient temperature of 25 °C, what is the maximum allowable case-to-ambient thermal resistance, R q c-a, of the heat sink on which the MOSFET is to bemounted?S22.4.The MOSFET-driven step-down converter circuit shown below produces the turn-onwaveforms which are shown with the circuit diagram.V = 125 V d+-DfI = 100 A o+-10 W-5 -10 -15 V G S125 V 0 VDI VD SD f= ideal diodea.What is the threshold voltage V GSth of the MOSFET?b.What is the MOSFET transconductance g m ?c.What is the on-state resistance r DS(on)?d.What is the gate-drain capacitance C gd ?e.What is the gate-source capacitance C gs ?S22.5.Shown below is a graph of the gate-source voltage V GS as a function of the gate chargeQ g with a specified drain current I D and drain-source voltage V DS . Such graphs are oftenincluded on specification sheets of MOSFETs and IGBTs and are aconvenient way of summarizing the influence of gate-source, gate-drain, and drain-source capacitances.These graphs are most useful in the design of circuits with clamped inductive loads such as is shown below. Express the slopes (Slope1 and Slope2) and breakpoints (V GSp ,Q g1and V GSp ,Q g2) indicated on the V GS versus Q g graph in terms of the parameters of the step-down converter circuit and the parameters of the MOSFET. Assume that all of the MOSFET parameters listed below are constant independent of MOSFET voltages or currents.v (t)i I oQ gV GSSlope2Slope1Q g1Q g2V GSpMOSFET parametersthreshold voltage V gs(th) ; transconductance g mgate-source capacitance C gs ; gate-drain capacitance C gdS22.6.Consider the MOSFET step-down converter shown below. It is operating in anambient temperature of 50 °C at a switching frequency of 30 kHz (duty cycle of 50%). The free-wheeling diode D f is ideal. Is the transistor being overstressed andif so, how? Be specific and quantitative in answering the question.100 V100 nH100 A10 W V drive+-D fQMOSFET Characteristics BV DSS = 150 VI D,max = 125 A T j,max = 150 °C R q ,j-a = 1 °C/W t ri = t fi = 50 ns t rv = t fv = 200 nsr DS(on) = 0.01 ohmsS22.7.Consider the MOSFET step-down converter circuit shown below. Assume I o = 100 A,V d = 100 V, R G = 25 ohms, and V i (t) is shown below. The parameters of the MOSFETare also listed below. Estimate the turn-on delay time t.v (t)iI oChapter 23 and 24 - SCRs and GTOsS23.1.Consider the SCR circuit shown below. The SCR has the following characteristics:T j,max = 125 °C ; V BO = 3000 V ; I A,max = 2000 A ; R q j-c = .05 °C/WV (on)AKa.Assume that the case temperature is 50 °C. What is the maximum average powerP SCR,max, that can be dissipated in the thyristors?b. Estimate the maximum power that can be delivered to the load.S23.2.The SCR inverter circuit shown below must deliver 1 megawatt of power to the load R L under maximum power conditions (trigger angle equal to zero). The thyristors are allidentical.T j,max = 125 °C ; V BO = 3000 V ; I A,max = 2000 A ; R q j-c = .05 °C/W440 V rms60 Hz 1 V3 V1000 AVIAa. Specify what the blocking voltage rating and maximum average forward currentrating of the SCRs should be. Include a factor of safety of 25% in the ratings.b. Estimate what the power dissipation rating of the thyristor should be includinga factor of safety of 25%.S23.3.A cascode circuit arrangement shown below has been proposed for the control of a GTO. Briefly discuss the advantages and disadvantages of this arrangement.To trigger circuit To trigger circuit High current-low voltage MOSFETS23.4.The stray inductance L s in the turn-off snubber of Fig. 24-3, pp. 617 of Power Electronics: Converters, Applications, and Design, 2nd Edition, by Mohan, Undeland,and Robbins will cause an overvoltage across the GTO. Estimate the maximum strayinductance that can be tolerated in the circuit if the overvoltage is not to exceed 1.5 V d.Express the estimate in terms of the circuit parameters. Assume that the turn-on snubber acts like a constant current source of value I o during the GTO current fall time t fi = 1µsec.Chapter 25 - IGBTsS25.1.Consider the symmetric and antisymmetric IGBTs shown below.Antisymmetric IGBT Symmetric IGBTa.Estimate the forward blocking voltage BV DSS of each IGBT.b. Estimate the reverse blocking voltage V RM of each IGBT.S25.2Consider the IGBT shown below.a. Estimate the forward blocking voltage BV DSS that will be printed on the specificationsheet for the IGBT shown above. The device manufacturer uses a 50% factor of safety in specifying the breakdown voltage.b. The IGBT is rated for a maximum drain current of 20 A and at this currentlevel, the drift region voltage drop is one volt. Assuming that the IGBT chip issquare in shape, specify the length and width of the chip on which the IGBT isfabricated. Only 25% of the total chip area is effective in carrying current, therest is used for connecting the many source and gate regions together. Use avalue n b = 1016 cm-3 as the excess carrier density value at which themobilities and carrier lifetime begin to decrease with further increases in excess carrier density.S25.3.Older types of IGBTs have an excess carrier distribution in the drift region that istriangular as shown below. Newer IGBT structures manage to get a flat distribution as is also shown in the figure. Compare the on-state resistance of the older IGBT against that of the newer IGBT assuming that both have the same drift region length, same excess carrier lifetime, same cross-sectional area, and the same breakdown voltage rating. Furtherassume that the maximum excess carrier density at the collector end of the drift region is the same for both devices.Excess carrier densityChapter 26 - Emerging DevicesS26.1.Consider the step-down converter shown below which employs an FCT and aMOSFET. The blocking gain, m , of the FCT is equal to 40.RG1RG2Q sT swD f+-I o = 200 AV d= 1000 V a. What should be the values of R G1 and R G2 in order to insure proper operation of the FCT? Assume R G1+ R G2 = 1 M W and include a 25% factor of safety in the blocking voltage capability of the circuit.b. Describe the characteristics the MOSFET in this circuit should have including breakdown voltage and maximum average current capability.S26.2.Consider the Schottky diode geometry shown below. For simplicity no guard rings or fieldplates are shown. The performance of this diode geometry implemented in silicon is to be compared against the same geometry implemented in gallium arsenide. The breakdown voltage of the diode is to be 125 volts. The properties of silicon and gallium arsenide are listed below.N = 10 cm -15-3N = 10 cm +19-3dAnodeCathodea. Find the appropriate length, W d, of the drift region for both the silicon and galliumarsenide versions of the diode. The length is to be minimized so that the resistance of the drift region is minimized.b.How does the drift region resistance of the silicon diode compare with that of the galliumarsenide diode. Each diode has the same cross-sectional area and the length W d found in part a.S26.3 A novice device engineer has designed the gallium arsenide rectifier diode shownbelow.It is supposed to have a breakdown voltage of 2000 V and a maximum average forward current rating of 2000 A. The maximum current density in the diode should not exceed 250 A/cm 2. The diode is a non-punch-through geometry.Test results reveal that the diode does not work properly. List what is wrong with the design and briefly describe how to correct each design fault. Treat each design error you find independent of all the others. A list of useful physicalproperties of GaAs are listed below.Parameter Value Bandgap @ 300 °K [eV] 1.43Relative dielectric constant 12.8Electron mobility @ 300 °K[cm 2/V-sec]8500Hole mobility @ 300 °K[cm 2/V-sec]1500Breakdown electric field [V/cm]4x105Thermal conductivity[W/cm-°C]0.5S26.4. Consider the step-down converter circuit shown below. The switching frequency is 15 kHz. The breakdown voltage of the free-wheeling diode is specified with a 50% factor of safety. The characteristics of the switch S w are given below.Maximum instantaneous current = 300 ABlocking voltage = 1000 Vt ri = t fi = 0.5 m s = t fv = t rvD f +-I o= 200 AVd= 600 VS wEstimate the reverse-recovery time t rr and reverse recovery current I rr of the free-wheeling diode assuming that it is a gallium arsenide diode.S26.5.A Schottky diode is to be fabricated using silicon carbide. The diode is to have a breakdown voltage rating of 1500 V and is to conduct a maximum averageforward current of 500 A. The physical parameters of silicon carbide are given below.e R = 9.7 ; E G = 2.2 eV ; m n = 1000 cm2 /V-sec ; E BD = 4x106 V/cma.Specify the doping density and length of the drift region.b.At the maximum forward current, the drift region drop is not to exceed 2 V. Specifythe cross-sectional area of the drift region.S26.6.Shown below are the vertical cross-sections of several power devices.Indentify each of them and answer the following questions regarding their basicproperties. Enter your answers on the table provided.Type of device - BJT, IGBT, GTO, etc.High power (V off•I on > 1 Megawatt)? yes or noFast (t on, t off < 0.5 m s)? yes or nodvdt &/or didt limits? specify which - no numerical values requiredS26.7.A Schottky diode is to be made from diamond and is to have a blocking voltage rating of 2000V and an on-state current rating of 1000 A. The current density must be limited to 800 A/cm2.a.Specify the doping density N d and the length W d of the drift region.b.Estimate the on-state voltage drop across the drift region when the maximumcurrent is flowing in the diode.S26.8.A silicon carbide schottky diode is to be designed to hold off 3000 V when reverse biasedand conduct 1000 A when forward biased. The basic structure is shown below. Assume that the depletion regions are plane and parallel with the surface of the wafer so that there are no field crowding problems.SiC Material DataN d N +W da.Specify the required doping density in the drift region and the length of the driftregion.b.Thermal considerations dictate that the power dissipation in the diode be limited to500 watts when it is forward biased. Assume that the forward bias voltage V fwd isonly the drift region drop, V drift . Specify the cross-sectional area of the diode.Bandgap @ 300 °K [ev ] 2.9Relative dielectric constant10Saturated drift velocity [cm/sec] 2.5x107Thermal conductivity [Watts/cm -°C] 5.0Maximum operating temperature [°K]1240Intrinsic carrier density [cm -3] @ 25 °C Melting temperature [°C]sublimes >1800Electron mobility @ 300 °K [cm 2/V-sec]600Breakdown electric field [V/cm]2x106S26.9.The so-called UMOSFET (or trench-gate MOSFET)shown below is to be fabricated in diamond. Some of the physical properties of diamond are listed in the tablebelow.a.Estimate the breakdown voltage V DSS .b.Estimate the cross-sectional area required if the MOSFET is to conduct 500 A in the on-state and the on-state voltage is not to exceed 1 V. You may assume that only the drift region contributes to the on-state losses.S26.10.Conduct a brief survey of commercially available high voltage Schottky diodes, bothsilicon, gallium arsenide. And silicon carbide. Include the first page of the specification sheets for the highest voltage Schottky you are able to find in each material.Property DiamondBandgap @300 °K [ev ] 5.5Relative dielectric constant 5.5Saturated drift velocity [cm/sec] 2.7x107Thermal conductivity [Watts/cm-°C]20Electron mobility @ 300 °K [cm 2/V-sec]2200Breakdown electric field [V/cm]1x107S26.11.A pn junction diode is to be fabricated in silicon carbide. A diagram of the diode is shown below. The diode is to have the following characteristics:BV BD = 2000 V ; I on,max = 2000 A ; V on = 2 V when I on = 1000 A A table listing the important characteristics of silicon carbide is shown below.PropertySiC Bandgap @ 300 °K [ev ] 2.2Relative dielectric constant 9.7Saturated drift velocity [cm/sec] 2.5x107Thermal conductivity [Watts/cm-°C]5.0Intrinsic carrier density [cm -3] @ 25 °C105Electron/hole mobility @ 300 °K [cm 2/V-sec]1000Breakdown electric field [V/cm]2x106a.Specify the length W d of the drift region and the doping level of the drift region.b.Specify the cross-sectional area A. You may assume that both the excess carrier lifetime and the carrier mobilities begin to decrease at carrier densities above n b = 1017 cm -3.W dS26.12.Shown below is the forward bias I-V curve of the new 600V-6A model SDP06S60 silicon carbide Schottky diode made by Infineon Technologies of Germany. Use theroom temperature I-V curve for this problem.a.Estimate the drift region length, W d, and its doping level N d of this diode.b.What is the approximate conducting area of the diode?500VD f100AS wChapter 27 - SnubbersS27.1.The step-down converter circuit shown below is switched at a 25 kHz rate. 100 watts of power are dissipated in the BJT including switching losses. The ambient temperature is25 °C. The BJT parameters are listed below. The collector current and collector-emittervoltage vary linearly in time during the switching transient. The rest of the circuitcomponents are ideal.dI = 100 AoL = 50 nHsBJT CharacteristicsBV CBO = 300Vb= 16T j,max = 150 °CR q,j-a = 2 °C/WI C,max = 125 At ri = t fv = 0.1 m st rv = t fi = 0.2 m st d,on = 0.1m st d,off = 0.3m sa. In what way or ways is the transistor being overstressed in this application. Justify youranswer quantitatively.b.Specify the type or types of snubber circuits needed in this circuit for reducing thestresses on the transistor to a safe level. The number of snubber circuits used should be minimized. Justify your choices.S27.2.Assume that the circuit of problem #S27.1 requires a turn-off snubber.a.Determine the values of R s and C s used in the snubber circuit.b.How much power is dissipated in the snubber resistance R s?c.Estimate the reduction in the transistor turn-off losses afforded by the turn-off snubber.S27.3. A turn-off snubber circuit is to be designed for the GTO step-down converter circuit shown below. The specifications for the GTO are listed below. Theother circuit components are ideal. The switching frequency is 5 kHz.I A,max = 1500 A, BV BO = 1500 V, b off = 5, dI Adt max = 500 A/m s ,dV AKdt max = 750 V/m s, t fi = 1 m sa.The design proceedure used for turn-off snubbers for BJTs will not produce satisfactoryresults if used for GTOs. Explain why.b. Estimate values for C s and R s for the GTO turn-off snubber.S27.4.Consider the step-down converter circuit shown below. The switching frequency is 10 kHz. The characteristics of the free-wheeling diode and the switch S w are given below.D f S wLifetime t = 0.5 microseconds Maximum instantaneous current = 250 ASnappiness S =1 Blocking voltage = 500 Vt ri = t fi = 0.5 m s = t fv = t rvD f +-I o = 200 AV d= 300 V S wa. Show that a turn-on snubber is required in this circuit.b. Estimate values for L s and R Ls for the turn-off snubber.S27.5.Consider the diode rectifier circuit shown below. The diode characteristics are also givenbelow.100 v base-to-peak 10 kHz square wave1 m H100 ADiode ParametersReverse recovery time t rr = 10 m s Snappiness factor S = 0.25a. What is the magnitude of the overvoltage across the diodes due to the reverse recovery current?b. Design a snubber circuit to limit the overvoltage. Indicate the placement of the snubber circuit as well as the component values.c. How much power is dissipated in the snubber resistance?S27.6.Consider the step-down converter shown below. It is switched at a 20 kHz rate and it has a33% duty cycle. The stray inductance L s = 100 nH. The IGBT specifications are givenbelow. Assume that the free-wheeling diode is idealBV DSS = 700 V ; I D,max = 200 A ; t ri = t fv = 200 nsec ; t rv = t fi = 500 nsec R q ja = 1 °C/W ; T j,max = 150 °C ; V DS,on = 0.8 + (0.01)I DD f +-I o = 40 AV d= 500 V QswL sa.Is the IGBT being overstressed? Specify the overstress quantitatively.b.Specify the type or types of snubber circuits needed in this circuit for reducing the stresses on the transistor to a safe level. The number of snubber circuits should be minimized. Justify your choices.S27.7.A turn-off snubber is to be designed for the circuit of problem #S27.6.a.Specify the values of capacitance C s and resistance R s .b.How much are the turn-off losses in the IGBT reduced by the turn-off snubber?S27.8.A step-down converter operating at a switching frequency of 20 kHz is shown below.The waveforms for the switch current and switch voltage for one switching cycle are also shown below. The switch is rated for amaximum instantaneous current of I sw,max = 250A and a maximum instantaneous voltage of V sw,max = 700 V.500 V200 AL sa.What is magnitude of the stray inductance in the circuit?b.What is the reverse recovery current of the free-wheeling diode?c.Does the switch require any snubbers to protect it? Specify the type or types needed, if any.d.Design a snubber to limit the peak switch voltage to 600 V.。

AS1系列指南手册说明书

AS1 SERIESINSTRUCTION MANUALCONTROLSOUT LED on receiver (RX)The yellow LED ON indicates the presence of the object into controlled area.POWER ON LED on receiver (RX)The green LED ON indicates the optimal device functioning.The fast blinking of the green LED indicates a critical device alignment. Please refer to “DIAGNOSTICS” paragraph for other indications.POWER ON LED on emitter (TX)The green LED ON indicates the correct device functioning.Please refer to “DIAGNOSTICS” paragraph for other indications.INSTALLATION MODEGeneral information on device positioning• Align the two receiver (RX) and emitter (TX) units, verifying that their distance is inside the device operating distance, in a parallel manner placing the sensitive sides one in front of the other, with the connectors oriented on the same side. The critical alignmentof the unit will be signalled by the fast blinking of the green receiver LED.• Mount the two receiver and emitter units on rigid supports which are not subject to strong vibrations, using specific fixing brackets and /or the holes present on the device lids.Precautions to respect when choosing and installing the device• Choose the device according to the minimum object to detect and the maximum controlled area requested.• In agro-industrial applications, the compatibility of light grid housing material and any chemical agents used in the production process has to be verified with the assistance of the DATASENSOR technical sales support department.• The AREA scan TM light grids are NOT safety devices, and so MUST NOT be used in the safety control of the machines where installed. Moreover the following points have to be considered:- Avoid installation near very intense and / or blinking light sources, in particular near to the receiver unit.- The presence of strong electromagnetic disturbances can jeopardise the correct functioning of the device. This condition has to be carefully evaluated and checked with the DATASENSOR technical sales support department;- The presence of smoke, fog and suspended dust in the working environment can reduce the device’s operating distance.- Strong and frequent temperature variations, with very low peak temperatures, can generate a thin condensation layer on the optics surfaces, compromising the correct functioning of the device.- Reflecting surfaces near the luminous beam of the AREA scan TM device (above, under or lateral) can cause passive reflections able to compromise object detection inside the controlled area.- if different devices have to be installed in adjacent areas, the emitter of one unit must not interfere with the receiver of the other unit.General information relative to object detection and measurement• For a correct object detection and / or measurement, the object has to pass completely through the controlled area. Testing the correct detection before beginning the process is suggested. The resolution is non uniform inside the entire controlled area. For example the resolution in the AS1-HR model depends on the scanning program chosen.CONNECTIONSAS1-HR AS1-SR AS1-HR AS1-SR1 – brown: +24 VDC +24 VDC 1 – brown: +24 VDC+24 VDC2 – white:SEL_RXNot used2 – white:SEL_TX Not used3 – blue: 0 V0 V3 – blue: 0 V 0 V4 – black: Switching output Switching output 4 – black:SYNC SYNCRECEIVER (RX):M12 5-pole connector5 – grey: SYNC SYNCEMITTER (TX):M12 4-pole connectorShielded cables are not foreseen in the standard connection.Ground connection of the two units is not necessary. If desired, this connection can be obtained replacing the screw provided in the packaging with the one indicated in the drawing, which blocks the lid of the connector side of each unit.The respect of the connection shown in the drawing, is necessary if ground connection of the entire system is requested.FUNCTIONING AND PERFORMANCESThe beam interruption due to the passage of an object inside the controlled area causes the closing of the switching output and the variation of the device analogue output signal. Small objects can be detected (reaching dimensions of only 0.5 mm) and with a reduced surface area.In particular:The switching output is always activated when at least one beam is obscured. The status variation is signalled by the yellow receiver LED that turns on.The device presents inputs (both on TX and Rx units) that consent the selection of the resolution and response time.Low response times correspond to worser resolutions and viceversa.The device does not require calibration; periodical checks of the resolution and / or measurement are however suggested.The blinking of the green receiver LED (stability function ) signals the critical alignment of the units and / or the functioning outside or near the maximum operating distance. In optimal conditions the LED remains on continuously.The two units are synchronised via cable (SYNC wire).Precarious connections or induced disturbances on the synchronism line can cause device malfunctioning or a temporary blocking.DIAGNOSTICSRECEIVER UNIT:Segnal StatusCauseActionONSwitching output.Presence of the object in the controlled area.OUT LEDOFFSwitching output.Controlled area free of objects.ONOptimal functioning. Fast blinkingCritical alignment of the unit or/and functioning closed to maximum operating distance.Slow blinkingWrong connections and/or malfunctioning.- Verify the output connections and any short-circuits.- Switch OFF and switch ON the device.- If condition persists, contact Datasensor.POWER ONLEDOFFDevice is not powered.- Verify the connections.- If condition persists, contact Datasensor.EMITTER UNIT:POWER ONLEDPROG. N°SEL_RXSEL_TXRESOLUTIONRESPONSE TIME (msec )1 0V or FLOAT 0V or FLOAT LOW 2.752 0V or FLOAT +24Vdc M/L3 3 +24Vdc 0V or FLOAT M/H 7.754 +24Vdc +24Vdc HIGH 8Resolution figure : the box indicated the area with highest resolutionPROGRAM 1PROGRAM 2PROGRAM 3 - 4Ideal for fast detection on entire controlled area, with low resolution.Ideal for fast detection on entire contolled area, with constant resolution onlimited area.Ideal for detection with high resolution on entirecontrolled area.DIMENSIONS 800-262-4332-------------------------------------------------------------------------------------------------------------------------------------------- DECLARATION OF CONFORMITYIDEC and DATASENSOR jointly declare under their sole responsibility that these products conform to the 2004/108/CE, 2006/95/CE Directives, and successive amendments.-------------------------------------------------------------------------------------------------------------------------------------------- IDEC and DATASENSOR reserve the right to make modifications and improvements without prior notification.826003450 Rev.00。

非极大值一致 nms的工作流程英语

非极大值一致 nms的工作流程英语Non-Maximum Suppression (NMS)。

Non-maximum suppression (NMS) is a technique used in object detection to remove redundant bounding boxes that overlap with each other. It aims to retain only the most confident bounding boxes that are likely to contain the object of interest.Workflow of Non-Maximum Suppression.The workflow of NMS involves the following steps:1. Input: NMS takes as input a set of bounding boxes and their corresponding confidence scores.2. Sort Confidence Scores: The bounding boxes are sorted in descending order of their confidence scores.3. Iterate Over Bounding Boxes: The algorithm iteratesover the bounding boxes in descending order of their confidence scores.4. Select Best Bounding Box: The bounding box with the highest confidence score is selected as the best bounding box.5. Calculate Overlap: For each subsequent bounding box in the iteration, the algorithm calculates the overlap between it and the best bounding box.6. Suppress Overlapping Boxes: If the overlap between a subsequent bounding box and the best bounding box exceeds a predefined threshold, the subsequent bounding box is suppressed and removed from the list of bounding boxes.7. Repeat Until No Overlap: Steps 5 and 6 are repeated until there are no more overlapping bounding boxes.8. Output: The output of NMS is a set of non-overlapping bounding boxes that represent the most confident object detections.Threshold Selection.The threshold used for overlap calculation is crucialfor the effectiveness of NMS. A low threshold can result in excessive suppression, while a high threshold may lead to missed detections. The optimal threshold value depends on the specific object detection task and the size of the bounding boxes.Variations of Non-Maximum Suppression.There are several variations of the basic NMS algorithm, including:Soft NMS: This variation allows for partialsuppression of overlapping bounding boxes, preserving bounding boxes with lower confidence scores but higher overlap.Adaptive NMS: This variation adjusts the suppression threshold based on the size of the bounding boxes toaccommodate scale variations.Weighted NMS: This variation assigns weights to the bounding boxes based on their confidence scores and spatial locations to prioritize suppression of less important bounding boxes.Applications of Non-Maximum Suppression.NMS is widely used in object detection and computer vision applications, such as:Object localization.Image classification.Facial detection.Pedestrian detection.Vehicle detection.Scene understanding.Additional Notes:NMS is a greedy algorithm, meaning it makes locally optimal decisions at each step without considering thelong-term impact on the result.NMS can be computationally expensive for large sets of bounding boxes.Alternative approaches to NMS for removing redundant bounding boxes include grouping and clustering techniques.。

vbscript invalid memory access

vbscript invalid memory access VBScript is a programming language that was popularly used in the early days of web development. While it had its advantages, it was prone to certain errors, one of which is the "invalid memory access" error. In this article, we will explore what this error means, why it occurs, and how to troubleshoot and fix it.What is VBScript's "invalid memory access" error?The "invalid memory access" error in VBScript typically occurs when a script attempts to access memory that it does not have permission to access. This error is commonly caused by coding errors such as accessing an uninitialized or freed memory block, writing or reading outside the bounds of an array, or accessing an object that has been destroyed.Why does the "invalid memory access" error occur?The "invalid memory access" error occurs primarily due to programming mistakes. Some common reasons for this error include referencing an object that has already been released, using variables without declaring or initializing them, or manipulating arrays outside their allocated boundaries. Additionally, unintended recursion or infinite loops can also lead to this error if not handledproperly.Troubleshooting and fixing the "invalid memory access" error:1. Debugging with error handling:When encountering the "invalid memory access" error, the first step is to enable error handling in your VBScript code. By using the "On Error Resume Next" statement, your script will continue executing even if an error occurs. This allows you to identify the specific line where the error has occurred.2. Identify the faulty code:Once you have enabled error handling, examine the code preceding the error line to identify the problematic piece. This may involve reviewing code blocks, loops, or array manipulations that could potentially cause the error.3. Check variable initialization:Ensure that all your variables are initialized before they are accessed. Variables declared without proper initialization can potentially lead to memory access issues. Review the script for any variables that have not been assigned a value before being used.4. Validate object references:Check for any code that references objects. It's crucial to ensure that objects are properly created, haven't been released, or haven't exceeded their scope. Invalid object references can result in memory access errors.5. Review array manipulations:Examine your code for any array manipulations such as indexing, iterating, or resizing. Ensure that you are not performing any operations that would exceed the bounds of the array. Accessing elements beyond the array's boundaries can result in an invalid memory access error.6. Avoid infinite loops and unintended recursion:If your code involves loops or recursive functions, make sure they are well-structured and not causing an infinite loop. Infinite loops can quickly deplete memory resources and lead to invalid memory access errors. Implement proper controls like loop counter variables or exit conditions to prevent these issues.7. Use appropriate memory management techniques:Consider implementing memory management techniques likeexplicitly releasing objects when they are no longer needed. By freeing up memory resources, you can reduce the chances of encountering an invalid memory access error.8. Debugging tools and techniques:Leverage available debugging tools and techniques to identify and resolve the error. VBScript supports tools like the Microsoft Script Debugger or third-party debugging software, which can help pinpoint the problematic code or provide insights intomemory-related issues.In conclusion, VBScript's "invalid memory access" error is a common issue that can occur due to coding errors and memory management mistakes. By following the troubleshooting steps outlined above, you can effectively identify and fix this error in your VBScript code. Remember to review your code for uninitialized variables, invalid object references, array manipulations, and potential infinite loops to minimize the chances of encountering this error.。

英语俱乐部招募新成员介绍自己作文

英语俱乐部招募新成员介绍自己作文全文共3篇示例，供读者参考篇1My Journey to Joining the English ClubAs I stand here today, ready to embark on a new chapter as a member of the prestigious English Club, I can't help but reflect on the winding path that led me to this moment. From a timid child who could barely string together a coherent sentence in English, to the confident young adult I am today, my journey has been one of perseverance, determination, and an unwavering love for the English language.Growing up in a household where English was not the primary language, I often found myself struggling to keep up with my classmates. While they effortlessly navigated through the intricacies of grammar and vocabulary, I would stumble over the simplest of phrases, my tongue tied in knots as I desperately tried to convey my thoughts. It was frustrating, to say the least, and I often found myself retreating into a shell, too embarrassed to participate in class discussions or engage with my peers.However, it was during those moments of self-doubt that a spark ignited within me – a burning desire to conquer this language that seemed so elusive. I began to devour books, immersing myself in the rich tapestry of English literature. From the whimsical worlds of Dr. Seuss to the profound philosophies of Shakespeare, I allowed myself to be swept away by the sheer beauty and depth of the English language.As my vocabulary expanded and my grasp of grammar solidified, I found myself gradually shedding the shackles of insecurity that had once held me back. I began to raise my hand in class, eager to contribute to discussions and share my newfound knowledge. My teachers took notice of my dedication, and they encouraged me to explore extracurricular activities that would further nurture my passion for English.It was then that I discovered the English Club – a haven for like-minded individuals who shared my fervor for the written and spoken word. At first, I was hesitant to join, plagued by the familiar doubts that had once held me captive. But the welcoming smiles and infectious enthusiasm of the club members soon put those fears to rest, and I found myself eagerly diving into the world of debates, poetry readings, and writing workshops.Each meeting was a revelation, a chance to expand my horizons and challenge my preconceptions about the English language. I reveled in the spirited discussions, where we would dissect the nuances of literary works and explore the intricate tapestry of language. It was in these moments that I truly felt alive, my mind racing with ideas and my heart swelling with a newfound sense of belonging.As I progressed through the ranks of the English Club, taking on leadership roles and organizing events, I realized that my journey had transcended mere language acquisition. It had become a testament to the power of perseverance and the transformative nature of education. I had not only gained proficiency in English but also the invaluable skills of public speaking, critical thinking, and teamwork – tools that would serve me well in any endeavor I pursued.Today, as I stand before you, eager to embark on this new chapter as a member of the Englis篇2My Passion for the English Language and LiteratureI still vividly remember the day I first fell in love with the English language. It was in my fourth-grade English class, andour teacher had us read a beautiful short story called "The Butterfly" by Patricia Polacco. As I followed along, transported into the vibrant world the author had painted with her words, I was struck by the magic and poetry of this foreign tongue. The rhythmic flow of the phrases, the nuanced depth of the vocabulary – it was like an intricate tapestry being woven before my eyes and ears.From that day on, I became insatiable for more English stories, novels, poems, and plays. I started devouring any English books I could get my hands on, classics like The Secret Garden by Frances Hodgson Burnett and modern tales like Harry Potter. With each new protagonist whose lives and adventures I experienced, my love and appreciation for the incomparable richness of the English language only grew deeper.While many of my peers saw English class as just another academic requirement, to me it was a window into entire worlds of magic and beauty. I would lean forward raptly during our literature units, hungrily drinking in the teacher's every word of analysis and contextual insight about the great works we studied. My favorite units were always the ones on poetry, as I found the economy and condensed power of poetic phrasing utterly mesmerizing.English opened my eyes not just to the artistic and creative potential of language, but also to fundamental truths about the human condition. As I explored writings across genres, cultures, and eras, I came to see how literature serves as a mirror into the depths of the human heart and psyche. The triumphs and tragedies, hopes and fears, joys and sorrows contained within the lines of great English works resonated profoundly within me.I realized that mastering English was not just about fluency in a global lingua franca, but about gaining a greater understanding of the common threads that join all of humanity together.Due to my profound passion for English, I have consistently excelled in the subject throughout my schooling. While my peers would groan about having to write the occasional essay or book report, I relished those opportunities to engage substantively with the texts and creatively express my thoughts and insights. My teachers have regularly praised my nuanced analysis, vibrant vocabulary, and effective argumentation in my writing. Just last year, I was even awarded the Outstanding Literary Analysis award at my school's annual English ceremony.Beyond my success in the classroom, I've also pursued several extracurricular projects and activities to further develop my English skills. For the past two years, I've been a writer andeditor for my school's literary magazine, "Word Tapestries." Getting to publish my own original poems and short stories while reviewing and polishing the creative submissions of my peers has been an incredibly enriching experience.I've also been an avid member of our school's Book Club, where we read and dissect a new novel every month. Our lively discussions analyzing plot, character, symbolism and more have constantly stretched me to view literature through new critical lenses. Some of my most cherished memories are from the weekend-long "Book Bashes篇3My Journey with the English Language - An Invitation to Join Our ClubGreetings, fellow students! Allow me to take you on a journey through my personal experiences with the English language, a journey that has led me to become a passionate advocate for linguistic exploration and cultural exchange. It is with great enthusiasm that I invite you to join our vibrant English club, where we embrace the richness of this remarkable language and foster an environment of growth, camaraderie, and intellectual curiosity.My love affair with English began at a tender age, when I was first introduced to the melodic cadence of its words. As a young child, I found myself captivated by the enchanting tales that unfolded within the pages of storybooks, each one a window into a world where imagination knew no bounds. It was in those early years that the seeds of my linguistic fascination took root, and I began to cultivate a deep appreciation for the intricacies of the English language.As I progressed through my academic journey, English became more than just a subject; it became a canvas upon which I could express my thoughts, emotions, and creative visions. The beauty of this language lies not only in its versatility but also in its ability to convey nuanced meanings and evoke powerful emotions. With each literary work I explored, I found myself transported to distant lands, immersed in diverse cultures, and exposed to perspectives that challenged my own worldview.It was during my high school years that I truly embraced the transformative power of the English language. I joined the school's debate team, where I honed my skills in articulating complex ideas, constructing persuasive arguments, and thinking critically. The thrill of engaging in intellectual discourse, of exchanging viewpoints and challenging preconceived notions,ignited a fire within me that continues to burn brightly to this day.Beyond the academic realm, my passion for English extended into the realm of creative writing. I found solace in the art of storytelling, weaving intricate narratives that allowed me to explore the depths of the human experience. With each poem, short story, or personal essay I crafted, I discovered the cathartic power of self-expression and the ability to connect with others on a profound level.However, my journey with English has not been a solitary one. It has been enriched by the invaluable guidance of dedicated teachers and the camaraderie of like-minded individuals who share my enthusiasm for language and culture. It was through their support and encouragement that I discovered the English club, a vibrant community where kindred spirits gather to celebrate their shared love for this remarkable language.Within the club, we engage in a myriad of activities that foster linguistic growth and cultural understanding. From lively discussions on contemporary literature to engaging debates on current events, we challenge one another to think critically, express ourselves eloquently, and broaden our horizons. Wedelve into the intricacies of grammar and vocabulary, exploring the nuances that make English such a rich and expressive language.But our club is more than just a platform for academic pursuits; it is a space where lifelong friendships are forged. We organize movie nights, cultural festivals, and language exchange programs, creating opportunities for cross-cultural connections and fostering a sense of global citizenship. Together, we celebrate the diversity that English encompasses, embracing the unique perspectives and traditions that make our community truly extraordinary.。

runtimeexception unexpected code -回复

runtimeexception unexpected code -回复RuntimeException Unexpected Code: A Comprehensive ExplanationIntroductionIn the world of programming, it is not uncommon to encounter unexpected errors and exceptions. One such exception that developers might come across is called "RuntimeException unexpected code." This error message may leave programmers scratching their heads, wondering what went wrong and how to fix it. In this article, we will dive deep into understanding the peculiar nature of this exception and explore the step-by-step process to troubleshoot and resolve it efficiently.Section 1: Understanding RuntimeExceptionRuntimeException is a subclass of the Exception class in Java. Unlike checked exceptions, RuntimeExceptions are unchecked, meaning that they do not need to be explicitly declared by methods. This makes them notorious for not being properly handled, leading to unexpected and often perplexing issues.RuntimeExceptions usually occur due to issues stemming from logical errors, incorrect data inputs, or an unexpected flow of the program. As a result, they may cause the program to terminate abruptly, leaving behind the confusing "unexpected code" error message.Section 2: Analyzing the Exception MessageThe error message "RuntimeException unexpected code" provides some clues on where to start debugging. However, it is often not detailed enough to provide direct insight into the root cause. To efficiently troubleshoot, we need to rely on techniques such as code review, testing, and debugging.Step 1: Review the CodeThe first step in resolving the "unexpected code" issue is to carefully review the code in question. Pay close attention to any areas where data is manipulated, method calls are made, or control flow statements are used. Look for any potential programming errors, such as null pointer dereferences, index out of bounds, orimproper use of language constructs.Step 2: Confirm the InputIf your code interacts with external inputs, such as user inputs or API responses, thoroughly validate and sanitize the input data. Validate the expected data types, check for null values, and make sure the data is within acceptable ranges. Unexpected inputs or incorrect data structures can trigger unexpected code paths and ultimately result in a RuntimeException.Step 3: Test with a Minimal Reproducible ExampleIf reviewing the code and verifying input data doesn't lead to a solution, it is helpful to create a minimal, reproducible example to isolate the issue. Create a small portion of the code that can reproduce the error consistently. By narrowing down the code to its essence, you can focus on finding the root cause without being distracted by extraneous details.Step 4: Debugging TechniquesWhen dealing with unexpected code exceptions, a debugger can be a valuable tool. Set breakpoints at critical points in the code and step through it line by line, observing the program's behavior. This will help identify the exact line or snippet of code where the exception is thrown. During the debugging process, inspect variables, verify assumptions, and verify that methods are invoked correctly.Step 5: Look for Specific Exception InformationRuntimeExceptions usually have subclasses that provide more specific information about the error. Inspect the exception stack trace to determine if any subclass or additional information is available. This may reveal more insights into the problem and help narrow down the troubleshooting process further.Section 3: Fixing the IssueOnce you have identified the root cause of the "RuntimeException unexpected code" error, take appropriate measures to fix it. Based on the specific situation, you may need to:1. Correct logical errors: Analyze the code that led to the exception and identify and fix any logical mistakes.2. Handle unexpected inputs: Implement appropriate validation and error-handling mechanisms to handle unexpected or incorrect input data.3. Normalize the program flow: Ensure that the program follows the expected control flow by checking conditions, handling edge cases, and properly implementing control flow statements.Section 4: Prevention is Better Than CureTo avoid encountering "RuntimeException unexpected code" errors in the future, practice defensive programming techniques. Perform thorough code reviews, employ automated testing frameworks, and write comprehensive test cases to cover a wide range of scenarios. Proper error handling, input validation, and adherence to coding best practices can significantly reduce the likelihood of runtime exceptions.ConclusionThe "RuntimeException unexpected code" error message can beboth puzzling and frustrating for developers. However, with a systematic approach comprised of code review, thorough testing, and effective debugging techniques, it is possible to identify and resolve the underlying issue. By being vigilant and proactive in applying preventive measures, developers can minimize the occurrences of unexpected code exceptions and enhance the stability and reliability of their programs.。

存在一个束缚态原子的光学腔中的光子阻塞(翻译)

一个束缚态原子的光学腔中的光子阻塞K.M.Birnbaum1,A.Boca1,ler1,A.D.Boozer1,T.E.Northup1&H.J. Kimble1在低温时，足够小的金属半导体装置表现出“库伦阻塞”效应，在这装置中的电荷转移是以电子和电子的相互作用位基础的。

例如，当半导体上的电荷能量远远高于热运动能量时，在金属半导体内的一个电子能够阻塞其他电子的流动。

类似的“光子阻塞”效应已经被用于在光学系统中的光传输；这涉及了在非线性光学腔中的光子与光子的相互作用[4-13]。

这里我们记述了在原子腔强耦合情况下含有一个束缚态原子的光学腔中光线传输的光子阻塞的观察。

第一个光子在原子腔系统中的受激阻塞了第二个光子的传输，因而将一个光子泊松流转变为一个非聚束的子泊松流。

这由传输场的光子统计测量来确定。

我们对光子阻塞的观察表现出了一种相对于传统非线性光学和激光物理学的优势，形成一种包括逐个的原子和光子的动力学过程的体系。

微电子装置中的电子传输和强耦合光学系统中的光子传输两者的类比在文献[5]中首次提及。

作者们提到类似于电子库伦阻塞的效应对光子与光子在非线性光学腔内的相互作用而引起光子的这种效应也是可能的。

在这个方案中，由电磁导入透明（EIT）引起的强色散相互作用使得腔中的第一个光子的出现阻塞了第二个光子的传输，进而引起一种传输场中产生有序的光子流。

最初的问题[6]解决之后，后续的工作确定了这样的光子阻塞对于一种多能态EIT结构的腔内只存在单个原子的结构中[7-9]是确实可行的。

光子阻塞在其他的设定中也具有可能性，包括与库伦阻塞[10]类似的效应以及局部等离子体表面的隧道贯穿效应[11]。

光子阻塞同样也被预测可以出现在与腔场模型耦合的二能级原子体系中[4/9/12/13]。

如图1a所展示的，潜在的物理机理与jaynes-cummings本征态能级不吻合。

频率为ω的光子的共振吸收产生了|1，-－>（其中|n,(+)->表示第n激发态的上能级（+）和下能级（-））态阻塞了第二个频率为ω的-光子的共振吸收，由于第二个光子与|2，±>态是共振失谐的。

Large Thermoelectric Power Factor Enhancement Observed in InAs

KEYWORDS: Nanowires, thermoelectrics, InAs, power factor, quantum dots, interference ﬃcient thermoelectric energy conversion requires materials with low thermal conductivity κ and with a high power factor. Semiconductor nanowires have attracted great interest for thermoelectrics because phonon surface scattering substantially reduces their κ1−4 and because one-dimensional (1D) electron conﬁnement eﬀects are predicted to signiﬁcantly enhance the power factor.5−9 However, this 1D power-factor enhancement eﬀect has to date not been realized, to the very best of our knowledge, in part because very thin nanowires (typically less than 20 nm),5−7,10 careful control of the carrier concentration,11,12 and either high electron mobility or very short wires are required. Here, we show that these strict conditions do not pose a limit to the performance of nanowirebased thermoelectrics. We report the observation of a power factor in InAs nanowires that exceeds that predicted by a singleband bulk model by up to an order of magnitude at temperatures below about 20 K. We attribute this enhancement eﬀect not to the long-predicted 1D subband eﬀects but to quantum-dot-like states that form in electrostatically nonuniform nanowires as a result of interference between propagating states and 0D energy resonances.13,14 Our result represents the ﬁrst observation of power-factor enhancement in nanowires due to quantum conﬁnement eﬀects. As this novel mechanism for power-factor enhancement is observed in ﬁeld eﬀect gated nanowires that are relatively thick (50−70 nm) and long

Sonza Reorda Testing a Switching Memory in a Telecommunication System

Testing a Switching Memory in a Telecommunication System 1S. BarbagalloF. Corno, P. Prinetto, M. Sonza ReordaItaltelPolitecnico di TorinoR&D Labs, Design Automation Dept.Dipartimento di Automatica e InformaticaSettimo Mil., ItalyTorino, Italy1Contact Person: Paolo PRINETTO, Politecnico di Torino, Dip. di Automatica e Informatica, Corso Duca degli Abruzzi 24, I-10129 Torino, Italy,tel. +39 11 564 7007, fax +39 11 564 7099, email Paolo.Prinetto@polito.itAbstractThe paper describes the approach followed for testing a real circuit produced by Italtel. Both on-line and off-line testing are considered, and the performance and area overheads are taken into account to meet the constraints imposed by the circuit customers. BIST is adopted to test some embedded memories, and Boundary Scan is exploited to activate the test and gather the results. Particular care is taken to minimize the additional logic, by using the same circuitry for both on-line and off-line testing.1. IntroductionMemory testing has been the subject of a great deal of research in the last decade: a number of approaches have been proposed, which allow the designer and the test engineer to find the optimal trade-off between test accuracy and cost. The former is measured in terms of coverage of the faults identified by one or more fault models. The latter is normally given by the algorithm complexity.When the memory is embedded in the chip and when external testing is not viable, BIST becomes an effective solution, as it is able to accurately test memories with reduced hardware and time tency is also a concern when errors must be detected during the normal behaviour of the circuit or system.This paper describes the testing approach followed by Italtel (the Italian leading manufacturer in the telecommunications industry) to test a switching memory circuit using a mixed approach. The circuit is the evolution of an existing design and belongs to the main unit of a telephone system; it is composed of two SRAM memories acting as switching matrix and address translator, respectively, and by the related circuitry. The goal was not only to devise a viable solution for the test to be performed at the end of the production process, but also to provide a reliable technique to test the circuit during its normal functioning.Several constraints had to be taken into account:• a maximum latency between a fault occurrence and its detection is imposed by the customer;• the switching memory circuit is a performance-critical part in the overall system, and a true on-line testing strategy is required;• the area and dissipation requirements call for minimizing the hardware overhead due to testing;• the performance degradation due to the insertion of additional hardware and to the activation of a test procedure has to be minimized.The adopted solution is a mix of a standard BIST technique [CPSB94] and a functional testing approach.The same hardware is mostly exploited for production and on-line testing.The next Section describes the circuit architecture and functionality; Section 3 reports the requirements and solutions adopted for testing, and Section 4 the protocol for test activation and test output verification.Quantitative data about the performance and area overhead required by this solution are provided in Section 5, showing the effectiveness of the proposed test architecture. Section 6 draws some conclusions.2. Functionality and Architecture of the Circuit2.1. General DescriptionThe circuit whose test is addressed in this paper is devoted to standard telephonic applications, i.e., to networks based on the circuit switching principle.The circuit is a programmable ASIC, capable of interconnecting a number of input channels with a number of output channels, independently of their own bit rate. The actual number of switched channels depends on the bit rate of the input flows.The software being executed on a master processor programs the speed and the internal structure of each accepted input flow, through a dedicated interface.In the present implementation the circuit accepts up to 24 input PCM flows and drives the same number of switched PCM outputs. The speed of each flow ranges from 8 to 32 Mbit/s.2.2. ArchitectureThe circuit basically consists of two large static memory arrays, which perform the switching between input and output channels (Fig. 1).The former memory, called Speech Memory, is actually written by the logic which samples the input flows and read by the output flow generators; the latter memory, named Command Memory, is used to supply the read address to the Speech Memory: in this way it actually controls the switching among the connected input and output channels.The Speech Memory has two separate access ports: one is used to write in the memory and is accessed by the logic which samples and synchronizes the input channels; the other is used to periodically drive each connected output channel. The address for this port is supplied by the Command Memory.The Command Memory owns two access ports, too: the former is a read-write port and is used by the master microprocessor to store and control the switching pattern, while the latter is a read-only port, which supplies the switching address to each cell within the Speech Memory. The address feeding this port is generated by a counter, which is pre-loaded by the master processor, and continuously browses the Command Memory.For both memories the two ports must be regarded as functionally separated: in other words, a write operation through one port and a read operation by means of the other port can be performed at the same time relying on different address decoders. In the case a conflict arises (the two ports are addressing at the same time the same memory cell) the write operation is correctly performed and the new data appears on the output bus; the generated word is the one which is being written and not the old content of the addressed cell.In the described implementation the Command Memory is composed of 4k words of 16 bits each. In order to match performance and power dissipation requirements (the maximum allowed working frequency is 32 MHz and the circuit has to dissipate less than 1.5 W), the memory is partitioned into eight blocks of 512 words per 16 bits each, using the three most significant address bits to select the block.In the same way, the Speech Memory memory is composed of 6 blocks, each made of 1k words per 8 bits, addressable with 13 out of 16 bits from the Command Memory, while the remaining 3 bits are used to store other information regarding the state of the switching matrix.3. Test Requirements and Architecture3.1. Industrial RelevanceAlthough used in a well established type of application, the circuit is expected to have great relevance for Italtel’s business, since it has to guarantee substantial cost savings in the production of a class of systems which still has a good acceptance in the market. According to the plans, Italtel will produce from 50,000 to 70,000 chips per year, while each chip is expected to cost about 50$.On the basis of these numbers, it is clear that the quality and reliability of the design have a real industrial impact.A very high quality test pattern, in terms of both fault coverage and application efficiency, has to be provided; at the same time a number of topics regarding the on-line testability of the whole system were addressed already at the chip level, as it will be explained in the following section.Since the circuit is part of a high quality and reliable system, it must satisfy very severe constraints; some of them concern the quality of the test performed on the chip before it is mounted on the board, some others forced Italtel to adopt suitable techniques for the on-line test of the circuit.3.2. On-Line TestIn the following Sections we will shortly describe the adopted strategy for the on-line test of each part within the circuit; then, we will discuss the implementation of the adopted strategy by means of a BIST approach. Further details can be found in [Barb95].3.2.1. Error Latency Requirements for the Whole Switching SystemBoth static and dynamic RAMs are known to be sensitive to the effects of alpha particles, which can alter their content [CaWi87]. To detect faults of this kind, as well as others of different origins, the chip must be continuously tested and its correct behaviour verified by a set of on-line diagnostic procedures. In order to meet the test constraints concerning the maximum time latency before a fault in the telephoneconnection is detected, the behaviour and the activation frequency of the procedures must be carefully chosen.In our solution, each part of the logic is continuously kept under control during the normal life of the system. More precisely, this means that the diagnostic routines running on the master processor must be able to access, at any time, some information items concerning the state of any functional part of the chip. Both the computation and the access to these information must be done in a true on-line fashion, i.e., without interfering with the normal behavior of the system.As soon as a hardware defect is detected, which may cause a faulty behavior, the system changes the switching pattern, in order to still guarantee safe connections.At the chip level, another important requirement is that normal circuit functions may never be interrupted, that is the normal flow of input streams toward output channels must never be slowed down and the master processor must always be free to change the switching connections, without having to wait for the end of internal test operations. This last requirement makes unacceptable any approach based on memory transparent testing, as it was proposed by [Nico92], since in that case writing to the memory during test is not allowed.On the other side, being Italtel a system maker rather than a silicon foundry, it is in the company strategy to develop test techniques as much independent as possible from the selected foundry’s library: therefore, on-line testing solutions which are based on re-organizing the low-level structure of memories (like the one in [KZNi95]) have not been taken into account.Given the above limitations and relying on the circuit internal structure, an ad hoc strategy was developed to guarantee sufficient on-line testing capabilities.3.2.2. On-Line Test of the Speech MemoryContinuous monitoring is performed resorting to a special block, called Embedded Connection Control (ECC), which performs the on-line verification of the correct execution of a required connection between an input and an output channel. To obtain the maximum fault coverage, input and output channels are sampled; in other words, ECC can read any input and output channel (Fig. 2). ECC is thus able to cyclically check every activated connection by properly sampling and comparing the input and output flows.As soon as a mismatch is detected, an alarm interrupt (Connection Fault) is sent to the master microprocessor, which is then able to identify the channels which have not been correctly connected.If a connection is disabled, the result of the corresponding test operation is discarded and the ECC skips to the next connection to be verified.Last, the ECC has a dedicated output used by the microprocessor to check if the block itself is correctly doing its job, so that ECC itself may be verified before restarting a new connection verification loop.3.2.3. On-Line Test of the Command MemoryAs it was described in the previous section, the ECC circuit allows the real time verification of each specific connection from an input channel onto the corresponding output channel. The problem now resides in how the ECC knows which output channel is connected at any time with a particular input channel.Actually, the ECC still relies on the address produced by the Command Memory on its read-only port. So, to be sure that the ECC can keep under control the whole connection pattern it is necessary to verify that both the Command Memory and its output port are working well at any time and for any address.Let's first examine the on-line test of the read-only port, while in the next sub-section the test of the memory array will be considered.Test of the Command Memory PortsAs already mentioned, the address for the Command Memory read-only port is generated through a counter, which performs a continuous 4k cycles loop, thus allowing to read the whole memory content in sequence.Since the other port, after the loading of the initial connection pattern, is seldom accessed by the master processor, during idle periods it is possible to make it work in parallel with the read-only one, so that the two outputs values may be compared.For this purpose a counter equal to the one used for the second port is embedded in the interface of the read-write port: as soon as the master processor finishes an access operation, the counter is loaded with the present value of the address at the second port; then the two counters evolve in parallel, so that at any cycle the two output busses should be equal, unless an error on one port happens. A comparator is used, and if a mismatch is detected, an error message is sent to the master processor.Test of the Command Memory ArrayThe operations described in the previous subsections are not enough to guarantee a full on-lineverification of chip functionality unless the memory arrays of the command RAM are checked, too.In order to perform such a task a spare RAM block is provided and the following test strategy has been adopted. Since the 4k words of the command RAM are distributed over 9 blocks, there is always one unused 512-words RAM array, whose content is not functionally required and to which an off-line, content destructive BIST procedure may be applied. Once the test of the i-th block is finished, this is used for normal behaviour in place of the (i+1)-th block, whose content is copied into the i-th block; the test of the new block is then started. In this way, the test procedure does not interfere with the normal behaviour of the circuit, and no delay is introduced in the processor activity.When the first 8 blocks have been tested, the test flags are updated and a new procedure is entered, in which each block is tested (starting from the ninth one), and then substitutes the (i-1)-th one. The whole procedure is described by the pseudo-code of Fig. 3.We demonstrated that during block test operations no interference is possible between test and functional memory access, since they always regard different blocks; on the contrary, a conflict may arise during memory copying, in the case the microprocessor has to access the same array which is involved in the copy operation. To avoid such conflicts and to guarantee that block copying keeps consistency of memory contents, even if one or more cell modifications happen during application, the copy operation is always interrupted when the microprocessor has to access the Command Memory. If a write operation must be performed on the source block, the new data is written at the same time also in the destination block.The copy operation consists in reading each memory cell and subsequent writing of the read word in the target block. In order to check the functionality of the data path used for the copy operation, the read operation on the block under copy is performed twice for each cell.If the microprocessor has to access the Command Memory, the single cell copy operation is completed, then the copy procedure is suspended until the microprocessor has performed its own operations.The same test procedure used for off-line test (see the next sub-section) may be applied in sequence to any RAM block without interfering with the normal functional operations of the Command Memory. However, some circuitry is required to select at any time the block under test, at to map the addresses generated by the functional logic into the 8 memory blocks which are not under test. The same circuitry is in charge of issuing the End_of_Test signal. In summary, this circuitry acts as a manager, orchestrating the work of the BIST controller and of the addressing logic in the circuit.In [CPSB94], the following expression was derived to determine the length of the proposed BIST procedure:total_test_cycles ~30*n*(log2(m)+p)where n is the number of words, m the number of bits per word and p the number of ports; from this formula we can derive the length of the on-line verification procedure.Each on-line verification run requires eight off-line BIST RAM applications plus eight block copy operations, not taking into account interrupts coming from the microprocessor. Each BIST procedure applied to a 512x16 dual port block thus requires:total_test_cycles ~ 30*512*(4+2) while each copy procedure requires:total_test_cycles ~ 2 * 512 Then the cost for the whole on-line verification run is:total_test_cycles ~8*(180+2)*512 = 745472This value is however a lower limit, since also the number of clock cycles subtracted by the microprocessor operations has to be taken into account. However, this time overhead is negligible since the microprocessor, which is supposed to require on the average a small number of memory accesses, just slows the test procedure when it interrupts a copy operation, which on the other hand, will take just a very small percentage of the whole test time.To ease the microprocessor verification task, an End_of_Test signal is provided, which is asserted when the final procedure result is available on output flags.3.3. Test for Incoming InspectionOn one side, the chip needs to be a high quality design: as a consequence, it must have a very accurate test program to be applied at incoming inspection, in order to detect bad elements before mounting them on a switching board. On the other side, it will be produced in many thousands of pieces per year: therefore, the test program must also be very efficient and applicable on unadvanced A TEs, like those used for large volumes at the production site.These considerations forced us to adopt a BIST technique for the RAMs embedded in the circuit, while the remaining glue logic is tested with a conventional partial scan approach. The applied BIST technique is basically the one developed in Italtel and illustrated in[CPSB94]; nevertheless, specific solutions have been introduced in order to obtain the highest possible efficiency with the minimum amount of added logic. For what concerns the incoming inspection, power dissipation limitations do not apply (the test itself takes a limited period of time and is usually performed at low frequency); therefore, in order to reduce the length of the test program, it is acceptable to test as many blocks as possible in parallel at the same time.This result is obtained by testing the six blocks of the Speech Memory in parallel, i.e., applying to each of them the same test address at the same time; in order to save test hardware, the output of each odd block is compared with the one belonging to the corresponding even RAM block (Fig. 4). Four bits are produced, belonging to a bit vector named OUTFLAGS, which reports the result of the tests; the vector is easily accessible from the outside of the chip.The Command Memory and the Speech Memory are tested in parallel, and the same address generation logic is exploited; since memory blocks of the former are half in size with respect to the ones of the latter, two runs of the BIST procedure can be made on the Command Memory while one is made on the Speech Memory. In the first run, all the even blocks are tested; in the second, all the odd ones are tested. The signal which determines whether the odd or even blocks are under test is the most significant one among the 10 address bits produced by the address generation logic.All the blocks but the first are tested in couples: in the first run of each test step the output ports of blocks 2 and 6 are compared with the same ports of blocks 4 and 8, respectively, while in the second run blocks 3 and 7 are compared with blocks 5 and 9 respectively; in this way, only two comparators and 12 bus multiplexers are required to perform the test of eight memory blocks with two ports each. The first block is tested in a different way: its outputs are compared with the expected word produced by the BIST Controller, thus verifying the BIST Controller itself. Moreover, this solution does not introduce any additional overhead, as the Comparator and Error Detection circuit of the first block are re-used in the on-line test.To verify both of the two read ports of the Command Memory, a further test step is introduced: while the test of the memory array is performed through the read write port, a further step is performed writing through the same port, but checking the output which appears on the read-only port. For this reason the two outputs busses of each block have also been multiplexed. The resulting test architecture is shown in Fig. 5.For what concerns the incoming inspection procedure, the first block is enabled like any other odd block, while its outputs are compared against the expected word produced by the BIST Controller. We will adopt again the formula given in [CPSB94] to compute the length of the BIST procedure for the 15 memory blocks of the circuit.In fact, the total test time is equal to the number of cycles required to test a single two ports RAM of 1k words per 16 bits, that is:total_test_cycles ~30*1024*(log2162) = 184,3204. Test ProtocolThe chip architecture implements a powerful and flexible interface for the activation of the test procedures, and for gathering the results they produced.The results of the BIST procedure are available in ten output flags, grouped in a vector called OUTFLAGS. For each flag, two bits are used, adopting a 1-out-of-2 code to shield the effect of faults on the flag generation logic. The two less significant flag bits (OUTFLAGS(1:0)) are used to store the information regarding the on-line test of the whole Command Memory and the off-line test of block 1 in the same RAM; OUTFLAGS(3:2) store the information about the result of off-line test application to the rest of the Command Memory; each couple of the remaining flags is used to store the results of the off-line test of the Speech Memory (OUTFLAGS(5:4) give information on blocks 1 and 2, OUTFLAGS(7:6) on blocks 3 and 4, and OUTFLAGS(9:8) on blocks 5 and 6). Soon after each restart of both on- and off-line test the good circuit flags must assume the hexadecimal value OUTFLAGS=2AA; at the end of the off-line test procedure their value must be 155, while after the completion of the on-line test their value must be 2A9; any other value means that the circuit is faulty, since it identifies a failure either in the memory arrays or in the BIST logic.The test circuitry issues a further signal named OUT_EOT which identifies the end of the on-line verification procedure; after any BIST logic restart it must be OUT_EOT=0, while at the end of the procedure OUT_EOT=1; if the flags assume their final good value (OUTFLAGS=2A9) when it is still OUT_EOT=0, then the circuit should be considered faulty, since this condition depends on a fault present in the test circuitry.The chip architecture supports two ways for activating the self-test capabilities and gathering the results:• through the microprocessor interface• through the TAP interface of the circuit.4.1. Test Interface through the TAP interfaceThe off-line BIST capabilities can be activated through the TAP thanks to a dedicated interface called BSBINT (Boundary Scan BIST Interface). This includes a parallel-input serial-output register which is connected between the TDI and TDO pins when the RUNBIST instruction is selected. The register can be loaded with the values of OUTFLAGS and can be used to serially shift them to the outside.The test protocol may be summarized as follows:• load the RUNBIST instruction• move the TAP Controller to the Run-Test state: BSBINT clears the BIST logic• move the TAP Controller to the Shift-DR state and check the initial content of the output flags • move again the TAP Controller to the Run-Test state: BSBINT starts the BIST procedure • remain in the Run_Test state until the required test period is elapsed• move again the TAP Controller to the Shift-DR state and check the final content of the outputflags.4.2. Test Interface through the MicroprocessorThe chip includes a couple of registers which are accessible by the microprocessor and allow it to activate the on-line and off-line test procedures and to read the results:• BIST_FLAGS_REGISTER is a read-only register which contains the OUTFLAGS values;an event flag is activated when the test procedurefinishes and BIST_FLAGS_REGISTER is readyfor access;• CONTROL_REGISTER is a read/write register: thw two bits NT and TONL allow themicroprocessor to specify the BIST procedure tobe activated. In particular:− if NT=0 no BIST procedure is activated− if NT=1 and TONL=0 the off-line test procedure is activated− if NT=1 and TONL=1 the on-line test procedure is activated.5. Test Logic OverheadThe chip is now being produced using the ST library ISB35000, implementing a 0.5µ, 3V technology. The area overhead due to the introduced test logic may be computed as follows.The 14 functional memory blocks occupy a total of 40,000,000 µm2. The logic overhead is due to:• the spare RAM block, 1 out of 14 total blocks (the size of the arrays used in the Command andin the Speech Memory is the same), implies a7.1 % area increase;• the logic used to generate the whole test procedure and to store the results occupies about1,4000,000 µm2, corresponding to a 3.5 % areaoverhead with respect to the 14 functionalblocks;• all the multiplexers which are used to switch between normal and test addresses and data;such gates require about 295,000 µm2, whichcorresponds to a 0.8 % area increase with respectto the functional memories.The whole area overhead for the proposedimplementation is less than 11.4 % of the functionalmemory area; however, this figure would considerablydecrease if the same architecture should be applied to ahigher number of RAM blocks. In fact, the maincontribution comes from the added memory, while onlythe blocks which perform the RAM selection within theBIST Control Logic depend on the number of memoryarrays to be tested.We also distinguished the test logic devoted to on-line testing from the one for off-line testing. All theblocks used for the latter are also used for the former;on the other side, the block in charge of managing theblock copying operation is the only one used for juston-line testing. The area overhead due to this block isno more than 0.3%, out of the 3.5% for the total BISTlogic.6. ConclusionsThe circuit was successfully designed and simulatedand the final development process is currentlyundergoing at the foundry site.The test strategy described in this paper allowed usto obtain a very high covering test program forincoming inspection. Every internal test resource ishandled by means of a Test Access Port, in compliancewith the 1149.1 IEEE standard.At the same time, by means of a dedicatedmicroprocessor interface, it is possible to activate anon-line verification procedure capable of givinginformation regarding the state of any part of thecircuit. For what concerns the Command Memory, thisrequirement was matched by adding a spare memoryblock and modifying the logic introduced to supportparallel off-line BIST of any memory array.。

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BRICS ISSN 0909-0878March 2005BRICSRS-05-9Frandsen&Miltersen:ReviewingBoundsontheCircuitSizeoftheHardestFunctionsCopyright c 2005,Gudmund Skovbjerg Frandsen&Peter BroMiltersen.BRICS,Department of Computer ScienceUniversity of Aarhus.All rights reserved.Reproduction of all or part of this workis permitted for educational or research useon condition that this copyright notice isincluded in any copy.See back inner page for a list of recent BRICS Report Series publications. Copies may be obtained by contacting:BRICSDepartment of Computer ScienceUniversity of AarhusNy Munkegade,building540DK–8000Aarhus CDenmarkTelephone:+4589423360Telefax:+4589423255Internet:BRICS@brics.dkBRICS publications are in general accessible through the World Wide Web and anonymous FTP through these URLs:http://www.brics.dkftp://ftp.brics.dkThis document in subdirectory RS/05/9/Reviewing Bounds on the Circuit Size of theHardest FunctionsGudmund Skovbjerg FrandsenPeter Bro MiltersenBRICS∗Department of Computer Science,University of Aarhus, IT-parken,Aabogade34,DK-8200Aarhus N,Denmark Email:{gudmund,bromille}@daimi.au.dkMarch16,2005AbstractIn this paper we review the known bounds for L(n),the circuit size complexity of the hardest Boolean function on n input bits.The best known bounds appear to be2nn −O(1n(1+3log nn))However,the bounds do not seem to be explicitly stated in theliterature.We give a simple direct elementary proof of the lowerbound valid for the full binary basis,and we give an explicit proofof the upper bound valid for the basis{¬,∧,∨}.Keywords:Computational complexity1IntroductionShannon introduced the Boolean circuit size as a complexity measure[1], and showed upper and lower bounds for the minimum number of gates,L(n),needed in a Boolean circuit for computing a hardest function in B n,the set of Boolean functions with n inputs and1output.Shannon proved that for every >0and n suﬃciently large[1](1− )2nnTheﬁrst improvement came when Lupanov showed a better upper bound[2]:L(n)≤2n√n±o(2nn (1+αlog nn (1+log nn))<L(n)Our proof is robust in that a change of the basis or simple improve-ments seem only to eﬀect the O(1n(1+O(log nn (1+3log nn)) 22Lower boundWe will demonstrate the lower bound by showing how to transform a Boolean circuit into a list of instructions for a simple stack machine and then use a counting argument to bound the length of the latter.Each instruction for the stack machine is either a push or a binary Boolean operation.Only the push operation has an argument,which is the number of an input or an(earlier)Boolean operation.Inputs are numbered1,...,n,and Boolean operations are numbered n+1,...,n+s in a stack program with s Boolean operations.Execution of a push operation places an input or an earlier computed bit designated by the argument on top of the stack.Each Boolean operation removes the2 topmost elements of the stack and writes a single element onto the stack. After execution of all instructions,there should be exactly one element left on the stack,namely the result.Require:circuit C of size s described as set of gates{g i←g i1op g i2|i= n+1,...,n+s}where g1,...,g n are inputs and g n+s is output gate Ensure:Stack program P computes same function as C1:Let P initially be empty2:virtualPush(n+s)Procedure virtualPush(i)3:if g i is an input then4:add program line“push i”to P5:if g i is already computed by the j th Boolean operation in P then 6:add program line“push n+j”to P7:if gate g i←g i1op g i2is not computed so far then8:virtualPush(i1)9:virtualPush(i2)10:add program line“operation op”to PBoolean operation decreases the stack size by one.Since the stack is initially empty and it contains only the single output value at the end,there must be exactly s +1push operations.The argument of a push operation can be represented by log(n +s ) bits.A single bit is needed to distinguish push operations from Boolean operations,and 4bits suﬃce to distinguish the Boolean operations.In total the stack program can be described using at most (s +1)(c +log(n +s ))bits,for c =7.Since there are 22n distinct Boolean functions on n inputs,for some function the optimal circuit size s must satisfy that (s +1)(c +log(n +s ))≥2n .The last inequality implies that s >2n /n ·(1+log n/n −c/n )for n suﬃciently large.We will argue this lower bound by way of contradiction,so we assume that s ≤2n /n ·(1+log n/n −c/n ),which by a simple rewriting is equivalent to n +s ≤2n /n ·(1+log n/n −c/n +n 2/2n ).Using that log(1+x )≤x log e ,the assumption implies that log(n +s )≤n −log n +(log n/n −c/n +n 2/2n )log e .Combining with the inequality of the previous paragraph,we see that2n ≤(s +1)(c +log(n +s ))≤2n n −c 2n )(n −log n +c +(log n n +n 2n 2(n +log n −c +n 2 −c 2n)log e )≤2nTheorem1L(n)≥2nn−O(1s ≤2n=2nn−3l o g n)=2nn+O(log2n n(1+3log nn))AcknowledgmentWe would like to thank the anonymous referee for comments that greatly improved the presentation of the results.References[1]C.E.Shannon,The synthesis of two-terminal switching circuits,BellSystem Tech.J.28(1949)59–98.[2]O.B.Lupanov,The synthesis of contact circuits,Dokl.Akad.NaukSSSR(N.S.)119(1958)23–26.[3]J.H.Lutz,Almost everywhere high nonuniform complexity,-put.System Sci.44(2)(1992)220–258.[4]R.G.Nigmatullin,Slozhnost bulevykh funktsii,Kazan.Gos.Univ.,Kazan ,1983.[5]I.Wegener,The complexity of Boolean functions,Wiley-Teubner Se-ries in Computer Science,John Wiley&Sons Ltd.,Chichester,1987.[6]J.E.Savage,Models of Computation,Addison Wesley,1998.6Recent BRICS Report Series PublicationsRS-05-9Gudmund Skovbjerg Frandsen and Peter Bro Miltersen.Re-viewing Bounds on the Circuit Size of the Hardest Functions.March2005.6pp.To appear in Information Processing Let-ters.RS-05-8Peter D.Mosses.Exploiting Labels in Structural Operational Semantics.February2005.15pp.Appears in FundamentaInformaticae,60:17–31,2004.RS-05-7Peter D.Mosses.Modular Structural Operational Semantics.February2005.46pp.Appears in Journal of Logic and Alge-braic Programming,60–61:195–228,2004.RS-05-6Karl Krukow and Andrew Twigg.Distributed Approximation of Fixed-Points in Trust Structures.February2005.41pp.RS-05-5A Dynamic Continuation-Passing Style for Dynamic Delim-ited Continuations.Dariusz Biernacki and Olivier Danvy andKevin Millikin.February2005.RS-05-4Andrzej Filinski and Henning Korsholm Rohde.Denotational Aspects of Untyped Normalization by Evaluation.February2005.RS-05-3Olivier Danvy and Mayer Goldberg.There and Back Again.January2005.iii+16pp.Extended version of an article toappear in Fundamenta Informatica.This version supersedesBRICS RS-02-12.RS-05-2Dariusz Biernacki and Olivier Danvy.On the Dynamic Extent of Delimited Continuations.January2005.ii+30pp.RS-05-1Mayer Goldberg.On the Recursive Enumerability of Fixed-Point Combinators.January2005.7pp.Superseedes BRICSreport RS-04-25.RS-04-41Olivier Danvy.Sur un Exemple de Patrick Greussay.December 2004.14pp.RS-04-40Mads Sig Ager,Olivier Danvy,and Henning Korsholm Rohde.Fast Partial Evaluation of Pattern Matching in Strings.Decem-ber2004.22pp.To appear in TOPLAS.Supersedes BRICSreport RS-03-20.。