EDA技术及软件外文翻译

EDA Technology And Software
EDA is Electronic Design Automation (Electronic Automation) is the abbreviation of themselves, in the early 1990s from computer aided Design (CAD), computer aided manufacturing (CAM), computer aided testing (CAT) and computer aided engineering (CAE) development of the concepts and come.
EDA technology is on the computer as the tool, the designer in EDA software platform, with VHDL HDL finish design documents, then by the computer automatically logic compilation, reduction, division, comprehensive, optimization, layout and wiring and simulation for a particular goal chips, until the adapter compilation, logic mapping and programming download, etc.
1 EDA technology concepts
EDA technology is in electronic CAD technology developed on the basis of computer software system by means of computer for working platform, shirt-sleeve application of electronic technology, computer technology and information processing and intelligent technology to the latest achievements of electronic products, the automatic design.
Using EDA tools, electronic stylist can be from concept, algorithm, agreement, etc, begin to design your electronic system a lot work can be finished by computer and electronic products can be from circuit design, performance analysis to design the IC territory or PCB layout the whole process of the computer automatically complete the processing.
Now on the concept of using EDA or category very wide. Included in machinery, electronics, communication, aerospace, chemical, mineral, biology, medicine, military and other fields, have EDA applications. Current EDA technology has in big companies, enterprises, institutions and teaching research departments extensive use. For example in the aircraft manufacturing process, from design, performance testing and characteristic analysis until a flight simulator, all may involve EDA technology. Globalization-the EDA technology, mainly in electronic circuit design, PCB design and IC design.
EDA can be divided into system level and circuit-level and physical implementation level.
2.Development Environment MAX + PLUS II / QUARTER II
Altera Corporation is the world's three major CPLD / FPGA manufacturers of the devices it can achieve the highest performance and integration, not only because of the use of advanced technology and new logic structure, but also because it provides a modern design tools MAX + PLUSIprogrammable logic development software, the software is launched the third generation of Altera PLD development system. Nothing to do with the structure provides a design environment for Altera CPLD designers to easily design entry, quick processing, and device programming. MAX + PLUS Iprovides a comprehensive logic design capabilities, including circuit
diagrams, text and waveform design entry and compilation, logic synthesis, simulation and timing analysis, and device programming, and many other features. Especially in the schematic so, MAX + PLUS n is considered the most easy to use, the most friendly man-machine interface PLD development software. MAX + PLUSn can develop anything other than the addition APEX20K CPLD / FPGA.
MAX + PLUS n development system has many outstanding features:
①open interface.
②design and construction related: MAX + PLUSn support Altera's Classic, ACEX 1K, MAX 3000, MAX 5000, MAX 7000, MAX 9000, FLEX 6000, FLEX 8000 and FLEX 10K series of programmable logic devices, gate count is 600 ~ 250 000 doors, offers the industry really has nothing to do with the structure of programmable logic design environment. MAX + PLUSn compiler also provides a powerful logic synthesis and optimization to reduce the burden on the user's design.
③can be run on multiple platforms: MAX + PLUSn software PC-based WindowsNT
4.0, Windows 98, Win dows 2000 operating systems, but also in Sun SPARCstations, HP 9000 Series 700/800, IBM RISC System/6000 such as run on workstations.
④fully integrated: MAX + PLUSn software design input, processing,
calibration functions are fully integrated within the programmable logic development tools, which can be debugged more quickly and shorten the development cycle.
⑤modular tools: designers can input from a variety of design, editing, calibration and programming tools to choose the device to form a user-style development environment, when necessary,to retain on the basis of the original features to add new features. The MAX + PLUSn Series supports a variety of devices, designers need to learn new development tools for the development of new device structures.
⑥mail-description language (HDL): MAX + PLUSn software supports a variety of HDL design entry, including the standard VHDL, Verilog HDL and Altera's own developed hardware description language AHDL.
⑦MegaCore Function: MegaCore are pre-validated for the realization of complex system-level functions provided by the HDL netlist file. It ACEX 1K, MAX 7000, MAX 9000, FLEX 6000, FLEX 8000 and FLEX 10K devices provide the most optimal design. Users can purchase them from the Altera MegaCore, using them can reduce the design task, designers can make more time and energy to improve the design and
final product up.
⑧OpenCore Features: MAX + PLUSn software with open characteristics of the kernel, OpenCore come to buy products for designers design their own assessment.
At the same time, MAX + PLUS n there are many other design entry methods, including:
①graphic design input: MAX + PLUSn graphic design input than other software easier to use features, because the MAX + PLUS n provides a rich library unit for the designer calls, especially in the MAX2LIB in the provision of the mf library includes almost all 74 series of devices, in the prim library provides all of the separatedigital circuit devices. So long as a digital circuit knowledge, almost no learning can take advantage of excess MAX + PLUSn for CPLD / FPGA design. MAX + PLUS n also includes a variety of special logic macros (Macro-Function) and the
parameters of the trillion of new features (Mega-Function) module. Full use of these modules are designed to greatly reduce the workload of designers to shorten design cycles and multiply.
②En ter the text editor: MAX + PLUS n text in put Ian guage and compiler system supports AHDL, VHDL language, VERILOG language of the three input methods.
③wave input: If you know the input, output waveform, the waveform input can also be used.
④hybrid approach: MAX + PLUS n design and development environment for graphical design entry, text editing input, waveform editing input hybrid editing. To do: in graphics editing, wave form editing module by editing the text include "module name. Inc" or the use of Function (... ..) Return ( ) Way call. Similarly, the text
editing module input form can also be called when the graphics editor, AHDL compiler results can be used in the VHDL language, VHDL compiler of the results can also be entered in the AHDL language or graphic to use. This flexible input methods, to design the user has brought great convenience.
Altera's Quartusn is a comprehensive PLD development software to support the schematic, VHDL, Verilog HDL, and AHDL (Altera Hardware Description Language) and other design input forms, embedded devices, and integrated its own simulator, you can complete the design input to complete the hardware configuration of the PLD design process.
Quartusn in the XP, Linux and Unix on the use, in addition to using the Tcl script to complete the design process, to provide a complete graphical user interface design. With running speed, unified interface, feature set, easy to use and so on.
Altera's Quartusn support IP core, including the LPM / MegaFunction macro function module library, allowing users to take full advantage of sophisticated modules, simplifying the design complexity and speed up the design speed. Good for third-party EDA tool support also allows the user to the various stages in the design process using the familiar third-party EDA tools.
In addition, Quartusn and DSP Builder tools and by Matlab / Simulink combination, you can easily achieve a variety of DSP applications; support Altera's programmable system chip (SOPC) development, set system-level design, embedded software development, programmable logic design in one, is a comprehensive development platform.
MaxPLUSn generation as Altera's PLD design software, due to its excellent ease of use has been widely used. Altera has now stopped MaxPLUSn update support, Quartusn not only support the device type as compared to the rich and the graphical interface changes. Altera Quartusn included in many such SignalTapn , Chip Editor and RTL Viewer design aids, integrated SOPC and HardCopy design process, and
inherit MaxPLUSn friendly graphical interface and easy to use.
MaxPLUSn generation as Altera's PLD design software, due to its excellent ease of use has been widely used. Altera has now stopped MaxPLUSn update support, Quartusn not only support the device type as compared to the rich and the graphical interface changes. Altera Quartusn included in many such SignalTapn , Chip Editor and RTL Viewer design aids, integrated SOPC and HardCopy design process, and
inherit MaxPLUSn friendly graphical interface and easy to use.
Altera QuartusH as a programmable logic desig n en vir onment, due to its stro ng design capabilities and intuitive interface, more and more digital systems designers welcome.
Altera's QuartusH is the fourth generation of programmable logic PLD software development platform. The platform supports a working group under the design requirements, including support for Internet-based collaborative design. Quartus platform and Cadence, ExemplarLogic, MentorGraphics, Synopsys and Synplicity EDA vendors and other development tools are compatible. LogicLock improve the software module design features, added FastFit compiler options, and promote the network editing performance, and improved debugging capabilities. MAX7000/MAX3000 devices and other items to support the product.
3.Development of language VHDL
VHDL (Very High Speed Integrated Circuit Hardware Description Language) is a very high speed integrated circuit hardware description language, it can describe the function of the hardware circuitry, signal connectivity and the time between languages. It can be more effective than the circuit diagram to express the characteristics of the hardware circuit. Using the VHDL language, you can proceed to the general requirements of the system, since the detailed content will be designed to come down to earth, and finally to complete the overall design of the system hardware. IEEE VHDL language has been the industry standard as a design to facilitate reuse and sharing the results. At present, it can not be applied analog circuit design, but has been put into research. VHDL program structure, including: entity (Entity), structure (Architecture), configure (Configuration), Package Collection (Package) and the Library (Library). Among them, the entity is the basic unit of a VHDL program, by entity and the structure of two parts: the physical design system that is used to describe the external interface signal; structure used to describe the behavior of the system, the system processes or system data structure form. Configuration select the required language from the library system design unit to form different versions of different specifications, so that the function is designed to change the system. Collection of records of the design module package to share the data types, constants, subroutines and so on. Database used to store the compiled entities, the body structure, including the collection and configuration: one is the development of engineering software user, the other
is the manufacturer's database.
VHDL, the main features are:
①powerful, high flexibility: VHDL language is a powerful language structure, clear and concise code can be used to design complex control logic. VHDL language also supports hierarchical design, support design databases and build reusable components. Currently, VHDL language has become a design, simulation, synthesis of standard hardware description language.
②Device independence: VHDL language allows designers to generate a design do not need to first select a specific device. For the same design description, you can use a variety of different device structures to achieve its function. So the design description stage, able to focus on design ideas. When the design, simulation, after the adoption of a specific device specified integrated, adapter
can be.
③Portability: VHDL language is a standard language, so the use of VHDL design can be carried out by different EDA tool support. Transplanted from one to
another simulation tools simulation tools, synthesis tools from a port to another integrated tool, from a working platform into another working platform. EDA tools used in a technical skills, in other tools can also be used.
④top-down design methods: the traditional design approach is bottom-up design or flat design. Bottom-up design methodology is to start the bottom of the module design, the gradual formation of the functional modules of complex circuits. Advantage of this design is obvious becauseit is a hierarchical circuit design, the general circuit sub-module are in accordance with the structure or function of division, so the circuit level clear, clear structure, easy people to develop, while the design archive file is easy, easy communication. Bottom-up design is also very obvious shortcomings, the overall design concept is often not leaving because the cost of months of low-level design in vain. Flat design is a module containing only the circuit, the circuit design is straightforward and, with no division structure and function, it is not hierarchical circuit design. Advantages of small circuit design can save time and effort, but with the increasing complexity of the circuit, this design highlights the shortcomings of the abnormal changes. Top-down design approach is to design top-level circuit description (top model), and then the top-level simulation using EDA software, if the top-level design of the simulation results meet the requirements, you can continue to lower the top-level module by the division level and simulation, design of such a level will eventually complete the entire circuit. Top-down design method compared with the first two are obvious advantages.
⑤rich data types: as a hardware description language VHDL data types are very rich language, in addition to VHDL language itself dozens of predefined data types, in the VHDL language programming also can be user-defined data types.
Std_logic data types in particular the use of VHDL language can make the most realistic complex signals in analog circuits.
⑥modeling convenience: the VHDL language can be integrated in the statement and the statement are available for simulation, behavior description ability, therefore particularly suitable for signal modeling language VHDL. The current VHDL syn thesizer to complex arithmetic comprehe nsive descripti ons (such as: Quartus n 2.0 and above versions of std_logic_vector type of data can add, subtract, multiply, divide), so the circuit modeling for complex simulation of VHDL language, whether or comprehensive description of the language are very appropriate.
⑦rich runtime and packages: The current package supports VHDL, very rich, mostly in the form of libraries stored in a specific directory, the user can at any time.
Such as the IEEE library collection std_logic_1164, std_logic_arith, std_logic_unsigned other package. In the CPLD / FPGA synthesis, EDA software vendors can also use the various libraries and provide package. VHDL language and the user using a variety of results can be stored in a library, in the design of the follow-up can continue to use.
⑧VHDL language is a modeling hardware description language, so with ordinary computer languagesare very different, common computer language is the CPU clock according to the beat, after an instruction to perform the next instruction, so instruction is a sequential, that is the order of execution, and execution of each instruction takes a specific time. VHDL language to describe the results with the
corresponding hardware circuit, which follows the characteristics of hardware, there is no order of execution of the statement is executed concurrently; and statements that do not like ordinary software, take some time each instruction, just follow their own hardware delay.
EDA技术及软件
EDA是电子设计自动化(Electronic Design Automation) 的缩写,在20世纪
90年代初从计算机辅助设计(CAD)、计算机辅助制造(CAM)计算机辅助测试(CAT) 和计算机辅助工程(CAE)的概念发展而来。

EDA技术就是以计算机为工具，设计者在EDA软件平台上，用硬件描述语言HDL 完成设计文件，然后由计算机自动地完成逻辑编译、化简、分割、综合、优化、布局、布线和仿真，直至对于特定目标芯片的适配编译、逻辑映射和编程下载等工作。

1EDA 技术的概念
EDA技术是在电子CAD技术基础上发展起来的计算机软件系统，是指以计算机为工作平台，融合了应用电子技术、计算机技术、信息处理及智能化技术的最新成果，进行电子产品的自动设计。

利用EDA工具，电子设计师可以从概念、算法、协议等开始设计电子系统，大量工作可以通过计算机完成，并可以将电子产品从电路设计、性能分析到设计出IC版图或PCB版图的整个过程的计算机上自动处理完成。

现在对EDA的概念或范畴用得很宽。

包括在机械、电子、通信、航空航天、化工、矿产、生物、医学、军事等各个领域，都有EDA的应用。

目前EDA技术已在各大公司、企事业单位和科研教学部门广泛使用。

例如在飞机制造过程中，从设计、性能测试及特性分析直到飞行模拟，都可能涉及到EDA技术。

本文所指的EDA技术，主要针对电子电路设计、PCB设计和IC设计。

EDA设计可分为系统级、电路级和物理实现级。

2开发环境MAX+PLUS/QUARTER
Altera公司是世界三大CPLDT FPGA厂家之一，它的器件能达到最高的性能和集成度，不仅仅因为采用了先进的工艺和全新的逻辑结构，还在于它提供了现代化的设计工具一MAX+PLUS可编程逻辑开发软件，该软件是Altera公司推出的第三代PLD 开发系统。

提供了一种与结构无关的设计环境，使Altera CPLD设计者能方便地进行设计输入、快速处理和器件编程。

MAX+PLUS提供了全面的逻辑设计能力，包括电路图、文本和波形的设计输入以及编译、逻辑综合、仿真和定时分析以及器件编程等诸多功能。

特别是在原理图输入等方面，MAX+PLUS被公认为是最易使用、人机界面最友好的PLD开发软件。

MAX+PLUS可以开发除
APEX20K以外的任何CPLDXFPGA
MAX+PLUS开发系统具有很多突出的特点：
①开放式的界面。

②设计与结构无关：MAX+PLUS支持Altera 公司的Classic、ACEX1K、MAX 3000、MAX 5000 MAX 7000 MAX 9000 FLEX 6000 FLEX 8000和FLEX 10K等系列可编程逻辑器件，门数为600〜250 000门，提供了业界真正与结构无关的
可编程逻辑设计环境。

MAX+PLUS的编译器还提供了强大的逻辑综合与优化功能以减轻用户的设计负担。

③可在多种平台运行：MAX+PLUS软件可在基于PC机的WindowsNT 4.0、Windows98、Win dows2000 操作系统下运行，也可在Sun SPARCstations、HP9000 Series 700/800 、IBM RISC System/6000 等工作站上运行。

④完全集成化：MAX+PLUS软件的设计输入、处理、校验功能完全集成于可
编程逻辑开发工具内，从而可以更快地进行调试，缩短开发周期。

⑤模块化工具：设计者可以从各种设计输入、编辑、校验及器件编程工具中作出选择，形成用户风格的开发环境，必要时还可在保留原始功能的基础上添加新的功能。

由于MAX+PLUS支持多种器件系列，设计者无需学习新的开发工具即可对新结构的器件进行开发。

⑥支持邮件描述语言(HDL：MAX+PLUS软件支持多种HDL的设计输入，包括标准的VH D L、Verilog HDL 及Altera 公司自己开发的硬件描述语言AHDL。

⑦MegaCore 功能：MegaCore 是经过预先校验的为实现复杂的系统级功能
而提供的HDL网表文件。

它为ACEX1K、MAX7000、MAX9000、FLEX6000、FLEX 8000和FLEX 10K系列器件提供了最优化设计。

用户可从Altera公司购买这些MegaCore,使用它们可以减轻设计任务，使设计者能将更多的时间和精力投入到改进设计和最终产品上去。

⑧OpenCore特点：MAX+PLUS软件具有开放性内核的特点，OpenCore可供
设计者在购买产品前来对自己的设计进行评估。

同时，MAX+PLUS还有多种设计输入方法，主要包括：
①图形设计输入：MAX+PLUS的图形设计输入是较其他软件更容易使用的特
点，因为MAX+PLUS提供了丰富的库单元供设计者调用，尤其是在MAX2LIB里
提供的mf库几乎包含了所有的74系列的器件，在prim库里提供了数字电路中所有的分离器件。

因此只要具有数字电路的知识，几乎不需要过多的学习就可以利用
MAX+PLUS进行CPLD/FPGA勺设计。

MAX+PLUS还包括多种特殊的逻辑宏功能( Macro—Function ：以及新型的参数化的兆功能( Mega—Function ：模块。

充分利用这些模块进行设计，可以大大减轻设计人员的工作量和成倍地缩短设计周期。

②文本编辑输入：MAX+PLUS的文本输入和编译系统支持AHDL语言、VHDL 语言、VERILOGS言三种输入方式。

③波形输入方式：如果知道输入、输出波形，也可以采用波形输入方式。

④混合输入方式：MAX+PLUS设计开发环境，可以进行图形设计输入、文本编辑输入、波形编辑输入混合编辑。

具体操作方法是：在图形编辑、波形编辑时形成模块，在文本编辑时通过in elude “模块名.inc ”或者采用Fu nction (…..)
Return(….)的方式进行调用。

同样，文本编辑输入形成的模块，也可以在图形编辑时调用，AHDL语言编译的结果可以在VHDL语言下使用，VHDL语言编译的结果也可以在AHDL语言或图形输入时使用。

这样灵活多变的输入方式，给设计使用者带来了极大的方便。

Quartus U是Altera 公司的综合性PLD开发软件，支持原理图、VHDLVerilog HDL 以及AHDL(Altera Hardware Description Language)等多种设计输入形式，内嵌自有的综合器以及仿真器，可以完成从设计输入到硬件配置的完整PLD设计流程。

Quartus U可以在XP Linux以及Unix上使用，除了可以使用Tel脚本完成设计流程外，提供了完善的用户图形界面设计方式。

具有运行速度快，界面统一，功能集中，易学易用等特点。

Quartus U支持Altera 的IP核，包含了LPM/MegaFunction宏功能模块库，使用户可以充分利用成熟的模块，简化了设计的复杂性、加快了设计速度。

对第三方EDA工具的良好支持也使用户可以在设计流程的各个阶段使用熟悉的第三方EDA 工具。

此外，Quartus U通过和DSP Builder工具与Matlab/Simulink 相结合，可以方便地实现各种DSP应用系统；支持Altera的片上可编程系统(SOPC开发，集系统级设计、嵌入式软件开发、可编程逻辑设计于一体，是一种综合性的开发平台。

MaxPLUS作为Altera的上一代PLD设计软件，由于其出色的易用性而得到了广泛的应
用。

目前Altera已经停止了对MaxPLUS的更新支持，Quartus S与之相比不仅仅是支持器件类型的丰富和图形界面的改变。

Altera在Quartus S中包含
了许多诸如SignalTap S 、Chip Editor 和RTLViewer 的设计辅助工具，集成了
SOP(和HardCopy设计流程，并且继承了MaxPLUS友好的图形界面及简便的使用方法。

MaxPLUS作为Altera的上一代PLD设计软件，由于其出色的易用性而得到了广泛的应用。

目前Altera已经停止了对MaxPLUSS的更新支持，Quartus S 与之相比不仅仅是支持器件类型的丰富和图形界面的改变。

Altera 在Quartus S中包含了许多诸如SignalTap S、Chip Editor和RTLViewer的设计辅助工具，集成了SOP(和HardCopy设计流程，并且继承了MaxPLUS友好的图形界面及简便的使用方法。

Altera Quartus S作为一种可编程逻辑的设计环境,由于其强大的设计能力和直观易用的接口，越来越受到数字系统设计者的欢迎。

Altera的Quartus S可编程逻辑软件属于第四代PLD开发平台。

该平台支持一个工作组环境下的设计要求，其中包括支持基于Internet 的协作设计。

Quartus 平台与Cadence、ExemplarLogic 、MentorGraphics 、Synopsys 和Synplicity 等EDA供应商的开发工具相兼容。

改进了软件的LogicLock模块设计功能，增添了FastFit 编译选项，推进了网络编辑性能，而且提升了调试能力。

支持MAX7000/MAX30C等乘积项器件。

3 开发语言VHDL
VHDL(VeryHigh SpeedIntegrated Circuit Hardware Description Language) 是非常高速集成电路硬件描述语言，是可以描述硬件电路的功能、信号连接关系
及定时关系的语言．它能比电路原理图更有效地表示硬件电路的特性。

使用VHDL 语言，可以就系统的总体要求出发，自上至下地将设计内容细化，最后完成系统
硬件的整体设计。

VHDL语言已作为一种IEEE的工业标准，设计结果便于复用和交流。

目前，它还不能应用于模拟电路的设计，但已有人投入研究。

VHDL程序
结构包括：实体(Entity) 、结构体(Architecture) 、配置(Configuration) 、包集合(Package)及库(Library)。

其中，实体是一个VHDL程序的基本单元，由实体说明和结构体两部分组成：实体说明用于描述设计系统的外部接口信号；结构体用于描述系统的行为、系统数据的流程或系统组织结构形式。

配置用语从库中选取所需的单元来组成系统设计的不同规格的不同版本，使被设计系统的功能发生变化。

包集合存放各设计模块能共享的数据类型、常数、子程序等。

库用于存放已编译的实体、构造体、包集合及配置：一种是用户自己开发的工程软件，另一种是制造商提供的库。

VHDL语言的主要特点是：
①功能强大，灵活性高：VHDL语言是一种功能强大的语言结构，可用简洁明确的代码来进行复杂控制逻辑的设计。

同时VHDL语言还支持层次化的设计，支持设计库和可重复使用的元件生成。

目前，VHDL语言已成为一种设计、仿真、综合的标准硬件描述语言。

②器件无关性：VHDL语言允许设计者在生成一个设计时不需要首先选择一个具体的器件。

对于同一个设计描述，可以采用多种不同器件结构来实现其功能。

因此设计描述阶段，可以集中精力从事设计构思。

当设计、仿真通过后，指定具体的器件综合、适配即可。

③可移植性：VHDL语言是一种标准的语言，故采用VHDL进行的设计可以被不同的EDA工具所支持。

从一个仿真工具移植到另一个仿真工具，从一个综合工具移植到另一个综合工具，从一个工作平台移植到另一个工作平台。

在一个EDA 工具中采用的技术技巧，在其它工具中同样可以采用。

④自顶向下的设计方法：传统的设计方法是，自底向上的设计或平坦式设计。

自底向上的设计方法是先从底层模块设计开始，逐渐由各个模块形成功能复杂的电
路。

这种设计方法优点是很明显的，因为它是一种层次设计电路，一般电路的子模块都是按照结构或功能划分，因此这种电路层次清楚，结构明确，便于多人合作开发，同时设计文件易于存档，易于交流。

自底向上设计方法的缺点也很明显，往往由于整体设计思路不对而使的花费几个月的低层设计付之东流。

平坦式设计是整个电路只含有一个模块，电路的设计是平铺直叙的，没有结构和功能上的划分，因此不是层次电路的设计方式。

优点是小型电路设计时可以节省时间和精力，但随着电路复杂程度的增加，这种设计方式的缺点变的异常突出。

自顶向下的设计方法是将要设计的电路进行最顶层的描述（顶层建模），然后利用EDA 软件进行顶层仿真，如果顶层设计的仿真结果满足要求，则可以继续将顶层划分的模块进行低一级的划分并仿真，这样一级一级设计最终将完成整个电路的设计。

自顶向下的设计方法与前面两种方法相比优点是很明显的。

⑤数据类型丰富：作为硬件描述语言的一种VHDL语言的数据类型非常丰富，除了VHDL语言自身预定义的十种数据类型外，在VHDL语言程序设计中还可以由用户自定义数据类型。

特别是std_logic数据类型的使用，使得VHDL语言能最真实模拟电路中的复杂信号。

⑥建模方便：由于VHDL语言中可综合的语句和用于仿真的语句齐备，行为描述能力强，因此VHDL语言特别适合信号建模。

目前VHDL勺综合器能对复杂的算术描述进行综合（如：Quartus n 2.0以上的版本都能对std_logic_vector 类型的数据进行加、减、乘、除），因此对于复杂电路的建模VHDL语言无论仿真还是综合都是非常合适的描述语言。

⑦运行库和程序包丰富：目前支持VHDL语言的程序包很丰富，大多以库的形式存放在特定的目录下，用户可随时调用。

如IEEE库收集了std_logic_1164、
std_logic_arith 、std_logic_unsigned 等程序包。

在CPLD/FPG综合时，还可以使用EDA软件商提供的各种库和程序包。

而且用户利用VHDL语言编写的各种成果都可以以库的形式存放，在后续的设计中可以继续使用。

⑧VHDL语言是一种硬件电路的建模描述语言，因此与普通的计算机语言有较大差别，普通计算机语言是CPU按照时钟的节拍，一条指令执行完后才能执行下一条指令，因此指令执行是有先后顺序的，也即是顺序执行，而每条指令的执行占用特定的时间。

而与VHDL语言描述结果相对应的是硬件电路，它遵循硬件电路的特点，语句的执行没有先后顺序，是并发的执行的；而且语句的执行不象普通软件那样每条指令占用一定的时间，只是遵循硬件电路自身的延迟时间。