FPGA可编程逻辑器件芯片XC2V1000-5FGG256I中文规格书
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Chapter 2: XPHY Architecture Figure 2: Relationship Between a Single XPHY Nibble, XP IOL, and IOB
X21592-042319
The following figure shows an XPHY NIBBLESLICE.
Figure 3: XPHY NIBBLESLICE with TX and RX Datapaths
Tristate
Control
Logic
Bidirectional
Pin
XPHY NIBBLESLICE Data from
Programmable
Logic Data to
Programmable
Logic X21593-121219
TX Datapath
The TX datapath is composed of the following:
•Serializer: The serializer supports 8:1, 4:1, and 2:1 serialization. This is set by the
TX_DATA_WIDTH attribute.
•Output Delay: Output delays can delay outgoing serialized data up to 512 taps (0–511 taps),with a minimum of 625 ps of available delay.
Refer to the Controlling Tristate Control section for latencies with and without the TX datapath using tristate control.
Related Information
Controlling Delays
Controlling Tristate Control
RX Datapath
The RX datapath is composed of:
•Input delay: Input delays can delay incoming serialized data up to 512 taps (0–511 taps), with
a minimum of 625 ps of available delay. Input delays can be increased to 1024 taps (0–1023
taps) for a minimum of 1250 ps of available delay by cascading the output delay of an XPHY NIBBLESLICE to the end of its input delay. For more information on cascading, see the
CASCADE_<0–5> attribute.
•Deserializer: The deserializer supports 1:8, 1:4, and 1:2 deserialization. This is determined by the RX_DATA_WIDTH attribute.
•FIFO: The receiver of an XPHY NIBBLESLICE has an 8-deep FIFO. The parallel data written to the FIFO is synchronized to the programmable logic clock domain of choice before passing to the programmable logic.
RX datapath latency changes depending on the data width (RX_DATA_WIDTH) and
FIFO_MODE_x attribute. Refer to Controlling FIFO Modes for RX datapath latencies.
IMPORTANT! Because each NIBBLESLICE routes to a specific pin, receiving a differential signal
(regardless of whether clock or data) consumes the pins and RX datapaths of both NIBBLESLICEs.
IMPORTANT! If receiving a strobe and RX_GATING = ENABLE, bitslip is not needed. For all other cases,
bitslip is needed for word alignment.
Related Information
FIFO
Bidirectional Datapath
The TX and RX datapaths within each XPHY NIBBLESLICE can be used together to form a bidirectional datapath. As shown in Figure 3, each TX datapath drives both to the pad and the RX datapath. As such, care must be taken when using the bidirectional datapath so as to tristate the buffer or gate the datapaths without data loss.
The XPHY offers transmit gating, receive gating, and tristating as mechanisms to control the bidirectional datapath. See the table below for a summary of how to enable these controls through the XPHY attributes.。