FPGA可编程逻辑器件芯片10M04DCU324C7G中文规格书

Multi-Point Support
Set only the speed for endpoint 0 because endpoint 0 only has the facilities to handle control transactions and there-fore is always associated with a device endpoint 0. Use bits 7–6 of the Type 0 register to set the speed. The register is located at address 0x1A when the index register is set to 0.
Multi-Point Operation
After allocating functions to endpoints and recording the operating speed of the target device, multi-point opera-tions can be configured. Most operations in a multi-point set-up are the same as for the equivalent actions where the core is attached to a single other device.
However, more steps are required when:
•The option of dynamically switching the allocation of functions to endpoints is taken (for example, to allow the support of a wider range of devices).
•The control packets normally associated with endpoint 0 are handled through a different endpoint.
If dynamic allocation is used, the program must monitor the current data toggle state associated with the endpoint and with each of the devices that are allocated to that endpoint. This knowledge allows the program to select the correct data toggle state when switching occurs between one device and the other. (This action is the programs re-sponsibility. The core cannot determine what data toggle state is expected when a function switches in and out of use.)
The data toggle state can be switched from its current state by writing to the appropriate USB_EP[n]_TXCSR_H or USB_EP[n]_RXCSR_H register. This activity sets the data toggle write enable and data toggle bits that are included in the registers when the core is in host mode.
Data toggle write enable and data toggle bits are also included in the USB_EP0_CSR[n]_H register. However, con-trol operations carried out through endpoint 0 of the core normally leave the data toggle in the expected state. Where control packets are handled through an endpoint other than endpoint 0, programs must prompt for each setup token to be sent. Programs must set the USB_EP[n]_TXCSR_H.SETUPPKT bit when the core operates in host mode, along with the USB_EP[n]_TXCSR_H.TXPKTRDY bit. If the USB_EP[n]_TXCSR_H.SETUPPKT bit is not set, an OUT token is sent.
Use endpoint 0 of the USB controller to handle control packets for all of the devices attached to the controller, and to switch the allocation of this endpoint, as appropriate. Sending the correct token is ensured, as is ensuring that the data toggle is correctly set for this endpoint.
Using a different endpoint for this function is possible, as described, but note the following:
•The control function must be allocated to an Rx/Tx endpoint pair (with the same endpoint number).
•The chosen endpoints must each be associated with FIFOs that can accommodate the packet size associated with EP0 transactions at the chosen operating speed. The size is a minimum of 8 bytes for low-speed or full-speed transactions but 64 bytes for high-speed transactions.
Suspending and Resuming the Controller
Suspend or Resume by Inactivity on the USB Bus (L0 to L2 State) in Peripheral Mode
The following steps occur in this mode.
1.Entry into suspend mode. When operating as a peripheral, the USB controller monitors activity on the USB
and when no activity has occurred for 3 ms, the controller goes into suspend mode. If the USB_IRQ.SUSPEND interrupt has been enabled, the USB controller now generates an interrupt. The USB_IRQ.SUSPEND output also goes low (if enabled).
The POWERDWN signal is also asserted to indicate that the application can stop USB_CLKIN to save power.
POWERDWN then remains asserted until either power is removed from the bus (indicating that the device has been disconnected) or resume signaling or reset signaling is detected on the bus.
2.When resume signaling occurs on the bus, the USB_CLKIN must be restarted, if necessary. The USB controller
then automatically exits suspend mode. If the USB_IRQ.RESUME interrupt is enabled, the USB controller gen-erates an interrupt.
3.Initiating a remote wake-up. T o initiate a remote wake-up while the controller is in suspend mode, set the
USB_POWER.RESUME bit=1. ( If USB_CLKIN has been stopped, it must be restarted before this write can oc-cur.) The software must leave then this bit set for approximately 10 ms (minimum of 2 ms, a maximum of 15 ms) before resetting it to 0. By this time the hub is driving resume signaling on the USB.
NOTE:The USB_IRQ.RESUME interrupt is not generated when the software initiates a remote wake-up. Suspend or Resume by Inactivity on the USB Bus (L0 To L2 State) in Host Mode The following steps occur in this mode.
1.Entry into suspend mode. When operating as a host, the USB controller can be prompted to go into suspend
mode by setting the USB_POWER.SUSPEND bit. When this bit is set, the USB controller completes the current transaction then stops the transaction scheduler and frame counter. No further transactions start and no SOF packets are generated. If the USB_POWER.SUSEN bit is set, the UTMI+ PHY goes into low-power mode when the controller goes into suspend mode and stops USB_CLKIN.
2.Sending resume signaling. When the application requires the controller to leave suspend mode, it clears the
USB_POWER.SUSPEND bit, sets the USB_POWER.RESUME bit, and leaves it set for 20 ms. While the
USB_POWER.RESUME bit is high, the controller generates resume signaling on the bus. After 20 ms, the pro-cessor core must clear the USB_POWER.RESUME bit, at which point the frame counter and transaction schedu-ler start.
3.Responding to remote wake-up. If resume signaling is detected from the target while the USB controller is in
suspend mode, the UTMI+ PHY is brought out of low-power mode and restarts USB_CLKIN. The controller then exits suspend mode and automatically sets the USB_POWER.RESUME bit to 1 to take over generating the resume signaling from the target. If the USB_IRQ.RESUME interrupt is enabled, the USB controller generates an interrupt.
USB Event Control
•When SRP signaling is detected (A device only)
•When device disconnect is detected (host mode)
•When a session ends (peripheral mode)
•When a device connection is detected (host mode)
•At start of frame (SOF)
•When reset signaling is detected on USB (peripheral mode)
•When babble is detected (host mode)
•In suspend mode, when resume signaling is detected on USB
•When suspend signaling is detected (peripheral mode)
The software generates interrupts for the following VBUS control requests:
•Drive VBUS greater than 4.4 V (default A device)
•Stop driving VBUS
•Start charging VBUS (peripheral mode)
•Stop charging VBUS
•Start discharging VBUS (peripheral mode)
•Stop discharging VBUS
Interrupt Handling
When interrupted with a USB interrupt, the processor core must read the interrupt status register to determine which endpoints have caused the interrupt and jump to the appropriate routine. If multiple endpoints have caused the interrupt, endpoint 0 must be serviced first, followed by the other endpoints. The USB Interrupt Service Rou-tine figure shows a flowchart for the USB interrupt service routine.。