FPGA可编程逻辑器件芯片XC7K355T-1FFG676C中文规格书

UltraScale Architecture-Based FPGAs Memory IP v1.4
PG150 January 21, 2021
Chapter 4:Designing with the Core
UE_FFA[63:32]
This register stores the decoded address (Bits[55:32]) of the first occurrence of an access with an uncorrectable error. The address format is defined in Table 3-1, page 32. In addition, the upper byte of this register stores the ecc_multiple signal. When the UE_STATUS bit in the ECC Status register is cleared, this register is re-enabled to store the address of the next uncorrectable error. Storing of the failing address is enabled after reset.
UE_FFD[31:0]
This register stores the (uncorrected) failing data (Bits[31:0]) of the first occurrence of an access with an uncorrectable error. When the UE_STATUS bit in the ECC Status register is cleared, this register is re-enabled to store the data of the next uncorrectable error. Storing of the failing data is enabled after reset.
UE_FFD[63:32]
This register stores the (uncorrected) failing data (Bits[63:32]) of the first occurrence of an access with an uncorrectable error. When the UE_STATUS bit in the ECC Status register is cleared, this register is re-enabled to store the data of the next uncorrectable error. Storing of the failing data is enabled after reset.
Table 4-55:
Uncorrectable Error First Failing Address [31:0] Register Bits
Name Core Access Reset Value Description 31:0UE_FFA [31:0]
R 0 Address (Bits[31:0]) of the first occurrence of an uncorrectable error.Table 4-56:
Uncorrectable Error First Failing Address [31:0] Register Bits
Name Core Access Reset Value Description 31:24UE_FFA[63:56]R 0ecc_multiple[7:0]. Indicates which bursts of the BL8 transaction associated with the logged address had an uncorrectable error. Bit[24] corresponds to the first burst of the BL8 transfer.
23:0UE_FFA[55:32]R 0
Address (Bits[55:32]) of the first occurrence of a correctable error.Table 4-57:
Uncorrectable Error First Failing Data [31:0] Register Bits
Name Core Access Reset Value Description 31:0UE_FFD[31:0] R
0 Data (Bits[31:0]) of the first occurrence of an uncorrectable error. Table 4-58:
Uncorrectable Error First Failing Data [63:32] Register Bits
Name Core Access Reset Value Description 31:0UE_FFD [63:32]
R 0 Data (Bits[63:32]) of the first occurrence of an uncorrectable error.
UltraScale Architecture-Based FPGAs Memory IP v1.4 PG150 January 21, 2021Chapter 3:Core Architecture
DDR_CAL_STATUS_SLOTx_6054Start Read Per-Bit Deskew28 155Done––256Start Read Per-Bit DBI Deskew29 357Done––458Start Read DQS Centering (Simple)30 559Done––660Start Read Sanity Check31 761Done––862Start Write DQS to DQ Deskew32
DDR_CAL_STATUS_SLOTx_7063Done––164Start Write DQS to DM/DBI Deskew33 265Done––366Start Write DQS to DQ (Simple)34 467Done––568Start Write DQS to DM/DBI (Simple)35 669Done––770Start Read DQS Centering DBI (Simple)36 871Done––
DDR_CAL_STATUS_SLOTx_8072Start Write Latency Calibration37 173Done––274Start Write Read Sanity Check 038 375Done––476Start Read DQS Centering (Complex)39 577Done––678Start Write Read Sanity Check 140 779Done––880Start Read V REF Training41
Table :Status Signal Description for Quad-Rank LRDIMM Card (Cont’d)
XSDB Status Register XSDB
Bits
[8:0]
Status
Port Bits
[127:0]
Description Calibration Stage Name
Calibration
Stage
Number
UltraScale Architecture-Based FPGAs Memory IP v1.4PG150 January 21, 2021Chapter 4:Designing with the Core 1
c0_ddr4_dqs_t[3]T1U_6P 1
c0_ddr4_dq[27]T1L_5N 1
c0_ddr4_dq[26]T1L_4P 1
c0_ddr4_dq[25]T1L_3N 1
c0_ddr4_dq[24]T1L_2P 1
–T1L_1N 1
c0_ddr4_dm_dbi[3]T1L_0P 1
–T0U_12–1
c0_ddr4_dq[23]T0U_11N 1
c0_ddr4_dq[22]T0U_10P 1
c0_ddr4_dq[21]T0U_9N 1
c0_ddr4_dq[20]T0U_8P 1
c0_ddr4_dqs_c[2]T0U_7N 1
c0_ddr4_dqs_t[2]T0U_6P 1
c0_ddr4_dq[19]T0L_5N 1
c0_ddr4_dq[18]T0L_4P 1
c0_ddr4_dq[17]T0L_3N 1
c0_ddr4_dq[16]T0L_2P 1
c0_ddr4_reset_n T0L_1N 1
c0_ddr4_dm_dbi[2]T0L_0P 0
c0_ddr4_bg[1]T3U_12–0
c0_ddr4_dq[15]T3U_11N 0
c0_ddr4_dq[14]T3U_10P 0
c0_ddr4_dq[13]T3U_9N 0
c0_ddr4_dq[12]T3U_8P 0
c0_ddr4_dqs_c[1]T3U_7N 0
c0_ddr4_dqs_t[1]T3U_6P 0
c0_ddr4_dq[11]T3L_5N 0
c0_ddr4_dq[10]T3L_4P 0
c0_ddr4_dq[9]T3L_3N 0
c0_ddr4_dq[8]T3L_2P 0
c0_ddr4_cke[0]T3L_1N 0c0_ddr4_dm_dbi[1]
T3L_0P Table 4-11:
Two 32-Bit DDR4 Interfaces Contained in Three Banks (Cont’d)Bank
Signal Name Byte Group I/O Type。