intersil HUF75307T3ST 数据手册

File Number
4364.4
HUF75307T3ST
2.6A,55V ,0.090Ohm,N-Channel UltraFET Power MOSFET
This N-Channel power MOSFET is manufactured using the innovative UltraFET™process.This advanced process technology achieves the
lowest possible on-resistance per silicon area, resulting in outstanding performance. This device is capable of
withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge.It was designed for use in applications where power efficiency is important, such as switching regulators,switching converters, motor drivers, relay drivers, low-voltage bus switches, and power management in portable and battery-operated products.Formerly developmental type T A75307.
Features
• 2.6A, 55V
•Ultra Low On-Resistance, r DS(ON) = 0.090Ω•Diode Exhibits Both High Speed and Soft Recovery •Temperature Compensating PSPICE™ Model •Thermal Impedance SPICE Model •Peak Current vs Pulse Width Curve •UIS Rating Curve
•Related Literature
-TB334, “Guidelines for Soldering Surface Mount Components to PC Boards”
Symbol
Packaging
SOT-223
Ordering Information
PART NUMBER PACKAGE BRAND
HUF75307T3ST
SOT -223
5307
NOTE:HUF75307T3ST is available only in tape and reel.
D
G
S
DRAIN
SOURCE
GATE
DRAIN (FLANGE)
Data Sheet
October 1999
查询HUF75307T3ST供应商
Absolute Maximum Ratings T A= 25o C, Unless Otherwise Specified
UNITS Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V DSS55V Drain to Gate Voltage (R GS = 20kΩ) (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V DGR55V Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V GS±20V V Drain Current
Continuous (Figure 2) (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I D Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I DM
2.6
Figure 5
A
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E AS Figures 6, 14, 15
Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P D Derate Above 25o C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1
9.09
W
mW/o C
Operating and Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T J, T STG-55 to 150o C Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T L Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T pkg 300
260
o C
o C
CAUTION:Stresses above those listed in“Absolute Maximum Ratings”may cause permanent damage to the device.This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.T J = 25o C to 125o C.
Electrical Specifications T A = 25o C, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BV DSS I D = 250µA, V GS = 0V (Figure 11)55--V Gate to Source Threshold Voltage V GS(TH)V GS = V DS, I D = 250µA (Figure 10)2-4V Zero Gate Voltage Drain Current I DSS V DS = 50V, V GS = 0V--1µA
V DS = 45V, V GS = 0V, T A = 150o C--250µA Gate to Source Leakage Current I GSS V GS =±20V--100nA Drain to Source On Resistance r DS(ON)I D = 2.6A, V GS = 10V) (Figure 9)-0.0700.090Ω
Turn-On Time t ON V DD = 30V, I D≅ 2.6A,
R L = 11.5Ω, V GS=10V,
R GS = 25Ω--55ns
Turn-On Delay Time t d(ON)-5-ns Rise Time t r-30-ns Turn-Off Delay Time t d(OFF)-35-ns Fall Time t f-25-ns Turn-Off Time t OFF--90ns
Total Gate Charge Q g(TOT)V GS = 0V to 20V V DD = 30V,
I D≅ 2.6A,
R L = 11.5Ω
I g(REF) = 1.0mA
(Figure 13)-1417nC
Gate Charge at 10V Q g(10)V GS = 0V to 10V-8.310nC Threshold Gate Charge Q g(TH)V GS = 0V to 2V-0.60.8nC
Gate to Source Gate Charge Qgs- 1.00-nC Gate to Drain “Miller” Charge Qgd- 4.00-nC
Input Capacitance C ISS V DS = 25V, V GS = 0V,
f = 1MHz
(Figure 12)-250-pF
Output Capacitance C OSS-115-pF Reverse Transfer Capacitance C RSS-30-pF Thermal Resistance Junction to Ambient RθJA Pad Area = 0.171 in2 (see note 2)--110o C/W
Pad Area = 0.068 in2--128o C/W
Pad Area = 0.026 in2--147o C/W Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Source to Drain Diode Voltage V SD I SD = 2.6A-- 1.25V Reverse Recovery Time t rr I SD = 2.6A, dI SD/dt = 100A/µs--40ns Reverse Recovered Charge Q RR I SD = 2.6A, dI SD/dt = 100A/µs--50nC NOTE:
2.110o C/W measured using FR-4 board with 0.171in2 footprint for 1000s.
Typical Performance Curves
FIGURE 1.NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE FIGURE 2.MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
FIGURE 3.NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
FIGURE 4.FORWARD BIAS SAFE OPERATING AREA FIGURE 5.PEAK CURRENT CAPABILITY
050100150
T A , AMBIENT TEMPERATURE (o C)P O W E R D I S S I P A T I O N M U L T I P L I E R
0.20.40.60.81.01.2I D , D R A I N C U R R E N T (A )
T A , AMBIENT TEMPERATURE (o C)
01.01.52.02.53.0
25
5075100125150
0.5R θJA = 110o C/W
0.001
0.01
0.1
1
10
10-510-410-3
10-210-1100101
102
103
Z θJ A , N O R M A L I Z E D
T H E R M A L I M P E D A N C E
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t 1/t 2
PEAK T J = P DM x Z θJA x R θJA + T A
P DM
t 1t 2
DUTY CYCLE - DESCENDING ORDER 0.50.20.10.050.01
0.02t, RECTANGULAR PULSE DURATION (s)
R θJA = 110o C/W
0.01
0.1
1
10
100
1
10100
200
V DS , DRAIN TO SOURCE VOLTAGE (V)
I D , D R A I N C U R R E N T (A )
T J = MAX RATED T A = 25o C
100µs 10ms
1ms
V DSS (MAX ) = 55V
LIMITED BY r DS(ON)AREA MAY BE
OPERATION IN THIS R θJA = 110o C/W
110
103
10210110010-110-2
10-3
30
t, PULSE WIDTH (s)
I D M , P E A K C U R R E N T (A )
I =I 25
150 - T A 125
FOR TEMPERATURES
ABOVE 25o C DERATE PEAK CURRENT AS FOLLOWS:
T A = 25o C R θJA = 110o C/W
NOTE:Refer to Intersil Application Notes AN9321 and AN9322.FIGURE 6.UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
FIGURE 7.SATURATION CHARACTERISTICS
FIGURE 8.TRANSFER CHARACTERISTICS
FIGURE 9.NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 10.NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE FIGURE 11.NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
110
0.01
0.11
10
20I A S , A V A L A N C H E C U R R E N T (A )
t AV , TIME IN AVALANCHE (ms)
t AV = (L)(I AS )/(1.3*RATED BV DSS - V DD )If R = 0
If R ≠ 0
t AV = (L/R)ln[(I AS *R)/(1.3*RATED BV DSS - V DD ) +1]
STARTING T J = 25o C
STARTING T J = 150o C
5
10
15
20
25
1
2
3
4
5
I D , D R A I N C U R R E N T (A )
V DS , DRAIN TO SOURCE VOLTAGE (V)
V GS = 6V
V GS = 10V V GS = 20V PULSE DURATION = 80µs T A = 25o C
V GS = 5V
V GS = 7V
DUTY CYCLE = 0.5% MAX 0
5
10
15
20
25
0 1.5 3.0 4.5 6.07.5
I D ,D R A I N C U R R E N T (A )
V GS , GATE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX V DD = 15V
150o C
25o C
-55o C 0.51.0
1.5
2.0
2.5-80
-40
04080120
160
N O R M A L I Z E D D R A I N T O S O U R C E T J , JUNCTION TEMPERATURE (o C)
O N R E S I S T A N C E
PULSE DURATION = 80µs V GS = 10V , I D = 2.6A
DUTY CYCLE = 0.5% MAX N O R M A L I Z E D G A T E T J , JUNCTION TEMPERATURE (o C)T H R E S H O L D V O L T A G E
0.40.60.81.01.2
-80
-4004080120160
V GS = V DS , I D = 250µA
B R E A K D O W N V O L T A G E
0.80.9
1.0
1.1
1.2-80
-4004080120160
T J , JUNCTION TEMPERATURE (o C)
N O R M A L I Z E D D R A I N T O S O U R C E I D = 250µA
FIGURE 12.CAPACITANCE vs DRAIN TO SOURCE VOLTAGE NOTE:Refer to Intersil Application Notes AN7254 and AN7260.FIGURE 13.GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
0100
200
300
400500
10
20304050
60
C , C A P A C I T A N C E (p F )
V DS , DRAIN TO SOURCE VOLTAGE (V)
C ISS
C OSS
C RSS
V GS = 0V , f = 1MHz C ISS = C GS + C GD C RSS = C GD
C OSS = C DS + C GD
2
4
6
8
10
024
68
V G S , G A T E T O S O U R C E V O L T A G E (V )
V DD = 30V
Q g , GATE CHARGE (nC)
I D = 2.6A I D = 1.5A I D = 0.5A
WAVEFORMS IN
DESCENDING ORDER:
Test Circuits and Waveforms
FIGURE 14.UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15.UNCLAMPED ENERGY WAVEFORMS
FIGURE 16.GATE CHARGE TEST CIRCUIT FIGURE 17.GATE CHARGE WAVEFORM
t P
V GS
0.01Ω
L
I AS
+
-V DS
V DD R G
DUT
VARY t P TO OBTAIN REQUIRED PEAK I AS
0V
V DD
V DS
BV DSS
t P
I AS
t AV
R L
V GS
+
-V DS
V DD
DUT
I g(REF)
V DD
Q g(TH)
V GS = 2V Q g(10)
V GS = 10V
Q g(TOT)
V GS = 20V
V DS
V GS I g(REF)0
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, T J(MAX), and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, P D(MAX),in an application. Therefore the application’s ambient
temperature, T A (o C), and thermal resistance R θJA (o C/W)must be reviewed to ensure that T J(MAX)is never exceeded.Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part.
In using surface mount devices such as the SOT -223
package, the environment in which it is applied will have a significant influence on the part’s current and maximum power dissipation ratings. Precise determination of the P D(MAX) is complex and influenced by many factors:1.Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board.2.The number of copper layers and the thickness of the board.3.The use of external heat sinks.4.The use of thermal vias.5.Air flow and board orientation.
6.For non steady state applications,the pulse width,the duty cycle and the transient thermal response of the part,the board and the environment they are in.Intersil provides thermal information to assist the designer’s preliminary application evaluation. Figure 20 defines the R θJA for the device as a function of the top copper
(component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady
state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse
applications can be evaluated using the Intersil device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve.
Displayed on the curve are the three R θJA values listed in the Electrical Specifications table. The three points were chosen to depict the compromise between the copper board area, the thermal resistance and ultimately the power
dissipation,P D(MAX).Thermal resistances corresponding to other component side copper areas can be obtained from Figure 20 or by calculation using Equation 2. The area, in square inches is the top copper area including the gate and source pads.
FIGURE 18.SWITCHING TIME TEST CIRCUIT FIGURE 19.RESISTIVE SWITCHING WAVEFORMS
Test Circuits and Waveforms (Continued)
V GS
R L
R GS
DUT
+
-V DD
V DS
V GS
t ON t d(ON)
t r
90%
10%
V DS
90%
10%
t f
t d(OFF)
t OFF 90%
50%
50%
10%
PULSE WIDTH
V GS 0
0(EQ. 1)
P D MAX ()T J MAX ()T A –()
R θJA
--------------------------------------------=FIGURE 20.THERMAL RESISTANCE vs MOUNTING PAD
AREA
50100
150
200
0.01
0.1
1.0
147o C/W - 0.026in 2
R θJA = 75.9 -19.3 ln(AREA)
AREA, TOP COPPER AREA (in 2)
R θJ A (o C /W )
128o C/W - 0.068in 2
110o C/W - 0.171in 2
(EQ. 2)
R θJA 75.919.3Area ()
ln ×–=
PSPICE Electrical Model
.SUBCKT HUF75307T3ST 2 1 3 ;
rev 7/25/97
CA 12 8 3.5e-10CB 15 14 3.7e-10CIN 6 8 2.26e-10
DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 57.4EDS 14 8 5 8 1EGS 13 8 6 8 1ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1EVTEMP 20 6 18 22 1IT 8 17 1
LDRAIN 2 5 1e-9LGATE 1 9 1.4e-9
LSOURCE 3 7 3.1e-10K1 LGATE LSOURCE 0.131MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1RDRAIN 50 16 RDRAINMOD 7.0e-3RGATE 9 20 1.9RLDRAIN 2 5 10RLGATE 1 9 14RLSOURCE 3 7 3
RSLC1 5 51 RSLCMOD 1e-6RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 5.6e-2RVTHRES 22 8 RVTHRESMOD 1RVTEMP 18 19 RVTEMPMOD 1S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*50),3))}
.MODEL DBODYMOD D (IS = 2.6e-13RS = 2.34e-2IKF = 5.5 N = 0.995 TRS1 = 2.8e-3TRS2 = 1.1e-5CJO = 3.7e-10TT = 3.5e-8 M = 0.46+ XTI = 5.5)
.MODEL DBREAKMOD D (RS = 0.5IKF = 0.1 N = 1 TRS1 = 3e-3TRS2 = -5e-5).MODEL DPLCAPMOD D (CJO = 5.6e-10IS = 1e-30N = 10 M = 0.92)
.MODEL MMEDMOD NMOS (VTO = 3.25 KP = 1.8 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.9).MODEL MSTROMOD NMOS (VTO = 3.68 KP = 13.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 2.83 KP = 0.03 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 19 RS = 0.1).MODEL RBREAKMOD RES (TC1 = 1.08e-3TC2 = 5e-7).MODEL RDRAINMOD RES (TC1 = 1.7e-2TC2 = 1e-4).MODEL RSLCMOD RES (TC1 = 1e-9 TC2 = 1e-4)
.MODEL RSOURCEMOD RES (TC1 = 3.3e-3 TC2 = 1e-9).MODEL RVTHRESMOD RES (TC1 = -1.9e-3 TC2 = -4e-6).MODEL RVTEMPMOD RES (TC1 = -2.9e-3TC2 = 2.2e-6).MODEL S1AMOD VSWITCH (RON = 1e-5ROFF = 0.1VON = -7.1VOFF= -4).MODEL S1BMOD VSWITCH (RON = 1e-5ROFF = 0.1VON = -4VOFF= -7.1).MODEL S2AMOD VSWITCH (RON = 1e-5ROFF = 0.1VON = 0.01VOFF= 1.9).MODEL S2BMOD VSWITCH (RON = 1e-5ROFF = 0.1
VON = 1.9VOFF= 0.01)
.ENDS
NOTE:For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options ; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
1822+
-6
8
+
-551
+
-
198
+-17
18
68
58
+-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17
181922
121315
S1A S1B
S2A S2B
CA
CB EGS
EDS
148138
1413MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
7
3
LSOURCE
RLSOURCE
CIN
RDRAIN EVTHRES 16
21
8
MMED
MSTRO
DRAIN 2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC RSLC110
5
51
50
RSLC2
1
GATE RGATE EVTEMP
9ESG
LGATE
RLGATE
20
+-
+
-+-
6
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only.Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-out notice.Accordingly,the reader is cautioned to verify that data sheets are current before placing rmation furnished by Intersil is believed to be accurate and reliable.However,no responsibility is assumed by Intersil or its subsidiaries for its use;nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
SPICE Thermal Model
REV 15 Nov 97HUF75307T3ST CTHERM1 7 6 7.5e-5CTHERM2 6 5 3.5e-4CTHERM3 5 4 1.2e-3CTHERM4 4 3 1.5e-2CTHERM5 3 2 6.9e-2CTHERM6 2 1 4.5e-1RTHERM1 7 6 7.5e-2RTHERM2 6 5 2.0e-1RTHERM3 5 4 1.2RTHERM4 4 3 3.3RTHERM5 3 2 28RTHERM6 2 1 90
RTHERM4RTHERM6RTHERM5RTHERM3RTHERM2RTHERM1
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
12
3
4
5
6
7
JUNCTION
CASE。