lowlevel_init过程注释了一遍

lowlevel_init过程注释了一遍
恩，大概以后再也不想看这块过程了。

解析的有点犯恶心了。

如果有问题，请各位看官斧正。

非常感谢。

#include <config.h>
#include <version.h>
#include <s3c6410.h>
#include "smdk6410_val.h"
_TEXT_BASE:
.word TEXT_BASE
.globl lowlevel_init
lowlevel_init:
mov r12, lr
;保存当前链接寄存器地址，等跳转回start.s时继续执行使用
ldr r0, =ELFIN_GPIO_BASE ;定基地址 0x7f008000
ldr r1, =0x55555555
str r1, [r0, #GPKCON0_OFFSET]; 0x7f008000 + 0x800 ;设置引脚GPIO-K［0-7］管脚为cfdata 模式
ldr r1, =0x55555555
str r1, [r0, #GPKCON1_OFFSET];0x7f008000 + 0x804 ;设置引脚GPIO-K［8-14］管脚为cfdata 模式
ldr r1, =0x22222666 ;0010 0010 0010 0010 0010 0110 0110 0110
str r1, [r0, #GPLCON0_OFFSET];0x7f008000 + 0x810
;设置引脚GPIO-L
;打开CF卡串口通信的0-2号三根地址线,其余不变，保持默认值
ldr r1, =0x04000000 ;01 00 00 00 00 00 00 00 00 00 00 00 00 00
str r1, [r0, #GPFCON_OFFSET];0x7f008000 + 0xA0
;设置引脚GPIO-F14为输出
;GPIO-F14连接CLKOUT输出
ldr r1, =0x2000; 10000000000000
str r1, [r0, #GPFDAT_OFFSET];0x7f008000 + 0xA4
;通过向GPIO锁存器写1,维持一个高电平信号。

/* LED on only #8 */
ldr r0, =ELFIN_GPIO_BASE ;0x7f008000
ldr r1, =0x00111111 ;0001 0001 0001 0001 0001 0001
str r1, [r0, #GPMCON_OFFSET] ;0x7f008000 + 0x820
;GPIO0-5引脚使能为输出
ldr r1, =0x00000555 ;010*********
str r1, [r0, #GPMPUD_OFFSET]
;由于刚启动上电信号不稳定，GPIO0-5引脚下拉电阻保证信号毛刺消除？为何要接下拉，下拉一般是输入时用啊
ldr r1, =0x002a; 101010
str r1, [r0, #GPMDAT_OFFSET] ;0x7f008000 + 0x824
;点亮第二个LED和第4个LED
ldr r1, =0 /*0x55555555 phantom*/ ;1010101010101010101010101010101
str r1, [r0, #MEM1DRVCON_OFFSET] ;0x7f008000 + 0x1D4
;内存驱动控制设置为默认值
/* Disable Watchdog */
ldr r0, =0x7e000000 @0x7e004000
orr r0, r0, #0x4000
mov r1, #0
str r1, [r0]
;关看门狗
@ External interrupt pending clear
ldr r0, =(ELFIN_GPIO_BASE+EINTPEND_OFFSET) /*EINTPEND*/;0x7f0 08000 + 0x924
ldr r1, [r0]
str r1, [r0]
;外部中断挂起
ldr r0, =ELFIN_VIC0_BASE_ADDR @0x71200000
ldr r1, =ELFIN_VIC1_BASE_ADDR @0x71300000
;中断向量表0和中断向量表1地址
@ Disable all interrupts (VIC0 and VIC1)
mvn r3, #0x0;反转为1
str r3, [r0, #oINTMSK];中断向量表0的中断使能清0
str r3, [r1, #oINTMSK];中断向量表1的中断是能清0
;
@ Set all interrupts as IRQ
mov r3, #0x0
str r3, [r0, #oINTMOD];0x7120000c
str r3, [r1, #oINTMOD];0x7130000c
;中断选择寄存器，设置为0，选择IRQ中断模式
@ Pending Interrupt Clear
mov r3, #0x0
str r3, [r0, #oVECTADDR]
str r3, [r1, #oVECTADDR]
;中断地址寄存器挂起清零。

注意，手册上写，这里无论设置任何值都将挂起中断。

;务必在中断服务程序执行完毕之后进行清零
;否则将会导致不可预知的异常
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;运行至此处，做完了下面几件事情
;1，gpio使能并设置为CF卡功能模式
;2，led灯点亮
;3，关闭看门狗
;4，关闭外部中断并挂起
;5，关闭中断并挂起;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
/* init system clock */
bl system_clock_init ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;运行至此处，做完了下面几件事情
; 运行至此处，时钟分频全部完成，设置为同步模式;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
/* for UART */
bl uart_asm_init
@至此，uart串口使能完毕。

ldr r0, =ELFIN_UART_BASE
ldr r1, =0x4b4b4b4b
str r1, [r0, #UTXH_OFFSET]
#if defined(CONFIG_NAND)
/* simple init for NAND */
bl nand_asm_init
#endif
bl mem_ctrl_asm_init
@跳到cpu_init.s文件中执行。

执行完毕，跳转回此处，再跳转回kernel流程
#if 1
ldr r0, =(ELFIN_CLOCK_POWER_BASE+RST_STAT_OFFSET) ldr r1, [r0]
bic r1, r1, #0xfffffff7
cmp r1, #0x8
beq wakeup_reset
#endif
1:
ldr r0, =ELFIN_UART_BASE
ldr r1, =0x4b4b4b4b
str r1, [r0, #UTXH_OFFSET]
mov lr, r12
mov pc, lr
#if 1
wakeup_reset:
/*Clear wakeup status register*/
ldr r0, =(ELFIN_CLOCK_POWER_BASE+WAKEUP_STAT_OFFSET) ldr r1, [r0]
str r1, [r0]
/*LED test*/
ldr r0, =ELFIN_GPIO_BASE
ldr r1, =0x3000
str r1, [r0, #GPNDAT_OFFSET]
/*Load return address and jump to kernel*/
ldr r0, =(ELFIN_CLOCK_POWER_BASE+INF_REG0_OFFSET) ldr r1, [r0] /* r1 = physical address of s3c6400_cpu_resume function*/
mov pc, r1 /*Jump to kernel (sleep-s3c6400.S)*/
nop
nop
#endif
/*
* system_clock_init: Initialize core clock and bus clock.
* void system_clock_init(void)
*/
system_clock_init:
ldr r0, =ELFIN_CLOCK_POWER_BASE @0x7e00f000;APLL 时钟地址
#ifdef CONFIG_SYNC_MODE
ldr r1, [r0, #OTHERS_OFFSET] ;0x7e00f000 + 0x900
mov r2, #0x40 ;100 0000
orr r1, r1, r2
;设置为异步模式，不修改其他设置
str r1, [r0, #OTHERS_OFFSET]
;开始浮空，等待指令生效
nop
nop
nop
nop
nop
ldr r2, =0x80 ; 1000 0000
;不理解此句，第八位开始是只读选项
orr r1, r1, r2
str r1, [r0, #OTHERS_OFFSET] ;0x7e00f000 + 0x900地址里的内容
check_syncack:
ldr r1, [r0, #OTHERS_OFFSET]
ldr r2, =0xf00 ;1111 0000 0000
and r1, r1, r2
cmp r1, #0xf00
bne check_syncack; bne 非零则跳转
#else /* ASYNC Mode */
#endif
mov r1, #0xff00
orr r1, r1, #0xff
str r1, [r0, #APLL_LOCK_OFFSET]
str r1, [r0, #MPLL_LOCK_OFFSET]
str r1, [r0, #EPLL_LOCK_OFFSET]
;使A，M，E三个时钟使能
/* CLKUART(=66.5Mhz) = CLKUART_input(532/2=266Mhz) / (UART_RATIO(3)+1) */
/* CLKUART(=50Mhz) = CLKUART_input(400/2=200Mhz) /
(UART_RATIO(3)+1) */
/* Now, When you use UART CLK SRC by EXT_UCLK1, We support 532MHz & 400MHz value */
#if defined(CONFIG_CLKSRC_CLKUART)
ldr r1, [r0, #CLK_DIV2_OFFSET] ;0x28
;取时钟分频地址
bic r1, r1, #0x70000 ;0111 0000 0000 0000 0000
orr r1, r1, #0x30000 ;0011 0000 0000 0000 0000
str r1, [r0, #CLK_DIV2_OFFSET]
#endif
ldr r1, [r0, #CLK_DIV0_OFFSET] /*Set Clock Divider*/
bic r1, r1, #0x30000
bic r1, r1, #0xff00
bic r1, r1, #0xff
ldr r2, =CLK_DIV_VAL;时钟频率设置，
;#if defined(CONFIG_CLK_800_133_66)
;#define Startup_APLLdiv 0
;#define Startup_HCLKx2div 2
;#elif defined(CONFIG_CLK_400_133_66)
;#define Startup_APLLdiv 1
;#define Startup_HCLKx2div 2
;#else
;#define Startup_APLLdiv 0
;#define Startup_HCLKx2div 1
;#endif
;#define Startup_PCLKdiv 3
;#define Startup_HCLKdiv 1
;#define Startup_MPLLdiv 1
;#define
CLK_DIV_VAL ((Startup_PCLKdiv<<12)|(Startup_HCLKx2div<<9 )|(Startup_HCLKdiv<<8)|(Startup_MPLLdiv<<4)|Startup_APLLdiv) orr r1, r1, r2
str r1, [r0, #CLK_DIV0_OFFSET]
ldr r1, =APLL_VAL
str r1, [r0, #APLL_CON_OFFSET]
ldr r1, =MPLL_VAL
str r1, [r0, #MPLL_CON_OFFSET]
ldr r1, =0x80200203 /* FOUT of EPLL is 96MHz */
str r1, [r0, #EPLL_CON0_OFFSET]
ldr r1, =0x0
str r1, [r0, #EPLL_CON1_OFFSET]
ldr r1, [r0, #CLK_SRC_OFFSET] /* APLL, MPLL, EPLL select to Fout */ ;选择为输出
#if defined(CONFIG_CLKSRC_CLKUART)
ldr r2, =0x2007
#else
ldr r2, =0x7
#endif
orr r1, r1, r2
str r1, [r0, #CLK_SRC_OFFSET]
/* wait at least 200us to stablize all clock */
mov r1, #0x10000
1: subs r1, r1, #1
bne 1b
;循环等待2000毫秒等待时钟生效
#ifdef CONFIG_SYNC_MODE /* Synchronization for VIC port */
ldr r1, [r0, #OTHERS_OFFSET]
orr r1, r1, #0x20
str r1, [r0, #OTHERS_OFFSET]
#else
ldr r1, [r0, #OTHERS_OFFSET]
bic r1, r1, #0x20
str r1, [r0, #OTHERS_OFFSET]
#endif
mov pc, lr
;跳转回 bl uart_asm_init这句后面
/*
* uart_asm_init: Initialize UART in asm mode, 115200bps fixed.
* void uart_asm_init(void)
*/
uart_asm_init:
/* set GPIO to enable UART */
@ GPIO setting for UART
ldr r0, =ELFIN_GPIO_BASE ;0x7f008000
ldr r1, =0x220022 ;0000 0000 0010 0010 0000 0000 0010 0010
str r1, [r0, #GPACON_OFFSET] ;0x00
;设置UART1串口发送接受寄存器使能
@设置GPIO-A2 GPIO-A3 寄存器为输入状态
;设置UART2串口发送接收寄存器使能
@设置GPIO-A6 GPIO-A7寄存器为输入状态
ldr r1, =0x2222 ;0000 0000 0000 0000 0010 0010 0010 0010
str r1, [r0, #GPBCON_OFFSET] ;0x7f008000 + 0x20
;设置UART2串口发送接受寄存器使能
;设置UART3串口发送接收寄存器使能
@设置GPIO-B3 GPIO-B7 寄存器为输入状态
;ok到这里我们已经有4个串口地址可以用了，同时可以发送接收32位数据，但是只是打开端口，没有驱动力
ldr r0, =ELFIN_UART_CONSOLE_BASE @0x7F005000 mov r1, #0x0
str r1, [r0, #UFCON_OFFSET] ;#define UFCON_OFFSET 0x08
str r1, [r0, #UMCON_OFFSET] ;#define UMCON_OFFSET 0x0C
;清零，非先入先出
mov r1, #0x3 @was 0.
str r1, [r0, #ULCON_OFFSET] ;设置传输方式为8bit，
1位停止位，无奇偶校验，
#if defined(CONFIG_CLKSRC_CLKUART)
ldr r1, =0xe45 /* UARTCLK SRC = 11 => EXT_UCLK1*/ #else
ldr r1, =0x245 /* UARTCLK SRC = x0 => PCLK */
#endif
str r1, [r0, #UCON_OFFSET] ;0x04 ，按照硬件手册配时钟频率
#if defined(CONFIG_UART_50)
ldr r1, =0x1A
#elif defined(CONFIG_UART_66)
ldr r1, =0x22
#else
ldr r1, =0x1A
#endif
str r1, [r0, #UBRDIV_OFFSET] ;0x28 设置串口波特率
#if defined(CONFIG_UART_50)
ldr r1, =0x3
#elif defined(CONFIG_UART_66)
ldr r1, =0x1FFF
#else
ldr r1, =0x3
#endif
str r1, [r0, #UDIVSLOT_OFFSET] ;波特率
ldr r1, =0x4f4f4f4f
str r1, [r0, #UTXH_OFFSET] @'O' ;0x20
@设置串口缓冲寄存器
mov pc, lr
@跳转回主干继续往下走
/*
* Nand Interface Init for SMDK6400 */
nand_asm_init:
ldr r0, =ELFIN_NAND_BASE ;nand flash 基址#define ELFIN_NAND_BASE 0x70200000
ldr r1, [r0, #NFCONF_OFFSET] ;#define NFCONF_OFFSET 0x00;
orr r1, r1, #0x70 ; 0 0000 0 00 000000000 111 0 111 0 111 0000
orr r1, r1, #0x7700
str r1, [r0, #NFCONF_OFFSET];nandflash控制寄存器配置完成
ldr r1, [r0, #NFCONT_OFFSET]
orr r1, r1, #0x03 ;0 0000 0 00 000000000 111 0 111 0 111 0000 AND 11
str r1, [r0, #NFCONT_OFFSET] ;0 0000 0 00 000000000 111 0 111 0 111 0011
mov pc, lr
@至此，nandflash简单的配置了一下，其实我觉得这里可以不用配置，在mm control过程中配置也是可以的。

从链接寄存器取出当前PC指针，跳回主干流程，执行mem_ctrl_asm_init过程。

当前ARM芯片工作模式为SVC模式，现在还没回到启动代码kernel中。

附上反汇编一份供参照
owlevel_init.o
lowlevel_init.o: file format elf32-littlearm
Disassembly of section .text:
00000000 <_TEXT_BASE>:
0: c7e00000 .word 0xc7e00000
00000004 <lowlevel_init>:
4: e1a0c00e mov ip, lr
8: e59f0248 ldr r0, [pc, #584] ; 258 <nand_asm_init+0x24>
c: e59f1248 ldr r1, [pc, #584] ; 25c <nand_asm_init+0x28>
10: e5801800 str r1, [r0, #2048]
14: e59f1240 ldr r1, [pc, #576] ; 25c <nand_asm_init+0x28>
18: e5801804 str r1, [r0, #2052]
1c: e59f123c ldr r1, [pc, #572] ; 260 <nand_asm_init+0x2c>
20: e5801810 str r1, [r0, #2064]
24: e3a01301 mov r1, #67108864 ; 0x4000000
28: e58010a0 str r1, [r0, #160]
2c: e3a01a02 mov r1, #8192 ; 0x2000
34: e59f021c ldr r0, [pc, #540] ; 258 <nand_asm_init+0x24>
38: e59f1224 ldr r1, [pc, #548] ; 264 <nand_asm_init+0x30>
3c: e5801820 str r1, [r0, #2080]
40: e59f1220 ldr r1, [pc, #544] ; 268 <nand_asm_init+0x34>
44: e5801828 str r1, [r0, #2088]
48: e3a0102a mov r1, #42 ; 0x2a
4c: e5801824 str r1, [r0, #2084]
50: e3a01000 mov r1, #0 ; 0x0
54: e58011d4 str r1, [r0, #468]
58: e3a0047e mov r0, #2113929216 ; 0x7e000000
5c: e3800901 orr r0, r0, #16384 ; 0x4000
60: e3a01000 mov r1, #0 ; 0x0
64: e5801000 str r1, [r0]
68: e59f01fc ldr r0, [pc, #508] ; 26c <nand_asm_init+0x38>
6c: e5901000 ldr r1, [r0]
70: e5801000 str r1, [r0]
74: e59f01f4 ldr r0, [pc, #500] ; 270 <nand_asm_init+0x3c>
78: e59f11f4 ldr r1, [pc, #500] ; 274 <nand_asm_init+0x40>
7c: e3e03000 mvn r3, #0 ; 0x0
80: e5803014 str r3, [r0, #20]
84: e5813014 str r3, [r1, #20]
88: e3a03000 mov r3, #0 ; 0x0
8c: e580300c str r3, [r0, #12]
94: e3a03000 mov r3, #0 ; 0x0
98: e5803f00 str r3, [r0, #3840]
9c: e5813f00 str r3, [r1, #3840]
a0: eb00001a bl 110 <system_clock_init>
a4: eb00004e bl 1e4 <uart_asm_init>
a8: e59f01c8 ldr r0, [pc, #456] ; 278 <nand_asm_init+0x44>
ac: e59f11c8 ldr r1, [pc, #456] ; 27c <nand_asm_init+0x48>
b0: e5801020 str r1, [r0, #32]
b4: eb00005e bl 234 <nand_asm_init>
b8: ebfffffe bl 0 <mem_ctrl_asm_init>
bc: e59f01bc ldr r0, [pc, #444] ; 280 <mem_ctrl_asm_init+0x280>
c0: e5901000 ldr r1, [r0]
c4: e2011008 and r1, r1, #8 ; 0x8
c8: e3510008 cmp r1, #8 ; 0x8
cc: 0a000004 beq e4 <mem_ctrl_asm_init+0xe4>
d0: e59f01a0 ldr r0, [pc, #416] ; 278 <mem_ctrl_asm_init+0x278>
d4: e59f11a0 ldr r1, [pc, #416] ; 27c <mem_ctrl_asm_init+0x27c>
d8: e5801020 str r1, [r0, #32]
dc: e1a0e00c mov lr, ip
e0: e1a0f00e mov pc, lr
000000e4 <wakeup_reset>:
e4: e59f0198 ldr r0, [pc, #408] ; 284 <mem_ctrl_asm_init+0x284>
e8: e5901000 ldr r1, [r0]
ec: e5801000 str r1, [r0]
f0: e59f0160 ldr r0, [pc, #352] ; 258 <mem_ctrl_asm_init+0x258>
f4: e3a01a03 mov r1, #12288 ; 0x3000
f8: e5801834 str r1, [r0, #2100]
fc: e59f0184 ldr r0, [pc, #388] ; 288 <mem_ctrl_asm_init+0x288>
100: e5901000 ldr r1, [r0]
104: e1a0f001 mov pc, r1
108: e1a00000 nop (mov r0,r0)
10c: e1a00000 nop (mov r0,r0)
00000110 <system_clock_init>:
110: e59f0174 ldr r0, [pc, #372] ; 28c <mem_ctrl_asm_init+0x28c>
114: e5901900 ldr r1, [r0, #2304]
118: e3a02040 mov r2, #64 ; 0x40
11c: e1811002 orr r1, r1, r2
120: e5801900 str r1, [r0, #2304]
124: e1a00000 nop (mov r0,r0)
128: e1a00000 nop (mov r0,r0)
12c: e1a00000 nop (mov r0,r0)
130: e1a00000 nop (mov r0,r0)
134: e1a00000 nop (mov r0,r0)
138: e3a02080 mov r2, #128 ; 0x80
13c: e1811002 orr r1, r1, r2
140: e5801900 str r1, [r0, #2304]
00000144 <check_syncack>:
144: e5901900 ldr r1, [r0, #2304]
148: e3a02c0f mov r2, #3840 ; 0xf00
14c: e0011002 and r1, r1, r2
150: e3510c0f cmp r1, #3840 ; 0xf00
154: 1afffffa bne 144 <mem_ctrl_asm_init+0x144> 158: e3a01cff mov r1, #65280 ; 0xff00
15c: e38110ff orr r1, r1, #255 ; 0xff
160: e5801000 str r1, [r0]
164: e5801004 str r1, [r0, #4]
168: e5801008 str r1, [r0, #8]
16c: e5901028 ldr r1, [r0, #40]
170: e3c11807 bic r1, r1, #458752 ; 0x70000
174: e3811803 orr r1, r1, #196608 ; 0x30000
178: e5801028 str r1, [r0, #40]
17c: e5901020 ldr r1, [r0, #32]
180: e3c11803 bic r1, r1, #196608 ; 0x30000
184: e3c11cff bic r1, r1, #65280 ; 0xff00
188: e3c110ff bic r1, r1, #255 ; 0xff
18c: e59f20fc ldr r2, [pc, #252] ; 290 <mem_ctrl_asm_init+0x290>
190: e1811002 orr r1, r1, r2
194: e5801020 str r1, [r0, #32]
198: e59f10f4 ldr r1, [pc, #244] ; 294 <mem_ctrl_asm_init+0x294>
19c: e580100c str r1, [r0, #12]
1a0: e59f10ec ldr r1, [pc, #236] ; 294 <mem_ctrl_asm_init+0x294>
1a4: e5801010 str r1, [r0, #16]
1a8: e59f10e8 ldr r1, [pc, #232] ; 298 <mem_ctrl_asm_init+0x298>
1ac: e5801014 str r1, [r0, #20]
1b0: e3a01000 mov r1, #0 ; 0x0
1b4: e5801018 str r1, [r0, #24]
1b8: e590101c ldr r1, [r0, #28]
1bc: e59f20d8 ldr r2, [pc, #216] ; 29c <mem_ctrl_asm_init+0x29c>
1c0: e1811002 orr r1, r1, r2
1c4: e580101c str r1, [r0, #28]
1c8: e3a01801 mov r1, #65536 ; 0x10000
1cc: e2511001 subs r1, r1, #1 ; 0x1
1d0: 1afffffd bne 1cc <mem_ctrl_asm_init+0x1cc> 1d4: e5901900 ldr r1, [r0, #2304]
1d8: e3811020 orr r1, r1, #32 ; 0x20
1dc: e5801900 str r1, [r0, #2304]
1e0: e1a0f00e mov pc, lr
000001e4 <uart_asm_init>:
1e4: e59f006c ldr r0, [pc, #108] ; 258 <mem_ctrl_asm_init+0x258>
1e8: e59f10b0 ldr r1, [pc, #176] ; 2a0 <mem_ctrl_asm_init+0x2a0>
1ec: e5801000 str r1, [r0]
1f0: e59f10ac ldr r1, [pc, #172] ; 2a4 <mem_ctrl_asm_init+0x2a4>
1f4: e5801020 str r1, [r0, #32]
1f8: e59f0078 ldr r0, [pc, #120] ; 278 <mem_ctrl_asm_init+0x278>
1fc: e3a01000 mov r1, #0 ; 0x0
200: e5801008 str r1, [r0, #8]
204: e580100c str r1, [r0, #12]
208: e3a01003 mov r1, #3 ; 0x3
20c: e5801000 str r1, [r0]
210: e59f1090 ldr r1, [pc, #144] ; 2a8 <mem_ctrl_asm_init+0x2a8>
214: e5801004 str r1, [r0, #4]
218: e3a01022 mov r1, #34 ; 0x22
21c: e5801028 str r1, [r0, #40]
220: e59f1084 ldr r1, [pc, #132] ; 2ac <mem_ctrl_asm_init+0x2ac>
224: e580102c str r1, [r0, #44]
228: e59f1080 ldr r1, [pc, #128] ; 2b0 <mem_ctrl_asm_init+0x2b0>
22c: e5801020 str r1, [r0, #32]
230: e1a0f00e mov pc, lr
00000234 <nand_asm_init>:
234: e59f0078 ldr r0, [pc, #120] ; 2b4 <mem_ctrl_asm_init+0x2b4>
238: e5901000 ldr r1, [r0]
23c: e3811070 orr r1, r1, #112 ; 0x70
240: e3811c77 orr r1, r1, #30464 ; 0x7700
244: e5801000 str r1, [r0]
248: e5901004 ldr r1, [r0, #4]
24c: e3811003 orr r1, r1, #3 ; 0x3
250: e5801004 str r1, [r0, #4]
254: e1a0f00e mov pc, lr
258: 7f008000 .word 0x7f008000
25c: 55555555 .word 0x55555555
260: 22222666 .word 0x22222666
264: 00111111 .word 0x00111111
268: 00000555 .word 0x00000555 26c: 7f008924 .word 0x7f008924 270: 71200000 .word 0x71200000 274: 71300000 .word 0x71300000 278: 7f005000 .word 0x7f005000 27c: 4b4b4b4b .word 0x4b4b4b4b 280: 7e00f904 .word 0x7e00f904 284: 7e00f908 .word 0x7e00f908 288: 7e00fa00 .word 0x7e00fa00 28c: 7e00f000 .word 0x7e00f000 290: 00003310 .word 0x00003310 294: 810a0301 .word 0x810a0301 298: 80200203 .word 0x80200203 29c: 00002007 .word 0x00002007 2a0: 00220022 .word 0x00220022 2a4: 00002222 .word 0x00002222 2a8: 00000e45 .word 0x00000e45 2ac: 00001fff .word 0x00001fff
2b0: 4f4f4f4f .word 0x4f4f4f4f
2b4: 70200000 .word 0x70200000。