FPGA可编程逻辑器件芯片XC2V500-4CS144I中文规格书
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It is directly accessible from the FPGA fabric. Configuration bits can be written to and/or read from depending on their function.
Each bit of memory is initialized with the value of the corresponding configuration memory bit in the bitstream. Memory bits can also be changed later through the ICAP.
SWITCH
Switches the CCLK frequency: Updates the frequency of the Master 01001 CCLK to the value specified by the OFSEL bits in the COR0 register.
Virtex-5 FPGA Configuration Guide UG191 (v3.13) July 28, 2020
Virtex-5 FPGA Configuration Guide UG191 (v3.13) July 28, 2020
Configuration Registers
IDCODE Register
Any writes to the FDRI register must be preceded by a write to this register. The provided IDCODE must match the device’s IDCODE. See “Configuration Sequence,” page 23. A read of this register returns the device IDCODE.
the configuration data pins are ignored.
CRCC
10000
When Readback CRC is selected, the CRC is calculated after full configuration and reconfiguration. Toggling GHIGH also calculates the CRC. This command can be used when GHIGH is not toggled during reconfiguration (active partial reconfiguration).
command.
RCFG
Reads Configuration Data: Used prior to reading configuration 00100 data from the FDRO.
START
Begins the Startup Sequence: Initiates the startup sequence. The 00101 startup sequence begins after a successful CRC check and a
Chapter 6: Configuration Details
Table 6-6: Command Register Codes (Continued)
Command Code
Description
GRESTORE
Pulses the GRESTORE signal: sets/resets (depending on user 01010 configuration) IOB and CLB flip-flops.
SHUTDOWN
01011
Begin Shutdown Sequence: Initiates the shutdown sequence, disabling the device when finished. Shutdown activates on the next successful CRC check or RCRC instruction (typically an RCRC instruction).
Table 6-6: Command Register Codes
Command Code
Description
NULL
00000 Null command.
WCFG
Writes Configuration Data: Used prior to writing configuration 00001 data to the FDRI.
The output of each memory bit drives the functional block logic, so the content of this memory determines the configuration of the functional block.
The address space can include status (read-only) and function enables (write-only). Readonly and write-only operations can share the same address space. Figure 5-1 shows how the configuration bits drive the logic in functional blocks directly in earlier FPGA families, and Figure 5-2 shows how the reconfiguration logic changes the flow to read or write the configuration bits.
MFW
Multiple Frame Write: Used to perform a write of a single frame 00010 data to multiple frame addresses.
DGHIGH/ LFRM
Last Frame: Deasserts the GHIGH_B signal, activating all 00011 interconnects. The GHIGH_B signal is asserted with the AGHIGH
GCAPTURE
Pulses GCAPTURE: Loads the capture cells with the current 01100 register states (see “Readback Capture,” page 151).
DESYNCH
Resets the DALIGN signal: Used at the end of configuration to 01101 desynchronize the device. After desynchronization, all values on
Chapter 5
Dynamic Reconfiguration Port (DRP)
Dynamic Reconfiguration of Functional Blocks
Background
In the Virtex-5 family of FPGAs, the configuration memory is used primarily to implement user logic, connectivity, and I/Os, but it is also used for other purposes. For example, it is used to specify a variety of static conditions in functional blocks, such as clock management tiles (CMTs).
Overview
This document describes the addressable, parallel write/read configuration memory that is implemented in each functional block that might require reconfiguration. This memory has the following attributes:
RCRC
00111 Resets CRC: Resets the CRC register.
AGHIGH
01000
Asserts the GHIGH_B signal: Places all interconnect in a High-Z state to prevent contention when writing new configuration data. This command is only used in shutdown reconfiguration. Interconnect is reactivated with the LFRM command.
DESYNC command are performed.
RCAP
Resets the CAPTURE signal after performing readback-capture in 00110 single-shot mode (see “Readback Capture,” page 151).
Sometimes an application requires a change in these conditions in the functional blocks while the block is operational. This can be accomplished by partial dynamic reconfiguration using the JTAG, ICAP, or SelectMAP ports. However, the dynamic reconfiguration port that is an integral part of each functional block simplifies this process greatly. Such configuration ports exist in the CMTs.
AXSS Register
Software uses this register to support the USR_ACCESS_VIRTEX5 primitive (see “USR_ACCESS_VIRTEX5,” page 103).
CSOB Register
Software uses this register to assert the CSO_B pin for parallel daisy-chain operation.
Command Register (CMD)
The Command Register is used to instruct the configuration control logic to strobe global signals and perform other configuration functions. The command present in the CMD register is executed each time CMD or FAR is loaded. The code bits are located in the LSB bits of the 32-bit CMD register, with the remaining MSB bits set to 0. Table 6-6 lists the Command Register commands and codes.
All configuration bits for this block
to Block Logic
Configuration Logic Functional Block (DCM or MGT)
UG191_c5_01_050406
Figure 5-1: Block Configuration Logic without Dynamic Interface
Each bit of memory is initialized with the value of the corresponding configuration memory bit in the bitstream. Memory bits can also be changed later through the ICAP.
SWITCH
Switches the CCLK frequency: Updates the frequency of the Master 01001 CCLK to the value specified by the OFSEL bits in the COR0 register.
Virtex-5 FPGA Configuration Guide UG191 (v3.13) July 28, 2020
Virtex-5 FPGA Configuration Guide UG191 (v3.13) July 28, 2020
Configuration Registers
IDCODE Register
Any writes to the FDRI register must be preceded by a write to this register. The provided IDCODE must match the device’s IDCODE. See “Configuration Sequence,” page 23. A read of this register returns the device IDCODE.
the configuration data pins are ignored.
CRCC
10000
When Readback CRC is selected, the CRC is calculated after full configuration and reconfiguration. Toggling GHIGH also calculates the CRC. This command can be used when GHIGH is not toggled during reconfiguration (active partial reconfiguration).
command.
RCFG
Reads Configuration Data: Used prior to reading configuration 00100 data from the FDRO.
START
Begins the Startup Sequence: Initiates the startup sequence. The 00101 startup sequence begins after a successful CRC check and a
Chapter 6: Configuration Details
Table 6-6: Command Register Codes (Continued)
Command Code
Description
GRESTORE
Pulses the GRESTORE signal: sets/resets (depending on user 01010 configuration) IOB and CLB flip-flops.
SHUTDOWN
01011
Begin Shutdown Sequence: Initiates the shutdown sequence, disabling the device when finished. Shutdown activates on the next successful CRC check or RCRC instruction (typically an RCRC instruction).
Table 6-6: Command Register Codes
Command Code
Description
NULL
00000 Null command.
WCFG
Writes Configuration Data: Used prior to writing configuration 00001 data to the FDRI.
The output of each memory bit drives the functional block logic, so the content of this memory determines the configuration of the functional block.
The address space can include status (read-only) and function enables (write-only). Readonly and write-only operations can share the same address space. Figure 5-1 shows how the configuration bits drive the logic in functional blocks directly in earlier FPGA families, and Figure 5-2 shows how the reconfiguration logic changes the flow to read or write the configuration bits.
MFW
Multiple Frame Write: Used to perform a write of a single frame 00010 data to multiple frame addresses.
DGHIGH/ LFRM
Last Frame: Deasserts the GHIGH_B signal, activating all 00011 interconnects. The GHIGH_B signal is asserted with the AGHIGH
GCAPTURE
Pulses GCAPTURE: Loads the capture cells with the current 01100 register states (see “Readback Capture,” page 151).
DESYNCH
Resets the DALIGN signal: Used at the end of configuration to 01101 desynchronize the device. After desynchronization, all values on
Chapter 5
Dynamic Reconfiguration Port (DRP)
Dynamic Reconfiguration of Functional Blocks
Background
In the Virtex-5 family of FPGAs, the configuration memory is used primarily to implement user logic, connectivity, and I/Os, but it is also used for other purposes. For example, it is used to specify a variety of static conditions in functional blocks, such as clock management tiles (CMTs).
Overview
This document describes the addressable, parallel write/read configuration memory that is implemented in each functional block that might require reconfiguration. This memory has the following attributes:
RCRC
00111 Resets CRC: Resets the CRC register.
AGHIGH
01000
Asserts the GHIGH_B signal: Places all interconnect in a High-Z state to prevent contention when writing new configuration data. This command is only used in shutdown reconfiguration. Interconnect is reactivated with the LFRM command.
DESYNC command are performed.
RCAP
Resets the CAPTURE signal after performing readback-capture in 00110 single-shot mode (see “Readback Capture,” page 151).
Sometimes an application requires a change in these conditions in the functional blocks while the block is operational. This can be accomplished by partial dynamic reconfiguration using the JTAG, ICAP, or SelectMAP ports. However, the dynamic reconfiguration port that is an integral part of each functional block simplifies this process greatly. Such configuration ports exist in the CMTs.
AXSS Register
Software uses this register to support the USR_ACCESS_VIRTEX5 primitive (see “USR_ACCESS_VIRTEX5,” page 103).
CSOB Register
Software uses this register to assert the CSO_B pin for parallel daisy-chain operation.
Command Register (CMD)
The Command Register is used to instruct the configuration control logic to strobe global signals and perform other configuration functions. The command present in the CMD register is executed each time CMD or FAR is loaded. The code bits are located in the LSB bits of the 32-bit CMD register, with the remaining MSB bits set to 0. Table 6-6 lists the Command Register commands and codes.
All configuration bits for this block
to Block Logic
Configuration Logic Functional Block (DCM or MGT)
UG191_c5_01_050406
Figure 5-1: Block Configuration Logic without Dynamic Interface