Self-calibrating A-D and digital-to-analog convert
- 1、下载文档前请自行甄别文档内容的完整性，平台不提供额外的编辑、内容补充、找答案等附加服务。
- 2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
- 3、如文档侵犯您的权益，请联系客服反馈,我们会尽快为您处理(人工客服工作时间：9:00-18:30)。
专利名称：Self-calibrating A-D and digital-to-analog converter
发明人：デイーター、ドラクセルマイル
申请号：JP特願平1-255115
申请日：19890929
公开号：JP特許第3095756号(P3095756)B2
公开日：
20001010
专利内容由知识产权出版社提供
摘要：PURPOSE: To reduce occupancy area by using a successive approximation register used for conversion also for calculating a calibration. CONSTITUTION: A controller (SAR, KL, RW, MUX1, MUX2, and SE) includes a single successive approximation register SAR. In a calibration stage in which a converter circuit network WCN and a calibrating and calibration circuit network KCN can be controlled in a multiplexed operation, a transistor T21 is conducted, and all the capacitance of a converter circuit network WCN are successively compared with the further low weighted capacitance of the circuit network, and the calibration capacitance or capacitance values of the calibrating and calibration circuit network KCN are confirmed. In a conversion stage, the transistor T2 is interrupted, and the output edge of the successive approximation register SAR is connected with the switch of the converter circuit network WCN. Thus, the occupancy area can be reduced.
申请人：シーメンス、アクチエンゲゼルシヤフト
地址：ドイツ連邦共和国ベルリン及ミユンヘン(番地なし)
国籍：DE
代理人：山口 巖
更多信息请下载全文后查看。