The Design and Veri cation of a Sorter Core

Fig. 1. Architecture of the 2-sorter
process begin wait until clk'event and clk='1' if a > b then x <= b y <= a else x <= a y <= b end if end process end behav
architecture behav of two_sorter_synth is begin
b a
n n
m u x b u s a>b
v r e g
x
m u x ork2 fsT comparator [(a,b), (a,b)] muxbus >|> vreg muxbus' >|> vreg
The rest of the paper is organised as follows. In Section 2, we introduce Lava by illustrating how to describe and verify a 2-sorter, the basic building block for our sorting networks. In Section 3, we show how to describe networks in general, and sorting networks in particular. In Section 4, we show di erent ways of visualising the described networks, which helps us pick fast implementations. In Section 5, we show how to formally verify properties of our networks using Lava. In Section 6, we describe periodic networks, which are easier to implement on FPGAs in an e cient way. Finally, in Section 7, we illustrate the complete implementation of the sorter core.
presented. We present several techniques and tools used to verify the functionality of the sorter. The sorter is a periodic sorter based on recursive butter y networks. Having a design language that is well-suited to describing these networks has helped us to explore the design space far more e ectively than is possible using conventional hardware description languages.
The Design and Veri cation of a Sorter Core
Koen Claessen1, Mary Sheeran1 , and Satnam Singh2
1
Chalmers University of Technology 2 Xilinx, Inc.
Abstract. The design and veri cation of a high speed sorter core is
Although this VHDL code is synthesisable, we require a very compact high speed 2-sorter with a speci c foot-print that is suitable for tiling in a butter y network. For this reason the actual 2-sorter is implemented in the Lava HDL which has been designed and implemented to support high performance oorplanned structural designs for Xilinx's Virtex and Virtex-II range of FPGAs. Figure 1 shows the implementation architecture for the 2-sorter. This implementation uses a comparator to determine which of a or b is greater. The result of the comparator is used as the select signal to two bus-multiplexors. The outputs of the bus-multiplexors are registered to allow the construction of pipelined sorters. The top-level Lava description of the two sorter is:
2 Design and Veri cation of a 2-Sorter
The basic element of the sorter butter y networks that we present in the following sections is a two-sorter circuit. This circuit takes a pair of n-bit numbers and returns the pair sorted into ascending order. The actual butter y networks implemented on FPGAs are pipelined. This is achieved by registering the output of each 2-sorter. First we describe the desired behaviour of the 2-sorter in terms of behavioural VHDL code. Then we present the actual implementation in the Lava HDL. We then use a proto-type netlist equivalence checker developed at Xilinx to ensure that the Lava structural implementation is faithful to the high level VHDL description. The equivalence checker is based on sequential equivalence checking software produced by Prover Technology.
1 Introduction
This paper describes the application of various formal and informal techniques to the design, implementation, optimisation and veri cation of a high speed sorter core realised on a large eld programmable gate array (FPGA). The sorter core presented here is considered to be a piece of intellectual property which places greater than usual emphasis on the veri cation of the circuit's correctness due to the unknown applications that customers will nd for cores. Examples of the application of high speed sorting are graphics algorithms for rendering and ray tracing. The design of the sorter core is based on recursively described butter y networks which are composed to realise periodic sorters. There are a large number of di erent but similar sorting network designs, resulting in circuits of varying performance (depending on the lengths of intermediate wires). Having a design language that is well-suited to describing these networks has helped us to explore the design space far more e ectively than is possible using conventional hardware description languages. We present several designs and instrument their performance. To produce an e cient sorter network one has to take care to carefully place the butter y network on the FPGA to manage the intermediate wire lengths and also ensure e ective use of the available silicon resource. We demonstrate how a layout combinator based style of description allows us to generate a compact layout without the tedious calculations that are necessary in a conventional HDL. The design environment used to describe and verify circuit cores we use in the paper is developed at Xilinx and at Chalmers University, and is called Lava 3]. Circuit descriptions in Lava are made in the functional language Haskell 6].
The sorter takes two numbers a and b as input and returns x and y where x is the smaller of a and b and y is the larger on the rising edge of the clk signal. This is the VHDL golden behavioural description that we use:
2.1 Behavioural Speci cation
The interface of the 2-sorter is given in VHDL code below.
package two_sorter_package is constant size : natural := 16 subtype num is natural range 0 to 2**size-1 component two_sorter_synth is port (signal a, b : in num signal clk : in bit signal x, y : out num) end component two_sorter_synth end package two_sorter_package