数字电路-计数器-74LVC161

SF00656
LOGIC SYMBOL
15
15 16
LOGIC SYMBOL (IEEE/IEC)
1 Q0 Q1 Q2 Q3 14 13 12 11 9 7 10 2 R M1 G3 G4 C2 /1,3,4+ CTR4
TC 3 4 5 6 9 D0 D1 D2 D3 PE CEP CET CP MR
D0 9 PE
D1
D2
D3
Parallel load
PARALLEL LOAD CIRCUITRY
Count Hold (do nothing)
TC 15
10 CET
7 CEP
2
CP
BINARY COUNTER
1 MR Q0 Q1 Q2 Q3
14
13
12
11
NOTES: * = The TC output is High when CET is High and the counter is at Terminal Count (HHHH) H = High voltage level h = High voltage level one setup time prior to the Low-to-High clock transition L = Low voltage level l = Low voltage level one setup time prior to the Low-to-High clock transition q = Lower case letters indicate the state of the referenced output one setup time prior to the Low-to-High clock transition X = Don’t care ↑ = Low-to-High clock transition
74LVC161
FUNCTIONAL DIAGRAM
3 4 5 6
FUNCTION TABLE
OPERATING MODES Reset (clear) INPUTS MR L H H H H H CP X ↑ ↑ ↑ X X CEP X X X h l X CET X X X h X l PE X l l h h h Dn X l h X X X OUTPUTS Qn L L H count qn qn TC L L * * * L
1998 May 20
2
853-1864 19421
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary counter; asynchronous reset
Hale Waihona Puke 74LVC161PIN CONFIGURATION
The 74LVC161 is a synchronous presettable binary counter which features an internal look–head carry and can be used for high–speed counting. Synchronous operation is provided by having all flip–flops clocked simultaneously on the positive–going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW level. A LOW level at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive–going edge of the clock (provided that the set–up and hold time requirements for PE are met). Preset takes place regardless of the levels at count enable inputs (CEP and CET). A low level at the master reset input (MR) sets all four outputs of the flip–flops (Q0 to Q3) to LOW level regardless of the levels at CP, PE, CET and CEP inputs (thus providing an asynchronous clear function). The look–ahead carry simplifies serial cascading of the counters. Both count enable inputs (CEP and CET) must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH level output of Q0. This pulse can be used to enable the next cascaded stage. The maximum clock frequency for the cascaded counters is determined by the CP to TC propagation delay and CEP to CP set–up time, according to the following formula:
fmax = 1 _______________________________
tp(max) (CP to TC) + tSU (CEP to CP)
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; TR = TF 2.5ns SYMBOL PARAMETER Propagation delay CP to Qn CP to TC MR to Qn MR to TC CET to TC maximum clock frequency input capacitance power dissipation capacitance per gate notes 1 and 2 CONDITIONS CL = 50 pF VCC = 3.3V TYPICAL 4.9 5.7 5.2 5.7 4.5 200 5.0 39 UNIT
3 4
1,2 D
14 13 12 11 15
7
10
2
1
5 6
4 CT=15 VCC = Pin 16 GND = Pin 8
SY00065
SY00066
1998 May 20
3
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary counter; asynchronous reset
DESCRIPTION
The 74LVC161 is a high–performance, low–power, low–voltage, Si–gate CMOS device and superior to most advanced CMOS compatible TTL families.
INTEGRATED CIRCUITS
74LVC161 Presettable synchronous 4-bit binary counter; asynchronous reset
Product specification Supersedes data of 1996 Aug 23 IC24 Data Handbook 1998 May 20
Philips Semiconductors
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary counter; asynchronous reset
74LVC161
FEATURES
• Wide supply voltage range of 1.2 V to 3.6 V • In accordance with JEDEC standard no. 8–1A • Inputs accept voltages up to 5.5 V • CMOS low power consumption • Direct interface with TTL levels • Asynchronous reset • Synchronous counting and loading • Two count enable inputs for n–bit cascading • Positive edge–triggered clock • Output drive capability 50 W transmission lines @85_C
tPHL/tPLH
ns
fMAX CI CPD
MHz pF pF
NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD x VCC2 x fi +Σ (CL x VCC2 x fo ) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; Σ (CL x VCC2 x fo ) = sum of the outputs 2. The condition is V1 = GND to VCC